Voltage detecting circuit and information processing apparatus

Abstract

To provide a voltage detecting circuit for measuring voltage accurately, and an information processing apparatus.SOLUTION: A ring oscillator 101 included in a reference-frequency generating circuit 11 and a comparative-frequency generating circuit 12 has a plurality of inverters 111 arranged in series annularly. A sampling portion acquires an output signal from the respective inverters 111 in each sampling cycle. A transition stage number calculating portion calculates the number of transition stages, which is the number of inverters 111 in which a value of the output signal has changed during the sampling cycle of each ring oscillator 101 on the basis of the output signal of each sampling cycle acquired by the sampling portion. A voltage detecting portion performs voltage detection on the basis of the number of transition stages acquired by the transition stage number calculating portion.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a voltage detection circuit and an information processing device. [Background technology]

[0002] When measuring the voltage of a digital circuit, a ring oscillator (ROSC) is often used due to its small circuit size and ease of measurement. The oscillation frequency of the ROSC changes depending on the applied voltage. Therefore, it is possible to detect the voltage by comparing the oscillation frequency of the ROSC operating at the measurement voltage, which is the voltage to be measured, with the oscillation frequency of the ROSC operating at the reference target voltage. In this method, to calculate the oscillation frequency, the number of times each node inside the ROSC transitions from high to low or low to high within a specified period is counted.

[0003] Conventionally, the following techniques have been proposed for measuring voltage using ROSC: For example, there is a technique in which the input frequency to an AD converter equipped with a ring oscillator is calculated based on information on the inflow and outflow currents of a high-voltage battery, and if the result of the map calculation is small, the input frequency is set to a low frequency, and if the absolute value is large, the input frequency is set to a high frequency. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-268068 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, there were various problems with the conventional technology for measuring voltage using ROSC. For example, when determining the number of revolutions of ROSC and how many stages have progressed from the starting point within a voltage comparison period, a reset is performed during measurement and transmission begins from the starting node. In this case, voltage measurement is difficult during the reset operation. If there is a period during which it is difficult to measure voltage, there is a risk of errors occurring under conditions where the voltage is fluctuating.

[0006] Furthermore, if the internal node and lap counters are sampled using a sampling clock and the overall number of stages advanced is determined from the difference with the previous sample result, there is a risk of large measurement errors due to the effect of metastable states that occur when the counters are sampled.

[0007] In addition, if a counter is provided at each node in the ROSC and the number of transitions is calculated by calculating the sum of the counters, there will be periods when it is difficult to detect the voltage due to the counter reset operation. In this case, too, if there are periods when it is difficult to measure the voltage, there is a risk of errors occurring when the voltage is fluctuating.

[0008] In addition, in the technology for changing the input frequency to the AD converter equipped with a ring oscillator based on the inflow and outflow current information of the high-voltage battery, the method for acquiring the oscillation frequency of the ROSC is not particularly considered, and there is a risk of errors occurring as with the conventional method. Thus, in the conventional technology for measuring voltage using ROSC, there is a risk of errors occurring in the voltage measurement, making it difficult to measure the voltage with high accuracy.

[0009] The disclosed technology has been made in consideration of the above, and has an object to provide a voltage detection circuit and an information processing device that measure voltage with high accuracy. [Means for solving the problem]

[0010] In one aspect of the voltage detection circuit and information processing device disclosed in the present application, there are two ring oscillators each having a plurality of inverters arranged in series in a ring shape. A sampling unit acquires an output signal from each of the inverters for each sampling period. A transition stage number calculation unit calculates a transition stage number, which is the number of inverters whose output signal value has transitioned during the sampling period for each of the ring oscillators, based on the output signal for each sampling period acquired by the sampling unit. A voltage detection unit performs voltage detection based on the transition stage number acquired by the transition stage number calculation unit. Effect of the Invention

[0011] In one aspect, the present invention is capable of measuring voltage with high accuracy. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic diagram of a regulator. [Diagram 2] FIG. 2 is a circuit diagram of an example of a voltage detection circuit according to an embodiment. [Diagram 3] FIG. 3 shows the internal state of the ROSC. [Figure 4] FIG. 4 is a diagram for explaining how to determine the number of transition stages. [Diagram 5] FIG. 5 is a timing chart showing signal changes and sampling results. [Figure 6] FIG. 6 is a diagram for explaining the absorption of errors in the voltage detection circuit according to the embodiment. [Figure 7] FIG. 7 is a flowchart of the voltage detection process. [Figure 8] FIG. 8 is a flowchart of the voltage control. [Figure 9] FIG. 9 is a diagram illustrating an example of a control result by the voltage control using the voltage detection circuit according to the embodiment. [Figure 10] FIG. 10 is a diagram for explaining a decrease in detection accuracy when there is a time during which voltage detection is disabled. [Figure 11]FIG. 11 is a diagram illustrating the timing of sampling by the voltage detection circuit according to the embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of an information processing device using a voltage detection circuit according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the voltage detection circuit and the information processing device disclosed in the present application will be described in detail with reference to the drawings. Note that the voltage detection circuit and the information processing device disclosed in the present application are not limited to the following embodiments. EXAMPLES

[0014] Fig. 1 is a schematic diagram of a regulator. The regulator 1 shown in Fig. 1 is an LDO (Low Drop Out) regulator. The regulator 1 adjusts the power supply voltage supplied from an external power supply 2 to a specified low voltage value and supplies it to a controlled circuit 3. As shown in Fig. 1, the regulator 1 has a voltage detection circuit 10, a target voltage output circuit 20, an LDO control logic circuit 30, and a PMOS (P-Channel Metal Oxide Semiconductor) header 40.

[0015] The external power supply 2 inputs the power used for operating the controlled circuit 3 to the regulator 1. The voltage value of the power output from the external power supply 2 is higher than the voltage value for operating the controlled circuit 3.

[0016] The controlled circuit 3 is, for example, a CPU (Central Processing Unit). The controlled circuit 3 operates using power supplied from an external power source 2 as a power source. More specifically, the controlled circuit 3 receives an input of power whose voltage value has been adjusted from the regulator 1. The controlled circuit 3 then operates using the input power as a power source.

[0017] The target voltage output circuit 20 has information of a preset constant voltage value, and outputs a target voltage having the preset voltage value.

[0018] The voltage detection circuit 10 receives a target voltage input from the target voltage output circuit 20. The voltage detection circuit 10 also receives an output voltage input from the PMOS header 40 that is fed back. The voltage detection circuit 10 then compares the output voltage from the PMOS header 40 with the target voltage to calculate a voltage difference. The voltage detection circuit 10 then outputs the calculated voltage difference to the LDO control logic circuit 30.

[0019] The LDO control logic circuit 30 receives an input of the voltage difference between the output voltage from the PMOS header 40 and the target voltage from the voltage detection circuit 10. The LDO control logic circuit 30 determines the on / off state of each PMOS transistor in the PMOS header 40 so as to reduce the difference in the obtained voltage values. The LDO control logic circuit 30 then outputs a signal to each PMOS transistor in the PMOS header 40 so as to bring them into the determined on / off state. This LDO control logic circuit 30 is an example of a "voltage control circuit."

[0020] The PMOS header 40 has many PMOS transistors arranged in parallel. The PMOS header 40 realizes variable resistance by changing the on / off ratio of the PMOS transistors. In the PMOS header 40, each PMOS transistor is turned on or off by a signal input from the LDO control logic circuit 30. With each PMOS transistor being controlled to be on or off, the PMOS header 40 receives an input of power from the external power supply 2. Then, the PMOS header 40 outputs the power adjusted by turning the PMOS transistors on and off to the controlled circuit 3.

[0021] 2 is a circuit diagram of an example of a voltage detection circuit according to an embodiment of the present invention. The voltage detection circuit 10 includes a reference frequency generation circuit 11, a comparison frequency generation circuit 12, an oscillator 13, and a difference calculation unit 14.

[0022] The reference frequency generation circuit 11 receives a target voltage as an input and outputs an oscillation frequency corresponding to the target voltage. Hereinafter, the oscillation frequency corresponding to the target voltage is referred to as the "reference frequency." The comparison frequency generation circuit 12 receives a feedback output voltage from the PMOS header 40 as an input and outputs an oscillation frequency corresponding to the output voltage from the PMOS header 40. Hereinafter, the oscillation frequency corresponding to the output voltage from the PMOS header 40 is referred to as the "comparison frequency."

[0023] The reference frequency generating circuit 11 and the comparison frequency generating circuit 12 have the same configuration. Therefore, the following will explain the details by taking the reference frequency generating circuit 11 as an example.

[0024] The reference frequency generating circuit 11 includes a ROSC 101, a sampling mechanism 102, and a transition stage counting mechanism 103, as shown in FIG.

[0025] The ROSC101 has an odd number of inverters 111 connected in series. In the POSC101, the output of the last inverter 111 is input to the first inverter 111. Each inverter 111 sequentially outputs a signal having a logic opposite to that of the input signal to the inverter 111 in the following stage. That is, when a signal having a High value is input, the inverter 111 outputs a signal having a Low value to the inverter 111 in the following stage. Conversely, when a signal having a Low value is input, the inverter 111 outputs a signal having a High value to the inverter 111 in the following stage. Hereinafter, a signal having a High value is referred to as a "High signal", and a signal having a Low value is referred to as a "Low signal". Hereinafter, the ROSC101 of the reference frequency generating circuit 11 is an example of a "first ring oscillator", and the ROSC101 of the comparison frequency generating circuit 12 is an example of a "second ring oscillator".

[0026] Since an odd number of inverters 111 are connected, the next signal input to each inverter 111 is a signal whose logic is inverted from the previous signal. That is, each inverter 111 alternately receives signals whose logic is inverted, and outputs signals whose logic is inverted. This causes ROSC101 to oscillate. An oscillation frequency is generated by the period from when a signal is input to a specific inverter 111 in ROSC101 until the next signal is input. Therefore, each inverter 111 outputs a signal whose logic is different for each oscillation period. Here, the inverter 111 included in ROSC101 of the reference frequency generation circuit 11 is an example of a "first inverter", and the inverter 111 included in ROSC101 of the comparison frequency generation circuit 12 is an example of a "second ring oscillator".

[0027] The sampling mechanism 102 receives a system clock input from the oscillator 13. The sampling mechanism 102 has the same number of FFs (Flip Flops) 121 as the inverters 111. The sampling mechanism 102 also has the same number of FFs 122 as the inverters 111. Here, the sampling mechanism 102 of the reference frequency generation circuit 11 is an example of a "first sampling mechanism", and the sampling mechanism 102 of the comparison frequency generation circuit 12 is an example of a "second sampling mechanism".

[0028] The input terminal of each of the FFs 121 is connected to a path connecting the output of each of the inverters 111 and the input of the next-stage inverter 111. In addition, the output terminal of each of the FFs 121 is branched, one of which is connected to the input terminal of the FF 122 and the other of which is connected to the XOR circuit 131 of the transition stage count mechanism 103.

[0029] The FF 121 receives the output signals from the inverters 111 every clock in accordance with the system clock. The edges of the system clock are the sampling timings of the FF 121. The period of the system clock is the sampling period of the sampling mechanism 102. Then, after one clock in accordance with the system clock input from the oscillator 13, the FF 121 outputs the input signals from the inverters to the FF 122 and the XOR circuit 131.

[0030] Here, among the output signals acquired by the FF 121 at the sampling timing, the interval between the inverter 111 that outputs the output signal whose value last transitioned in that sampling period and the next inverter 111 is called the "edge" of the transition of the value of the output signal. That is, in the next sampling period, the value transitions from the output signal of the inverter 111 next to the edge.

[0031] The input terminals of the FFs 122 are connected to the output terminals of the FFs 121. The output terminals of the FFs 122 are connected to the XOR circuit 131 of the transition stage counting mechanism 103.

[0032] The FF122 receives the output signal from the inverter 111, delayed by one clock from the FF121. Then, the FF122 outputs the input signals from the inverters to the FF122 and the XOR circuit 131 one clock later.

[0033] In this way, the FF 122 adds a one-clock delay to the output signal from the clock 121. That is, the XOR circuit 131 receives the signal sampled by the FF 121 in a certain sampling period and the signal sampled by the FF 121 in the sampling period one period before that.

[0034] Here, it is preferable that the sampling period is greater than twice the oscillation frequency. In other words, it is preferable that (sampling period / 2)>oscillating frequency. For example, when (sampling period / 2)=oscillating frequency, the value of the signal held by FF122 at the sampling timing is the opposite of the value of the signal held by FF121. Also, when (sampling period / 2)<oscillating frequency, the edge will make one or more revolutions around ROSC101 during the sampling period, resulting in an inverter 111 whose output transitions two or more times.

[0035] 3 is a diagram showing the internal state of ROSC. In the upper part of the paper, ROSC 101 and FF 121 are diagrammatically illustrated. In addition, table 201 in the lower part of the paper shows the values ​​of the signal stored in FF 121 at time T0, time T1 one clock after time T0, and time T2 one clock after time T1. Here, a case where nine inverters 111 and FF 121 are arranged will be described. That is, Ph0 in table 201 represents the value of the signal held by the first FF 121, Ph2 to Ph7 represent the values ​​held by the FF 121 one stage after in order, and Ph8 represents the value held by the highest FF 121.

[0036] For example, the signal values ​​sampled by each FF 121 at time T0 are arranged as "0, 1, 0, 1, 1, 0, 1, 0, 1" from the first FF 121 to the latter. And, at time T0, the edge of the signal is position 211 between FF 121 of Ph3 and FF 121 of Ph4. Here, a signal with a value of 1 corresponds to a High signal, and a signal with a value of 0 corresponds to a Low signal.

[0037] The signal values ​​sampled at time T1 one sampling period later are arranged as "0, 1, 0, 1, 0, 1, 0, 1, 1" from the first FF 121 to the latter stages. Then, at time T1, the edge of the signal is at position 212 between FF 121 of Ph7 and FF 121 of Ph8. That is, during one sampling period, the signal moves the distance of four inverters 111 from FF 121 of Ph4 to FF 121 of Ph7.

[0038] Furthermore, the values ​​of the signal sampled at time T2 one sampling period later are arranged as "1, 0, 1, 0, 0, 1, 0, 1, 0" from the first FF 121 to the latter stages. Then, at time T2, the edge of the signal is at position 212 between FF 121 of Ph3 and FF 121 of Ph4. That is, during one sampling period, the signal moves the distance of five inverters 111 from FF 121 of Ph8 to FF 121 of Ph3.

[0039] Substituting the values ​​of the signals held by FF121 and FF122 into this table, when FF121 is in a state where it is holding the signal at time T1, FF122 is holding the signal at time T0. Also, when FF121 is in a state where it is holding the signal at time T2, FF122 is holding the signal at time T1.

[0040] The transition stage counting mechanism 103 includes an XOR circuit 131 and a population counter 132. Here, the transition stage counting mechanism 103 of the reference frequency generation circuit 11 corresponds to an example of a "first transition stage counting mechanism", and the transition stage counting mechanism 103 of the comparison frequency generation circuit 12 corresponds to an example of a "second transition stage counting mechanism".

[0041] The XOR circuit 131 receives an input of a signal sampled by FF121 in the latest sampling period from FF121. Also, the XOR circuit 131 receives an input of a signal sampled by FF121 in the previous sampling period from FF122.

[0042] Then, the XOR circuit 131 calculates the exclusive OR of the signal sampled by the FF 121 in the latest sampling period and the signal sampled by the FF 121 in the sampling period one period before, for each FF 121. Then, the XOR circuit 131 outputs the calculated operation result to the population counter 132.

[0043] The population counter 132 receives an input of the calculation result for each FF 121 of the exclusive OR of the signal sampled by the FF 121 in the latest sampling period and the signal sampled by the FF 121 in the sampling period one period before from the XOR circuit 131. Then, the population counter 132 counts the number of 1s in the calculation results of the XOR circuit 131.

[0044] In other words, the population counter 132 finds the number of FFs 121 whose values ​​differ between the signal sampled in the latest sampling period and the signal sampled in the previous sampling period. That is, the number counted by the population counter 132 can be said to be the number of FFs 121 whose held signal value has transitioned, and corresponds to the number of inverter 111 stages whose output signal value has transitioned. Hereinafter, the number of inverter 111 stages whose output signal value has transitioned is referred to as the "transition stage number of inverters 111." Thereafter, the population counter 132 outputs the counted number to the difference calculation unit 14.

[0045] 4 is a diagram for explaining how to obtain the number of transition stages. Here, a case will be explained in which 15 inverters 111 and 15 FFs 121 and 122 are arranged. For example, at times T00 and T01, FF 121 holds a signal having a value shown in table 202. In this case, at the timing when the signal at time T01 is input from FF 121 to the XOR circuit 131, the signal at time 00 is input from FF 122 to the XOR circuit 131.

[0046] The calculation result by the XOR circuit 131 becomes the value shown in the bottom row of the table 202. In this case, the range 221 where the value is 1 corresponds to the FF 121 where the signal has changed, and the range 222 where the value is 0 corresponds to the FF 121 where the signal has not changed.

[0047] In this case, the population counter 132 counts the number of 1's as 12. That is, the number of FFs 121 whose signal values ​​have changed is 12, and it can be said that the outputs of 12 stages of the inverter 111 have transitioned.

[0048] Fig. 5 is a timing chart showing signal changes and sampling results. Graph 203 in Fig. 5 shows changes in the signal output from the inverter 111. Graph 204 shows the signal stored in FF 121. Graph 203 shows the passage of time on the horizontal axis and the inverters 111 at each stage on the vertical axis. Here, a case will be described in which nine inverters 111 are connected. Also, a case will be described in which numbers 0 to 8 shown on the left side of graph 203 are assigned to each inverter 111.

[0049] In graph 204, the horizontal axis represents the passage of time, and the vertical axis represents FFs 121 corresponding to each inverter. Each FF 121 stores an output signal from an inverter 111 that is assigned the same number as the number shown on the left side of graph 204. That is, FF 121 No. 0 stores an output signal from inverter 111 No. 0.

[0050] Time T in graph 203 represents the oscillation period. In graph 204, the position between a square with a vertically arranged diagonal line pattern and a square with a dot pattern indicates the position where the edge of the signal exists at that timing. One period in which the edge passes through the inverter 111 coincides with the oscillation period T.

[0051] For example, at time T02, each FF 121 holds the signal group 241. Moreover, at time T03, each FF 121 holds the signal group 241. For example, a case will be described where time T02 is the sampling timing and time T03 is the sampling timing in the next sampling period after time T02.

[0052] In this case, a signal group 241 is input from FF121 to the XOR circuit 131. Also, a signal group 242 is input from FF122 to the XOR circuit 131. In this case, the XOR circuit 131 outputs a numerical value group 243. The population counter 132 receives the numerical value group 243 and counts the number of 1's as five. That is, the number of stages of the inverters 111 whose outputs obtained from the counter of the population counter 132 have transitioned is five, which coincides with the number of inverters 111 whose edges have moved between time T02 and T03 in the graphs 203 and 204.

[0053] In this way, the number output from the population counter 132 can be the number of transition stages of the inverter 111 during a sampling period. The number output from the population counter 132 represents the oscillation frequency of the ROSC 101.

[0054] In summary, if a specific sampling period is defined as a specific period and the sampling period preceding the specific period is defined as a previous period, the transition stage counting mechanism 103 performs the following process: That is, the transition stage counting mechanism 103 counts the number of inverters 111 in the ring oscillator 101 from the inverter 111 whose output signal value last changed in the previous period to the inverter 111 whose output signal value last changed in the specific period, and sets this as the number of transition stages.

[0055] The difference calculation unit 14 calculates the difference between the reference frequency and the comparison frequency during the measurement period. The difference calculation unit 14 has a subtraction circuit 141 and an accumulator 142. The difference between the reference frequency and the comparison frequency indicates a difference due to a difference in the reference voltage, and the calculation of the difference between the reference frequency and the comparison frequency is an example of "voltage detection". The difference calculation unit 14 is an example of a "voltage detection unit".

[0056] The difference calculation unit 14 receives an input of the number of transition stages of the inverter 111 in a sampling period when the target voltage is input from the reference frequency generation circuit 11. The difference calculation unit 14 also receives an input of the number of transition stages of the inverter 111 in a sampling period when the output voltage from the PMOS header 40 is input from the comparison frequency generation circuit 12.

[0057] Next, the difference calculation unit 14 calculates a difference in the number of transition stages by subtracting the number of transition stages of the inverter 111 input from the comparison frequency generation circuit 12 from the number of transition stages of the inverter 111 input from the reference frequency generation circuit 11. Then, the difference calculation unit 14 outputs the calculated difference in the number of transition stages to the accumulator 142. The difference calculation unit 14 repeats the calculation of the difference in the number of transition stages during the measurement period, and outputs it to the accumulator 142 in sequence.

[0058] The accumulator 142 receives an input of the difference in the number of transition stages from the difference calculation unit 14. The accumulator 142 accumulates the differences in the number of transition stages and adds them all up until the end of the measurement period. Then, the accumulator 142 outputs the addition result to the LDO control logic circuit 30.

[0059] 6 is a diagram for explaining the absorption of errors in a voltage detection circuit according to an embodiment. For example, a case where the measurement period Tm is a period of four sampling periods will be explained. In this case, it is assumed that sampling is performed at timings 331 to 335 during the measurement period Tm.

[0060] Here, an error may occur at a point where the sampling frequency and the edge of the ring collide due to metastable state. In that case, the value of the output signal at that sampling time is determined probabilistically. For example, if an error occurs due to metastable state at timing 333, the error caused by the sampling at timing 333 is absorbed by the sampling at timing 334 with the remaining probability. Since the accumulator 142 sums up the difference of the measurement period Tm, for example, when the signal transitions to 1, the question is which cycle of the sampling at timing 333 or timing 334 should be counted as 1, and the error will eventually become invisible. That is, the error caused at timings 332 to 334 is hidden by the addition of the difference of the measurement period by the accumulator 142, so that the occurrence of the error is limited to the sampling at the start of the first stage and the sampling at the stop of the last stage. In this way, the voltage detection circuit 10 according to this embodiment can minimize the measurement error.

[0061] 7 is a flowchart of the voltage detection process. Next, the flow of the voltage detection process by the voltage detection circuit 10 according to the present embodiment will be described with reference to FIG.

[0062] The ROSC 101 of the reference frequency generation circuit 11 oscillates upon receiving a voltage input from the external power supply 2. The ROSC 101 of the comparison frequency generation circuit 12 oscillates upon receiving an output voltage input from the PMOS header 40. In both the reference frequency generation circuit 11 and the comparison frequency generation circuit 12, the sampling mechanism 102 uses FFs 121 and 122 to sample the internal state of the oscillating ROSC 101 at a sampling period determined by the system clock (step S1).

[0063] The XOR circuit 131 of the transition stage counting mechanism 103 receives the signals output from each inverter 111 from each of the FFs 121 and 122. Then, the XOR circuit 131 calculates the exclusive OR of the signal input from each FF 121 and the signal input from the corresponding FF 122. The population counter 132 counts the number of 1s in the results of the exclusive OR by the XOR circuit 131 to calculate the number of transition stages. As a result, the transition stage counting mechanism 103 calculates the number of transition stages from the difference between the sampling results whose sampling periods differ by one period (step S2).

[0064] The subtraction circuit 141 of the difference calculation unit 14 receives an input of the number of transition steps per sampling period from the reference frequency generation circuit 11 and the comparison frequency generation circuit 12. Then, the subtraction circuit 141 subtracts the number of transition steps input from the comparison frequency generation circuit 12 and the number of transition steps input from the reference frequency generation circuit 11 from the number of transition steps input from the reference frequency generation circuit 11 to calculate a difference in the number of transition steps per sampling period (step S3).

[0065] The accumulator 142 of the difference calculation unit 14 receives an input of the transition step number difference for each sampling period in the measurement period from the subtraction circuit 141. Then, the accumulator 142 adds up the transition step number difference for the measurement period (step S4).

[0066] The accumulator 142 outputs the sum of the transition step number differences for the measurement period to the LDO control logic circuit 30. The LDO control logic circuit 30 performs a logical operation using the sum of the transition step number differences for the measurement period to determine the on / off state of each PMOS transistor in the PMOS header 40. The LDO control logic circuit 30 then applies a voltage to each PMOS transistor according to the determined on / off state to control the voltage output to the controlled circuit 3 (step S5).

[0067] Thereafter, the voltage detection circuit 10 determines whether to stop the operation based on whether an instruction to power off the system has been received or not (step S6). If the operation is not to be stopped (step S6: No), the voltage detection circuit 10 returns to step S1. On the other hand, if the operation is to be stopped (step S6: Yes), the voltage detection circuit 10 ends the voltage detection process.

[0068] Fig. 8 is a flowchart of voltage control. Each process in the flow shown in Fig. 8 corresponds to an example of the process executed in step S5 in Fig. 7. Next, the flow of voltage control will be briefly described with reference to Fig. 8.

[0069] The voltage detection circuit 10 outputs the sum of the differences in the number of transition stages for the measurement period to the LDO control logic circuit 30 (step S11).

[0070] The LDO control logic circuit 30 receives an input of the sum of the differences in the number of transition stages for the measurement period from the voltage detection circuit 10. Next, the LDO control logic circuit 30 performs a regulator control calculation (step S12).

[0071] Thereafter, the LDO control logic circuit 30 determines the on / off state of each PMOS transistor in the PMOS header 40 so as to achieve the adjustment amount calculated by the regulator control calculation. Then, the LDO control logic circuit 30 applies a voltage to each PMOS transistor according to the determination. The output voltage of the PMOS header 40 changes as the LDO control logic circuit 30 controls the on / off state of each PMOS transistor (step S13).

[0072] Next, a specific example of regulator control calculation by the LDO control logic circuit 30 and voltage control based on the calculation result will be described. Here, we will explain the case where the difference is directly reflected in the number of PMOS transistors to be turned on. Here, the number of PMOS transistors that are turned on at the time of control is set to 50.

[0073] For example, the LDO control logic circuit 30 obtains 10 as the sum of the differences in the number of transition stages for the measurement period. In this case, since the number of transition stages of the inverter 111 input from the reference frequency generation circuit 11 is greater, it is considered that the output voltage from the PMOS header 40 is lower than the target voltage. Therefore, the LDO control logic circuit 30 decides to increase the number of PMOS transistors to be turned on in order to increase the output voltage from the PMOS header 40. Then, the LDO control logic circuit 30 adds 10, which is the sum of the differences in the number of transition stages, to the number of PMOS transistors currently turned on (50), to change the number of PMOS transistors to be turned on to 60. After that, the LDO control logic circuit 30 applies a voltage to each PMOS transistor in the PMOS header 40 so that the number of PMOS transistors to be turned on becomes 60.

[0074] Next, the LDO control logic circuit 30 obtains 5 as the sum of the differences in the number of transition stages for the measurement period. In this case, too, since the number of transition stages of the inverter 111 input from the reference frequency generation circuit 11 is greater, it is considered that the output voltage from the PMOS header 40 is lower than the target voltage. Therefore, the LDO control logic circuit 30 decides to increase the number of PMOS transistors to be turned on in order to increase the output voltage from the PMOS header 40. Then, the LDO control logic circuit 30 adds 5, which is the sum of the differences in the number of transition stages, to 60, which is the number of PMOS transistors currently turned on, to change the number of PMOS transistors to be turned on to 65. After that, the LDO control logic circuit 30 applies a voltage to each PMOS transistor in the PMOS header 40 so that the number of PMOS transistors to be turned on becomes 65.

[0075] Next, the LDO control logic circuit 30 obtains −2 as the sum of the differences in the number of transition stages for the measurement period. In this case, since the number of transition stages of the inverter 111 input from the comparison frequency generation circuit 12 is greater, it is considered that the output voltage from the PMOS header 40 is higher than the target voltage. Therefore, the LDO control logic circuit 30 decides to reduce the number of PMOS transistors to be turned on in order to lower the output voltage from the PMOS header 40. Then, the LDO control logic circuit 30 adds −2, which is the sum of the differences in the number of transition stages, to 65, which is the number of PMOS transistors currently turned on, to change the number of PMOS transistors to be turned on to 63. After that, the LDO control logic circuit 30 applies a voltage to each PMOS transistor in the PMOS header 40 so that the number of PMOS transistors to be turned on becomes 63.

[0076] The LDO control logic circuit 30 repeats the above process to continue control so that the difference between the number of transition stages of the reference frequency generation circuit 11 and the number of transition stages of the comparison frequency generation circuit 12 approaches 0. Fig. 9 is a diagram showing an example of a control result by voltage control using a voltage detection circuit according to an embodiment. The voltage convergence process in a simplified model will be described with reference to Fig. 9.

[0077] For simplicity, the control using the sum of the difference in the number of transition stages output from the voltage detection circuit 10 and the period of change in the output voltage are described as being the same as one measurement period. In addition, general I (Integral) control is executed as the voltage control for the PMOS header 40. Furthermore, although the voltage is usually changed by controlling the PMOS header 40 based on the calculation result by the LDO control logic circuit 30, here, the calculation result and the output voltage are assumed to be equal. Here, the difference between the output voltage of the PMOS header 40 and the target voltage multiplied by a coefficient is set as the difference of the detection circuit.

[0078] 9, the horizontal axis represents the measurement period, and the vertical axis represents the output voltage of the PMOS header 40. In period 303, the target voltage was set to 100V, and in the subsequent period 304, the target voltage was set to 80V.

[0079] In period 303, the target voltage is 100V, and as a result of the LDO control logic circuit 30 repeating voltage control, the output voltage of the PMOS header 40 approaches 100V, as shown by curve 301. When the target voltage subsequently changes to 80V, the LDO control logic circuit 30 repeats voltage control, causing the output voltage of the PMOS header 40 to transition from 100V to 80V, as shown by curve 302.

[0080] Here, the accuracy of voltage detection by the voltage detection circuit 10 according to the present embodiment will be described in comparison with the case where there is a time when voltage detection is disabled. FIG. 10 is a diagram for explaining the deterioration of detection accuracy when there is a time when voltage detection is disabled. In FIG. 10, the horizontal axis represents the passage of time, and the vertical axis represents voltage. FIG. 11 is a diagram showing the timing of sampling by the voltage detection circuit according to the embodiment. Graph 321 in FIG. 11 shows the system clock, graph 322 shows the sampling period according to the clock and the samples obtained by sampling, and graph 323 shows the difference between the sampling results shifted by one period. In graphs 321 to 323 in FIG. 11, time passes as it progresses to the right on the paper.

[0081] For example, when an inverter that is the starting point of the operation during measurement in ROSC is determined or when a counter is arranged corresponding to each inverter, resetting of ROSC and counter is performed. When such a reset operation is performed, for example, as shown in Fig. 10, the measurement period includes a measurement implementation period 311 and a reset period 312 before the measurement implementation period 311. Since the voltage detection process is not performed during this reset period 312, the measurement result of the voltage performed during the measurement period includes measurement errors 313 to 315.

[0082] In contrast, the voltage detection circuit 10 according to this embodiment, as shown in Fig. 11, continuously acquires samples in accordance with the system clock of the graph 312. The voltage detection circuit 10 does not acquire samples during any period of the measurement.

[0083] The voltage detection circuit 10 acquires samples Ts1 to Ts6 shown in graph 322 for each sample period. Then, the voltage detection circuit 10 calculates the difference between samples shifted by one period as shown in graph 323. For example, the voltage detection circuit 10 subtracts Ts0 from Ts1 to calculate difference 324, subtracts Ts1 from Ts2 to calculate difference 325, and repeats the calculation of differences thereafter. In this way, the voltage detection circuit 10 can continuously calculate differences during the measurement period without interruption.

[0084] Since the number of transition stages is obtained from the difference shown in graph 323, there is no period during which voltage detection is not performed in the voltage detection circuit 10. Therefore, the voltage detection circuit 10 can improve the detection accuracy of voltage detection compared to a case in which errors 313 to 315 shown in FIG. 10 do not occur and there is a period during which voltage detection is disabled.

[0085] 12 is a diagram showing an example of an information processing device using a voltage detection circuit according to an embodiment of the present invention. Next, with reference to FIG. 12, an example of an information processing device using a voltage detection circuit 10 will be described.

[0086] For example, the voltage detection circuit 10 can be used in an information processing device 90 shown in Fig. 12. The information processing device 90 has an external power supply 2, an LSI (Large Scale Integration) chip 91, a memory 92, a hard disk 93, and a network interface 94. The LSI 91 is connected to the memory 92, the hard disk 93, and the network interface 94 via a bus.

[0087] The network interface 94 is a communication interface between the information processing device 90 and external devices. The hard disk 93 stores various programs including an OS (Operating System) and the like.

[0088] The LSI chip 91 has a plurality of regulators 1A to 1C and cores 3A to 3C. The regulators 1A to 1C are arranged to correspond to the cores 3A to 3C, respectively. The regulators 1A to 1C can independently control the cores 3A to 3C, respectively. For example, the voltage supplied by the regulator 1A to the core 3A, the voltage supplied by the regulator 1B to the core 3B, and the voltage supplied by the regulator 1C to the core 3C can be made different from each other. Specifically, by making the target voltages of the regulators 1A to 1C different from each other, the voltages supplied to the cores 3A to 3C can be made different from each other.

[0089] When the computing power of the information processing device 90 is not being fully used, power saving can be achieved by reducing some of the processing of the cores 3A to 3C. For example, the computing power of the cores 3B to 3C can be fully used, while the frequency of the core 3A can be lowered to suppress the computing power. When the frequency is lowered to suppress the computing power, the operating voltage can be lowered. For example, the target voltage of the regulator 1A can be lowered to lower the operating voltage of the core 3A and operate it at a slower speed, while the target voltages of the regulators 1B to 1C can be maintained to operate the cores 3B to 3C normally with the operating voltage unchanged.

[0090] Conversely, it is also possible to increase the computing power by raising some of the operating voltages. For example, the target voltage of regulator 1A can be increased to raise the operating voltage of core 3A and operate it at high speed, while the target voltages of regulators 1B to 1C can be maintained and the operating voltages of cores 3B to 3C can be left unchanged to operate normally.

[0091] If the operating voltages of the cores 3A to 3C are not controlled individually, all the cores will operate at the same voltage, resulting in unnecessary voltage consumption. In contrast, by independently controlling the operating voltages of the cores 3A to 3C using the regulators 1A to 1C equipped with the voltage detection circuit 10 according to this embodiment, it is possible to suppress some of the voltages and achieve power saving.

[0092] As described above, the voltage detection circuit according to the present embodiment periodically samples the state of each inverter in the ROSC, compares the sampling results shifted by one cycle, and counts the number of transitions of each node.Then, using the number of transitions, it compares the target voltage with the output voltage to the controlled circuit to perform voltage detection.

[0093] The voltage detection circuit according to the present embodiment can continuously detect voltage without generating periods when voltage detection is not possible because it does not perform resetting, etc., and can suppress detection errors in voltage detection. In addition, it is not necessary to mount a counter for each ROSC, so the mounting area can be reduced. [Explanation of symbols]

[0094] 1. 1A~1C regulator 2 External power supply 3. Controlled circuit 3A~3C Core 10 Voltage detection circuit 11 Reference frequency generation circuit 12 Comparison frequency generation circuit 13 Oscillators 14 Difference calculation part 20 Target voltage output circuit 30 LDO control logic circuit 40 PMOS Header 90 Information processing equipment 91 LSI chip 92 Memory 93 Hard Disk 94 Network Interface 101 ROSC 102 Sampling mechanism 103 Transition step count mechanism 111 Inverter 121, 122 FF 131 XOR circuit 132 Population Counter 141 Subtraction Circuit 142 Accumulator

Claims

1. Two ring oscillators each having a plurality of inverters arranged in series in a ring shape; A sampling unit that acquires an output signal from each of the inverters at each sampling period; a transition stage number calculation unit that calculates a transition stage number, which is the number of inverters whose output signal value has transitioned during the sampling period for each of the ring oscillators, based on the output signal for each of the sampling periods acquired by the sampling unit; a voltage detection unit that performs voltage detection based on the number of transition stages acquired by the transition stage number calculation unit; A voltage detection circuit comprising:

2. The ring oscillator comprises: a first ring oscillator having a first inverter; a second ring oscillator having the same number of second inverters as the first inverters; The sampling unit includes: a first sampling mechanism that acquires a first output signal from the first inverter in the first ring oscillator to which a target voltage is input; a second sampling mechanism for acquiring a second output signal from the second inverter in a second ring oscillator to which a comparison voltage is input; The transition stage number calculation unit a first transition stage number counting mechanism that calculates a first transition stage number, which is the transition stage number of the first inverter, based on the first output signal; a second transition stage number counting mechanism that calculates a second transition stage number, which is the transition stage number of the second inverter, based on the second output signal; The voltage detection unit detects the comparison voltage by comparing the first transition stage number with the second transition stage number.

2. The voltage detection circuit according to claim 1 .

3. the sampling unit acquires a specific output signal of each of the inverters in a specific sampling period and a previous output signal of each of the inverters in a sampling period one period before the specific sampling period; The transition stage number calculation unit calculates the transition stage number by comparing the specific output signal with the previous output signal.

2. The voltage detection circuit according to claim 1 .

4. 4. The voltage detection circuit according to claim 3, wherein the transition stage calculation unit calculates the transition stage number by counting the number of inverters in the ring oscillator from the inverter whose output signal value last changed in the previous sampling period to the inverter whose output signal value last changed in the specific sampling period.

5. An information processing device having a voltage detection circuit, a voltage control circuit, and a processor, The voltage detection circuit includes: Two ring oscillators each having a plurality of inverters arranged in series in a ring shape; A sampling unit that acquires an output signal from each of the inverters at each sampling period; a transition stage number calculation unit that calculates a transition stage number, which is the number of inverters whose output signal value has transitioned during the sampling period for each of the ring oscillators, based on the output signal for each of the sampling periods acquired by the sampling unit; a voltage detection unit that performs voltage detection based on the number of transition stages acquired by the transition stage number calculation unit, the voltage control circuit controls a voltage output to the processor based on the voltage detected by the voltage detection circuit, and applies the voltage output to the processor to one of the ring oscillators; The processor operates by receiving an input of a voltage controlled by the voltage control circuit.

23. An information processing apparatus comprising:

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