Information processing apparatus, log storage method, and program

Abstract

To enable efficient use of a storage area for logs related to a process of initializing.SOLUTION: A BIOS 100 stored in a NVRAM 60 causes a CPU 10 to perform processes of initializing an information processing apparatus 1, detecting the occurrence of an error during the initialization, and acquiring logs of the operating status of the information processing apparatus 1 during the initialization. However, in the process of acquiring logs, if the occurrence of an error is detected, the log is acquired with a degree of detail corresponding to a level previously associated with the type of the error. A BMC 50 stores the logs acquired by the information processing apparatus 1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an information processing device, a log storage method, and a program. [Background technology]

[0002] There is known a technique for detecting a fault occurring in an information processing device by processing a basic input / output system (BIOS) (see, for example, Patent Documents 1 and 2).

[0003] For example, a technology of a fault information processing program for making a computer execute an acquisition step and a reduction step is known. The acquisition step is a step of acquiring first fault information about a fault that has occurred in the device itself, which is generated by the BIOS of the computer. The reduction step is a step of reducing the data amount of the first fault information to generate second fault information, which is fault information to be transmitted to a management device.

[0004] Also, a technology for an electronic device is known that includes a memory storing a BIOS program, an error information storage means, a notification method storage means, and a control means. The error information storage means stores types of errors that can be detected during a startup process by the BIOS program in association with the severity of the errors. The notification method storage means stores error notification methods in association with the severity. The control means executes the BIOS program at system startup, and if an error is detected, identifies the severity of the error from the error information storage means, and notifies the error using the notification method stored in the notification method storage means in association with the identified severity. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-160009 A [Patent Document 2] JP 2010-231381 A Summary of the Invention [Problem to be solved by the invention]

[0006] When saving logs about the processing status of the initialization process by the BIOS in an information processing device in a BMC (Baseboard Management Controller) of the information processing device, it is necessary to reduce the amount of output of the logs, because the data storage area of ​​the BMC available for such logs is small.

[0007] However, simply reducing the amount of log output may result in a situation where the log of information required to determine the cause of a failure that occurred during the initialization process is not saved.

[0008] In one aspect, the present invention aims to enable efficient use of storage areas for logs related to initialization processing. [Means for solving the problem]

[0009] In one proposal, an information processing device includes a processor, a storage unit in which a BIOS is stored, and a save unit. The BIOS causes the processor to perform a process of initializing the information processing device, a process of detecting an occurrence of an error in the initialization, and a process of acquiring a log of the operating status of the information processing device in the initialization. However, in the process of acquiring the log, if an occurrence of an error is detected, the log is acquired at a level of detail corresponding to a level previously associated with the type of the error. The save unit saves the log acquired by the processor. Effect of the Invention

[0010] According to one aspect, the area for storing logs relating to the initialization process can be used efficiently. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram illustrating an example of a hardware configuration of an information processing device. [Diagram 2] FIG. 2 is a diagram showing a first example of the configuration of each piece of software stored in an information processing device. [Diagram 3] FIG. 13 is a diagram showing a second example of the configuration of each piece of software stored in the information processing device. [Figure 4] 11 illustrates an example of a data structure of log level information. [Diagram 5] FIG. 11 illustrates an example of a data structure of memory error information. [Figure 6] 13 is a flowchart showing the processing contents of a start-up process. [Figure 7] 13 is a flowchart showing the contents of a memory training process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings.

[0013] [1: Hardware configuration example]

[0014] First, a description will be given of Fig. 1. Fig. 1 shows an example of the hardware configuration of an information processing device 1 according to an embodiment. This information processing device is, for example, a server device.

[0015] The information processing device 1 includes a CPU 10 as a processor. Note that "CPU" is an abbreviation for Central Processing Unit. In the following description, the CPU 10 may be written as "CPU(0)."

[0016] The information processing device 1 further includes eight DIMMs 20 as memory. Note that "DIMM" is an abbreviation for Dual Inline Memory Module.

[0017] The CPU(0) has two built-in memory controllers 11. Each memory controller 11 has two channels 30 for connecting two DIMMs 20, and the DIMMs 20 are connected to the CPU(0) via the memory controllers 11.

[0018] In the following description, when it is necessary to distinguish between the two memory controllers 11 built into the CPU(0), the two memory controllers 11 will be written as "MC(0)" and "MC(1)", respectively.

[0019] Furthermore, when distinguishing between the two channels 30 owned by MC(0), the two channels 30 will be written as "CH(00)" and "CH(01)," respectively. When distinguishing between the two channels 30 owned by MC(1), the two channels 30 will be written as "CH(10)" and "CH(11)," respectively.

[0020] Furthermore, when distinguishing between the eight DIMMs 20 included in the information processing device 1, the two DIMMs 20 connected to CH(00) will be written as "DIMM(000)" and "DIMM(001)", respectively. The two DIMMs 20 connected to CH(01) will be written as "DIMM(010)" and "DIMM(011)", respectively. The two DIMMs 20 connected to CH(10) will be written as "DIMM(100)" and "DIMM(101)", respectively. The two DIMMs 20 connected to CH(11) will be written as "DIMM(110)" and "DIMM(111)", respectively.

[0021] The information processing device 1 further includes an SB 40. The SB 40 is an integrated circuit called a south bridge, and is connected to the CPU (0). The SB 40 manages the transmission and reception of various types of data between the CPU (0) and various types of hardware included in the information processing device 1.

[0022] The information processing device 1 further includes a BMC 50 and a NVRAM 60.

[0023] The BMC 50 is an integrated circuit called a baseboard management controller, and is connected to the SB 40. The BMC 50 provides functions such as hardware monitoring and power supply control of the information processing device 1, independent of the CPU (0). The BMC 50 stores BMC-FW200, which is software, and the BMC 50 provides the functions by having a processor (not shown) that is provided in the BMC 50 execute the BMC-FW200. Note that "FW" is an abbreviation for Firmware.

[0024] The NVRAM 60 is a non-volatile random access memory, such as a flash memory. The NVRAM 60 is a storage unit in which the BIOS 100, which is software, is stored, and is connected to the SB 40.

[0025] The information processing device 1 has the above-mentioned hardware configuration. Note that the configuration shown in Fig. 1 is merely an example, and other configurations may be used. For example, the number of CPUs 10 included in the information processing device 1, the number of memory controllers 11 included in the CPUs 10, the number of channels 30 that the memory controllers 11 have, the number of DIMMs 20 connected to one channel 30, etc. may be different from the configuration in Fig. 1.

[0026] [2: First example of a method for acquiring and storing logs]

[0027] Next, a first example of a technique for acquiring and saving a log when the information processing device 1 in FIG. 1 is started will be described.

[0028] First, a description will be given of Fig. 2. Fig. 2 shows a first example of the configuration of each piece of software stored in the information processing device 1.

[0029] The BIOS 100 is executed by the CPU(0) when the information processing device 1 is powered on and power supply starts. The CPU(0) executes the BIOS 100 to perform a process of initializing the information processing device 1. Through this initialization process, the CPU(0) provides each function, such as a memory initialization unit 110, a memory error processing unit 120, and a log transmission unit 130.

[0030] The memory initialization unit 110 initializes the DIMM 20 and performs training on the DIMM 20. Training is a task of optimizing communication between the memory controller 11 and the DIMM 20 by adjusting various parameters related to the timing of inputting and outputting data to and from the DIMM 20 and the signal waveform of the data, which are set in the memory controller 11. The memory initialization unit 110 also acquires logs related to the execution of the above-mentioned initialization and training.

[0031] The memory error processor 120 acquires a log of an error that has occurred in the DIMM 20 .

[0032] The log transmission unit 130 transmits a log of the operating status of the information processing device 1, for example, a log of when a function such as the memory initialization unit 110 or the memory error processing unit 120 is executed, to the BMC 50. The log transmission unit 130 transmits the log to the BMC 50 using, for example, a universal asynchronous receiver / transmitter (UART) as a communication method.

[0033] As described above, the BMC-FW 200 is executed by the processor included in the BMC 50, and provides various functions such as the log receiving unit 210, for example.

[0034] The log receiving unit 210 receives logs sent from the CPU(0) that executes the BIOS 100, and stores the received logs as a plurality of log data 220 in a non-volatile storage area (not shown) that the BMC 50 has.

[0035] In the first configuration example shown in FIG. 2, the above-mentioned functions are provided by the respective software programs stored in the information processing device 1.

[0036] Next, a procedure for acquiring and saving a log in a first example of a method for acquiring and saving a log when the information processing device 1 in FIG. 1 is started will be described.

[0037] First, when the information processing device 1 is turned on and power supply starts, the CPU(0) reads the BIOS 100 from the NVRAM 60 and executes it, thereby starting a process of initializing the information processing device 1.

[0038] At this time, the memory initialization unit 110 initializes the DIMM 20 and also performs training on the DIMM 20. This training is performed for each memory controller 11, each channel 30, and each DIMM 20, and various parameters in each memory controller 11 are adjusted to appropriate values. In addition, the memory initialization unit 110 acquires a log related to the execution of the above-mentioned initialization and training.

[0039] The log acquired by the memory initialization unit 110 is stored in a non-volatile storage area of ​​the BMC 50. However, the amount of data that can be stored in this non-volatile storage area is small. For this reason, in this first example, the target of log acquisition by the memory initialization unit 110 is limited to information such as the names of the implementation items in training and the implementation results for each implementation item.

[0040] Incidentally, a memory error may occur in the DIMM 20 while the memory initialization unit 110 is performing initialization or training. When the memory error processing unit 120 detects the occurrence of this memory error, it acquires a log relating to the occurrence of the memory error.

[0041] 1, the memory controller 11 has an ECC (Error Checking and Correction) function for the data stored in the DIMM 20. That is, the memory controller 11 has a function for detecting errors (memory errors) in the data stored in the DIMM 20 and correcting the detected errors in the stored data when possible.

[0042] The memory error processing unit 120 detects the occurrence of a memory error in the DIMM 20 by monitoring the operation of the memory controller 11. Furthermore, when the memory error processing unit 120 detects the occurrence of a memory error, it acquires information indicating whether the memory error is a correctable error or an uncorrectable error from the memory controller 11 and includes the information in a log. In the following description, a correctable error is referred to as a "CE" (Correctable Error), and an uncorrectable error is referred to as an "UE" (Uncorrectable Error). CE and UE are examples of types of memory errors.

[0043] When the memory controller 11 detects the occurrence of a UE in the DIMM 20, the CPU(0) executing the BIOS 100 performs a process of degenerating the DIMM 20 so that the DIMM 20 is not used.

[0044] The logs acquired by the memory initialization unit 110 and the memory error processing unit 120 in the above manner are transmitted to the BMC 50 by the log transmission unit 130. In the BMC 50 in which the BMC-FW 200 is running, the transmitted logs are received by the log reception unit 210, and the logs are stored in the non-volatile storage area of ​​the BMC 50 as a plurality of log data 220. Note that the amount of log data 220 stored in the non-volatile storage area of ​​the BMC 50 is limited by the BMC-FW 200, and when the limit is exceeded, the oldest stored data is erased (the newest data is overwritten).

[0045] In the information processing device 1 of Fig. 1 in which each piece of software configured as in the first example shown in Fig. 2 is stored, the log is acquired and saved at startup in the above manner. The log data 220 saved in the BMC 50 in this manner is used for later analysis of the cause of a memory error that has occurred in the DIMM 20 and consideration of remedial measures.

[0046] [3: Second example of log acquisition and storage method]

[0047] Next, a second example of a method for acquiring and saving a log when the information processing device 1 in FIG. 1 is started will be described.

[0048] In the method of the first example described above, the memory initialization unit 110 acquires a log limited to information such as the results of initialization and training success or failure, etc. For this reason, the log data 220 stored in the BMC 50 lacks information useful for analyzing the cause of a memory error that has occurred in the DIMM 20, which may make the analysis difficult.

[0049] Therefore, in a second example described below, when an error is detected during the initialization process of the information processing device 1, the level of detail of the log that is limited to the information described in the first example is increased. However, the level of detail of the log at this time is set to a level of detail corresponding to a log level that is previously associated with the type of error, so that the log does not become excessively detailed when the severity of the error is low, enabling efficient use of the storage area for the log.

[0050] [3-1: Software configuration]

[0051] First, a description will be given of Fig. 3. Fig. 3 shows a second example of the configuration of each piece of software stored in the information processing device 1.

[0052] In the second configuration example shown in Fig. 3, components with the same names as those shown in the first configuration example shown in Fig. 2 are given the same reference numerals. The functions provided by these components shown in Fig. 3 include the functions provided by the components given the same reference numerals in Fig. 2. The description of these functions is omitted here.

[0053] In the second configuration example shown in Fig. 3, log level information 70 and memory error information 80 are added to the first configuration example shown in Fig. 2. It is shown that the log level information 70 and memory error information 80 are stored in the NVRAM 60 (see Fig. 1). Furthermore, the BIOS 100 further has the functions of an error severity determination unit 140 and a log level information management unit 150 in addition to the functions of a memory initialization unit 110, a memory error processing unit 120, and a log transmission unit 130. Furthermore, the function of a log control unit 111 is added to the memory initialization unit 110, and the function of an error information storage unit 121 is added to the memory error processing unit 120.

[0054] The error severity determination unit 140 creates the log level information 70 .

[0055] Here, the log level information 70 will be described. Fig. 4 shows an example of the data structure of the log level information 70. The log level information 70 is information in which "level" data is associated with each of the data "CPU", "MC", "CH", and "DIMM".

[0056] The information in each column of the log level information 70 shown as a table in FIG. 4 will be described.

[0057] The "No." column is a number assigned to identify each line of the log level information 70. The "Supplementary explanation" column provides supplementary explanations about the status of each line of the log level information 70. The "No." and "Supplementary explanation" data are information assigned for the sake of convenience in FIG. 4 and are not included in the log level information 70.

[0058] The "CPU" column contains information that identifies the CPU 10. The data "0" in this column identifies CPU(0).

[0059] The "MC" column contains information that identifies the memory controller 11. Data "0" and "1" in this column identify MC(0) and MC(1), respectively.

[0060] The "CH" column contains information for identifying channel 30. The data "00", "01", "10", and "11" in this column identify CH(00), CH(01), CH(10), and CH(11), respectively.

[0061] The "DIMM" column contains information that identifies the DIMM 20. The data "000," "001," "010," and "011" in this column identify DIMM(000), DIMM(001), DIMM(010), and DIMM(011), respectively. Also, the data "100," "101," "110," and "111" in this column identify DIMM(100), DIMM(101), DIMM(110), and DIMM(111), respectively.

[0062] The above "CPU", "MC", "CH", and "DIMM" data identify a target point in the information processing device 1, that is, a position on the information processing device 1 where a log of the memory operation of the DIMM 20 is to be acquired.

[0063] The "level" column contains information about the log level when acquiring logs for target points identified by the data for "CPU", "MC", "CH", and "DIMM". The log level is information that indicates the level of detail of the acquired log.

[0064] In this embodiment, four log levels are defined, from "0" to "3."

[0065] A log level of "0" means that no logging will be performed.

[0066] A log level of "1" indicates the acquisition of a log with the same level of detail as the log acquired in the first example of the log acquisition and storage method described above, i.e., the acquisition of a log limited to information such as the names of the training items and the results of each item.

[0067] Log level "2" represents acquisition of a log with a higher level of detail than the log acquired at log level "1." In this embodiment, log level "2" represents acquisition of a log of more detailed information regarding the execution of training for the DIMM 20 identified at the target point, in addition to the log acquired at log level "1." Note that the more detailed information is, for example, information such as each parameter value at the time of execution for each implementation item in the training and the implementation result for each parameter value.

[0068] Log level "3" indicates acquisition of a log with a higher level of detail than the log acquired at log level "2". That is, log level "3" indicates acquisition of a log of more detailed information at the target point in addition to the logs acquired at log levels "1" and "2". The more detailed information is, for example, information such as a dump of the SPD of the DIMM 20 identified at the target point, or a dump of the registers provided in the memory controller 11 identified at the target point. Note that "SPD" is an abbreviation for Serial Presence Detect.

[0069] 4 has the above-described data structure. The error severity determination unit 140 determines the severity of the error whose occurrence has been detected by referring to the memory error information 80, and creates the log level information 70 according to the severity.

[0070] Here, the memory error information 80 will be described. Fig. 5 shows an example of the data structure of the memory error information 80. The memory error information 80 is information in which each piece of data, "CPU", "MC", "CH", and "DIMM", is associated with each piece of data, "CE count", "UE count", and "UE occurrence time".

[0071] The information in each column of the memory error information 80 shown as a table in FIG. 5 will be described.

[0072] Note that the “No.” column is a number assigned to identify each row of the memory error information 80, and is information assigned for convenience in FIG. 5 and is not included in the memory error information 80.

[0073] The columns "CPU", "MC", "CH", and "DIMM" contain the same data as the columns "CPU", "MC", "CH", and "DIMM" in the log level information 70 illustrated in Fig. 4. The data in the columns "CPU", "MC", "CH", and "DIMM" identifies the point at which the occurrence of a memory error was detected.

[0074] "CE count" is data on the number of times a CE occurred that was detected in DIMM 20, and the "CE count" data is arranged in correspondence with each of the "CPU", "MC", "CH", and "DIMM" data that identify the target point where the occurrence of a CE was detected.

[0075] "UE count" is data on the number of times a UE occurred that was detected in DIMM 20, and the "UE count" data is arranged in correspondence with each of the "CPU", "MC", "CH", and "DIMM" data that identify the target point where the occurrence of a UE was detected.

[0076] "UE occurrence time" is data indicating the time when a UE detected in DIMM 20 occurred, and the data of "UE occurrence time" is arranged in association with each of the data of "CPU", "MC", "CH", and "DIMM" which specify the target point where the occurrence of the UE was detected. In this embodiment, as the data indicating this time, the data of the value of a TSC (Time Stamp Counter), which is a counter built into CPU(0) and which counts the number of clocks supplied to CPU(0) from the start of operation of CPU(0), is used.

[0077] 5 has the above-mentioned data structure. This memory error information 80 is created by the error information storage unit 121.

[0078] When the memory error processing unit 120 detects the occurrence of a memory error in the DIMM 20, it causes the error information storage unit 121 to function and create and store memory error information 80. Based on information obtained from the CPU(0) incorporating the memory controller 11, the error information storage unit 121 creates memory error information 80 regarding the memory error detected by the memory error processing unit 120, and stores and stores it in the NVRAM 60.

[0079] The error severity determination unit 140 refers to the memory error information 80 stored in the NVRAM 60, and determines the log level for the memory error based on the "CE count" and "UE count" for the memory error that has been detected to have occurred, and creates log level information 70.

[0080] The log level information management unit 150 stores the log level information 70 created by the error severity determination unit 140 in the NVRAM 60 and manages the NVRAM 60 .

[0081] The log control unit 111 acquires a log for a target point indicated in the log level information 70 stored in the NVRAM 60, with a level of detail corresponding to the log level associated with the target point in the log level information 70. The log acquired by the log control unit 111 is also transmitted to the BMC 50 by the log transmission unit 130.

[0082] In BMC 50, the log sent from CPU(0) executing BIOS 100 is received and stored as multiple log data 220 in a non-volatile storage area (not shown) provided in BMC 50, similar to the first example of the method of acquiring and storing logs described above.

[0083] In the second example of the method for acquiring and saving a log when the information processing device 1 is started up, the log is acquired and saved as described above.

[0084] [3-2: Method for determining log level]

[0085] Next, an example of a method for determining a log level by the error severity determining unit 140 will be described.

[0086] When the memory error detected in the memory operation of the DIMM 20 is a CE, the error severity determination unit 140 determines the log level of the target point for the DIMM 20 where the CE was detected to be "2." When the memory error detected in the memory operation of the DIMM 20 is a UE, which is a more serious error than a CE, the error severity determination unit 140 determines the log level of the target point for the DIMM 20 where the UE was detected to be "3." In this way, when a memory error in the DIMM 20 is detected, the error severity determination unit 140 determines the log level, which is previously associated with the type of error detected, for the target point for the DIMM 20 where the error was detected.

[0087] The error severity determining unit 140 determines the log level to be "1" for the target point of the DIMM 20 in which the occurrence of a memory error has not been detected.

[0088] However, when memory errors are detected in multiple DIMMs 20 of the information processing device 1, acquiring logs at the log level according to the above-mentioned method may result in an excessive total amount of logs, making it impossible to store all the logs in the non-volatile storage area of ​​the BMC 50. Therefore, in order to prevent such a situation from occurring, the error severity determination unit 140 determines the log level according to the rules described below.

[0089] First, for log levels "2" and "3" which will acquire logs with a relatively high level of detail, the number of target points (the number of occurrences of errors) that the error severity determination unit 140 can determine as the log level is limited. In this embodiment, the target point that can be determined as log level "3" is limited to only one location in the information processing device 1, and the target point that can be determined as log level "2" is limited to any three locations in the information processing device 1.

[0090] Here, if the number of target points that can be determined to be log level "3" or log level "2" exceeds the above-mentioned limit number, the association between the error type and the level is changed.

[0091] First, when a CE is detected in multiple DIMMs 20 of the information processing device 1, the error severity determination unit 140 selects target points for which log level "2" is to be determined based on the "CE count" data in the memory error information 80. In this embodiment, among the target points for each of the multiple DIMMs 20 for which a CE has been detected, the target points for which log level "2" is to be determined are selected in descending order of "CE count". If the number of target points for which log level "2" is to be determined as a result of this selection in descending order of "CE count" exceeds the above-mentioned limit, the log level "1" is determined for the target points exceeding the limit.

[0092] Furthermore, when a UE is detected in multiple DIMMs 20 of the information processing device 1, the error severity determination unit 140 determines, based on the data of "UE occurrence time" in the memory error information 80, that only the target points for the DIMM 20 where the UE occurred first are to be set to log level "3." Here, for the target points for the DIMM 20 where the UE did not occur first, the error severity determination unit 140 selects target points for which log level "2" is to be set in the order in which the UE occurred. However, if the number of target points for which log level "2" is to be set exceeds the above-mentioned limit as a result of this selection of the order in which the UE occurred, the error severity determination unit 140 determines the log level to be "1" for the target points that exceed the limit.

[0093] Furthermore, when detection of memory error occurrences in the DIMM 20 is concentrated in only a specific memory controller 11, the error severity determination unit 140 determines the target points for the remaining memory controllers 11 in which no error occurrences are detected to be at log level "0." In other words, the target points for the remaining memory controllers 11 in which no error occurrences are detected are determined to have a low priority for log acquisition, and log acquisition is not performed, thereby reducing the total amount of logs.

[0094] The error severity determination unit 140 determines the log level according to the rules described above, and creates log level information 70 by associating information on the determined log level with information on the target point at which the occurrence of a memory error was detected during memory operation.

[0095] The error severity determination unit 140 may determine the log level according to a further rule. For example, if all memory errors detected in multiple DIMMs 20 are CEs, the error severity determination unit 140 may determine the log level to be "3" for the DIMM 20 with the highest "CE count" in the memory error information 80 among the target points in which CEs are detected. This further rule is not adopted in this embodiment.

[0096] [3-3: Startup processing]

[0097] Next, a description will be given of the startup process performed by the CPU(0) when the information processing device 1 is started. Fig. 6 is a flowchart showing the processing contents of the startup process, which is for realizing the acquisition and storage of logs in the information processing device 1 according to the second example of the above-mentioned method of acquiring and storing logs.

[0098] The BIOS 100 includes a startup processing program that causes the CPU(0) to perform the processing shown in the flowchart of Fig. 6. When the information processing device 1 is turned on and power supply starts, the CPU(0) starts up, reads and executes the BIOS 100 from the NVRAM 60, and starts the processing for initializing the information processing device 1. Then, the startup processing of Fig. 6 starts.

[0099] 6, the processes of S101 and S102 are processes that provide the function of the error severity determination unit 140. That is, in S101, a process is performed in which the memory error information 80 and the log level information 70 are read and acquired from the NVRAM 60. Then, in the following S102, a process is performed in which the log level information 70 acquired in the process of S101 is updated by the memory error information 80 acquired in the process of S101, and the memory error information 80 is initialized.

[0100] In updating the log level information 70, the error severity determination unit 140 creates the log level information 70 based on the memory error information 80 as described above. Then, the log level information management unit 150 replaces the log level information 70 stored in the NVRAM 60 with the created log level information 70.

[0101] Moreover, when the memory error information 80 is initialized, the data for the "CE count", "UE count", and "UE occurrence time" are all set to "0" for all target points.

[0102] Following S102, memory training processing is performed in S103. The memory training processing is processing in which the memory initialization unit 110 executes initialization of the DIMM 20 and training for the DIMM 20, and acquires a log related to the training at a level of detail according to the log level information 70. Also, in the memory training processing, the memory error processing unit 120 monitors the DIMM 20 in which the training is being performed, detects the occurrence of a memory error, and creates memory error information 80 related to the memory error. Details of this memory training processing will be described later.

[0103] The processes from S104 to S110 following S103 are processes that provide the function of the memory error processing unit 120.

[0104] First, in S104, a process is performed to determine whether or not a memory error has been detected by checking whether the memory error information 80 has been updated in the memory training process in S103. If it is determined in this process that a memory error has been detected (if the determination result is YES), the process proceeds to S105. On the other hand, if it is determined in this process that a memory error has not been detected (if the determination result is NO), the startup process is terminated.

[0105] In S105, the memory error information 80 is referenced to determine whether or not the memory errors detected in the memory training process in S103 include a UE. If it is determined in this determination process that a UE has been detected (if the determination result is YES), the process proceeds to S106. On the other hand, if it is determined in this determination process that a memory error has not been detected (if the determination result is NO), the process proceeds to S108.

[0106] In S106, a process is performed to determine whether or not a log with a high level of detail at log level "3" has already been acquired at the target point for the DIMM 20 where the occurrence of a UE has been detected.

[0107] Although details will be described later, in the memory training process of S103, a log is acquired at the log level after the log level information 70 has been updated by the most recent process of S102, and the memory training process does not include a process of updating the log level information 70. Therefore, the determination process of S106 may refer to the log level information 70 stored in the NVRAM 60 at the time of this process, and determine whether the target point for the DIMM 20 in which the occurrence of a UE was detected is set to log level "3."

[0108] In the determination process of S106, if it is determined that a log with a high level of detail at log level "3" has been acquired at the target point for the DIMM 20 where the occurrence of a UE was detected (if the determination result is YES), the process proceeds to S107. On the other hand, in the determination process of S106, if it is determined that a log with such a high level of detail has not been acquired (if the determination result is NO), the process proceeds to S110.

[0109] In S107, a process is performed to degrade and not use the DIMM 20 for the target point where the occurrence of a UE has been detected and a highly detailed log has been obtained at log level "3", and then the process proceeds to S110.

[0110] In S108, a process is performed to determine whether or not any of the target points for the DIMM 20 in which the occurrence of a memory error was detected in the memory training process in S103 remains without detailed log acquisition. Those for which detailed log acquisition has not been performed are those with log level "0" or those with log level "1" in which the number of target points does not exceed the limit number for log level "2". In this determination process, when it is determined that there is any of the target points for the DIMM 20 in which the occurrence of a memory error was detected without detailed log acquisition (when the determination result is YES), the process proceeds to S109. On the other hand, in this determination process, when it is determined that there is no of the target points for the DIMM 20 in which the occurrence of a memory error was detected without detailed log acquisition (when the determination result is NO), the startup process is terminated.

[0111] In S109, a process is performed to determine whether the count value of the device restart counter has exceeded a predetermined specified value. In this process, if it is determined that the count value has exceeded the specified value (if the determination result is YES), the startup process is terminated. On the other hand, in this process, if it is determined that the count value has not yet exceeded the specified value (if the determination result is NO), the process proceeds to S110.

[0112] Here, the device restart counter will be described.

[0113] Each time the information processing device 1 is restarted, the occurrence of a CE may be detected in a different DIMM 20, or in a different memory area of ​​the same DIMM 20. The device restart counter is intended to eliminate repeated restarts of the information processing device 1 that may occur in such cases, and is a counter that counts the number of restarts of the information processing device 1. The count value of the device restart counter is reset when the information processing device 1 is started up for the first time.

[0114] In S110, the count value of the device restart counter is incremented by one, and a process of restarting the information processing device 1 is performed. This process causes the CPU(0) to execute the BIOS 100 again to start the process of initializing the information processing device 1, and execute the process of Fig. 6 again from S101. However, this restart does not initialize the log level information 70 and memory error information 80 stored in the NVRAM 60. Therefore, when the process of Fig. 6 is executed again, the log level information 70 and memory error information 80 stored in the NVRAM 60 at the time of the process of S110 are used.

[0115] The above processing is the startup processing.

[0116] [3-4: Memory training process]

[0117] Next, a description will be given of the details of the memory training process, which is the process of S103 in the above-mentioned startup process of Fig. 6. Fig. 7 is a flowchart showing the process contents of the memory training process.

[0118] 7 is a process that is started by the CPU(0) in parallel with the initialization process of the DIMM 20 by the memory initialization unit 110 and the start of the execution of training for the DIMM 20. In the process of FIG. 7, the processes from S201 to S206 are repeatedly executed until the result of the determination process of S207 becomes YES.

[0119] 7 is started, first, in S201, a process is performed in which a log at a target point for the DIMM 20 where initialization and training are being performed is acquired with a level of detail according to the log level for the target point, and output to the BMC 50. The log level for the target point is indicated by the log level information 70 stored in the NVRAM 60. This process provides a function for acquiring logs by the log control unit 111 and the memory error processing unit 120.

[0120] The log output to the BMC 50 by the S201 process includes information identifying the position of the target point in the information processing device 1. Therefore, when the occurrence of a memory error is detected, a log including information identifying the position of the target point where the occurrence of the memory error was detected is acquired with a level of detail according to the log level for the target point and output to the BMC 50. The output log is stored as log data 220 in the BMC 50.

[0121] Next, in S202, a process is performed to determine whether or not a memory error has occurred in the memory area of ​​the DIMM 20 for which initialization and training are being performed. This process provides the function of the memory error processing unit 120.

[0122] In the judgment process of S202, if it is determined that a memory error has been detected (if the judgment result is YES), the process proceeds to S203, and if it is determined that a memory error has not been detected (if the judgment result is NO), the process proceeds to S207.

[0123] The processing from S203 to S206 is processing that provides the function of the error information storage unit 121 of the memory error processing unit 120.

[0124] First, in S203, a process is performed to update the memory error information 80 of the target point for the DIMM 20 in which the occurrence of a memory error was detected, which is stored in the NVRAM 60. In this process, if the memory error determined to have occurred by the process of S202 is a CE, a process is performed to increment (increase by 1) the value of the "CE count" for the target point in the memory error information 80. Also, if the memory error determined to have occurred by the process of S202 is a UE, a process is performed to increment (increase by 1) the value of the "UE count" for the target point in the memory error information 80.

[0125] Next, in S204, a process is performed to determine whether or not the memory error whose occurrence was detected in the process of S202 is a UE. In this determination process, when it is determined that the memory error is a UE (when the determination result is YES), the process proceeds to S205, and a process is performed to determine whether or not the UE has occurred for the first time in the DIMM 20 in which the occurrence of the UE was detected.

[0126] In the determination process of S205, when it is determined that the occurrence of a UE in the DIMM 20 in which the occurrence of a UE was detected is the first time (when the determination result is YES), the process proceeds to S206. Then, in S206, a process is performed to update the memory error information 80 of the target point for the DIMM 20 in which the occurrence of a UE was detected, which is stored in the NVRAM 60. In this process, a process is performed to substitute the value of the occurrence time of the UE determined to have been detected in the process of S202 as the "UE occurrence time" for the target point in the memory error information 80. As described above, for example, the value of the TSC in CPU(0) when the occurrence of the first UE was detected is used as this value.

[0127] When the process of S206 described above is completed, the process proceeds to S207. Also, when the result of the determination process of either S204 or S205 is NO, the process proceeds to S207.

[0128] In S207, a process is performed to determine whether the initialization and training by the memory initialization unit 110 has been performed on all memory areas of all DIMMs 20 included in the information processing device 1. This process provides the function of the memory error processing unit 120.

[0129] When it is determined in the determination process of S207 that the initialization and training have been completed for all memory areas (when the determination result is YES), the process of Fig. 7 is terminated. On the other hand, when it is determined in the determination process that there are memory areas remaining for which the initialization and training have not been performed (when the determination result is NO), the process returns to S201, and the above-mentioned processes from S201 onwards are performed again.

[0130] The above-mentioned processing is the memory training processing.

[0131] In a second example of a method for acquiring and saving a log when the information processing device 1 in FIG. 1 starts up, the CPU(0) performs the processes shown in FIGS. 6 and 7, thereby acquiring and saving the log.

[0132] [3-5: Example]

[0133] Next, a specific embodiment in which logs are acquired and stored according to the processes shown in FIGS. 6 and 7 will be described.

[0134] The information processing device 1 according to this embodiment has the hardware configuration shown in FIG. 1, and each piece of software stored in the information processing device 1 complies with the second example configuration shown in FIG.

[0135] In this embodiment, the log level information 70 stored in the NVRAM 60 is set to a log level of "1" as an initial state for all of No. 1 to No. 8 in the table shown in Fig. 4. Furthermore, the memory error information 80 stored in the NVRAM 60 is set to "0" as an initial state for all of No. 1 to No. 8 in the table shown in Fig. 5.

[0136] [3-5-1: First startup process]

[0137] When the information processing device 1 is turned on and power supply starts, the CPU(0) starts up and reads and executes the BIOS 100 from the NVRAM 60. Then, the CPU(0) starts the process of initializing the information processing device 1, and starts the start-up process (first start-up process) of FIG.

[0138] At this time, the memory error information 80 and the log level information 70 are acquired from the NVRAM 60 by the process of S101. Note that the memory error information 80 and the log level information 70 stored in the NVRAM 60 at this time are both data in the initial state described above.

[0139] In the next process of S102, the log level information 70 is updated based on the memory error information 80 and the memory error information 80 is initialized. However, since the memory error information 80 at this time is information in the initial state as described above and is information in a state in which the occurrence of a memory error has not been detected, the log level information 70 is not updated. In other words, in this process, the data in the initial state is maintained as is. Furthermore, the memory error information 80 after initialization by this process is the same as the data in the initial state.

[0140] Next, the memory training process in S103 starts the initialization and training of the DIMM 20 by the memory initialization unit 110, and in parallel, the process in FIG. 7 starts.

[0141] 7 is started, first, in the process of S201, a log at a target point for the DIMM 20 where initialization and training are being performed is acquired at a level of detail corresponding to the log level of the target point, and output to the BMC 50. At this time, the log level information 70 stored in the NVRAM 60 maintains the initial state data, and is set to log level "1" for all target points. Therefore, in the process of S201 at this time, a log is acquired at the target point for the DIMM 20 where initialization and training are being performed, at the level of detail of the log level "1" as described above.

[0142] This process is followed by a judgment process in S202 to judge whether or not a memory error has been detected in the memory area of ​​the DIMM 20 where initialization and training are being performed. Here, it is assumed that no memory error has occurred at this time. Therefore, as a result of this judgment process, the process proceeds to S207.

[0143] Then, the determination process of S207 determines whether or not the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1. Here, it is assumed that there are memory areas remaining at this time that have not been initialized or trained. Therefore, as a result of this determination process, the process returns to S201, and thereafter, each process of S201, S202, and S207 is repeated for a while in that order.

[0144] Then, suppose that a CE occurs in the DIMM 20 for which initialization and training are being performed. Then, in the determination process of S202 during the repetition of each process described above, it is determined that a memory error has been detected, and the process proceeds to S203. It is assumed that the target point for the DIMM 20 where the CE occurred is the target point identified by CPU(0), MC(0), CH(01), and DIMM(011).

[0145] At this time, the process of S203 updates the memory error information 80 of the target point for the DIMM 20 in which the occurrence of the memory error was detected, which is stored in the NVRAM 60. This update changes the data of "CE count" in the row of the target point identified by CPU(0), MC(0), CH(01), and DIMM(011) in the table shown in Fig. 5, i.e., in row No. 4, from the initial value "0" to "1."

[0146] Thereafter, in the determination process of S204, it is determined that the memory error determined to have occurred in the process of S202 is not a UE (is a CE), and the process proceeds to S207.

[0147] Then, the determination process of S207 determines whether the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1. Here, it is assumed that there are still memory areas left at this time that have not been initialized or trained. Therefore, as a result of this determination process, the process returns to S201, and thereafter, each process of S201, S202, and S207 is repeated for a while in that order.

[0148] Thereafter, it is assumed that a new CE occurs in the DIMM 20 for which initialization and training are being performed. Then, in the determination process of S202 during the repetition of each process described above, it is determined that the occurrence of a memory error has been detected, and the process proceeds to S203. Note that the target point for the DIMM 20 in which the occurrence of this new CE was detected is the target point identified by CPU(0), MC(0), CH(01), and DIMM(011). In other words, it is assumed that the target point for the DIMM 20 in which the occurrence of the new CE was detected is the same as the target point for the DIMM 20 in which the occurrence of the CE was previously detected.

[0149] At this time, the processing of S203 updates the memory error information 80 of the target point for the DIMM 20 in which the occurrence of the memory error was detected, which is stored in the NVRAM 60. This update changes the data of "CE count" in the row of the target point identified by CPU(0), MC(0), CH(01), and DIMM(011) in the table shown in FIG. 5, i.e., in row No. 4, from "1" to "2."

[0150] Thereafter, in the determination process of S204, it is determined that the memory error whose occurrence was determined to have been detected in the process of S202 is not a UE (it is a CE), and the process proceeds to S207.

[0151] Then, the determination process of S207 determines whether the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1. Here again, it is assumed that there are still memory areas left at this time for which the initialization and training have not been performed. Therefore, as a result of this determination process, the process returns to S201, and thereafter, each process of S201, S202, and S207 is repeated for a while in that order.

[0152] After that, suppose that a UE occurs in the DIMM 20 for which initialization and training are being performed. Then, in the determination process of S202 during the repetition of each process described above, it is determined that a memory error has been detected, and the process proceeds to S203. Note that the target point for the DIMM 20 where the UE was detected is the target point identified by CPU(0), MC(0), CH(00), and DIMM(001).

[0153] At this time, the process of S203 updates the memory error information 80 of the target point for the DIMM 20 in which the occurrence of the memory error was detected, which is stored in the NVRAM 60. In this update, the data of "UE count" in the row of the target point identified by CPU(0), MC(0), CH(00), and DIMM(001) in the table shown in Fig. 5, i.e., in row No. 2, is changed from the initial value "0" to "1."

[0154] Thereafter, the determination process of S204 determines that the memory error determined to have occurred in the process of S202 is now a UE, and the process proceeds to S205. Then, the determination process of S205 determines that the UE has occurred for the first time in the DIMM 20 in which the UE occurrence was detected, and the process proceeds to S206.

[0155] At this time, the memory error information 80 of the target point for the DIMM 20 where the occurrence of a UE was detected, which is stored in the NVRAM 60, is updated by the process of S206. In this update, the value of the occurrence time of the UE whose occurrence was determined to have been detected by the process of S202 is substituted for the data of "UE occurrence time" in the row of No. 2 of the table shown in Fig. 5. In this embodiment, it is assumed that "12300000" is substituted for this data of "UE occurrence time".

[0156] Thereafter, it is determined by the determination process of S207 whether the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1. Here, too, it is assumed that there are still memory areas left that have not been initialized and trained at this time. Therefore, as a result of this determination process, the process returns to S201, and thereafter, each process is repeated for a while in the order of S201, S202, and S207. In the repetition of each process, it is assumed that the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1 without detecting the occurrence of a memory error. Then, the result of the determination process of S207 becomes YES, and the process of FIG. 7 ends.

[0157] The data example of the memory error information 80 shown in FIG. 5 is stored in the NVRAM 60 at the end of the memory training process in FIG.

[0158] When the memory training process ends, the process returns to S104 in the startup process of Fig. 6. At this time, the determination process of S104 determines that the occurrence of a memory error has been detected, and the process proceeds to S105. Then, the determination process of S105 determines that the memory errors detected in the memory training process of S103 included a UE, and the process proceeds to S106.

[0159] At this time, in the determination process of S106, it is determined that a highly detailed log at log level "3" has not been acquired at the target point for the DIMM 20 where the occurrence of a UE was detected, and the process proceeds to S110.

[0160] Then, by the process of S110 at this time, the count value of the device restart counter is incremented from "0" to "1" and the information processing device 1 is restarted. Then, the CPU(0) starts the process of initializing the information processing device 1 and restarts the start-up process of FIG. 6.

[0161] [3-5-2: Second startup process]

[0162] When the second startup process is started, first, the memory error information 80 and the log level information 70 are acquired from the NVRAM 60 by the process of S101. Note that the log level information 70 stored in the NVRAM 60 at this time remains as the initial state data, but the memory error information 80 stored in the NVRAM 60 at this time is the data exemplified in FIG.

[0163] In the subsequent process of S102, the log level information 70 is updated based on the memory error information 80, and the memory error information 80 is initialized.

[0164] When updating the log level information 70, the error severity determination unit 140 determines the log level in accordance with the rules described above. As described above, the memory error information 80 at this time is the data exemplified in Fig. 5. The rules described above are applied to this data.

[0165] The data example in FIG. 5 shows the occurrence of a UE in the DIMM 20 for the target point shown in row No. 2, and the occurrence of a CE in the DIMM 20 for the target point shown in row No. 4. Therefore, according to the above-mentioned rule, the log level is determined to be "3" for the target point shown in row No. 2, and the log level is determined to be "2" for the target point shown in row No. 4. Note that, as a result of this determination, there is only one target point determined to be at log level "3," and there is also only one target point determined to be at log level "2," and the number of target points in both cases falls within the range of the above-mentioned limit number.

[0166] By the way, referring to the data example in Figure 5, it can be seen that the memory errors that have been detected are concentrated in MC(0), and no memory errors have been detected in MC(1). Therefore, according to the above-mentioned rule, it is decided to set the log level to "0" for each of the target points No. 5 to No. 8, which are the target points for MC(1).

[0167] The log level information 70 after updating according to the result of the log level determination described above is the example data shown in Fig. 4. Furthermore, by initializing the memory error information 80, the data for "CE count", "UE count", and "UE occurrence time" are all set to "0" for all of No. 1 to No. 8 in the table shown in Fig. 5.

[0168] Next, the memory training process of S103 starts the execution of initialization and training for the DIMM 20 by the memory initialization unit 110, and in parallel, the process of FIG. 7 starts.

[0169] When the process of FIG. 7 is started, first, in the process of S201, a log is acquired at a target point for the DIMM 20 where initialization and training are being performed, and output to the BMC 50. This log is acquired at a level of detail corresponding to the log level for the target point, which is shown in the data example of the log level information 70 shown in FIG. 4. Therefore, at the target point shown in the row No. 2 of FIG. 4, a log is acquired at a level of detail of the log level "3" as described above. Also, at the target point shown in the row No. 4 of FIG. 4, a log is acquired at a level of detail of the log level "2" as described above. Then, at the target points shown in the rows No. 1 and No. 3 of FIG. 4, a log is acquired at a level of detail of the log level "1" as described above. On the other hand, at each of the target points No. 5 to No. 8 of FIG. 4, the log level is set to "0", so no log is acquired.

[0170] This process is followed by a judgment process in S202 to judge whether or not a memory error has been detected in the memory area of ​​the DIMM 20 where initialization and training are being performed. Here, it is assumed that no memory error has occurred at this time. Therefore, as a result of this judgment process, the process proceeds to S207.

[0171] Then, the determination process of S207 determines whether or not the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1. Here, it is assumed that there are memory areas remaining at this time that have not been initialized or trained. Therefore, as a result of this determination process, the process returns to S201, and thereafter, each process of S201, S202, and S207 is repeated for a while in that order.

[0172] Then, suppose that a UE occurs in the DIMM 20 for which initialization and training are being performed. Then, in the determination process of S202 during the repetition of each process described above, it is determined that a memory error has been detected, and the process proceeds to S203. Note that the target point for the DIMM 20 where the UE occurred is the same as the target point in the first startup process, that is, the target point identified by CPU(0), MC(0), CH(00), and DIMM(001).

[0173] At this time, the process of S203 updates the memory error information 80 of the target point for the DIMM 20 in which the occurrence of the memory error was detected, which is stored in the NVRAM 60. In this update, the data of "UE count" in the row No. 2 in the table shown in Fig. 5 is changed from the initial value "0" to "1."

[0174] Thereafter, the determination process of S204 determines that the memory error determined to have occurred in the process of S202 is a UE, and the process proceeds to S205. Then, the determination process of S205 determines that the UE has occurred for the first time in the DIMM 20 in which the UE was detected (the first time since the start of the second startup process), and the process proceeds to S206.

[0175] At this time, the processing of S206 updates the memory error information 80 of the target point for the DIMM 20 where the occurrence of a UE was detected, which is stored in the NVRAM 60. In this update, the value of the occurrence time of the UE whose occurrence was determined to have been detected by the processing of S202 is substituted for the data of "UE occurrence time" in the row No. 2 of the table shown in FIG.

[0176] Thereafter, it is determined by the determination process of S207 whether the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1. Here, too, it is assumed that there are still memory areas left that have not been initialized and trained at this time. Therefore, as a result of this determination process, the process returns to S201, and thereafter, each process is repeated for a while in the order of S201, S202, and S207. In the repetition of each process, it is assumed that the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1 without detecting the occurrence of a memory error. Then, the result of the determination process of S207 becomes YES, and the process of FIG. 7 ends.

[0177] When the memory training process ends, the process returns to S104 in the startup process of Fig. 6. At this time, the determination process of S104 determines that the occurrence of a memory error has been detected, and the process proceeds to S105. Then, the determination process of S105 determines that the memory errors detected in the memory training process of S103 included a UE, and the process proceeds to S106.

[0178] At this time, a log with a high level of detail set to log level "3" is acquired at the target point for the DIMM 20 where the occurrence of a UE was detected. Therefore, the result of the determination process in S106 is YES, and the process proceeds to S107. Then, the process in S107 degrades the DIMM 20 related to the target point and makes it unavailable, and then the process proceeds to S110.

[0179] Then, by the process of S110 at this time, the count value of the device restart counter is incremented from "1" to "2", and the information processing device 1 is restarted. Then, the CPU(0) starts the process of initializing the information processing device 1, and restarts the start-up process of FIG. 6.

[0180] [3-5-3: Third startup process]

[0181] When the third startup process is started, first, memory error information 80 and log level information 70 are obtained from NVRAM 60 by the process of S101. At this time, the log level information 70 stored in NVRAM 60 is the data exemplified in Fig. 4. Meanwhile, for the memory error information 80 stored in NVRAM 60 at this time, the data for "UE count" in row No. 2 of the table shown in Fig. 5 is "1". Also, the data for "UE occurrence time" in row No. 2 is the value substituted by the process of S206 in Fig. 7 that was most recently executed.

[0182] In the subsequent process of S102, the log level information 70 is updated based on the memory error information 80, and the memory error information 80 is initialized.

[0183] When the above-mentioned rules are applied to the data of the memory error information 80, the target point shown in line No. 2 is determined to have a log level of "3". However, referring to the data example of FIG. 4 showing the log level information 70 at this point, the target point shown in line No. 2 is already set to log level "3". In this case, it is determined that a highly detailed log equivalent to log level "3" has been acquired for the target point, and the log level for the target point is returned to the initial state, log level "1". Furthermore, since the occurrence of a memory error has not been detected for the other target points, the log level for all of them is determined to be the initial state, log level "1".

[0184] As a result of the above, the log level information 70 for each target point is set to log level "1." Also, by initializing the memory error information 80, the data for "CE count," "UE count," and "UE occurrence time" are all set to "0" for all of No. 1 to No. 8 in the table shown in FIG. 5.

[0185] Next, the memory training process of S103 starts the execution of initialization and training for the DIMM 20 by the memory initialization unit 110, and in parallel, the process of FIG. 7 starts.

[0186] 7 is started, first, in the process of S201, logs at the target points for the DIMM 20 where initialization and training are being performed are acquired with a level of detail corresponding to the log level of the target points, and output to the BMC 50. At this time, the log level information 70 stored in the NVRAM 60 is set to log level "1" for all target points. Therefore, in the process of S201 at this time, logs are acquired with a level of detail of log level "1" at the target points for the DIMM 20 where initialization and training are being performed.

[0187] This process is followed by a judgment process in S202 to judge whether or not a memory error has been detected in the memory area of ​​the DIMM 20 where initialization and training are being performed. Here, it is assumed that no memory error has occurred at this time. Therefore, as a result of this judgment process, the process proceeds to S207.

[0188] Then, the determination process of S207 determines whether the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1. Here, it is assumed that there are memory areas remaining that have not been initialized and trained at this time. Therefore, as a result of this determination process, the process returns to S201, and thereafter, each process is repeated for a while in the order of S201, S202, and S207. In the repetition of each process, it is assumed that the initialization and training have been performed on all memory areas of all DIMMs 20 included in the information processing device 1 without detecting the occurrence of a memory error. Then, the result of the determination process of S207 becomes YES, and the process of FIG. 7 ends.

[0189] When the memory training process ends, the process returns to S104 in the startup process of Fig. 6. At this time, it is determined by the determination process of S104 that the occurrence of a memory error has not been detected, and the process of Fig. 6 ends.

[0190] In the second example of the technique for acquiring and saving logs, the logs at the start-up of the information processing device 1 are acquired and saved as described above. This enables efficient use of the storage area for logs related to the initialization process.

[0191] Although the disclosed embodiments and their advantages have been described in detail above, it will be appreciated that those skilled in the art may make various modifications, additions, and omissions therein without departing from the scope of the present invention as clearly set forth in the claims. [Explanation of symbols]

[0192] 10 CPU 11 Memory Controller 20 DIMM 30 Channels 40SB 50 BMC 60 NVRAM 70 Log level information 80 Memory error information 100 BIOS 110 Memory Initialization Unit 111 Log control section 120 Memory error processing unit 121 Error information storage unit 130 Log transmission unit 140 Error severity judgment unit 150 Log level information management section 200 BMC-FW 210 Log receiver 220 Log Data

Claims

1. An information processing device, A processor; A BIOS, A process of initializing the information processing device; A process of detecting an occurrence of an error in the initialization; a process of acquiring a log of an operation status of the information processing device during the initialization, and acquiring the log with a level of detail corresponding to a level previously associated with a type of the error when the occurrence of the error is detected; a storage unit in which the BIOS that causes the processor to perform the above-mentioned steps is stored; a storage unit for storing the log acquired by the processor; An information processing device comprising:

2. The information processing device according to claim 1, characterized in that in the process of acquiring the log, when the occurrence of the error is detected, the log is acquired with a level of detail corresponding to the level for the location where the occurrence of the error was detected in the information processing device.

3. 3 . The information processing apparatus according to claim 2 , wherein the log acquired when the occurrence of the error is detected includes information specifying a position in the information processing apparatus where the occurrence of the error is detected.

4. When the occurrence of the error is detected, the BIOS causes the processor to perform a process of initializing the information processing device again; In the process of acquiring the log, when the occurrence of the error is detected, the log having a level of detail corresponding to the level is acquired from an operating status of the information processing device when the information processing device is initialized again.

4. The information processing apparatus according to claim 1, wherein the information processing apparatus is a computer.

5. a memory coupled to the processor; The process of initializing the information processing device includes a process of initializing the memory, the process of detecting occurrence of an error includes a process of detecting occurrence of a memory error in the memory, The log includes a log of an operating status of the memory during the initialization of the memory.

4. The information processing apparatus according to claim 1, wherein the information processing apparatus is a computer.

6. a type of the memory error detected in the process of detecting the occurrence of the error includes an uncorrectable error; The BIOS further causes the processor to perform a process of degenerating the memory in which the occurrence of the memory error, which is an uncorrectable error, is detected after acquiring the log with a level of detail corresponding to the level for the memory.

6. The information processing apparatus according to claim 5,

7. The information processing device according to claim 5, characterized in that, when the occurrence of the memory error is detected in more than one of the memories and the number of occurrences of any of the types of errors for the memory errors detected in each of the multiple memories exceeds a predetermined limit, the BIOS further causes the processor to perform a process of changing the correspondence between the error type and the level from a predetermined correspondence.

8. Initialize the information processing device, Detecting an occurrence of an error in the initialization, acquiring a log of an operation status of the information processing device during the initialization, and when occurrence of the error is detected, acquiring the log with a level of detail corresponding to a level previously associated with a type of the error; The log is stored in a storage unit. A log storage method, characterized in that the processing is performed by a processor.

9. Initialize the information processing device, Detecting an occurrence of an error in the initialization, acquiring a log of an operation status of the information processing device during the initialization, and when occurrence of the error is detected, acquiring the log with a level of detail corresponding to a level previously associated with a type of the error; The log is stored in a storage unit. A program that causes a processor to perform a process.

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