Semiconductor device and communication system

Abstract

To provide a semiconductor device capable of reducing a communication data amount of serial communication when setting data for multiple channels.SOLUTION: A semiconductor device (10) includes: an interface (1) configured to receive write data (WDT) transmitted via serial communication from outside; a register (21) configured to store setting data (DIMSETn) corresponding to multiple channels; and an update controller (22) configured to update the setting data on the basis of the write data. The write data includes first data (PAFLG) in which each bit indicates whether or not there is data update in a channel of the multiple channels, and second data (DutyDT) for data update in each of the multiple channels, which is set as having the data update by the first data.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a communication system. [Background technology]

[0002] Semiconductor devices having a serial communication function are used in a variety of applications.

[0003] An example of circuit technology relating to serial communication is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-224946 A

[0005] [overview] Here, the semiconductor device may have a function of performing PWM (Pulse Width Modulation) dimming as a device for driving light emitting elements of multiple channels, for example. When performing such PWM dimming, a duty may be set for each channel by serial communication. In this case, it is desired to reduce the amount of data transmitted to the semiconductor device by serial communication as much as possible.

[0006] An object of the present disclosure is to provide a semiconductor device that makes it possible to reduce the amount of serial communication traffic when data is set for multiple channels.

[0007] For example, a semiconductor device according to an embodiment of the present disclosure includes: an interface unit configured to receive write data transmitted by serial communication from an external device; A register configured to store configuration data corresponding to a plurality of channels; an update control unit configured to update the setting data based on the write data; Equipped with The write data is First data, each bit of which indicates whether data is updated in each of the plurality of channels; Second data for updating data in a channel set to be updated by the first data; The composition includes the following: [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing a configuration of a semiconductor device according to an exemplary embodiment of the present disclosure. [Diagram 3] FIG. 3 is a diagram showing the data structure of the received data RX. [Figure 4] FIG. 4 is a diagram illustrating a configuration example regarding updating of dimming settings in a semiconductor device. [Diagram 5] FIG. 5 is a register map showing the storage of dimming setting data in the low resolution mode. [Figure 6] FIG. 6 is a register map for settings for updating dimming settings in the low resolution mode. [Figure 7] FIG. 7 is a configuration diagram showing an example of updating dimming setting data in the low resolution mode and the absolute mode. [Figure 8] FIG. 8 is a register map showing the storage of dimming setting data in the registers in the high resolution mode. [Figure 9] FIG. 9 is a register map relating to settings for updating dimming settings in the high resolution mode. [Figure 10] FIG. 10 is a configuration diagram showing an example of updating dimming setting data in the high resolution mode and the relative mode. [Figure 11] FIG. 11 is a diagram showing an example of the correspondence relationship between the range of the on-duty when gradation dimming is performed and the step by which the on-duty is changed.

[0009] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0010] <1. Communication Systems> 1 is a diagram showing a configuration of a communication system 501 according to an exemplary embodiment of the present disclosure. The communication system 501 includes an MCU (Micro Controller Unit) 20, a CAN (Controller Area Network) transceiver 30, a CAN transceiver 40, and a plurality of semiconductor devices 10. Note that the communication system 501 is used, for example, in a vehicle.

[0011] Communication between the MCU 20 and the CAN transceiver 30 is performed using UART (Universal Asynchronous Receiver / Transmitter). UART is a protocol for exchanging serial data between two devices. In UART, bidirectional communication is performed between the sender and receiver using two lines.

[0012] Communication between the CAN transceivers 30, 40 is performed via a CAN bus 35. CAN is a serial communication protocol standardized by international standards such as ISO11898.

[0013] The CAN transceiver 30 has a TXD (transmit data input) terminal 30A and an RXD (receive data output) terminal 30B. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 30B.

[0014] The CAN transceiver 40 has an RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 40A.

[0015] The semiconductor device 10 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light emitting diode) driver IC. All of the multiple semiconductor devices 10 may be LED driver ICs, or some of the semiconductor devices may be LED driver ICs. Details of the semiconductor device 10 as an LED driver IC will be described later.

[0016] The semiconductor device 10 has an RX (received data input) terminal 10A and a TX (transmitted data output) terminal 10B. The RX terminals 10A of the semiconductor devices 10 are commonly connected to an RXD terminal 40A. The TX terminals 10B of the semiconductor devices 10 are commonly connected to a TXD terminal 40B.

[0017] The received data RX output from the RXD terminal 40A is input to the RX terminal 10A of each of the multiple semiconductor devices 10. The received data RX is designated with a device address of one of the multiple semiconductor devices 10. Moreover, the transmitted data TX output from the TX terminal 10B of each of the multiple semiconductor devices 10 is input to the TXD terminal 40B.

[0018] <2. Configuration of semiconductor device> Fig. 2 is a diagram showing a configuration of a semiconductor device 10 according to an exemplary embodiment of the present disclosure. The semiconductor device 10 shown in Fig. 2 is configured as an LED driver IC that drives an LED 6. An LED is an example of a light-emitting element. In other words, an LED driver is an example of a light-emitting element driving device.

[0019] The LED 6 is provided in a plurality of channels. In the following, the number of channels of the LED 6 is assumed to be 24 as an example. The number of channels of the LED 6 may be a number other than 24. The LED 6 in each channel is configured by connecting LED elements in series. However, the LED 6 in each channel may be configured by connecting LED elements in series / parallel, or may be configured by a single LED element.

[0020] The semiconductor device 10 includes, integrated together, a UART interface 1, a control unit 2, a PWM generating unit 3, and a current driver 4. The semiconductor device 10 also includes, as external terminals for establishing electrical connection with the outside, an RX terminal 10A, a TX terminal 10B, and a cathode terminal 10C.

[0021] As described above, received data RX input from the outside to the RX terminal 10A is input to the UART interface 1. Moreover, transmitted data TX output from the UART interface 1 is output to the outside from the TX terminal 10B, as described above.

[0022] The control unit 2 has a register 21. When the received data RX input to the UART interface 1 indicates a write, the control unit 2 updates the data in the register 21 based on the write data included in the received data RX. On the other hand, when the received data RX input to the UART interface 1 indicates a read, the control unit 2 reads data from the register 21. Details of the RX data will be described later.

[0023] The PWM generating unit 3 is provided corresponding to each channel of the LED 6. Therefore, if the LED 6 has 24 channels, the PWM generating unit 3 is provided for each of the channels CH01 to CH24. The channel CHn corresponds to the n-th channel. The register 21 stores dimming setting data for each channel. The PWM generating unit 3 for each channel generates a PWM signal with an on-duty based on the dimming setting data for each channel. That is, the dimming setting data for each channel represents the on-duty for PWM dimming for each channel.

[0024] A PWM signal is a pulse signal consisting of high and low levels. In one cycle (PWM cycle), the period when the PWM signal is at a first level (e.g., high level) is the on period, and the period when the PWM signal is at a second level (e.g., low level) is the off period.

[0025] A current driver 4 is provided corresponding to each channel of the LED 6. Therefore, if the LED 6 has 24 channels, a current driver 4 is provided for each of the channels CH01 to CH24. The current driver 4 of each channel is connected to the cathode of the LED 6 of each channel via the cathode terminal 10C. The anodes of the LED 6 of each channel are commonly connected to the application terminal of the power supply voltage Vcc.

[0026] Each PWM signal generated by the PWM generating unit 3 for each channel is used to control the on / off state of the current driver 4 for each channel. Specifically, during the on period of the PWM signal, the current driver 4 is in the on state, and during the off period of the PWM signal, the current driver 4 is in the off state. When the current driver 4 is in the on state, a constant current flows through the LED 6, causing the LED 6 to emit light. When the current driver 4 is in the off state, no current flows through the LED 6, causing the LED 6 to turn off. The on-duty of the PWM dimming is the percentage of the on-period in one cycle. The higher the on-duty, the brighter the LED 6.

[0027] With this configuration, the dimming setting data of each channel can be updated based on the received data RX by UART communication, and the LEDs 6 of each channel can be PWM dimmed based on the on-duty set for each channel. As will be described later, in this embodiment, the dimming setting data of only some of the 24 channels (single or multiple channels) can be updated by one communication of received data RX.

[0028] <3. Structure of received data> FIG. 3 is a diagram showing the data structure of the received data RX. In UART, communication is performed in data units called frames. A frame is made up of bit data from a start bit to a stop bit. The start bit is at low level, and the stop bit is at high level. A predetermined number of bits of bit data are placed between the start bit and the stop bit. In the following, the predetermined number of bits is assumed to be 8 bits as an example. In this case, the frame is made up of 10 bits of bit data.

[0029] As shown in FIG. 3, the received data RX includes, from the beginning, a synchronization frame SYNC, a device frame Device, a data number frame NumofData, an address frame Address, data frames Data1 to DataN (N is an integer equal to or greater than 1), a CRC (Cyclic Redundancy Check) lower frame CRC16L, and a CRC upper frame CRC16H.

[0030] The synchronization frame SYNC is bit data for setting the baud rate in the semiconductor device 10 .

[0031] The device frame Device includes a device address and a Read / Write bit, etc. The device address is bit data indicating the address of the target device (semiconductor device 10). The Read / Write bit is bit data indicating a read or write.

[0032] The data number frame NumofData is bit data indicating the number of frames (that is, N) of the data frames Data1 to DataN.

[0033] The address frame "Address" is bit data indicating an address for accessing the register 21.

[0034] The data frames Data1 to DataN are bit data indicating data for updating the data in the register 21. When the Read / Write bit in the device frame Device indicates a read, the data frames Data1 to DataN are not included in the received data RX.

[0035] The CRC lower frame CRC16L and the CRC upper frame CRC16H are bit data indicating an error detection code added to the data frames Data1 to DataN.

[0036] <4. Update dimming settings> Next, a description will be given of a method for updating the dimming setting data in the register 21. Fig. 4 is a diagram showing a configuration example regarding updating of the dimming setting in the semiconductor device 10.

[0037] As shown in Fig. 4, the UART interface 1 has a buffer 11. When reception data RX is input to the UART interface 11, reception data 11A is stored in the buffer 11. The reception data 11A includes address data Address and write data WDT. The write data WDT is data transmitted by data frames Data1 to DataN (Fig. 3).

[0038] The control unit 2 has a register 21 and an update control unit 22. The update control unit 22 updates the dimming setting data DIMSET01 to DIMSET24 in the register 21 based on the received data 11A. The update control unit 22 has a relative calculation unit 221. The relative calculation unit 221 is used in the case of relative update of the dimming setting data, which will be described later.

[0039] The dimming setting data DIMSET01 to DIMSET24 are stored in the register 21. The dimming setting data DIMSETn is a dimming setting for a channel CHn, and indicates the on-duty of the channel CHn. The on-duty has a value of 0 to 100%.

[0040] The register 21 stores resolution setting data HAMODE and relative mode setting data RELMODE.

[0041] The resolution setting data HAMODE is 1-bit data, and indicates the setting of the high-resolution mode or the low-resolution mode. The low-resolution mode is a mode in which the dimming setting data DIMSETn is updated as a first predetermined number of bits (e.g., 8 bits), and the on-duty can be adjusted with the resolution of the first predetermined number of bits. When the first predetermined number of bits is, for example, 8 bits, the on-duty can be adjusted in steps of about 0.4%. The high-resolution mode is a mode in which the dimming setting data DIMSETn is updated as a second predetermined number of bits (e.g., 12 bits) higher than the first predetermined number of bits, and the on-duty can be adjusted with the resolution of the second predetermined number of bits. When the second predetermined number of bits is, for example, 12 bits, the on-duty can be adjusted in steps of about 0.02%.

[0042] The relative mode setting data RELMODE is 1-bit data and indicates the setting of relative mode or absolute mode. The relative mode is a mode in which the dimming setting data DIMSETn is updated based on a relative change from the current value. The absolute mode is a mode in which the dimming setting data DIMSETn is updated with an absolute value.

[0043] <<Low resolution mode>> Here, a method of updating the dimming setting data when the resolution mode is set to the low resolution mode (HAMODE=0) will be described. Here, the first predetermined number of bits is assumed to be 8 bits as an example.

[0044] Fig. 5 is a diagram (register map) showing storage of dimming setting data DIMSETn in the register 21 in the low resolution mode. Fig. 5 shows the correspondence between addresses in the register 21 and the dimming setting data DIMSETn stored in the addresses. As shown in Fig. 5, the number of bits of data that can be stored in one address in the register 21 is a first predetermined number of bits (here, 8 bits). Note that the specific addresses shown in Fig. 5 and subsequent figures are merely examples.

[0045] Each of the consecutive addresses from address 0x4B to 0x62 stores one of DIMSET01 to DIMSET24, each of which is 8 bits.

[0046] Fig. 6 is a register map relating to settings for updating dimming settings in the register 21. As shown in Fig. 6, the channel setting flag PAFLG is stored in consecutive addresses from 0x7B to 0x7D. The channel setting flag PAFLG is 24-bit data, and each bit of the channel setting flag PAFLG indicates whether or not the dimming setting data for each of the 24 channels has been updated.

[0047] The lowest 8 bits of the channel setting flag PAFLG are stored in address 0x7B, the middle 8 bits of the channel setting flag PAFLG are stored in address 0x7C, and the most significant 8 bits of the channel setting flag PAFLG are stored in address 0x7D. The lowest 8 bits of the channel setting flag PAFLG correspond to channels CH01 to CH08 from the lowest bit to the most significant bit. The middle 8 bits of the channel setting flag PAFLG correspond to channels CH09 to CH16 from the lowest bit to the most significant bit. The most significant 8 bits of the channel setting flag PAFLG correspond to channels CH17 to CH24 from the lowest bit to the most significant bit.

[0048] As shown in FIG. 6, duty setting data DutyDT01 to DutyDTm are stored consecutively in order starting from address 0x7E. m can take on values ​​of 01 to 24. The duty setting data DutyDT indicates the on-duty setting value of the channel set to be updated by the channel setting flag PAFLG, and is 8 bits per channel. m is the number of channels set to be updated by the channel setting flag PAFLG. The duty setting data DutyDT is data for updating the dimming setting data DIMSETn with an absolute value.

[0049] When updating the dimming setting data DIMSETn, the following transmission is performed by the receive data RX (Fig. 3). The address 0x7B is specified in the address frame Address. Furthermore, the lower 8 bits, middle 8 bits, and upper 8 bits of the channel setting flag PAFLG, as well as the duty setting data DutyDT for the channels set to be updated by the channel setting flag PAFLG, are transmitted in order by the data frames Data1 to DataN.

[0050] FIG. 7 is a configuration diagram showing an example of updating the dimming setting data DIMSETn in the low resolution mode and the absolute mode (HAMODE=0, RELMODE=0) (corresponding to FIG. 4).

[0051] In the example of FIG. 7, receive data RX is input to the UART interface 1, and receive data 11A is stored in the buffer 11. The receive data 11A includes write data WDT along with an address 0x7B. The write data WDT includes the lower 8 bits (PAFLG[7:0]), middle 8 bits (PAFLG[15:8]), upper 8 bits (PAFLG[23:16]) of the channel setting flag PAFLG, and duty setting data DutyDT01 to 05. Here, as an example, PAFLG[7:0]=0x03 (00000011), PAFLG[15:8]=0x00, and PAFLG[23:16]=0xE0 (11100000). Since PAFLG=1 indicates that there is an update and PAFLG=0 indicates that there is no update, the channels set to have an update are channels CH01, 02, 22, 23, and 24. As a result, the duty setting data DutyDT is set to DutyDT01 to 05.

[0052] The update control unit 22 updates the channel setting flag PAFLG and the duty setting data DutyDT (FIG. 6) at consecutive addresses in the register 21 starting from the address 0x7B, based on the channel setting flag PAFLG and the duty setting data DutyDT in the write data WDT stored in the buffer 11. Then, the update control unit 22 updates the dimming setting data DIMSETn corresponding to the channels set to be updated in the register 21, based on the data updated in this way. In the example of FIG. 7, each of DIMSET01, 02, 22, 23, and 24 corresponding to the channels CH01, 02, 22, 23, and 24 set to be updated is updated by an absolute value based on each of the duty setting data DutyDT01 to 05.

[0053] In this manner, in this embodiment, it is possible to update the dimming setting data of only some of the 24 channels. In the case of a method (method according to the first comparative example) in which the dimming setting data of all 24 channels is transmitted by the reception data RX in order to update the dimming setting data of only some of the channels, the required transmission data is 24ch×1 byte+6 bytes (SYNC, Device, NumofData, Address, CRC16L, CRC16H)=30 bytes.

[0054] Also, suppose that a method (method according to the second comparative example) is adopted in which the received data RX is transmitted for each of a group of consecutive channels starting from channel CH01 set to be updated and a group of consecutive channels starting from channel CH24 set to be updated in order to update the dimming setting data of only some channels. In this case, in the example of Fig. 7, the group of consecutive channels set to be updated is divided into a group of channels CH01, 02 and a group of channels 22, 23, 24, so that the received data RX needs to be transmitted twice, and the required transmission data is 17 bytes, which is a sum of 2ch x 1 byte + 6 bytes and 3ch x 1 byte + 6 bytes.

[0055] In contrast, in this embodiment, in the example of Figure 7, the received data RX needs to be transmitted only once, and the required transmission data is 3 bytes (PAFLG) + 1 byte x 5 (DutyDT01 to 05) = 8 bytes, making it possible to reduce the amount of communication.

[0056] In this embodiment, it is possible to set dimming setting data for any part of the 24 channels, and the degree of freedom in setting is higher than in the method according to the second comparative example.

[0057] <<High resolution mode>> Here, a method of updating the dimming setting data when the resolution mode is set to the high resolution mode (HAMODE=1) will be described. Here, the second predetermined number of bits is assumed to be 12 bits, as an example.

[0058] FIG. 8 is a register map showing storage of the dimming setting data DIMSETn in the register 21 in the high resolution mode.

[0059] Address 0x4B stores the upper 8 bits of DIMSET01. Address 0x4C stores the lower 4 bits of DIMSET01 at the upper level, and the lower 4 bits of DIMSET02 at the lower level. Address 0x4D stores the upper 8 bits of DIMSET02. Similar to the storage pattern of dimming setting data at addresses 0x4B to 0x4D, addresses 0x4E and onward store DIMSET03 to DIMSET24. In this way, 12 bits of DIMSET01 to DIMSET24 can be stored in each of the consecutive addresses from 0x4B to 0x6E.

[0060] Fig. 9 is a register map relating to settings for updating dimming settings in the register 21 in the high resolution mode. As shown in Fig. 9, the channel setting flag PAFLG is stored in consecutive addresses 0x7B to 0x7D. The channel setting flag PAFLG is as described above.

[0061] Furthermore, polarity data SG01 to SGm, gain data GAIN01 to GAINm, and relative value data DUTY01 to DUTYm are stored consecutively in order from address 0x7E, where m can take a value of 01 to 24. The polarity data SG, gain data GAIN, and relative value data DUTY for one address correspond to one channel.

[0062] The polarity data SG is 1-bit data, and indicates a decrease or increase from the current value of the dimming setting data DIMSETn. For example, SG=0 indicates a decrease, and SG=1 indicates an increase.

[0063] The gain data GAIN is 2-bit data and indicates a gain value. For example, GAIN=0 indicates a gain of 1, GAIN=1 indicates a gain of 2, GAIN=2 indicates a gain of 8, and GAIN=3 indicates a gain of 16.

[0064] The relative value data DUTY is 5-bit data and indicates a relative change value. The relative value data DUTY can take a value from 0 to 31.

[0065] The dimming setting data DIMSETn of the channel CHn is updated by the polarity data SG, the gain data GAIN, and the relative value data DUTY according to the following equation (1). DIMSETn=DIMSETn±DUTY×GAIN (1) Note that DIMSETn on the right side indicates the current value, and DIMSETn on the left side indicates the updated value. Additionally, ± indicates + (increase) or - (decrease) according to the polarity data SG.

[0066] For example, when SG=0, GAIN=1, and DUTY=5, DIMSETn=DIMSETn-5×2.

[0067] When high resolution mode and relative mode (RELMODE=1) are set, the following transmission is performed by the receive data RX (Fig. 3) when updating the dimming setting data DIMSETn. The address 0x7B is specified in the address frame Address. In addition, the lower 8 bits, middle 8 bits, and upper 8 bits of the channel setting flag PAFLG, as well as the polarity data SG, gain data GAIN, and relative value data DUTY for the channels set to be updated by the channel setting flag PAFLG, are transmitted in order by the data frames Data1 to DataN.

[0068] FIG. 10 is a configuration diagram showing an example of updating the dimming setting data DIMSETn in the high resolution mode and the relative mode (HAMODE=1, RELMODE=1) (corresponding to FIG. 4).

[0069] In the example of FIG. 10, the receive data RX is input to the UART interface 1, and the receive data 11A is stored in the buffer 11. The receive data 11A includes the address 0x7B and the write data WDT. The write data WDT includes the lower 8 bits (PAFLG[7:0]), the middle 8 bits (PAFLG[15:8]), the upper 8 bits (PAFLG[23:16]), the polarity data SG, the gain data GAIN, and the relative value data DUTY of the channel setting flag PAFLG. Here, as an example, PAFLG[7:0]=0x03 (00000011), PAFLG[15:8]=0x00, and PAFLG[23:16]=0xE0 (11100000). Therefore, the channels set to be updated are channels CH01, 02, 22, 23, and 24. As a result, the polarity data SG, the gain data GAIN, and the relative value data DUTY are SG01 to SG05, GAIN01 to GAIN05, and DUTY01 to DUTY05.

[0070] The update control unit 22 updates the channel setting flag PAFLG, polarity data SG, gain data GAIN, and relative value data DUTY (FIG. 9) at consecutive addresses starting from address 0x7B in the register 21 based on the channel setting flag PAFLG, polarity data SG, gain data GAIN, and relative value data DUTY in the write data WDT stored in the buffer 11. Then, the update control unit 22 updates the dimming setting data DIMSETn corresponding to the channel set to be updated in the register 21 based on the data updated in this way. In the example of FIG. 10, each of DIMSET01, 02, 22, 23, and 24 corresponding to the channels CH01, 02, 22, 23, and 24 set to be updated is updated by the calculation of the relative calculation unit 221 as follows.

[0071] The relative calculation unit 221 performs the calculation according to the above-mentioned formula (1). For example, for channel CH01 in the example of FIG. 10, DIMSET01=DIMSET01±DUTY01×GAIN01 The dimming setting data DIMSET01 is updated thereby. However, ± represents + or - according to the polarity data SG01. In FIG. 10, illustration of the update of the dimming setting data for channels other than channel CH01 is omitted.

[0072] As in this embodiment as described above, it becomes possible to relatively update the dimming setting data DIMSETn with high resolution (for example, 12 bits) for some channels among 24 channels. Here, FIG. 11 is a diagram showing an example of the correspondence relationship between the range of the on-duty in the case of performing gradation dimming and the steps of changing the on-duty. In this way, the larger the duty, the larger the step. In gradation dimming, the on-duty is increased in the specified steps from the current value to the target value. By representing the on-duty with high resolution, the minimum step can be made smaller. In such gradation dimming and the like, since the required steps are small, dimming is possible by updating the dimming setting data in the relative mode.

[0073] When updating the dimming setting data for 5 channels as in the example of FIG. 10, in the absolute mode, at least 10.5 bytes of data transmission of 3 bytes (PAFLG) + 5ch × 12 bits is required, but in the relative mode, 3 bytes + 5ch × 8 bits = 8 bytes of data transmission is sufficient, and reduction of the communication amount becomes possible.

[0074] Also, as shown in FIG. 1, when each RX terminal 10A of a plurality of semiconductor devices 10 is commonly connected to the same RXD terminal 40A of the CAN transceiver 40, assume that the plurality of semiconductor devices 10 are LED driver ICs. In this case, when updating the dimming setting data in each of the plurality of semiconductor devices 10, it is necessary to sequentially transmit the received data RX to each of the plurality of semiconductor devices 10 by serial communication, and it is effective to reduce the communication amount in one transmission in the low resolution mode and the high resolution mode.

[0075] <<Confirmation of NumofData>> When the reception data RX is transmitted, the update control unit 22 checks the data number frame NumofData as follows. Specifically, for the channel setting flag PAFLG included in the write data WDT stored in the buffer 11, Number of bytes in PAFLG + number of channels set to update in PAFLG = number of data frames Number of frames indicated by NumofData (2) If formula (2) is satisfied, the process proceeds to update control of the dimming setting data DIMSETn.

[0076] For example, in the examples of Figures 7 and 10, the number of bytes of PAFLG is 3, and the number of channels set to be updated in PAFLG is 5, so it is confirmed whether the number of frames indicated by the data number frame NumofData is 8.

[0077] <5.Other> In addition to the above-mentioned embodiment, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-mentioned embodiment, but should be understood to include all modifications that fall within the meaning and scope equivalent to the scope of the claims.

[0078] For example, serial communication is not limited to UART communication. 2 C communication, etc.

[0079] <6. Notes> As described above, the semiconductor device (10) according to one embodiment of the present disclosure is An interface unit (1) configured to receive write data (WDT) transmitted from an external device via serial communication; A register (21) configured to store setting data (DIMSETn) corresponding to a plurality of channels; an update control unit (22) configured to update the setting data based on the write data; Equipped with The write data is First data (PAFLG), each bit of which indicates whether data is updated in each of the plurality of channels; Second data (DutyDT) for updating data in a channel set to be updated by the first data; The first configuration includes the above.

[0080] According to this configuration, the amount of data to be transmitted, including the write data required to update the setting data for multiple channels, can be reduced, thereby solving the problem of reducing the amount of serial communication traffic when setting data for multiple channels.

[0081] In the first configuration, the number of bits of data that can be stored in one address in the register is a first predetermined number of bits (e.g., 8 bits); The first data and the second data may be transmitted with the first predetermined number of bits as a data unit (second configuration).

[0082] In the second configuration, the setting data (DIMSETn) for one channel is the first predetermined number of bits, The second data of the data unit may update the setting data of one channel with an absolute value (third configuration).

[0083] In the second or third configuration, in the high resolution mode, the setting data for one channel has a second predetermined number of bits (e.g., 12 bits) higher than the first predetermined number of bits, The second data of the data unit includes polarity data (SG) representing a decrease or an increase, gain data (GAIN) representing a gain value, and relative value data (DUTY) representing a relative change value, corresponding to one channel; the update control unit has a relative calculation unit (221) configured to subtract or add a value obtained by multiplying the relative change value by the gain value to a current value of the setting data in accordance with the polarity data to calculate a calculation result, The update control unit may be configured to update the setting data based on the calculation result (fourth configuration).

[0084] In the above fourth configuration, the gain value may be set to 1 based on the gain data (fifth configuration).

[0085] Furthermore, in the above fourth or fifth configuration, in the high resolution mode, the register may be configured such that the upper bits of the setting data for the first channel are stored in a first address, the lower bits of the setting data for the first channel and the lower bits of the setting data for the second channel are stored in a second address obtained by incrementing the first address, and the upper bits of the setting data for the second channel are stored in a third address obtained by incrementing the second address (sixth configuration).

[0086] In any one of the first to sixth configurations, the setting data may indicate a duty of PWM dimming (seventh configuration).

[0087] In the fourth configuration, the setting data indicates a duty of PWM dimming, A configuration may be adopted in which the step for changing the on-duty becomes larger as the on-duty of the PWM dimming becomes higher, and gradation dimming is possible in which the on-duty is increased according to the step (eighth configuration).

[0088] In the second configuration, a data frame including the first predetermined number of bits of data and a data number indicating the number of the data frames can be transmitted by the serial communication, The update control unit may be configured to check whether the sum of the number of data units of the first data and the number of channels set to update by the first data matches the number of data (ninth configuration).

[0089] In the ninth configuration, the serial communication may be UART communication (tenth configuration).

[0090] Moreover, a communication system (501) according to one embodiment of the present disclosure includes a semiconductor device (10) having any one of the first to tenth configurations described above, and a transmitting device (40) configured to transmit the write data (eleventh configuration).

[0091] In the eleventh configuration, an input terminal (10A) provided in each of the plurality of semiconductor devices (10) and configured to receive the write data may be commonly connected to a same output terminal (40A) provided in the transmitting device (40) (twelfth configuration). [Industrial Applicability]

[0092] The present disclosure can be used, for example, in an in-vehicle communication system. [Explanation of symbols]

[0093] 1 UART Interface 2. Control section 3 PWM generation section 4 Current Drivers 6 LED 10 Semiconductor device 10A RX terminal 10B TX terminal 10C Cathode terminal 11 Buffer 11A Received Data 21 Registers 22 Update control section 30,40 CAN transceiver 30A TXD terminal 30B RXD terminal 35 CAN bus 40A RXD terminal 40B TXD terminal 221 Relative Calculation Section 501 Communication Systems

Claims

1. an interface unit configured to receive write data transmitted by serial communication from an external device; A register configured to store configuration data corresponding to a plurality of channels; an update control unit configured to update the setting data based on the write data; Equipped with The write data is First data, each bit of which indicates whether data in each of the plurality of channels has been updated; second data for updating data in a channel set to be updated by the first data; 13. A semiconductor device comprising:

2. the number of bits of data that can be stored in one address in the register is a first predetermined number of bits; 2 . The semiconductor device according to claim 1 , wherein said first data and said second data are transmitted with said first predetermined number of bits as a data unit.

3. the setting data for one channel is the first predetermined number of bits, 3. The semiconductor device according to claim 2, wherein the setting data of one channel is updated with an absolute value by the second data of the data unit.

4. In the high resolution mode, the setting data for one channel has a second predetermined number of bits that is higher than the first predetermined number of bits, The second data of the data unit includes polarity data representing a decrease or an increase, gain data representing a gain value, and relative value data representing a relative change value, corresponding to one channel; the update control unit has a relative calculation unit configured to subtract or add a value obtained by multiplying the relative change value by the gain value to a current value of the setting data in accordance with the polarity data to calculate a calculation result, The semiconductor device according to claim 2 , wherein said update control unit updates said setting data based on said calculation result.

5. The semiconductor device according to claim 4 , wherein the gain value is set to 1 by the gain data.

6. 5. The semiconductor device according to claim 4, wherein in the high resolution mode, in the register, upper bits of the setting data of a first channel are stored in a first address, lower bits of the setting data of the first channel and lower bits of the setting data of a second channel are stored in a second address obtained by incrementing the first address, and upper bits of the setting data of the second channel are stored in a third address obtained by incrementing the second address.

7. The semiconductor device according to claim 1 , wherein the setting data indicates a duty of PWM dimming.

8. The setting data indicates a duty of PWM dimming, 5. The semiconductor device according to claim 4, wherein the step for changing the on-duty of the PWM dimming is larger as the on-duty of the PWM dimming is higher, and gradation dimming is possible in which the on-duty is increased according to the step.

9. A data frame including the first predetermined number of bits of data and a data number indicating the number of the data frames can be transmitted by the serial communication, 3. The semiconductor device according to claim 2, wherein the update control unit checks whether a sum of the number of the data units of the first data and the number of channels set to update by the first data matches the number of data.

10. 10. The semiconductor device according to claim 9, wherein the serial communication is UART communication.

11. 11. A communication system comprising: the semiconductor device according to claim 1; and a transmitting device configured to transmit the write data.

12. 12. The communication system according to claim 11, wherein an input terminal provided in each of the plurality of semiconductor devices and configured to receive the write data is commonly connected to a same output terminal provided in the transmission device.

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