Quantum bit routing

Abstract

To provide quantum bit routing.SOLUTION: A method may include obtaining a graph in which a first and a second node respectively represent a first qubit and a second qubit. The method may include generating candidate paths between the first and second qubits along one or more edges, each candidate path specifying a path that arrives at a target edge between a first node and a second node. The method may include computing scores for a plurality of path pairs, a respective score indicating how efficiently a respective path pair routes the first node to the second node via a target edge. The score may be weighted based on an order in which operations of a quantum circuit are performed with earlier operations being weighted more heavily than later operations. The method may include selecting the path pair that corresponds to a highest score for routing the first node to the second node via the target edge.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates generally to systems and methods for qubit routing. [Background technology]

[0002] Quantum computers can use qubits ("qubits"), which can represent information as 1, 0, or 1 and 0 simultaneously. Quantum computers can perform some types of calculations, such as optimization problems, integer factorization, simulation modeling, and / or data analysis, more efficiently and / or more accurately than classical computing systems. However, existing quantum computers contain only a limited number of qubits and, as a result, are unable to perform or are not suitable for some computationally demanding tasks, so existing quantum computers may be classified as noisy intermediate-scale quantum (NISQ) devices.

[0003] The subject matter claimed in this disclosure is not limited to embodiments that solve any shortcomings or that operate only in environments such as those described above. Rather, this background is provided only to illustrate one example technology area where some embodiments described in this disclosure may be practiced. Summary of the Invention [Means for solving the problem]

[0004] According to an aspect of an embodiment, a method may include obtaining a graph in which a first node and a second node represent a first qubit and a second qubit, respectively. The method may include generating candidate paths between the first qubit and the second qubit along one or more edges, each candidate path specifying a path to reach a target node between the first node and the second node. The method may include calculating a score for a plurality of path pairs, each score indicating how efficiently the respective path pair routes the first node to the second node through the target edge. The scores may be weighted based on the order in which operations of the quantum circuit are executed, with earlier operations being given a greater weight than later operations. The method may include selecting a path pair corresponding to a highest score for routing the first node to the second node through the target edge.

[0005] The object and advantages of the embodiments will be realized and attained at least by the elements, features, and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are illustrative only and are not restrictive of the invention as claimed. [Brief description of the drawings]

[0006] Example embodiments will be described and explained with additional specificity and detail through the accompanying drawings.

[0007] [Figure 1] FIG. 1 illustrates an example operating environment in which an initial qubit mapping may be determined, according to one or more embodiments of the present disclosure.

[0008] [Figure 2A] 1 shows a first exemplary graph representing a qubit in a quantum computing system.

[0009] [Figure 2B] 1 shows a second exemplary graph representing a qubit in a quantum computing system.

[0010] [Diagram 3] 1 is a flowchart of an example method for determining an initial qubit mapping, according to one or more embodiments of the present disclosure.

[0011] [Figure 4] 1 is a flowchart of an example method for generating a quadratic assignment problem corresponding to a qubit graph, in accordance with one or more embodiments of the present disclosure.

[0012] [Diagram 5] 1 is a flowchart of an example method for generating a graph representation of qubits of a quantum computing system, according to one or more embodiments of the present disclosure.

[0013] [Figure 6] FIG. 1 illustrates an example operating environment in which qubit routing may be determined in accordance with one or more embodiments of the present disclosure.

[0014] [Figure 7A] 1 shows an exemplary graph containing a set of candidate paths between two qubits in a quantum computing system.

[0015] [Figure 7B] 1 shows a graph illustrating a particular pair of candidate paths and edges included in the particular candidate paths that connect two qubits in a quantum computing system.

[0016] [Figure 8] 1 is a flowchart of an example method for generating candidate routes according to one or more embodiments of the present disclosure.

[0017] [Figure 9]1 is a flowchart of an example method for determining qubit routing in accordance with one or more embodiments of the present disclosure.

[0018] [Figure 10] 1 is an exemplary computer system according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Quantum computers use quantum bits, or "qubits," that are configured to store values ​​of 0, 1, or a superposition of both 0 and 1. Because qubits can store multiple values ​​simultaneously, quantum computers can perform calculations more quickly than classical computers that use classical bits that store values ​​of either 0 or 1. As a result, quantum computers can perform calculations such as optimization problems more efficiently, improving computations in a variety of technological fields, such as physics, chemistry, materials design, drug discovery, and machine learning.

[0020] However, existing quantum computers are physically constrained with respect to the number of qubits that can be included in a particular quantum computing system. Existing quantum computers are referred to as noisy intermediate-scale quantum (NISQ) devices because the computational performance of such NISQ devices is constrained by the current physical and technological limitations of quantum computers. The sensitivity and reliability issues of NISQ devices to external interference are typically caused by the susceptibility of quantum hardware to errors caused by noise due to stray electromagnetic radiation, material defects, or other external obstructions that disrupt the operation of the quantum computer. Furthermore, qubits exhibit quantum properties for a finite period of time, and the computations performed by NISQ devices involve measuring values ​​associated with the qubits during the period of time in which the qubits exhibit quantum properties.

[0021] The noise interference and error resistance of a particular NISQ device depends in part on the location of the qubits associated with the particular NISQ device. Existing NISQ computer chips may include quantum circuits that include tens or hundreds of qubits that have a sparse structure such that each qubit included in the quantum circuit is not directly connected with each other qubit in the quantum circuit. As a result, the qubits included in the quantum circuit are not necessarily configured to communicate directly with each other. The exchange of information between two disconnected qubits may be facilitated by using one or more swap gate operations to rearrange one or both of the disconnected qubits until the two disconnected qubits are directly connected to each other according to the sparse structure of the quantum circuit.

[0022] However, each swap gate operation introduces additional noise into the operation of the NISQ device, increasing the likelihood of an erroneous computation. The manner in which the qubits in a particular quantum circuit are arranged or mapped may make it easier to make direct connections between qubits that are more likely to communicate with each other for a particular computational operation, reducing the noise experienced by the NISQ device during the operation. As the number of operations performed by a NISQ device increases, it may be desirable to increase the number of direct connections between the qubits performing the operations, thereby reducing the noise experienced by the NISQ device during the performance of said operations.

[0023] The present disclosure relates, among other things, to logically mapping qubits to increase the number of directly connected qubit pairs used in the operation of a particular NISQ device and to reduce the number of swap gates used to achieve direct connections between qubit pairs during operation of a particular NISQ device. Mapping qubits according to one or more embodiments of the present disclosure may include modeling circuitry associated with a particular NISQ device as a weighted graph, where nodes of the graph represent the qubit architecture of the particular NISQ device and edges between the nodes represent direct connections between the qubits. The weighting of the nodes may be such that certain nodes representing qubits involved in earlier operation of the particular NISQ device are weighted more heavily, while qubits involved in later operation of the particular NISQ device are given less weight. The weighted graph representing the particular NISQ device may be modeled as a quadratic assignment problem (QAP) that is solved to determine an initial mapping of qubits that reduces the distance between pairs of qubits involved in the operation of the particular NISQ device.

[0024] Weighting graph edges representing gates based on the order in which operations are performed by a particular NISQ device can result in improved qubit mappings over existing methods of determining qubit mapping locations, which typically do not consider the entire sequence of operations being performed by a particular NISQ device and can determine inefficient qubit mappings based only on a first subset of operations that can be performed by a qubit.

[0025] Additionally or alternatively, the present disclosure relates to, among other things, identifying one or more paths for routing qubits to increase the number of directly connected qubit pairs used in the operation of a particular NISQ device and to reduce the number of swap gates used to achieve direct connections between qubit pairs during operation of the particular NISQ device. Routing qubits according to one or more embodiments of the present disclosure may include modeling a circuit associated with a particular NISQ device as a graph, where nodes of the graph represent the qubit architecture of the particular NISQ device and edges between the nodes represent direct connections between the qubits. A path between any two particular qubits included in a particular NISQ device may be represented as a series of direct connections between the nodes representing the two particular qubits. Candidate paths between two nodes representing the two particular qubits may be identified, and each of the candidate paths may be evaluated to determine a respective score associated with each of the candidate paths. The scoring of the candidate paths may be related to an operation that the qubit associated with the candidate path is scheduled to perform. Candidate paths between qubits involved in performing earlier operations of a particular NISQ device may be weighted more heavily, while candidate paths between qubits involved in performing later operations may be given less weight. The candidate paths may be selected based on a score associated with each of the candidate paths.

[0026] Weighting candidate paths based on the order in which operations are performed by a particular NISQ device can result in improved qubit routing over existing qubit routing methods, which typically do not consider the entire sequence of operations being performed by a particular NISQ device and can determine inefficient qubit routing based only on a first subset of operations that can be performed by a qubit.

[0027] An embodiment of the present disclosure will be described with reference to the drawings.

[0028] 1 is a diagram of an example operating environment 100 in which an initial qubit mapping may be determined in accordance with one or more embodiments of the present disclosure. The operating environment 100 may include a quantum circuit 110, a weighted graph 130, a quadratic assignment problem (QAP) 150, and / or a graphing module configured to obtain qubit mappings 170 as inputs and / or outputs, a quadratic modeling module 140, and / or a quadratic assignment problem solver 160.

[0029] In some embodiments, the graphing module 120, the quadratic modeling module 140, and / or the QAP solver 160 (collectively referred to herein as “computing modules”) may include code and routines configured to enable a computing system to perform one or more operations. Additionally or alternatively, one or more of the computing modules may be implemented using hardware, including a processor, a microprocessor (e.g., performing or controlling the execution of one or more operations), a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC). In some other cases, the computing modules may be implemented using a combination of hardware and software. In this disclosure, operations described as being performed by a computing module may include operations that the computing module may direct one or more corresponding systems to perform. The computing modules may be configured to perform a set of operations related to the quantum circuit 110, the weighted graph 130, the QAP 150, and / or the qubit mapping 170. This is described in further detail below with respect to example method 300, example method 400, and / or example method 500 as described with respect to Figures 3, 4, and / or 5, respectively.

[0030] Quantum circuit 110 may include quantum bits ("qubits"), and a particular qubit of quantum circuit 110 may be connected to one or more other qubits of quantum circuit 110 through a quantum gate. Quantum circuit 110 may be a noisy intermediate-scale quantum (NISQ) circuit including between about 40 qubits and about 1000 qubits. The qubits included in the NISQ circuit may be sparsely connected such that each qubit included in the NISQ circuit is not connected to each other qubit included in the NISQ circuit due to physical limitations of the NISQ circuit.

[0031] To perform a computation using quantum circuit 110, a first qubit may be designated to communicate with a second qubit through a quantum gate that connects the first qubit to the second qubit. In some situations, one or more additional qubits may be disposed between the first qubit and the second qubit, such that the first qubit and the second qubit may or may not be directly connected to each other through a quantum gate. For example, a third qubit may be directly connected to the first qubit and the second qubit, but the first qubit and the second qubit may not be directly connected to each other. In these and other situations, a swap gate may be implemented between the third qubit and either the first qubit or the second qubit to swap the third qubit with either the first qubit or the second qubit by logically exchanging the positioning of the two qubits affected by the swap gate. In other words, the third qubit may be logically designated, during operation of quantum circuit 110, to perform a calculation and / or operation originally designated to the second qubit.

[0032] Graphing module 120 may be configured to take quantum circuit 110 and output a weighted graph 130 that represents quantum circuit 110. In some embodiments, weighted graph 130 may be a graph that visually represents quantum circuit 110. Additionally or alternatively, weighted graph 130 may quantitatively represent quantum circuit 110 using one or more matrices. Weighted graph 130 may include nodes that represent qubits of quantum circuit 110 and edges that connect one or more of the nodes to each other, representing quantum gates connecting the qubits.

[0033] For example, FIG. 2A illustrates a first exemplary graph 200 of a quantum computing system. The first graph 200 includes nodes, such as a first node 210, a second node 220, and a third node 230, and edges, such as a first edge 240 and a second edge 245. As illustrated in FIG. 2A, the first node 210 is connected to the second node 220 by the first edge 240, and the first node 210 is connected to the third node 230 by the second edge 245. However, the second node 220 is not directly connected to the third node 230 because no edge exists between the second node 220 and the third node 230.

[0034] As an additional or alternative example, FIG. 2B illustrates a second exemplary graph 250 of a quantum computing system. The second graph 250 includes a first node 260 connected to a second node 270 via a first edge 290 and a third node 280 connecting to the second node via a second edge 295. FIG. 2B further illustrates that the positions associated with the logical qubits represented by the first node 260, the second node 270, and / or the third node 280 may be swapped. For example, the first node 260 may be swapped with the second node 270 via the first edge 290 to facilitate a direct connection between the first node 260 and the third node 280 via the second edge 295. As an additional or alternative example, the second node 270 may be swapped with the third node 280 via the second edge 295 to facilitate a direct connection between the same direct connection between the first node 260 and the third node 280. As shown in the second graph 250, in these and other embodiments, the physical qubits corresponding to the first node 260, the second node 270, and the third node 280 are not rearranged by a particular swap gate. Rather, operations logically associated with the qubits corresponding to the first node 260, the second node 270, and the third node 280 may be reassigned to another qubit by a particular swap gate.

[0035] Returning to the discussion of FIG. 1, representing quantum circuit 110 as a weighted graph 130 may present quantum circuit 110 in a quantitative form that is more easily and effectively analyzed to determine a mapping of qubits that facilitates more efficient operation of quantum circuit 110. For a quantum circuit 110 configured to perform a particular sequence of operations, the qubits of quantum circuit 110 involved in performing the particular sequence of operations may be known; that is, it is known which qubits are used in the operation of quantum circuit 110, and in what order the qubits are used. However, the logical configuration of quantum circuit 110 (i.e., the initial mapping of the logical qubits) may or may not be readily apparent given the qubits assigned to particular operations and the order in which the operations are scheduled to be performed.

[0036] In some embodiments, weighted graph 130 may be represented by one or more matrices that quantitatively describe quantum circuit 110. For example, graphing module 120 may generate a flow matrix that quantifies the connections between nodes of weighted graph 130. Given a particular quantum circuit 110 that includes M two-qubit gates operating on Q qubits, weighted graph 130 may be represented by a set of matrices (V,E c ), where V and E c The dimensions of V are set based on the integers Q and M, respectively. i is the number of qubits q i It can correspond to E c A particular two-qubit gate g in the set u can be expressed in terms of the two qubits that a particular two-qubit gate connects. For example, the first qubit, q i and the second qubit q j The two-qubit gate that connects i ,q j ) may be specified.

[0037] Additionally or alternatively, the graphing module 120 may generate a distance matrix that quantifies the distances between nodes in the weighted graph 130. For example, a piecewise function r(q i ,q j ) is the first qubit, q i and the second qubit q j and the function calculates the shortest distance between the first qubit and the second qubit in situations where the first qubit and the second qubit are not the same qubit. In situations where the first qubit and the second qubit are the same qubit, the function may return a value of zero. That is, the function may be expressed according to the following equation:

number

[0038] Additionally or alternatively, graphing module 120 may assign weight values ​​to edges of weighted graph 130 to indicate the importance or lack of importance of a particular edge between pairs of qubits to determine the initial mapping of qubits given a particular set of operations performed by quantum circuit 110. Whether a particular edge between a pair of qubits is important for determining the initial mapping of qubits may depend on the gate depth of the particular edge. The gate depth of a particular qubit gate, which may be represented by each edge of the graph, describes the sequence and / or frequency with which two qubits associated with the particular qubit gate participate in operations of quantum circuit 110. For example, a particular quantum circuit 110 may include performing 100 operations, each operation involving two qubits. A first particular qubit involved in a first operation of a particular quantum circuit 110 may include a lower gate depth than a second particular qubit involved in the 100th operation of the particular quantum circuit 110. The gate depth of a particular qubit may influence the initial mapping of the qubit for quantum circuit 110 because qubits involved in earlier operations of quantum circuit 110 are more likely to also be involved in later operations of quantum circuit 110 and / or be involved in swap gate operations related to qubits involved in later operations of quantum circuit 110. Qubit mappings for earlier operations of quantum circuit 110 may be given greater weight than qubit mappings for later operations of quantum circuit 110 because swap gates are more likely to be used to rearrange qubits during operations of quantum circuit 110.

[0039] In some embodiments, the gate depth is determined by the i The space-time coordinates (t i ,x i For example, the gate depth can be quantitatively described by the set E c where a particular element e iThe gate depth for i Thus, the gate depth may be expressed by the following relationship:

number

[0040] The quadratic modeling module 140 may be configured to model the input weighted graph 130 as a QAP 150. In some embodiments, the QAP 150 may represent an optimizable quantitative description of the weighted graph 130. For example, a flow matrix and a distance matrix corresponding to the weighted graph 130 may be combined and represented by the following QAP 150:

number

[0041] Additionally or alternatively, a bias term may be introduced into QAP 150 represented by equation (3) to take into account self-referential flows (i.e., qubits connected to themselves by one-qubit gates) associated with one or more qubits included in quantum circuit 110. Taking the bias term into account, QAP 150 may be represented by the following relationship:

number

[0042] Equations (3) and (4) may represent a graph corresponding to an unweighted quantum circuit and may not account for varying degrees of importance between different qubit gates, represented as edges between graph nodes, included in the unweighted quantum circuit. For example, a critical qubit gate that is used in multiple operations (e.g., because the critical qubit gate appears in an early scheduled operation of the quantum circuit and a later scheduled operation of the quantum circuit) may be considered equivalent to another qubit gate that is not used in any operation of the quantum circuit. In some embodiments, quadratic modeling module 140 may be configured to generate QAP 150 taking into account the gate depth of quantum circuit 110 to represent the variation in importance of different qubit gates. For example, a depth-aware quadratic routing length may be represented by the following relationship:

number

[0043] Additionally or alternatively, the rules associated with gate depth may be inverted so that earlier operations are assigned larger gate depths and later operations are assigned smaller gate depths. In these and other embodiments, equation (5) may be modified into an optimization problem whose objective is to maximize the output value of the equation, rather than minimizing the output value as written in equation (5).

[0044] Additionally or alternatively, the QAP 150 may be expressed as a quadratic binary optimization problem (QBP) that can be more easily solved by the QAP solver 160. e and / or the routing length minimization term x ij is introduced into QAP 150, the following relationship can be derived:

number

[0045] QAP 150 may be obtained by QAP solver 160, which may be configured to output qubit mapping 170. In some embodiments, QAP solver 160 may be a quantum computer configured to use quantum computing techniques to solve optimization problems, such as QAP 150. Additionally or alternatively, QAP solver 160 may be a classical computing system that emulates quantum computing techniques. Additionally or alternatively, QAP solver 160 may include a classical software solver configured to obtain and solve the optimization problem. In some embodiments, QAP 150 may include so many variables that it becomes difficult for QAP solver 160 to solve QAP 150. In these and other embodiments, initial QAP 150 may be decomposed into two or more smaller optimization problems to facilitate operation of QAP solver 160.

[0046] Qubit mapping 170 output by QAP solver 160 may specify which physical qubits of quantum circuit 110 are assigned to which logical virtual qubits. As described above with respect to weighted graph 130 and QAP 150, the gate depth may be determined according to the order in which operations of quantum circuit 110 are performed and the qubits involved in performing the operations. One or more swap gates may be implemented to virtually reassign the initial positions of the qubits such that the qubits involved in an operation of quantum circuit 110 are adjacent to one another before the operation begins. This may reduce the likelihood that the operation of quantum circuit 110 is affected by errors associated with using swap gates, caused by environmental factors or for any other reason.

[0047] Modifications, additions, or omissions may be made to environment 100 without departing from the scope of the present disclosure. For example, the designation of different elements in the manner described is intended to help illustrate the concepts described herein and is not intended to be limiting. For example, in some embodiments, quantum circuit 110, weighted graph 130, QAP 150, and qubit mapping 170 are depicted in a particular manner described to help illustrate the concepts described herein, but such depictions are not intended to be limiting. Additionally, environment 100 may include any number of other elements or may be implemented in other systems or contexts other than those described.

[0048] 3 is a flowchart of an example method 300 for determining initial qubit mappings in accordance with one or more embodiments of the present disclosure. Method 300 may be performed by any suitable system, apparatus, or device. For example, graphing module 120, quadratic modeling module 140, and / or QAP solver 160 of FIG. 1 may perform one or more operations associated with method 300. Although shown in discrete blocks, steps and operations associated with one or more of the blocks of method 300 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the particular implementation.

[0049] Method 300 may begin at block 302, where a quantum circuit may be obtained. In some embodiments, the quantum circuit may include an architecture that includes physical qubits connected to each other via two-qubit gates. The quantum circuit may include a sparsely connected structure. In a sparsely connected structure, one or more of the qubits of the quantum circuit may not be connected to one or more other qubits via two-qubit gates, such that there may not be a direct connection between all pairs of qubits included in the quantum circuit.

[0050] At block 304, a graph representation of the quantum circuit may be generated. In the graph representation of the quantum circuit, a particular qubit may be represented as a respective node of the graph, and a particular gate connecting two qubits may be represented as a respective edge between two nodes of the graph.

[0051] In block 306, weight values ​​may be assigned to the edges. The weight values ​​assigned to the edges may be based on the gate depth of the corresponding node to which the edge is associated. In some embodiments, nodes involved in earlier operations of the quantum circuit may include a lower gate depth and may be given a larger weight value.

[0052] At block 308, the weighted graph representing the quantum circuit may be modeled as a QAP. In some embodiments, modeling the weighted graph as a QAP may involve generating a first matrix (e.g., a flow matrix) that quantifies the connections between nodes and a second matrix (e.g., a distance matrix) that quantifies the distances between the nodes. In these and other embodiments, weight values ​​assigned to edges based on gate depth may be taken into account to adjust one or more elements of the first and / or second matrices used to model the QAP. For example, the QAP may be represented by equation (5) described in connection with the operating environment 100 of FIG. 1.

[0053] Additionally or alternatively, the weighted graph may be modeled as a QBP that specifies binary constraints on one or more variables involved in the optimization problem. For example, the QBP may be represented by equation (6) described in conjunction with the operating environment 100 of FIG. 1.

[0054] In block 310, an initial qubit mapping may be determined based on a solution to the QAP. In some embodiments, quantum computing techniques may be used to solve the QAP and provide one or more feasible solutions to the QAP.

[0055] Modifications, additions, or omissions may be made to method 300 without departing from the scope of the present disclosure. For example, the designation of different elements in the described manner is intended to help explain the concepts described herein and is not intended to be limiting. Additionally, method 300 may include any number of other elements or may be implemented in other systems or contexts other than those described.

[0056] 4 is a flowchart of an example method 400 of generating a QAP corresponding to a qubit graph, according to one or more embodiments of the present disclosure. Method 400 may be performed by any suitable system, apparatus, or device. For example, graphing module 120, quadratic modeling module 140, and / or QAP solver 160 of FIG. 1 may perform one or more operations associated with method 400. Although shown in discrete blocks, steps and operations associated with one or more of the blocks of method 400 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the particular implementation.

[0057] The method 400 may begin at block 402, where a first matrix may be generated that quantifies node connectivity. In some embodiments, the first matrix may be a flow matrix, such as the flow matrix described above in connection with the graphing module 120 of FIG.

[0058] A second matrix quantifying node distances may be generated at block 404. In some embodiments, the second matrix may be a distance matrix, such as the distance matrix described above in connection with graphing module 120 of FIG.

[0059] At block 406, one or more matrix elements may be adjusted based on edge weights associated with the gate depths of one or more of the qubit gates included in the quantum circuit. In some embodiments, a first qubit gate used in a first operation scheduled to be executed before a second operation involving a second qubit gate may be given a greater weight than the second qubit gate. In these and other embodiments, the weight values ​​corresponding to each qubit gate may be used to modify one or more elements of the first matrix and / or the second matrix.

[0060] At block 408, a QAP may be set up based on the weighted first and second matrices. In some embodiments, the QAP may be a QBP that includes a binary constraint, such as the QBP described with respect to equation (6) of FIG.

[0061] Modifications, additions, or omissions may be made to method 400 without departing from the scope of the present disclosure. For example, the designation of different elements in the described manner is intended to help explain the concepts described herein, and is not intended to be limiting. Additionally, method 400 may include any number of other elements or may be implemented in other systems or contexts other than those described.

[0062] 5 is a flowchart of an example method 500 of generating a graph representation of qubits of a quantum computing system, according to one or more embodiments of the present disclosure. Method 500 may be performed by any suitable system, apparatus, or device. For example, graphing module 120, quadratic modeling module 140, and / or QAP solver 160 of FIG. 1 may perform one or more operations associated with method 500. Although shown in discrete blocks, steps and operations associated with one or more of the blocks of method 500 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the particular implementation.

[0063] The method 500 may begin at block 502, where an empty graph is created. For example, an empty graph H may be created.

[0064] Nodes corresponding to the logical qubits of the quantum circuit may be added to the empty graph at block 504. For example, a particular quantum circuit may contain Q qubits, and thus a corresponding number of nodes Q may be added to the empty graph H.

[0065] Edges corresponding to the quantum gates of the quantum circuit may be added to the graph between the nodes in block 506. For example, the particular quantum circuit described in connection with block 504 may include M two-qubit gates, and thus a corresponding number of edges M may be added to the graph H.

[0066] At block 508, an edge weight may be applied for each edge of the graph. The edge weight may represent the order in which qubit gates of the quantum circuit are used in operations of the quantum circuit. For example, a particular quantum circuit configured to perform N operations may include N edge weights in the range of {1, 2, ..., N-1, N}. As an additional or alternative example, depending on how the QAP is specified (e.g., as a maximization problem rather than a minimization problem), more weights may be given to qubit gates associated with operations scheduled earlier and less weights may be given to qubit gates associated with operations scheduled later.

[0067] Modifications, additions, or omissions may be made to method 500 without departing from the scope of the present disclosure. For example, the designation of different elements in the described manner is intended to help explain the concepts described herein, and is not intended to be limiting. Additionally, method 500 may include any number of other elements or may be implemented in other systems or contexts other than those described.

[0068] 6 is a diagram of an example operating environment 600 in which qubit routing may be determined in accordance with one or more embodiments of the present disclosure. The operating environment 600 may include a path generation module 620, a scoring module 640, and / or a path selection module 660 configured to take as inputs and / or output a quantum circuit graph 610, candidate paths 630, candidate path scores 650, and / or a selected path 670.

[0069] In some embodiments, the path generation module 620, the scoring module 640, and / or the path selection module 660 (collectively referred to herein as "computing modules") may include code and routines configured to enable a computing system to perform one or more operations. Additionally or alternatively, one or more of the computing modules may be implemented using hardware, including a processor, a microprocessor (e.g., performing or controlling the execution of one or more operations), a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC). In some other cases, one or more of the computing modules may be implemented using a combination of hardware and software. In this disclosure, operations described as being performed by a computing module may include operations that the computing module may direct one or more corresponding systems to perform. The computing module may be configured to perform a set of operations with respect to the quantum circuit graph 610, the candidate paths 630, the candidate path scores 650, and / or the selected path 670. This is described in further detail below with respect to example method 800 and / or example method 900 as described with respect to Figures 8 and / or 9, respectively.

[0070] NISQ devices may include quantum circuits configured to perform computational operations. A quantum circuit may include quantum bits ("qubits") connected by gates between pairs of qubits ("two-qubit gates" or "qubit gates"), and a graph that models a quantum circuit may represent the qubits as nodes and the qubit gates as edges connecting the nodes. In some embodiments, quantum circuit graph 610 may represent the hardware architecture that corresponds to the quantum circuit. In other words, the nodes and edges included in quantum circuit graph 610 may visually represent the physical qubits and qubit gates of a corresponding quantum circuit.

[0071] The operations of the path generation module 620, the scoring module 640, and / or the path selection module 660 that result in the determination of the candidate paths 630, the candidate path scores 650, and / or the selected paths 670 describing the swap gate operations may refer to logical qubits and / or qubit gates rather than the physical hardware architecture of the quantum circuit itself. For example, a swap gate operation that swaps a position associated with a first qubit with a position associated with a second qubit may indicate that the physical second qubit may be assigned to logically perform the operation associated with the first qubit rather than swapping physical positions with the first qubit. Performing one or more swap gate operations on a quantum circuit may facilitate connecting any two qubits included in the quantum circuit through a single qubit gate.

[0072] In some embodiments, quantum circuit graph 610 may include a series of node pairs that indicate the order in which operations are scheduled to be performed by the represented quantum circuit. A particular operation of a quantum circuit may involve two qubits that are adjacent to each other and connected by a two-qubit gate (or in other words, the two qubits are "directly connected" at the target edge). However, the qubits involved in an operation may not be adjacent to each other, due to the sparse connectivity of the quantum circuit, due to a swap gate operation associated with a previous operation of the quantum circuit that shifted the logical locations of those qubits away from each other, due to some combination thereof, or any other reason.

[0073] The path generation module 620 may be configured to identify one or more candidate paths 630 between each pair of nodes representing qubits scheduled to perform an operation of a quantum circuit. A particular candidate path 630 may specify a route from a first node to a second node, and a swap gate operation may be performed thereon to move one or both of the first node and the second node until the first node and the second node are directly connected.

[0074] For example, FIG. 7A illustrates an example graph 700 including a set of candidate paths representing a candidate path 630 between two qubits of a quantum circuit. The graph 700 includes a first node 710 and a second node 720, which are not originally directly connected to each other. As illustrated, the path generation module 620 may propose three (or more) candidate paths, including a first candidate path 722, a second candidate path 724, and a third candidate path 726. As a result of performing a swap gate operation with respect to either the first node 710 or the second node 720 along the first candidate path 722, the second candidate path 724, or the third candidate path 726, the first node 710 and the second node 720 may become directly connected to each other.

[0075] In some embodiments, the route generation module 620 may be configured to generate the particular candidate route according to an example method 800 as described in connection with FIG. 8. The method 800 may be performed by any suitable system, apparatus, or device. For example, the route generation module 620, the scoring module 640, and / or the route selection module 660 of FIG. 6 may perform one or more operations associated with the method 800. Although shown in discrete blocks, the steps and operations associated with one or more of the blocks of the method 800 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the particular implementation.

[0076] Method 800 may begin at block 802, where a first node location corresponding to a first node and a second node location corresponding to a second node are determined. The first node and the second node may represent logical qubits of a quantum circuit configured to perform one or more computational operations. To perform the computational operations, the qubits corresponding to the first node and the second node may need to be directly connected to each other via a target edge between the first node and the second node.

[0077] The first node location and the second node location may be determined according to the location of the first node and the second node with respect to the physical hardware of the quantum circuit. For example, the first node location may correspond to the location of a physical qubit of the quantum circuit with which the first node is associated, and the second node location may correspond to the location of a physical qubit with which the second node is associated.

[0078] In block 804, a node directly connected to the first node may be selected. When the first node is connected to one or more neighboring nodes, a corresponding number of edges may extend from the first node to the neighboring nodes. One or more of the neighboring nodes may be selected as the node directly connected to the first node. In some embodiments, the selection of the neighboring nodes may be performed randomly such that any node adjacent to the first node is equally likely to be selected. For example, for a particular first node that includes 10 edges connecting to neighboring nodes, any of the 10 neighboring nodes may be selected with a 10 percent probability.

[0079] Additionally or alternatively, the selection of the neighboring node may be performed subject to the next step of method 800. At block 806, it may be determined whether the node position of the adjacent node is closer to the second node position than to the first node position. Determining whether the node position of the adjacent node is closer to the second node position compared to the first node position may be performed by calculating a first distance between the first node position and the second node position and a second distance between the adjacent node position and the second node position. In response to determining that the second distance is greater than the first distance (i.e., the adjacent node position is farther from the second node position compared to the first node position), the adjacent node may be discarded from consideration as being part of a candidate path between the first node and the second node.

[0080] In block 808, in response to determining that the second distance is less than the first distance (i.e., the adjacent node position is closer to the second node position than the first node position), the first node may be moved to a node position corresponding to the adjacent node. Whether an adjacent node may be selected as part of a candidate path according to the steps described with respect to blocks 804, 806, and 808 may be represented by the following quantitative relationship: min{0,d(i,v)-d(j,v)} (10) Statement (10) describes a proportional probability for determining whether to include a particular neighboring node as part of a particular candidate path. In response to a first distance d(i,v) between a first node position i and a second node position v being less than a second distance d(j,v) between a neighboring node position j and a second node position v, statement (10) indicates that the proposed neighboring node position is farther from the second node position than the first node position. As a result, the proposed neighboring node position and the corresponding neighboring node may be rejected. In response to the first distance being greater than the second distance, statement (10) indicates that the proposed neighboring node position is closer to the second node position than the first node position. As a result, the proposed neighboring node position and the corresponding neighboring node may be accepted as part of a particular candidate path.

[0081] The method 800 may be iteratively repeated at step 810 to include additional adjacent nodes and increase the length of the candidate path. For example, as shown in FIG. 7A, the distance between the first node 710 and the second node 720 along the first candidate path 722, the second candidate path 724, or the third candidate path 726 includes six additional nodes. In other words, six swap gate operations would be used to position the first node 710 adjacent to the second node 720 according to the first candidate path 722, the second candidate path 724, or the third candidate path 726.

[0082] At block 812, a complete candidate path may be specified. In some embodiments, the candidate path may be considered a complete candidate path after iteratively performing method 800 at blocks 802, 804, 806, and 808, and step 810, where the length of the candidate path corresponds to the distance between the first node and the second node. In these and other embodiments, the operations associated with method 800 may be performed to generate any number of candidate paths. For example, the number of candidate paths to be generated may be specified by a user, and the operations of method 800 may be performed iteratively to generate a set of candidate paths that includes the number of candidate paths specified by the user. As an additional or alternative example, the operations of method 800 may be performed iteratively until a newly generated candidate path is identical to an existing candidate path already included in the set of generated candidate paths.

[0083] Modifications, additions, or omissions may be made to method 800 without departing from the scope of the present disclosure. For example, the designation of different elements in the described manner is intended to help explain the concepts described herein and is not intended to be limiting. Additionally, method 800 may include any number of other elements or may be implemented in other systems or contexts other than those described.

[0084] Returning to the description of FIG. 6, the candidate path 630 may be obtained by the scoring module 640, and the scoring module 610 may output a candidate path score 650. The particular candidate path score 650 may describe how well a pair including the particular candidate path 630 and a particular edge along the particular candidate path 630 satisfies an optimization constraint. The optimization constraint may include, for example, reducing the number of swap gate operations used to directly connect two qubits, as described in further detail below with respect to equation (11). Additionally or alternatively, the optimization constraint may include performing swap gate operations in a manner that facilitates a particular direct connection between two qubits that does not increase the number of swap gate operations used to directly connect qubits involved in future operations. A particular pair including a particular candidate path 630 and a particular edge calculated as having a greater candidate path score 650 may provide a more efficient route between a first node and a second node than another pair having a lower candidate path score 650.

[0085] For example, FIG. 7B illustrates a graph 700 showing a particular pair including a particular candidate path that is the same as a third candidate path 726 and an edge 740 included in the particular candidate path 726 that connects two qubits in a quantum computing system. The candidate path 726 may represent one route along which a first qubit 710 and a second qubit 720 may be moved. As illustrated in FIG. 2B, a particular edge 740 along the candidate path 726 may be selected as an edge 240 that directly connects a first node 710 and a second node 720. For the edge 740 to directly connect the two nodes, the first node 710 may be moved to a first node location 730 and the second node 720 may be moved to a second node location 735, with the edge 740 connecting the first node location 730 and the second node location 735. Although edge 740 is shown to appear equidistant between the first node 710 and the second node 720, edge 740 may be located at any edge between the first node 710 and the second node 720, resulting in different pairs involving candidate path 726 and different edges.

[0086] Returning to the discussion of FIG. 6, in some embodiments, candidate path score 650 may be weighted with respect to the order in which operations of a quantum circuit are executed. A first operation scheduled to execute earlier than a second operation of a quantum circuit may be given a greater weight because routing a qubit for the first operation may affect how a qubit is routed for the second operation. Additionally or alternatively, candidate path score 650 may take into account the distance between two or more nodes involved in a subsequent operation of the quantum circuit after routing a previous pair of nodes because it may be desirable to reduce the distance between two or more nodes involved in a subsequent operation while routing a qubit associated with an earlier scheduled operation.

[0087] In these and other embodiments, the scoring module 640 may be configured to calculate the candidate path score 650 according to the following formula:

number

[0088] Prioritization factor λ w(gk) is a fundamental value λ, greater than 0 and less than 1, and an integer exponent w(g k ), so that earlier scheduled operations may be given a larger prioritization factor, while later scheduled operations may be given a smaller prioritization factor as the exponent increases. Thus, a candidate path score 650 corresponding to a pair including a particular candidate path 630 and a particular edge that involves an earlier scheduled operation (e.g., the first operation of the quantum circuit's 50 scheduled operations) may be scored higher than a pair that involves a later scheduled operation (e.g., the 50th operation).

[0089] The path selection module 660 may be configured to select a particular pair of candidate paths and edges based on the candidate path scores 650 calculated by the scoring module 640. Depending on whether a higher candidate path score indicates a more efficient qubit routing or a lower candidate path score indicates a more efficient qubit routing, the selection of a particular pair of candidate paths and edges may be based on selecting a particular pair of candidate paths and edges that includes a maximum and / or minimum candidate path score.

[0090] In some embodiments, the path selection module 660 may output the selected path 670 according to the following formula:

number

[0091] The selected path 670 may include a path included in the set of candidate paths 630 output by the path generation module 620 and a target edge included in the selected path. The target edge may indicate which edge along the selected path 670 is designated as an edge that directly connects a first node and a second node that are routed along the selected path 670. Thus, the selected path 670 may specify how to perform a swap gate operation for both the first node and the second node such that the two nodes are directly connected.

[0092] In some embodiments, the path generation module 620, the scoring module 640, and the path selection module 660 may iteratively perform operations based on the number of operations that the quantum circuit to which the quantum circuit graph 610 pertains is configured to perform. For example, after determining a selected path 670 for a first node and a second node configured to perform a first operation of the quantum circuit, the path generation module 620, the scoring module 640, and the path selection module 660 may determine paths and target edges corresponding to a third node and a fourth node configured to perform a second operation of the quantum circuit. The environment 600 may facilitate determining the selected path 670 representing a route for each pair of qubits configured to perform a particular set of operations scheduled by the quantum circuit.

[0093] Modifications, additions, or omissions may be made to environment 600 without departing from the scope of the present disclosure. For example, the designation of different elements in the manner described is intended to help explain the concepts described herein and is not intended to be limiting. For example, in some embodiments, quantum circuit graph 610, candidate paths 630, candidate path scores 650, and / or selected paths 670 are depicted in the particular manner described to help explain the concepts described herein, but such depictions are not intended to be limiting. Additionally, environment 600 may include any number of other elements or be implemented in other systems or contexts other than those described.

[0094] 9 is a flowchart of an example method 900 of determining qubit routing in accordance with one or more embodiments of the present disclosure. Method 900 may be performed by any suitable system, apparatus, or device. For example, path generation module 620, scoring module 640, and / or path selection module 660 of FIG. 6 may perform one or more operations associated with method 900. Although shown in discrete blocks, steps and operations associated with one or more of the blocks of method 900 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the particular implementation.

[0095] Method 900 may begin at block 902, where a graph representing a quantum circuit may be obtained. The graph may include nodes representing qubits of the quantum circuit and edges representing qubit gates connecting those qubits. In some embodiments, the graph may represent a physical architecture of the quantum circuit that includes physical qubits and connects qubit gates between the physical qubits. Additionally or alternatively, the graph may represent a logical representation of the quantum circuit corresponding to the physical architecture in which positions associated with the qubits may be logically swapped. For example, a first physical qubit may be configured to logically perform an operation corresponding to a second physical qubit, which may be represented in the graph by swapping the position of a first node corresponding to the first physical qubit with the position of a second node corresponding to the second physical qubit without swapping the physical positions of the qubits.

[0096] At block 904, a first set of candidate paths between the first node and the second node may be generated. The candidate paths in the first set of candidate paths may specify paths along which the first node and the second node travel to reach a target edge between the first node and the second node.

[0097] At block 906, a first score corresponding to one or more first pairs may be calculated, each first pair representing a particular first candidate path and a particular target edge included in the particular first candidate path. The particular first score may indicate how efficiently each first pair routes the first node to a target edge that directly connects to the second node. In some embodiments, the first score may be weighted with respect to the order in which operations of a quantum circuit including a qubit corresponding to the first node and a qubit corresponding to the second node are performed, with earlier operations of the quantum circuit being given a greater weight than later operations of the quantum circuit.

[0098] A first pair corresponding to the highest first score may be selected in block 908. The selected first pair may specify a particular path of nodes in the graph of the quantum circuit along which a swap gate operation may be performed to logically move the first node and / or the second node to positions adjacent to each other via a particular target edge.

[0099] At block 910, the steps described with respect to blocks 902, 904, 906, and 908 may be repeated until the qubits associated with the last operation of the quantum circuit have been routed. Performing the steps described with respect to method 900 at blocks 902, 904, 906, and 908 may facilitate determining a route between a first qubit and a second qubit of a quantum circuit and determining how to perform one or more swap gate operations on the first qubit and the second qubit to position the two qubits adjacent to one another along a target edge. Iteratively performing the steps of method 900 for each operation scheduled to be performed by the quantum circuit may facilitate the routing and positioning of some or all of the qubits involved in performing the operations of the quantum circuit.

[0100] Modifications, additions, or omissions may be made to method 900 without departing from the scope of the present disclosure. For example, the designation of different elements in the described manner is intended to help explain the concepts described herein, and is not intended to be limiting. Additionally, method 900 may include any number of other elements or may be implemented in other systems or contexts other than those described.

[0101] 10 is an exemplary computer system 1000 according to one or more embodiments of the present disclosure. The computing system 1000 may include a processor 610, a memory 1020, a data storage 1030, and / or a communication unit 1040, all of which may be communicatively coupled. Any or all of the environment 100 of FIG. 1 and / or the environment 600 of FIG. 6 may be implemented as a computing system consistent with the computing system 1000.

[0102] In general, the processor 1010 may include any suitable special purpose or general purpose computer, computing entity, or processing device including various computer hardware or software modules and may be configured to execute instructions stored on any applicable computer-readable storage medium. For example, the processor 1010 may include a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other digital or analog circuitry configured to interpret and / or execute program instructions and / or process data.

[0103] 10 as a single processor, it is understood that the processor 1010 may include any number of processors distributed across any number of networks or physical locations configured to individually or collectively perform any number of operations described in this disclosure. In some embodiments, the processor 1010 may interpret and / or execute program instructions and / or process data stored in the memory 1020, the data storage 1030, or the memory 1020 and the data storage 1030. In some embodiments, the processor 1010 may fetch program instructions from the data storage 1030 and load the program instructions into the memory 1020.

[0104] After the program instructions are loaded into the memory 1020, the processor 1010 may execute the program instructions, such as instructions that cause the computing system 1000 to perform the operations of method 300 of FIG. 3, method 400 of FIG. 4, method 500 of FIG. 5, method 800 of FIG. 8, and / or method 900 of FIG. 9. For example, the computing system 1000 may execute the program instructions to obtain a quantum circuit, generate a graph representation of the quantum circuit, assign weight values ​​to edges in the graph, model the weighted graph representing the quantum circuit as a QAP, and / or determine an initial qubit mapping based on a solution to the QAP. As additional or alternative examples, the computing system 1000 may execute the program instructions to obtain a graph representing the quantum circuit, generate a first set of candidate paths, calculate a first score for a first pair in the first set of candidate paths, and / or select the first pair corresponding to the highest first score.

[0105] The memory 1020 and data storage 1030 may include a computer-readable storage medium or one or more computer-readable storage media for storing computer-executable instructions or data structures. Such computer-readable storage media may be any available medium that may be accessed by a general-purpose or special-purpose computer, such as the processor 1010. For example, the memory 1020 and / or data storage 1030 may include the quantum circuit 110, weighted graph 130, QAP 150, and / or qubit mapping 170 of FIG. 1. As additional or alternative examples, the memory 1020 and / or data storage 1030 may include the quantum circuit graph 610, candidate paths 630, candidate path scores 650, and / or selected path 670 of FIG. 6. In some embodiments, the computing system 1000 may or may not include any of the memory 1020 and data storage 1030.

[0106] By way of example, and not limitation, such computer-readable storage media may include non-transitory computer-readable storage media including random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory devices (e.g., solid-state memory devices), or any other storage medium that can be used to store desired program code in the form of computer-executable instructions or data structures and that can be accessed by a general-purpose or special-purpose computer. Combinations of the above may also be included within the scope of computer-readable storage media. Computer-executable instructions may include, for example, instructions and data configured to cause the processor 1010 to perform a certain operation or group of operations.

[0107] The communication unit 1040 may include any component, device, system, or combination thereof configured to transmit or receive information over a network. In some embodiments, the communication unit 1040 may communicate with other devices at other locations, at the same location, or even other components in the same system. For example, the communication unit 1040 may include a modem, a network card (wireless or wired), an optical communication device, an infrared communication device, a wireless communication device (such as an antenna), and / or a chipset (such as a Bluetooth device, an 802.6 device (e.g., a metropolitan area network (MAN)), a WiFi device, a WiMax device, a cellular communication facility, etc.). The communication unit 1040 may enable data to be exchanged with a network and / or any other device or system described in this disclosure. For example, the communication unit 1040 may allow the system 1000 to communicate with other systems, such as computing devices and / or other networks.

[0108] Those skilled in the art, after reviewing this disclosure, may recognize that modifications, additions, or omissions may be made to system 1000 without departing from the scope of the disclosure. For example, system 1000 may include more or fewer components than explicitly illustrated and described.

[0109] The foregoing disclosure is not intended to limit the disclosure to the precise form or specific field of use disclosed. Thus, various alternative embodiments and / or modifications to the disclosure are contemplated in light of the disclosure, whether expressly described or implied herein. Although embodiments of the disclosure have been thus described, it will be recognized that changes can be made in form and details without departing from the scope of the disclosure. Thus, the disclosure is limited only by the scope of the claims.

[0110] In some embodiments, the different components, modules, engines, and services described herein may be implemented as objects or processes (e.g., as separate threads) executing on a computing system. Although some of the systems and processes described herein are generally described as being implemented in software (stored and / or executed on general-purpose hardware), specific hardware implementations, or combinations of software and specific hardware implementations, are also possible and contemplated.

[0111] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open terms" (e.g., the term "including" should be interpreted as "including, but not limited to").

[0112] Furthermore, if a specific number of claim recitations to be introduced is intended, such intent is expressly stated in the claim, and in the absence of such a statement, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation with the indefinite article "a" or "an" limits any particular claim that includes such an introduced claim recitation to an embodiment that includes only one such recitation, even if the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"). The same applies to the use of definite articles used to introduce claim recitations.

[0113] In addition, even when a particular number of introduced claim recitations is explicitly recited, one of ordinary skill in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the recitation "two recitations" without other modifiers means at least two recitations, or more than two recitations). Furthermore, when idiomatic expressions similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, such constructions are generally intended to include A only, B only, C only, both A and B, both A and C, both B and C, or all of A, B, and C, etc.

[0114] Moreover, any disjunctive phrase preceding two or more alternative terms, whether in the present document, claims, or drawings, should be understood to contemplate the possibility of including one of those terms, either of those terms, or both of those terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0115] All examples and conditional language described in this disclosure are intended for educational purposes to help the reader understand the concepts contributed by the inventor to further the art, and should be interpreted without limitation to such specifically described examples and conditions. Although the embodiments of the present disclosure have been described in detail, various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

[0116] The following supplementary notes are further disclosed regarding the embodiments including the above examples. (Appendix 1) obtaining a graph including a plurality of nodes and a plurality of edges, a first node of the plurality of nodes representing a first qubit of a quantum circuit and a second node of the plurality of nodes representing a second qubit of the quantum circuit; generating a set of first candidate paths between the first node and the second node along one or more edges of the plurality of edges, each first candidate path in the set of first candidate paths specifying a path along which the first node and the second node travel to arrive adjacent to one another at a target edge directly connecting the first node and the second node; calculating first scores for a plurality of first path pairs, each first score indicating how efficiently a respective first path pair of the plurality of first path pairs routes the first node to the second node via the target edge; a particular first path pair of the plurality of first path pairs includes a particular first candidate path and a particular target edge on the particular first candidate path between the first qubit and the second qubit; the first score is weighted with respect to the order in which operations of the quantum circuit including the first qubit and the second qubit are performed, with earlier operations being given greater weight than later operations. stages and; selecting the first path pair corresponding to a highest first score for routing the first node to the second node via the target edge; method. (Appendix 2) identifying a third node corresponding to a third qubit and a fourth node corresponding to a fourth qubit, the third qubit and the fourth qubit configured to perform a second operation after a first operation performed by the first qubit and the second qubit; generating a set of second candidate paths between the third node and the fourth node along one or more of the edges of the graph, each second candidate path in the set of second candidate paths specifying a path along which the third node and the fourth node travel to reach a target edge between the third node and the fourth node; calculating second scores for a plurality of second path pairs, each second score indicating how efficiently a respective second path pair of the plurality of second path pairs routes the third node to the fourth node via the target edge; selecting the second path pair corresponding to the highest second score for routing the third node to the fourth node via the target edge. The method described in Appendix 1. (Appendix 3) 3. The method of claim 2, further comprising repeating the steps of the method of claim 2 until a node associated with a qubit used in a final operation of the quantum circuit has been routed. (Appendix 4) Generating a particular candidate route from the set of candidate routes comprises: A) determining a first node location corresponding to the first node and a second node location corresponding to the second node; B) identifying a fifth node directly connected to the first node, the fifth node having a fifth node position adjacent to the first node position; C) determining whether the fifth node location is closer to the second node location than the first node location; D) in response to determining that the fifth node location is closer to the second node location than the first node location, setting the first node location as the fifth node location; and E) iteratively repeating steps B), C), and D) until the first node location is adjacent to the second node location. The method described in Appendix 1. (Appendix 5) 2. The method of claim 1, wherein calculating the first scores for the plurality of first pairs is based on an order in which the operations of the quantum circuit involving the first node and the second node are scheduled to be performed and a distance between nodes involved in a subsequent operation of the quantum circuit after routing through the first node and the second node. (Appendix 6) Calculating the first scores for the plurality of first pairs includes:

number

number

number

[0117] 110 Quantum circuit 120 Graphing Module 130 Weighted Graphs 140 Secondary Modeling Module 150 Quadratic Assignment Problems 160 QAP Solver 170 Cubit Mapping Get 302 quantum circuits 304 Generate a graph representation of a quantum circuit 306 Assigning weight values ​​to edges 308 Modeling a weighted graph representing a quantum circuit as a quadratic assignment problem (QAP) Determine the initial qubit mapping based on the solution to 310 QAP 402 Generate the first matrix to quantify node connectivity 404 Generate a second matrix that quantifies node distances 406 Adjust matrix elements based on edge weights 408 Set up the QAP based on the weighted first matrix and the weighted second matrix 502 Create an empty graph 504 Add a node corresponding to a logical qubit to the graph Added edges corresponding to quantum gates between 506 qubits 508 Add edge weight for each edge of the graph 610 Quantum circuit 620 Route Generation Module 630 candidate routes 640 Scoring Module 650 Candidate Path Score 660 Routing Module 670 Selected Routes 802 Determine the first node position and the second node position 804 Select the nodes directly connected to the first node 806 Determine whether the node position of the adjacent node is closer to the second node position than to the first node position. 808 Move the first node to the node position of the adjacent node 810 Specify complete candidate route 902 Obtain a graph representing a quantum circuit 904 Generate the first set of candidate routes 906 Calculate a first score for a first pair in the first set of candidate paths. 908 Select the first pair that corresponds to the highest first score 910 Iterate through the steps until the qubit associated with the last operation of the quantum circuit is routed. 1000 Systems 1010 Processor 1020 Memory 1030 Data Storage 1040 Communication unit

Claims

1. obtaining a graph including a plurality of nodes and a plurality of edges, a first node of the plurality of nodes representing a first qubit of a quantum circuit and a second node of the plurality of nodes representing a second qubit of the quantum circuit; generating a set of first candidate paths between the first node and the second node along one or more edges of the plurality of edges, each first candidate path in the set of first candidate paths specifying a path along which the first node and the second node travel to arrive adjacent to one another at a target edge directly connecting the first node and the second node; calculating first scores for a plurality of first path pairs, each first score indicating how efficiently a respective first path pair of the plurality of first path pairs routes the first node to the second node via the target edge; a particular first path pair of the plurality of first path pairs includes a particular first candidate path and a particular target edge on the particular first candidate path between the first qubit and the second qubit; the first score is weighted with respect to the order in which operations of the quantum circuit including the first qubit and the second qubit are performed, with earlier operations being given greater weight than later operations. Stages and; selecting the first path pair corresponding to the highest first score for routing the first node to the second node via the target edge. method.

2. identifying a third node corresponding to a third qubit and a fourth node corresponding to a fourth qubit, the third qubit and the fourth qubit configured to perform a second operation after a first operation performed by the first qubit and the second qubit; generating a set of second candidate paths between the third node and the fourth node along one or more of the edges of the graph, each second candidate path in the set of second candidate paths specifying a path along which the third node and the fourth node travel to reach a target edge between the third node and the fourth node; calculating second scores for a plurality of second path pairs, each second score indicating how efficiently a respective second path pair of the plurality of second path pairs routes the third node to the fourth node via the target edge; selecting the second path pair corresponding to the highest second score for routing the third node to the fourth node via the target edge. The method of claim 1.

3. 3. The method of claim 2, further comprising repeating the steps of the method of claim 2 until a node associated with a qubit used in a final operation of the quantum circuit has been routed.

4. Generating a particular candidate route from the set of candidate routes comprises: A) determining a first node location corresponding to the first node and a second node location corresponding to the second node; B) identifying a fifth node directly connected to the first node, the fifth node having a fifth node position adjacent to the first node position; C) determining whether the fifth node location is closer to the second node location than the first node location; D) in response to determining that the fifth node location is closer to the second node location than the first node location, setting the first node location as the fifth node location; and E) iteratively repeating steps B), C), and D) until the first node location is adjacent to the second node location. The method of claim 1.

5. 2. The method of claim 1 , wherein calculating the first scores for the plurality of first pairs is based on an order in which the operations of the quantum circuit involving the first node and the second node are scheduled to be performed and a distance between nodes involved in a subsequent operation of the quantum circuit after routing through the first node and the second node.

6. Calculating the first scores for the plurality of first pairs includes: [0010] It is expressed as δ G (e,p) represents a particular first score; S(g i , e, p) is the path from the first node g to the second node g via a particular candidate path p. i represents the number of swap gates used to route to the second node e; λ w(gk) represents a priority factor based on the order in which the operations of the quantum circuit are scheduled to be executed; d gi,e,p (g k ) represents the distance between nodes after routing the first node to the second node along the particular candidate path; The method according to claim 5.

7. One or more non-transitory computer-readable storage media configured to store instructions that, in response to being executed, cause a system to perform operations, such as: obtaining a graph including a plurality of nodes and a plurality of edges, a first node of the plurality of nodes representing a first qubit of a quantum circuit and a second node of the plurality of nodes representing a second qubit of the quantum circuit; generating a set of first candidate paths between the first node and the second node along one or more edges of the plurality of edges, each first candidate path in the set of first candidate paths specifying a path along which the first node and the second node travel to arrive adjacent to one another at a target edge directly connecting the first node and the second node; calculating first scores for a plurality of first path pairs, each first score indicating how efficiently a respective first path pair of the plurality of first path pairs routes the first node to the second node via the target edge; a particular first path pair of the plurality of first path pairs includes a particular first candidate path and a particular target edge on the particular first candidate path between the first qubit and the second qubit; the first score is weighted with respect to the order in which operations of the quantum circuit including the first qubit and the second qubit are performed, with earlier operations being given greater weight than later operations. Stages and; selecting the first path pair corresponding to the highest first score for routing the first node to the second node via the target edge. One or more non-transitory computer-readable storage media.

8. The act of: identifying a third node corresponding to a third qubit and a fourth node corresponding to a fourth qubit, the third qubit and the fourth qubit configured to perform a second operation after a first operation performed by the first qubit and the second qubit; generating a set of second candidate paths between the third node and the fourth node along one or more of the edges of the graph, each second candidate path in the set of second candidate paths specifying a path along which the third node and the fourth node travel to reach a target edge between the third node and the fourth node; calculating second scores for a plurality of second path pairs, each second score indicating how efficiently a respective second path pair of the plurality of second path pairs routes the third node to the fourth node via the target edge; selecting the second path pair corresponding to the highest second score for routing the third node to the fourth node via the target edge. One or more non-transitory computer-readable storage media as recited in claim 7.

9. 10. The one or more non-transitory computer-readable storage media of claim 8, further comprising repeating the steps of the method of claim 8 until a node associated with a qubit used in a final operation of the quantum circuit has been routed.

10. Generating a particular candidate route from the set of candidate routes comprises: A) determining a first node location corresponding to the first node and a second node location corresponding to the second node; B) identifying a fifth node directly connected to the first node, the fifth node having a fifth node position adjacent to the first node position; C) determining whether the fifth node location is closer to the second node location than the first node location; D) in response to determining that the fifth node location is closer to the second node location than the first node location, setting the first node location as the fifth node location; repeating steps B), C), and D) iteratively until the first node location is adjacent to the second node location. One or more non-transitory computer-readable storage media as recited in claim 7.

11. 8. The one or more non-transitory computer-readable storage media of claim 7, wherein calculating the first scores for the plurality of first pairs is based on an order in which the operations of the quantum circuit involving the first node and the second node are scheduled to be performed and a distance between nodes involved in a subsequent operation of the quantum circuit after routing through the first node and the second node.

12. Calculating the first scores for the plurality of first pairs includes: [0025] It is expressed as δ G (e,p) represents a particular first score; S(g i , e, p) is the path from the first node g to the second node g via a particular candidate path p. i represents the number of swap gates used to route to the second node e; λ w(gk) represents a priority factor based on the order in which the operations of the quantum circuit are scheduled to be executed; d gi,e,p (g k ) represents the distance between nodes after routing the first node to the second node along the particular candidate path; 12. One or more non-transitory computer-readable storage media as recited in claim 11.

13. one or more processors; and one or more non-transitory computer-readable storage media configured to store instructions that, in response to being executed, cause the system to perform operations, including: obtaining a graph including a plurality of nodes and a plurality of edges, a first node of the plurality of nodes representing a first qubit of a quantum circuit and a second node of the plurality of nodes representing a second qubit of the quantum circuit; generating a set of first candidate paths between the first node and the second node along one or more edges of the plurality of edges, each first candidate path in the set of first candidate paths specifying a path along which the first node and the second node travel to arrive adjacent to one another at a target edge directly connecting the first node and the second node; calculating first scores for a plurality of first path pairs, each first score indicating how efficiently a respective first path pair of the plurality of first path pairs routes the first node to the second node via the target edge; a particular first path pair of the plurality of first path pairs includes a particular first candidate path and a particular target edge on the particular first candidate path between the first qubit and the second qubit; the first score is weighted with respect to the order in which operations of the quantum circuit including the first qubit and the second qubit are performed, with earlier operations being given greater weight than later operations. Stages and; selecting the first path pair corresponding to the highest first score for routing the first node to the second node via the target edge. system.

14. The act of: identifying a third node corresponding to a third qubit and a fourth node corresponding to a fourth qubit, the third qubit and the fourth qubit configured to perform a second operation after a first operation performed by the first qubit and the second qubit; generating a set of second candidate paths between the third node and the fourth node along one or more of the edges of the graph, each second candidate path in the set of second candidate paths specifying a path along which the third node and the fourth node travel to reach a target edge between the third node and the fourth node; calculating second scores for a plurality of second path pairs, each second score indicating how efficiently a respective second path pair of the plurality of second path pairs routes the third node to the fourth node via the target edge; selecting the second path pair corresponding to the highest second score for routing the third node to the fourth node via the target edge. The system of claim 13.

15. 15. The system of claim 14, further comprising repeating the steps of the method of claim 14 until a node associated with a qubit used in a final operation of the quantum circuit has been routed.

16. Generating a particular candidate route from the set of candidate routes comprises: A) determining a first node location corresponding to the first node and a second node location corresponding to the second node; B) identifying a fifth node directly connected to the first node, the fifth node having a fifth node position adjacent to the first node position; C) determining whether the fifth node location is closer to the second node location than the first node location; D) in response to determining that the fifth node location is closer to the second node location than the first node location, setting the first node location as the fifth node location; repeating steps B), C), and D) iteratively until the first node location is adjacent to the second node location. The system of claim 13.

17. 14. The system of claim 13, wherein calculating the first scores for the plurality of first pairs is based on an order in which the operations of the quantum circuit involving the first node and the second node are scheduled to be performed and a distance between nodes involved in a subsequent operation of the quantum circuit after routing through the first node and the second node.

18. Calculating the first scores for the plurality of first pairs includes: [0030] It is expressed as δ G (e,p) represents a particular first score; S(g i , e, p) is the path from the first node g to the second node g via a particular candidate path p. i represents the number of swap gates used to route to the second node e; λ w(gk) represents a priority factor based on the order in which the operations of the quantum circuit are scheduled to be executed; d gi,e,p (g k ) represents the distance between nodes after routing the first node to the second node along the particular candidate path; 20. The system of claim 17.

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