Device for processing data to be received

Abstract

To realize a high speed of a decoding of a range coding.SOLUTION: A device contains an expansion circuit for decoding a N-bit column by expanding one part or a whole part of an input code compressed on the basis of a range coding. N is an integer number that is larger than 1, and K expresses each integer number from 1 to N. A bit value of K-th bit of the input code is decoded on the basis of a bit history of the bit before the K-th bit. The expansion circuit executes each calculation of a plurality of candidate bits to a plurality of bits on the basis of a plurality of bit histories that may have a bit before the K-th bit for a candidate bit value of the bit in N-bit column.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a technique for decoding input codes that have been compressed based on range codes. [Background technology]

[0002] Storage systems, which are information devices for storing and managing large amounts of data, can reduce the cost per unit of capacity by storing more data. For this reason, some storage systems are equipped with a function to compress written data before storing it on the disk drive.

[0003] For example, in recent years, solid state drives (SSDs) equipped with NAND flash memory, a non-volatile semiconductor memory, have been adopted as storage media in storage systems in addition to or instead of hard disk drives (HDDs). SSDs do not have a physical head seek mechanism for data access like HDDs, so they have less head-seeking delay (latency) and excellent response performance in random data reads.

[0004] For this reason, in applications such as databases that require high-speed random reads, storage systems are increasingly replacing HDDs with SSDs as the storage medium. However, although the bit cost of SSDs is becoming cheaper every year as flash memory cells become more highly integrated, it still remains about three times higher than the bit cost of HDDs.

[0005] Therefore, many storage systems that use SSDs as storage media have adopted lossless compression technology and are equipped with a function to reduce the size of data stored in the SSD, which makes the system's storage capacity appear virtually larger, lowering the cost per capacity and bringing it closer to that of storage systems that use HDDs as storage media.

[0006] When a storage system receives a read request for compressed data from a host, the storage system decompresses the compressed data and returns it to the original plain data before returning it to the host. It is preferable to perform the decompression process of the compressed data as quickly as possible so that the read response time is not significantly worse than when reading uncompressed data.

[0007] The higher the compression ratio of the compression algorithm used in the data compression function of a storage system, the lower the cost per capacity. The LZMA algorithm is a lossless data compression algorithm known for its high compression ratio. This algorithm combines sliding dictionary compression with arithmetic coding called range coding.

[0008] Range coding requires a multiplication every time one bit is input (when encoding) or output (when decoding). Therefore, the bit rate of range coding is very slow. A table is referenced to get the value used for multiplication in range coding, and the index used for reference is determined by the bit history of the input (when encoding) or output (when decoding). If the multiplication in range coding can be performed in parallel for multiple bits, the performance will improve, and the processing performance of the LZMA algorithm will improve.

[0009] Regarding the range code encoding process (at the time of compression), there is a known technique for speeding up the process by preparing bit history in advance, parallelizing table lookups, and performing multiplications for multiple bits in parallel, as described in Non-Patent Document 1. If the degree of parallelism is N, then the encoding performance is improved by N times. This makes it possible to speed up the LZMA compression process. [Prior art documents] [Non-patent literature]

[0010] [Non-Patent Document 1] “A Parallel Adaptive Range Coding Compressor: Algorithm, FPGA Prototype, Evaluation”, Ivan Shcherbakov and Norbert Wehn, Data Compression Conference, 2012. Summary of the Invention [Problem to be solved by the invention]

[0011] When decoding range codes (during decompression), it is difficult to perform table lookup and multiplication using the lookup value in parallel for multiple bits because the bit history is uncertain until the previous bit is decoded.

[0012] Therefore, for example, when range coding is applied to the compression and decompression function of a storage system, the decompression performance is low, so that the read response time to a read request from the host increases, which may reduce the convenience of the storage system. [Means for solving the problem]

[0013] One aspect of the present invention is an apparatus for processing received data, comprising an decompression circuit that decompresses part or all of an input code compressed based on a range code to decode an N-bit string, where N is an integer greater than 1 and K represents an integer from 1 to N, and the bit value of the Kth bit of the input code is decoded based on the bit history of the bit preceding the Kth bit, and the decompression circuit calculates, for a plurality of bits, a plurality of candidate bit values ​​for the bits of the N-bit string based on a plurality of possible bit histories of the bits preceding the Kth bit. Effect of the Invention

[0014] According to one aspect of the present invention, the decoding of range codes can be accelerated. [Brief description of the drawings]

[0015] [Figure 1] 1 illustrates an example of the configuration of a storage system. [Figure 2A] This gives an overview of the LZMA algorithm. [Figure 2B] A specific example of dictionary compression processing will be described. [Figure 3A] FIG. 2 shows a functional block diagram of range encoding. [Figure 3B] FIG. 2 shows a functional block diagram of range decoding. [Figure 4A] An example will be given to explain the principle of range coding. [Figure 4B] Another example will be given to explain the principle of range codes. [Figure 5A] 1 shows a flowchart of a range encoding process. [Figure 5B] 1 shows a flowchart of a range decoding process. [Figure 6] FIG. 1 shows a functional block diagram of a method for increasing the speed of range encoding processing. [Figure 7] 1 shows a flowchart of a method for increasing the speed of range encoding processing. [Figure 8] FIG. 1 shows a functional block diagram of a method for increasing the speed of range decoding processing. [Figure 9] 1 shows a flowchart of a method for increasing the speed of range decoding processing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] In the following, when necessary for convenience, the description will be divided into multiple sections or examples, but unless otherwise specified, they are not unrelated to each other, and one is related to the other as a partial or complete modification, detail, supplementary explanation, etc. Furthermore, in the following, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited in principle to a specific number, etc.

[0017] (1) System Configuration In the following, a storage system having a data compression function will be described as an embodiment of this specification. The storage system reduces the amount of stored data by lossless compression. The decoding of the range code described in this specification can be applied to a system other than the storage system, for example, a communication system.

[0018] 1 shows an example of the configuration of a storage system according to an embodiment of this specification. The storage system 101 includes a host I / F (Interface) 102, a storage controller 103, multiple SSDs (Solid State Drives) 105, and a cache memory 106 that uses a volatile memory such as a DRAM (Dynamic Random Access Memory).

[0019] The storage controller 103 is connected to the host I / F 102, SSD 105, and cache memory 106, and includes a microprocessor that controls them. The microprocessor interprets the contents of read / write commands from a host (not shown), transmits and receives data to and from the host, compresses and decompresses data using the LZMA compression / decompression circuit 104, and transfers data between the SSD 105 and the cache memory 106.

[0020] The host I / F 102 is an interface mechanism for connecting to an external host, and responds to read / write commands in order to send data to the host and receive data from the host. The mechanism of the host I / F 102 and the protocol for sending and receiving commands and data comply with, for example, a standard interface specification.

[0021] The storage controller 103 includes an LZMA compression / decompression circuit 104 and a transfer circuit 108. The transfer circuit 108 receives and transmits data compressed or decompressed by the LZMA compression / decompression circuit 104. The transfer circuit 108 transfers data between components of the storage system 101, for example, between the LZMA compression / decompression circuit 104 and the cache memory 106. In order to reduce the amount of data stored in the SSD 105, which is a storage drive, the LZMA compression / decompression circuit 104 reversibly compresses write data received in response to a write command to generate compressed data. Also, in order to transmit the original plain data to the host in response to a read command, the LZMA compression / decompression circuit 104 decompresses the compressed data read from the SSD 105 to generate plain data.

[0022] The write data from the host is first temporarily stored in the cache memory 106. At this point, the storage controller 103 returns a write completion to the host. The data is then converted into compressed data via the LZMA compression / decompression circuit 104, and the compressed data is also temporarily stored in the cache memory 106. The compressed data is then written to the SSD 105.

[0023] On the other hand, read data to the host is read in a compressed state from the SSD 105 and first temporarily stored in the cache memory 106. After that, the data is converted to plain text data through the LZMA compression / decompression circuit 104, and the plain text data is also temporarily stored in the cache memory 106. The plain text data is then transmitted to the host.

[0024] In this way, since data writes execute compression processing after returning write completion, the write performance seen by the host is constant regardless of whether compression is used or not, but since data reads are not completed until data has been returned to the host, the read response performance seen by the host depends on the decompression time of the compressed data. In other words, the LZMA compression / decompression circuit 104 is required to perform high-performance decompression processing.

[0025] The LZMA compression / decompression circuit 104 is implemented as hardware (logic circuitry) designed based on a data decompression method according to an embodiment of this specification, for example. The LZMA compression / decompression circuit 104 has high-speed data decompression performance, so that the storage system 101 can utilize the high-speed random read performance, which is a feature of SSDs, not only for uncompressed data but also for compressed data. The function of the LZMA compression / decompression circuit 104 may be implemented by a plurality of processing devices that execute programs. The processing devices include a processor, a processor core, a central processing unit, and the like. A type of storage drive different from the SSD, for example, a hard disk drive (HDD), may be used.

[0026] (2) LZMA Algorithm As background knowledge for explaining the data decompression method according to an embodiment of this specification, the LZMA algorithm will be explained with reference to FIGS. 2A to 5. FIG.

[0027] (2-1) Overview of the LZMA algorithm 2A shows an overview of the LZMA algorithm. In the LZMA compression process, plain text data 201 before compression is first subjected to a dictionary compression process 202. The dictionary compression result is then subjected to a range encoding process 203. This generates LZMA compressed data 204.

[0028] On the other hand, in the LZMA decompression process, the compressed data 204 is first subjected to a range decryption process 205. The decrypted result is then subjected to a plaintext expansion process 206. This produces the original plaintext data 201.

[0029] (2-2) Dictionary compression processing 2B shows a concrete example of dictionary compression process 202 constituting the LZMA algorithm. It checks in order whether the same character string appears again in the character string stream of plaintext data 201. If a character string matches L characters consecutively from the Jth character before the first character, this character string is converted to a copy symbol [L, J].

[0030] For example, in a four-character string 211 of "b,c,d,e," there is a match for four consecutive characters starting from six characters before the first character "b." In this case, the string 211 is converted to a copy symbol [4,6]. Similarly, in a four-character string 212 of "a,b,a,b," there is a match for four consecutive characters starting from two characters before the first character "a" (including overlapping parts). In this case, the string 212 is converted to a copy symbol [4,2].

[0031] Similarly, in the four-character string 213 "c,d,e,f," there is a match for four consecutive characters starting from the first character "c" and 14 characters before. In this case, the string 213 is converted to a copy symbol [4,14]. Since the amount of data of these copy symbols is less than the amount of data of the original string, this conversion can reduce the amount of data.

[0032] The range of the string stream (hereafter referred to as the dictionary) referenced in the match search is from one character back to a specified number of characters back. Because the dictionary range slides backwards with each search, this compression technique is also called sliding dictionary compression. If there are multiple matching strings within the dictionary range, the longest consecutive matching string is converted to a copy symbol. This has the effect of further reducing the amount of data.

[0033] To generate data to be input to the subsequent range encoding process 203, it is necessary to encode the characters that have not been converted to copy symbols (hereinafter referred to as literal characters) and the copy symbols using a specified bit pattern and concatenate them to create a bit stream.

[0034] 2B shows a bit stream resulting from encoding according to the rules of the LZMA specification. This bit stream is input to range encoding process 203. For example, bit pattern 221 is 12 bits long and represents copy symbol [4,6]. Bit pattern 222 is 11 bits long and represents copy symbol [4,2]. Bit pattern 223 is 13 bits long and represents copy symbol [4,14]. In this way, the length of the bit pattern corresponding to the copy symbol is not fixed. On the other hand, a literal character is represented by a 9-bit bit pattern in which one zero bit is added to the beginning of the 8-bit value of the character.

[0035] The range decryption process 205 outputs such a bit stream in the LZMA decompression process. When the plaintext expansion process 206 receives such a bit stream, it interprets it as copy symbols or literal characters and restores the character string stream of the plaintext data 201.

[0036] (2-3) Range encoding and decoding process FIG. 3A shows a functional block diagram of range encoding, and FIG. 3B shows a functional block diagram of range decoding. The range encoding function 300 will be described with reference to FIG. 3A. The encoder 301 is a calculation block that receives input from an input bit string 302 bit by bit and generates an output code 303. In the example of FIG. 3A, the input bit string is "1, 1, 0, 1". A method for generating the output code 303 will be described in the next section with reference to FIGS. 4A and 4B. The output code 303 corresponds to the compressed data of the LZMA algorithm (the LZMA 204 compressed data in FIG. 2A).

[0037] The encoder 301 also uses as input a probability value taken from a probability table 304. The probability value P(x) indicates the probability that the next input bit from the input bit string 302 is a "0" given that the bit history 305 input so far is x.

[0038] The encoder 301 performs adaptation through learning every time it uses the probability value P(x). For example, if the next input bit is actually "0", it increases P(x), and if it is "1", it decreases P(x). Note that at the start of encoding, all unused P(x) values ​​are 0.5 (the probability of "0" and "1" is equal).

[0039] Next, the range decoding function 310 will be described with reference to Fig. 3B. The decoder 311 is an arithmetic block that receives an input code 312 and generates an output bit string 313 bit by bit. The generation method will be described in the next section with reference to Figs. 4A and 4B. The output bit string 313 corresponds to the input bit stream to the plaintext expansion process of the LZMA algorithm (plaintext expansion process 206 in Fig. 2), i.e., the output bit stream from the dictionary compression process 202 in Fig. 2.

[0040] The decoder 311 also uses as input a probability value taken from a probability table 314. The probability value P(x) indicates the probability that the next output bit will be a "0" when the bit history 315 output so far is x.

[0041] Like the encoder 301, the decoder 311 adapts the probability value P(x) by learning every time it uses it. For example, if the next output bit is actually "0", it increases P(x), and if it is "1", it decreases P(x). Note that at the start of decoding, all unused P(x) values ​​are 0.5 (the probability of "0" and "1" is equal).

[0042] When the output code 303 of the range encoding function 300 and the input code 312 of the range decoding function 310 are the same, the changes due to learning of all probability values ​​P(x) in the probability table 304 and the probability table 314 are the same. Therefore, the changes during encoding are reproduced during decoding.

[0043] (2-4) Principles of range encoding and decoding 4A and 4B show examples for explaining the principle of range encoding and decoding. The encoding process performed by the encoder 301 in FIG. 3A divides the numerical axis [0, 1) into lengths according to the probability that each bit value of the input bit string is "0", and repeats leaving one of the intervals as a division target for the next bit. The encoding process outputs the coordinate values ​​included in the final remaining interval as a code. Note that if the bit is "0", the left-hand divided interval is left, and if the bit is "1", the right-hand divided interval is left. The probability that each bit value is "0" is obtained from the probability table 304 by using the input bit history up to that point as an index.

[0044] According to the LZMA algorithm, the bit history for referencing the probability value is cleared under a predetermined condition. For example, in the case of 9 bits representing a literal character, the encoder 301 encodes the first bit of the 8 bits excluding the 1 header bit using a null bit history. The encoder 301 encodes the last 8th bit with the 1st to 7th bits as the bit history, and then clears the bit history.

[0045] The decoding process performed by the decoder 311 in Fig. 3B divides the numerical axis [0, 1) into lengths according to the probability that each bit value in the output bit string is "0", as shown in Fig. 4A and 4B. Furthermore, the decoder 311 checks which interval the input code (coordinate value) is included in, determines each bit in the output bit string, and leaves the interval that was included as a division target for the next bit, repeating this process. Finally, all values ​​of the output bit string are determined.

[0046] When the left section contains a code, the decoder 311 determines that the bit is "0", and when the right section contains a code, the decoder 311 determines that the bit is "1". The probability that each bit value is "0" is obtained from the probability table 314 by using the output bit history up to that point as an index.

[0047] The decoder 311 clears the bit history for referencing the probability value under the same conditions as the encoding. For example, in the case of 9 bits representing a literal character, the decoder 311 decodes using a bit history in which the first bit of the 8 bits excluding the 1 header bit is null. The decoder 311 decodes the last 8th bit by using the 1st to 7th bits as the bit history, and then clears the bit history.

[0048] 4A and 4B both show examples of transition of numerical axis division in encoding / decoding processing of a bit string "1,1,0,1". However, the probability values ​​of the bit value being "0" are different. In the example of FIG. 4A, the probability value of "0" is always 0.5. In the example of FIG. 4B, the probability values ​​of "0" are 0.25, 0.25, 0.75, and 0.25, respectively, in bit order. FIG. 4A shows a case where the probability values ​​referred to from the probability tables 304 and 314 are in the initial state. FIG. 4B shows a case where the probability values ​​referred to from the probability tables 304 and 314 are changed by learning.

[0049] In range encoding and decoding, if the bit string "1,1,0,1" is frequently processed, it is learned that in the probability tables 304 and 314, "1" is likely to appear first, if the history is "1", "1" is likely to appear next, if the history is "11", "0" is likely to appear next, and if the history is "110", "1" is likely to appear next. As this learning of probabilities progresses and predictions of how bits will appear become correct, the output code of range encoding becomes shorter.

[0050] The encoding flow in FIG. 4A is as follows. · First step: According to the input "1", the right half section [1 / 2~2 / 2] remains. · Second step: According to the input "1", the right 1 / 2 section [3 / 4~4 / 4] remains. · Third step: According to the input "0", the left 1 / 2 section [6 / 8~7 / 8] remains. · Fourth step: According to the input "1", the right 1 / 2 section [13 / 16~14 / 16] remains. The output code for the last section, 13 / 16 (1101 in binary), is 401.

[0051] On the other hand, the coding flow in FIG. 4B is as follows: · First step: According to the input "1", the right 3 / 4 section [1 / 4~4 / 4] remains. · Second step: According to the input "1", the right 3 / 4 section [7 / 16~16 / 16] remains. · Third step: According to the input "0", the left 3 / 4 section (28 / 64~55 / 64) remains. · Fourth step: According to the input "1", the right 3 / 4 section (139 / 256~220 / 256) remains. The output code for the last section, 3 / 4 (11 in binary), is 411.

[0052] The more the bit string is input according to the probability prediction, the larger the size of the interval remaining after division will be. Therefore, fewer bits are required to express the coordinate values ​​of the output code contained in the final remaining interval. The example in Figure 4A requires 4 bits, whereas the example in Figure 4B requires only 2 bits. In this way, range codes improve the compression rate by learning the bit occurrence probability according to the bit history.

[0053] (2-5) Range encoding and decoding flow chart Fig. 5A shows a flow chart of an example of range encoding. Fig. 5B shows a flow chart of an example of range decoding. First, the procedure of range encoding will be described with reference to Fig. 5A.

[0054] The encoder 301 refers to the probability table 304 according to the input bit history to the probability value that the next bit is "0" (501). The encoder 301 divides the numerical axis range (the range to be divided) into two intervals according to the probability value (502). When dividing, the range size is multiplied by the probability value. This is the most time-consuming part of the encoding process. The encoder 301 then selects one of the two intervals according to whether the input bit value is "0" or "1" (503).

[0055] Next, in step 504, the encoder 301 determines whether the input of bits has ended. If the input of bits has ended (504: YES), the process proceeds to step 506. If there is more input (504: NO), the process proceeds to step 505.

[0056] In step 505, the encoder 301 updates the probability value used for the probability table 304, and updates the bit history for encoding the next bit. The probability value is updated by increasing it if the input bit value is "0" and decreasing it if it is "1". The bit history is updated by, for example, changing the input bit next to "11" to "110" if it is "0". After this, the encoder 301 returns to step 501 to continue the encoding process.

[0057] On the other hand, in step 506, the encoder 301 outputs, as a code, the coordinate value that identifies the last remaining interval, for example, the value contained in that interval that is expressed with the fewest number of bits, and ends the encoding process.

[0058] With reference to FIG. 5B, the procedure of an example of range decoding will be described. The decoder 311 refers to the probability table 314 according to the output bit history to obtain the probability value that the next bit is "0" (511). The decoder 311 divides the numerical axis range into two intervals according to the probability value (512). When dividing, the decoder 311 multiplies the range size by the probability value. This is the most time-consuming part of the decoding process. The decoder 311 then selects one of the two intervals that contains the value of the input code (513). The decoder 311 outputs the bit value "0" or "1" represented by the selected interval (514).

[0059] Next, in step 515, the decoder 311 determines whether the output of bits has ended. If so (515: YES), the decoding process ends. If there is more output (515: NO), the process proceeds to step 516.

[0060] In step 516, the decoder 311 updates the probability value used for the probability table 314, and updates the bit history for decoding the next bit. The probability value is updated by increasing it if the output bit value is "0" and by decreasing it if it is "1". The bit history is updated by changing it to "110" if the output bit next to "11" is "0". After this, the decoder 311 returns to step 511 to continue the decoding process.

[0061] (3) Range encoding speed-up method Fig. 6 shows a functional block diagram of an example of a method for speeding up range encoding processing. The LZMA compression / decompression circuit 104 in Fig. 1 performs the compression processing shown in this block diagram. In the example described with reference to Figs. 3A to 5B, a multiplication process is performed by referring to a probability every time one bit is input. Therefore, only one bit can be processed in one calculation cycle, which may cause the processing performance of the LZMA algorithm to be slow.

[0062] The range encoding function 600 shown in Fig. 6 speeds up the range encoding process by operating multiple encoders simultaneously. That is, N ranges to be divided are prepared (N>1), and N types of bit histories are prepared in advance from the input bit string. This range encoding function 600 simultaneously refers to N probability values ​​in a probability table, and performs multiplication processing in parallel for the N input bits, improving encoding performance by N times.

[0063] Figure 6 shows an example of encoding using this high-speed technique when N=4. All four encoders 601A-601D perform the same process as encoder 301 in Figure 3A. Each encoder retrieves and uses one probability value from probability table 604. These four probability values ​​are referenced using bit histories 605A-605D as indexes.

[0064] Bit history 605A is used when the first bit "1" of input bit string 602 is processed by encoder 601A, and its value is null. Bit history 605B is used when the second bit "1" of input bit string 602 is processed by encoder 601B, and its value is "1."

[0065] Bit history 605C is used when encoder 601C processes the third bit “0” of input bit string 602, and has a value of “11.” Bit history 605D is used when encoder 601D processes the fourth bit “1” of input bit string 602, and has a value of “110.”

[0066] To generalize, the bit history used to encode the Nth bit is composed of a concatenation of the 1st to (N-1)th bits. By preparing four types of bit histories in this way, the four encoders 601A to 601D can simultaneously refer to four probability values ​​from the probability table 604 and simultaneously perform multiplication using these probability values.

[0067] The four sub-codes 603A-603D output from the encoders 601A-601D are finally concatenated to form an output code 606. The output code 606 corresponds to compressed data of the LZMA algorithm. According to this method, a 4-bit input can be processed in one calculation cycle, so that the performance of range encoding in the compression process of the LZMA algorithm is improved four times as much as conventional methods.

[0068] FIG. 7 shows an example of a flowchart of the range encoding speed-up method described with reference to FIG. 6. The procedure of the range encoding speed-up method will be described with reference to the flowchart in FIG. 7. First, the LZMA compression / decompression circuit 104 creates N types of bit histories used to encode N bits of an input bit string (701). N is an integer equal to or greater than 2. The N encoders obtain, from the probability table, a probability value that the next bit is "0" based on each bit history (702). The N encoders divide each of the N numerical axis ranges (ranges to be divided) into two intervals according to these probability values ​​(703).

[0069] The multiplication of the range size and the probability value by the N encoders is performed in parallel. In the first cycle, the numerical axis range (range size) is common to the N encoders, and is [0, 1] in the example shown in FIG. 6. In the second cycle and onwards, the range selected by the relevant encoder in the previous cycle becomes the target numerical axis range (range size). Each encoder selects one of the two ranges on the left and right depending on whether the input bit value is "0" or "1" (704).

[0070] Next, in step 705, the LZMA compression / decompression circuit 104 determines whether the input of bits has ended, and if the input of bits has ended (705: YES), the process proceeds to step 707, and if there is still input (705: NO), the process proceeds to step 706. In step 706, the LZMA compression / decompression circuit 104 updates the N probability values ​​used in the probability table. The probability value is updated by increasing it if the input bit value is "0" and decreasing it if it is "1".

[0071] After this, the LZMA compression / decompression circuit 104 returns to step 701 to continue the encoding process. For example, when N is 4 and 8 bits of a literal character are encoded, the first cycle of this flow encodes the first 4 bits, and the second cycle encodes the last 4 bits. In the second cycle, the bit history used to encode the 5th bit is the bit string of the first 4 bits.

[0072] For example, if the input bit string is 6 bits, the first cycle may encode the first 4 or 3 bits, and the second cycle may encode the last 2 or 3 bits. The maximum value of the input bit string to the LZMA compression and expansion circuit 104 is 4, and bit strings below this value can be encoded.

[0073] In step 707, each encoder generates a coordinate value that identifies the last remaining section, for example, a value contained in the section that has the smallest number of bits to represent. The LZMA compression / decompression circuit 104 outputs a bit string that concatenates these N values ​​as a code, and the encoding process ends.

[0074] In the range coding example shown in Figure 6, the integer N>1 and the number of input bits is N bits, i.e. the length of the bit history is at most (N-1) bits. This range coding can speed up coding by N times using N ranges to be divided. As mentioned in the explanation with reference to Figure 7 for the example of 8 bits of literal characters, if the integer M>N and the number of input bits is M bits, i.e. the length of the bit history is at most (M-1) bits, the N ranges to be divided can be used to speed up coding of the input bits.

[0075] The method will be described below using an example where M=8 and N=4. The LZMA compression / decompression circuit 104 has a probability table with 255 entries indexed by a bit history of up to 7 bits. The LZMA compression / decompression circuit 104 prepares four types of bit history (empty, 1 bit, 2 bits, and 3 bits, respectively) used to encode the first 4 bits of an 8-bit input bit string, and simultaneously refers to the four probability values ​​corresponding to these in the probability table. The LZMA compression / decompression circuit 104 uses these probability values ​​to encode the first 4 bits in parallel in the first cycle.

[0076] Next, the LZMA compression / decompression circuit 104 prepares four types of bit histories (4 bits, 5 bits, 6 bits, and 7 bits, including the first 4 bits at the beginning) to be used for encoding the last 4 bits of the input bits, and simultaneously refers to the corresponding four probability values ​​from the probability table. The LZMA compression / decompression circuit 104 uses these probability values ​​to encode the last 4 bits in parallel in the second cycle.

[0077] In this way, the LZMA compression / decompression circuit 104 processes an 8-bit input in two cycles (i.e., four times the performance), generates four sub-codes, and constructs an output code by concatenating them.

[0078] In general, the performance of the encoding process of the range code inputting M bits is improved by processing M bits in [M / N] operation cycles using a probability table with (2^M-1) entries indexed by the bit history of up to (M-1) bits and N encoders. Note that the LZMA compression / decompression circuit 104 may generate subcodes without performing the above parallel processing.

[0079] (4) Speed-up method for range decoding Speeding up range decoding processing by N times cannot be achieved by simply operating N decoders 311 in Fig. 3B in parallel. This is because the bit history used in the processing of a certain decoder X is uncertain until decoder Y, which decodes the previous bit, outputs the processing result. Therefore, decoder X cannot look up probability values ​​from the probability table and perform multiplication using those values ​​at the same time as decoder Y, and parallelization cannot be achieved.

[0080] A method for speeding up range decoding processing according to an embodiment of this specification will be described below. Fig. 8 shows a functional block diagram of the method for speeding up range decoding processing. The LZMA compression / decompression circuit 104 in Fig. 1 performs decompression processing using a range decoding function 800 shown in this block diagram.

[0081] FIG. 8 shows an example of range decoding when N=4, that is, the number of bits in the output bit string is 4. All of the 15 decoders 8A (1), 8B0 and 8B1 (2), 8C00 to 8C11 (4), and 8D000 to 8D111 (8) perform the same process as the decoder 311 in FIG. 3B. In FIG. 8, some of the decoders are omitted. The four sub-codes 803A to 803D input to these 15 decoders are separated from the input code 802 (corresponding to compressed data in the LZMA algorithm) and are the same as the four sub-codes 603A to 603D in FIG. 6. Note that one sub-code may be shared by multiple decoders.

[0082] Each decoder uses one probability value from the probability table 804 to output a candidate bit value, with the 15 probability values ​​indexed into the full set of possible bit histories.

[0083] The bit history value used by one decoder 8A for decoding the first bit of the output bit string 806 is NULL. The bit history values ​​used by two decoders 8B0 and 8B1 for decoding the second bit of the output bit string 806 are "0" and "1", respectively.

[0084] The bit history values ​​used by the four decoders 8C00-8C11 for decoding the third bit of the output bit string 806 are "00", "01", "10", and "11", respectively. The bit history values ​​used by the eight decoders 8D000-8D111 for decoding the fourth bit of the output bit string 806 are "000", "001", "010", "011", "100", "101", "110", and "111", respectively.

[0085] To generalize, the number of bit histories used to decode the K-th bit is 2^(K-1). Each bit history is a (K-1)-bit bit pattern (bit string) that is possible as the 1st to (K-1)th bits of the output bit string 806. By preparing 15 types of bit histories in this way, 15 probability values ​​are simultaneously referenced from the probability table 804, and the 15 decoders simultaneously perform multiplication using these probability values.

[0086] If the first bit of the output bit string 806 output by the decoder 8A is "1", it is clear that the second bit output by the decoder 8B1, which performed decoding assuming that the first bit was "1", out of the two decoders 8B0 and 8B1, is the correct result. Therefore, the selector 805B selects "1" output by the decoder 8B1 from the two second bit candidates output by the decoders 8B0 and 8B1. In other words, the first and second bits are determined to be "11".

[0087] This shows that the third bit output by decoder 8C11, which performed decoding on the assumption that the first and second bits were "11" among decoders 8C00-8C11, is the correct result. Therefore, selector 805C selects "0" output by decoder 8C11 from the four third bit candidates output by decoders 8C00-8C11. In other words, the first to third bits are determined to be "110".

[0088] This shows that the fourth bit output by the decoder 8D110, which performed decoding on the assumption that the first to third bits were "110" among the decoders 8D000 to 8D111, is the correct result. Therefore, the selector 805D selects "1" output by the decoder 8D110 from the eight fourth bit candidates output by the decoders 8D000 to 8D111.

[0089] As a result of the above, the four bits of the output bit string 806 are determined to be "1101." To generalize, the LZMA compression and decompression circuit 104 has 2^(K-1) decoders to decode the K-th bit, and holds 2^(K-1) K-th bit candidates output by these decoders. The LZMA compression and decompression circuit 104 selects, as the K-th bit, a candidate output by one decoder that performed decoding assuming that the already determined values ​​of the 1st to (K-1)th bits are bit history.

[0090] The bit selection process by the selectors 805B to 805D is performed in a much shorter time than the multiplication process by the decoder. Therefore, this method allows 4-bit output to be processed in one calculation cycle. As a result, the performance of the range decoding process in the decompression process of the LZMA algorithm is improved by four times compared to the conventional method.

[0091] The procedure of the range decoding speed-up method described with reference to Fig. 8 will be described below with reference to Fig. 9. First, the LZMA compression / decompression circuit 104 creates (2^N-1) bit histories that may be used to decode N bits of the output bit string (901). The number of bit histories used to decode the Kth bit is 2^(K-1).

[0092] Each of the (2^N-1) decoders obtains a probability value that the next bit is "0" from the probability table 804 according to the bit history it is responsible for (902), and divides the numerical axis range (range to be divided) into two intervals according to the probability value (903). The numerical axis range divided by the 2^(K-1) decoders used to decode the K-th bit is common. Specifically, the numerical axis range of all decoders in the first cycle is common, which is [0,1] in the example of FIG. 8. From the second cycle onwards, the numerical axis range of the decoder for the K-th bit is the range of the division result by the decoder that output the correct answer for the K-th bit in the previous cycle. When dividing, the range size is multiplied by the probability value.

[0093] The decoder selects one of the two intervals that the input subcode value includes (904), and generates a bit value "0" or "1" represented by the selected interval (905). The number of bit values ​​to be generated is (2^N-1), and the number of candidates for the Kth bit is 2^(K-1). The selector then selects one correct bit from each candidate, starting from the first bit, and determines and outputs an N-bit pattern (906). The correct values ​​of the 1st to (K-1)th bits are used as a bit history to select the correct value for the Kth bit.

[0094] Next, in step 906, the LZMA compression / decompression circuit 104 determines whether the output of bits has been completed. If so (906: YES), the decoding process ends. If there is more output (906: NO), the process proceeds to step 907.

[0095] In step 907, the LZMA compression and expansion circuit 104 updates the N probability values ​​used for the probability table 804. The probability value is updated by increasing it if the output bit value is "0" and decreasing it if the output bit value is "1". Furthermore, the LZMA compression and expansion circuit 104 adopts the interval selected in step 904 by the decoder that output the correct bit value as the numerical axis range for the next cycle. The interval selected in step 904 by one decoder that output the correct value of the Kth bit among the 2^(K-1) decoders for the Kth bit is adopted as the numerical axis range to be divided in step 903 in the next decoding of the Kth bit.

[0096] After that, the LZMA compression / decompression circuit 104 continues the decoding process by returning to step 901. For example, if the first 4 bits and the last 4 bits of the 8 bits of a literal character are encoded in two cycles, the bit history used to decode the 5th bit in the second cycle of this flow is the bit string of the first 4 bits.

[0097] For example, if 6-bit input data is divided into the first 4 bits and the remaining 2 bits and coded in two cycles, the LZMA compression / decompression circuit 104 may decode 4 bits or 3 bits in the first cycle, and then decode 2 bits or 3 bits in the second cycle. The maximum value of the input bit string to the LZMA compression / decompression circuit 104 is 4, and bit strings below this value can be decoded.

[0098] In the method for accelerating the decoding process of a range code shown in Fig. 8, when the integer N>1, the number of input bits is N bits (i.e., the length of the bit history is a maximum of (N-1) bits), and N ranges to be divided are used to speed up the decoding process N times. As mentioned with reference to Fig. 9 for the example of an 8-bit literal character, when the integer M>N and the number of input bits is M bits, i.e., the length of the bit history is a maximum of (M-1) bits, N ranges to be divided can be used to speed up the decoding of the output bit string.

[0099] An example of decoding an 8-bit output bit string will be described below. The LZMA compression / decompression circuit 104 has 15 decoders as in Fig. 8, and inputs four sub-codes separated from an input code (corresponding to compressed data in the LZMA algorithm) to these 15 decoders as in Fig. 8. Each decoder uses a probability value obtained one by one from a 255-entry probability table indexed by a maximum 7-bit bit history.

[0100] The 15 probability values ​​referenced in the first cycle are values ​​referenced using as indexes all the possible bit histories (empty, 1 bit, 2 bits, 3 bits, respectively) for the first 4 bits of the 8-bit output bit string. The bit history value used by one decoder to decode the first bit of the output bit string is empty (NULL).

[0101] The two decoders that decode the second bit of the output bitstream use bit history values ​​of "0" and "1", respectively. The four decoders that decode the third bit of the output bitstream use bit history values ​​of "00", "01", "10", and "11", respectively. The eight decoders that decode the fourth bit of the output bitstream use bit history values ​​of "000", "001", "010", "011", "100", "101", "110", and "111", respectively.

[0102] The 15 decoders perform multiplication in parallel using the probability values ​​referenced in their bit histories. Then, as in Figure 8, the selector's bit selection process determines the values ​​of the 1st to 4th bits in order. Here, we set the values ​​to "1101" for example.

[0103] Next, the 15 probability values ​​referenced in the second cycle are values ​​referenced using as indexes all possible bit histories for the last 4 bits of the 8-bit output bit string (4 bits, 5 bits, 6 bits, and 7 bits, respectively, starting with "1101" determined in the first cycle).

[0104] The bit history value used by one decoder to decode the fifth bit of the output bitstream is "1101". The bit history values ​​used by two decoders to decode the sixth bit of the output bitstream are "11010" and "11011", respectively. The bit history values ​​used by four decoders to decode the seventh bit of the output bitstream are "110100", "110101", "110110", and "110111", respectively.

[0105] The bit history values ​​used by the eight decoders to decode the eighth bit of the output bit string are “1101000”, “1101001”, “1101010”, “1101011”, “1101100”, “1101101”, “1101110”, and “1101111”, respectively.

[0106] The 15 decoders perform multiplication in parallel using the probability values ​​referenced in their bit histories.Then, as in Figure 8, the selector's bit selection process determines the values ​​of the 5th to 8th bits in order.

[0107] As in Figure 8, the bit selection process of the selector is performed in a much shorter time than the multiplication process of the decoder. Therefore, this method allows 8-bit output to be processed in two calculation cycles. As mentioned above, in a probability table with 255 entries, 15 entries are referenced in the first cycle, and 15 entries are selected from the remaining 240 entries and referenced in the second cycle. In the second cycle, the number of entries referenced is narrowed down to 1 / 16 by indexing with the bit history including the first 4 bits determined in the first cycle.

[0108] In general, the performance of the decoding process of a range code that outputs M bits can be improved by using a probability table with (2^M-1) entries indexed by the bit history of up to (M-1) bits and (2^N-1) decoders to process M bits in [M / N] calculation cycles.

[0109] As described above, one embodiment of the present specification can quickly decompress data compressed by range coding, thereby improving the read response performance of compressed data in, for example, an appliance storage system having a data compression function using a range coding algorithm.

[0110] The present invention is not limited to the above-described embodiment, but includes various modified examples. For example, the above-described embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to those including all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration.

[0111] In addition, the above-mentioned configurations, functions, processing units, etc. may be realized in part or in whole by hardware, for example, by designing them as integrated circuits. In addition, the above-mentioned configurations, functions, etc. may be realized in software by a processor interpreting and executing a program that realizes each function. Information such as the program, table, file, etc. that realizes each function can be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card or SD card.

[0112] In addition, the control lines and information lines shown are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are connected to each other.

[0113] [Additional Notes] Several aspects of the disclosure are described below. (1) An apparatus for processing received data, comprising: a circuit for receiving an input code compressed based on a range code; a decompression circuit for decompressing a part or all of the input code to decode an N-bit string; Including, N represents an integer greater than 1, and K represents an integer from 1 to N, a bit value of the K-th bit of the input code is decoded based on a bit history of bits prior to the K-th bit; The expansion circuit includes: calculating a plurality of candidate bit values ​​for the bits of the N-bit string based on a plurality of possible bit histories of the bits preceding the K bit in parallel for the plurality of bits; and iteratively selecting a correct bit value for the K bits from the plurality of candidate bit values ​​based on a correct bit history prior to the K bits, thereby decoding the N-bit string. (2) The device according to (1), The expansion circuit includes: storing probability values ​​of bit values ​​occurring according to said bit history; An apparatus for selecting and updating, from the stored probability values, a probability value corresponding to a bit history on which a correct bit constituting the decoded N-bit string is based. (3) The device according to (1), The candidate bit value of the Kth bit in the N-bit string is calculated by multiplying the range to be divided by the probability value of each of 2^(K-1) possible bit histories, dividing the range into two partitions, and determining each of 2^(K-1) possible candidate bit values ​​from the partition identified by a sub-code among the two partitions of the K bits in the input code. (4) The device according to (1), The decompression circuit performs multiple cycles of decoding a sequence of bits from a portion of the input code if the number of bits to decode from the entire input code is greater than a preset maximum value. (5) The device according to (4), In a second or subsequent cycle among the multiple cycles, a division target range for determining each of the candidate bit values ​​of the K bits is a section for the correct bit value of the K bits in the immediately preceding cycle. (6) 1. A storage system comprising: an interface for receiving requests from a host; a controller that writes data to the storage drive and reads data from the storage drive in response to commands from the host; The controller includes the decompression circuit according to (1), the controller generates read data by decrypting the input code transferred from the storage drive in response to a read command from the host using the decompression circuit; The storage system returns the read data to the host via the interface. (7) The storage system according to (6), The expansion circuit includes: storing probability values ​​of bit values ​​occurring according to said bit history; A storage system that selects and updates a probability value of each correct bit value constituting the decoded N-bit string from the stored probability values. (8) The storage system according to (6), A storage system in which a candidate bit value for the Kth bit in the N-bit string is calculated by dividing a range to be divided into two partitions by multiplying the range by the probability value of each of 2^(K-1) bit histories, and determining a candidate bit value from each of the 2^(K-1) partitions for the K-bit subcode in the input code. (9) The storage system according to (6), The decompression circuit performs multiple cycles of decoding a bit string from a portion of the input code when a number of bits to be decoded from the entire input code is greater than a preset maximum value. (10) The storage system according to (6), In a second or subsequent cycle among the multiple cycles, a division target range for determining each of the candidate bit values ​​of the K bits is a section for the correct bit value of the K bits in an immediately preceding cycle. (11) A method for decoding an N-bit string by decompressing a part or all of an input code compressed based on a range code, comprising the steps of: N represents an integer greater than 1, and K represents an integer from 1 to N, The method comprises: Calculating candidate bit values ​​for each bit of the N-bit string in parallel, calculating the candidate bit value for the K-th bit in the N-bit string by multiplying a division target range by a probability value of each bit history to divide the range into two partitions, and determining candidate bit values ​​from each partition for the K-bit sub-code in the input code; selecting a correct bit value for the K bits from the candidate bit values ​​based on a correct bit history prior to the K bits to decode the N-bit string. (12) The method according to (11), A method for selecting and updating a probability value of each correct bit value constituting the decoded N-bit string from the preset probability values. (13) The method according to (11), The method for calculating the candidate bit value for the Kth bit in the N-bit string includes dividing a range to be divided into two partitions by multiplying the range by the probability value of each of 2^(K-1) bit histories, and determining a candidate bit value from each of the 2^(K-1) partitions for the K-bit subcode in the input code. (14) The method according to (11), performing multiple cycles of decoding a sequence of bits from a portion of the input code if the number of bits to decode from the entire input code is greater than a preset maximum value. (15) The method according to (14), The method according to claim 1, wherein in a second or subsequent cycle among the multiple cycles, a range to be divided for determining each of the candidate bit values ​​of the K bits is a partition for the correct bit value of the K bits in an immediately preceding cycle. (16) An apparatus for processing received data, comprising: a circuit for receiving an input code compressed based on a range code; a plurality of decompression circuits for decompressing a part or all of the input code to decode a bit string; a bit value of a bit of the input code is decoded based on a bit history of bits preceding the bit, The plurality of expansion circuits include calculating a plurality of candidate bit values ​​for a bit in the bit string based on a plurality of possible bit histories of a bit preceding the bit; A correct bit value is repeatedly selected from the plurality of candidate bit values ​​based on a correct bit history of bits preceding the correct bit, thereby decoding the bit string. (17) An apparatus for processing received data, comprising: a decompression circuit for decompressing a part or all of the input code compressed based on the range code to decode a bit string; a bit value of a bit in the bit string is decoded based on a bit history of bits preceding the bit in the bit string; the decompression circuit includes a plurality of decoders; Each of the plurality of decoders calculating a candidate bit value for a bit in the bit string based on a probability value associated with a plurality of candidate bit histories that may be taken by a bit preceding the bit in the bit string; The expansion circuit includes: and repeatedly selecting a correct bit value from a plurality of candidate bit values ​​calculated by each of the plurality of decoders based on a bit history of a bit preceding the selected bit, thereby decoding the bit string. (18) The device according to (17), The expansion circuit includes: storing said probability values ​​of bit values ​​occurring as a function of said bit history; an apparatus for selecting and updating from among the stored probability values ​​a probability value that has been used in decoding the bit sequence; (19) The device according to (17), the bit string is an N-bit string, N being an integer greater than 1, and K being an integer between 1 and N; The candidate bit value of the Kth bit in the N-bit string is calculated by multiplying the range to be divided by the probability value of each of 2^(K-1) possible bit histories to divide the range to be divided into two partitions, and determining each of 2^(K-1) possible candidate bit values ​​from the partition identified by a subcode separated from the input code among the two partitions of the K bits in the input code. (20) The device according to (17), The decompression circuit performs multiple cycles of decoding a sequence of bits from a portion of the input code if the number of bits to decode from the entire input code is greater than a preset maximum value. (twenty one) The device according to (20), In a second or subsequent cycle among the multiple cycles, a division target range for determining each of the multiple candidate bit values ​​is a section for the correct bit value in the immediately preceding cycle. (twenty two) 1. A storage system comprising: an interface for receiving requests from a host; a controller that writes data to the storage drive and reads data from the storage drive in response to commands from the host; The controller includes the expansion circuit according to (17), the controller generates read data by decrypting the input code transferred from the storage drive in response to a read command from the host using the decompression circuit; The storage system returns the read data to the host via the interface. (twenty three) 1. A method for processing received data by an apparatus, comprising: The apparatus includes a decompression circuit for decompressing a part or all of the compressed input code based on the range code to decode a bit string; the decompression circuit includes a plurality of decoders; a bit value of a bit in the bit string is decoded based on a bit history of bits preceding the bit in the bit string; The method further comprises the steps of: calculating, by each of the plurality of decoders, a candidate bit value for a bit in the bit sequence based on a probability value associated with a plurality of candidate bit histories that may be taken by a bit preceding the bit in the bit sequence, the candidate bit value being determined based on the probability value; a bit history of a bit preceding said bit, said bit string being decoded by repeatedly selecting a correct bit value from a plurality of candidate bit values ​​calculated by each of said plurality of decoders based on the bit history of said bit. [Explanation of symbols]

[0114] 101...storage system, 103...storage controller, 104...LZMA compression / decompression circuit, 301, 601A-D...encoders, 311, 8A, 8B0, 8B1, 8C00, 8C11, 8D000, 8D111...decoders, 304, 314, 604, 804...probability tables, 302, 602...input bit strings, 303, 606...output codes, 312, 802...input codes, 313, 806...output bit strings

Claims

1. An apparatus for processing received data, comprising: a decompression circuit for decompressing a part or all of the input code compressed based on the range code to decode an N-bit string; N represents an integer greater than 1, and K represents an integer from 1 to N, a bit value of the Kth bit of the input code is decoded based on a bit history of bits prior to the Kth bit; The expansion circuit includes: The apparatus calculates, for a plurality of bits, a plurality of candidate bit values ​​for the bits of the N-bit string based on a plurality of possible bit histories of bits prior to the K bit.

2. 2. The apparatus of claim 1, and iteratively selecting a correct bit value for the K bits from the plurality of candidate bit values ​​based on a correct bit history prior to the K bits, thereby decoding the N-bit string.

3. 2. The apparatus of claim 1, The apparatus performs the step of calculating each of the plurality of candidate bit values ​​in parallel for the plurality of bits.

4. 2. The apparatus of claim 1, The calculation of the plurality of candidate bit values ​​is performed in parallel for three or more of the plurality of bits; The apparatus calculates one candidate bit value for the K bit, calculates two candidate bit values ​​for the K+1th bit, and calculates four candidate bit values ​​for the K+2th bit.

5. 2. The apparatus of claim 1, The expansion circuit includes: storing probability values ​​of bit values ​​occurring according to said bit history; An apparatus for selecting and updating, from the stored probability values, a probability value corresponding to a bit history on which a correct bit constituting the decoded N-bit string is based.

6. 2. The apparatus of claim 1, The candidate bit value of the Kth bit in the N-bit string is calculated by dividing the range to be divided into two partitions by multiplying the range by the probability value of each of 2^(K-1) possible bit histories, and determining each of the 2^(K-1) possible candidate bit values ​​from the partition identified by a sub-code among the two partitions of the K bits in the input code.

7. 2. The apparatus of claim 1, The expansion circuit includes: The apparatus performs multiple cycles of decoding bits from a portion of the input code if the number of bits to decode from the entire input code is greater than a preset maximum value.

8. 8. The apparatus of claim 7, In a second or subsequent cycle among the multiple cycles, a division target range for determining each of the candidate bit values ​​of the K bits is a section for the correct bit value of the K bits in the immediately preceding cycle.

9. 1. A storage system comprising: an interface for receiving requests from a host; a controller that writes data to the storage drive and reads data from the storage drive in response to commands from the host; the controller includes a decompression circuit for decompressing a part or all of the input code compressed based on the range code to decode an N-bit string; N represents an integer greater than 1, and K represents an integer from 1 to N, a bit value of the Kth bit of the input code is decoded based on a bit history of bits prior to the Kth bit; The expansion circuit includes: calculating a plurality of candidate bit values ​​for the bits of the N-bit string based on a plurality of possible bit histories of the bits preceding the K bit, for each of the plurality of bits; the controller generates read data by decrypting the input code transferred from the storage drive in response to a read command from the host using the decompression circuit; The storage system returns the read data to the host via the interface.

10. 10. The storage system according to claim 9, The expansion circuit includes: The storage system decodes the N-bit string by repeatedly selecting a correct bit value for the K bits from the plurality of candidate bit values ​​based on a correct bit history prior to the K bits.

11. 10. The storage system according to claim 9, The expansion circuit includes: A storage system, wherein the calculation of the plurality of candidate bit values ​​is performed in parallel for the plurality of bits.

12. 10. The storage system according to claim 9, The expansion circuit includes: The calculation of the plurality of candidate bit values ​​is performed in parallel for three or more of the plurality of bits; a storage system that calculates one candidate bit value for the K bit, calculates two candidate bit values ​​for the K+1th bit, and calculates four candidate bit values ​​for the K+2th bit.

13. 10. The storage system according to claim 9, The expansion circuit includes: storing probability values ​​of bit values ​​occurring according to said bit history; A storage system that selects and updates, from the stored probability values, a probability value that corresponds to a bit history on which a correct bit that constitutes the decoded N-bit string is based.

14. 10. The storage system according to claim 9, A storage system in which a candidate bit value for the Kth bit in the N-bit string is calculated by dividing the range to be divided into two partitions by multiplying the range by the probability value of each of 2^(K-1) possible bit histories, and determining each of 2^(K-1) possible candidate bit values ​​from the partition identified by a sub-code among the two partitions of the K bits in the input code.

15. 10. The storage system according to claim 9, The expansion circuit includes: When the number of bits to be decoded from the entire input code is greater than a preset maximum value, the storage system performs multiple cycles of decoding a bit string from a portion of the input code.

16. 1. A method for decoding an N-bit string by decompressing a part or all of an input code compressed based on a range code, comprising: N represents an integer greater than 1, and K represents an integer from 1 to N, a bit value of the Kth bit of the input code is decoded based on a bit history of bits prior to the Kth bit; The method comprises: The method includes calculating, for a plurality of bits, a plurality of candidate bit values ​​for the bits of the N-bit string based on a plurality of possible bit histories of bits prior to the K bit.

17. 17. The method of claim 16, a correct bit value for the K bits is repeatedly selected from the plurality of candidate bit values ​​based on a correct bit history prior to the K bits, thereby decoding the N-bit string.

18. 17. The method of claim 16, The method of claim 1, further comprising: calculating each of the plurality of candidate bit values ​​in parallel for the plurality of bits.

19. 17. The method of claim 16, A method of calculating in parallel each of the candidate bit values ​​based on a probability value of the bit value occurring according to the bit history.

20. 17. The method of claim 16, performing multiple cycles of decoding a sequence of bits from a portion of the input code if the number of bits to decode from the entire input code is greater than a preset maximum value.

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