Switch circuit

Abstract

To suppress transmission delay at the time of turning off a circuit current and an output switching element.SOLUTION: A switch circuit (100) includes: an output switching element (M1); a driving voltage generation circuit (120) for generating a driving voltage (VBST) for tuning on the output switching element; a level shifter (LVS1) for generating a shifted control signal by shifting the level of an original control signal (CNT) using the driving voltage; and a driver circuit (130) for driving the output switching element based on the driving voltage, according to the shifted control signal. The level shifter includes a pull-up resistor (R1) and a transistor for shifting (M2) connected to the pull-up resistor in series, and generates the shifted control signal for turning off the output switching element by turning on the transistor for shifting to flow current through the pull-up resistor when the original control signal designates turning off of the output switching element.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a switch circuit. [Background technology]

[0002] The switch circuit has an output switching element inserted between two nodes, and turns the output switching element on or off in response to a given control signal, thereby establishing or blocking conduction between the two nodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-188429 A

[0004] [overview] In a switch circuit, a drive signal for driving an output switching element is generated based on a control signal. It is required to shorten the propagation delay when the contents of the control signal are propagated to the drive signal. It is especially required to shorten the propagation delay when switching the output switching element from on to off. At the same time, it is also required to suppress the circuit current.

[0005] A switch circuit according to one embodiment of the present disclosure includes an output switching element provided between a first node and a second node, a drive voltage generation circuit configured to generate a drive voltage for turning on the output switching element, a level shifter configured to generate a shift control signal by level-shifting an original control signal specifying a state of the output switching element using the drive voltage, and a drive circuit configured to drive the output switching element in accordance with the shift control signal based on the drive voltage, wherein the level shifter has a pull-up resistor and a shift transistor connected in series to the pull-up resistor, and generates the shift control signal for turning off the output switching element by turning on the shift transistor and flowing a current through the pull-up resistor when the original control signal specifies that the output switching element is to be turned off. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic configuration diagram of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the semiconductor device according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is a circuit diagram of an overvoltage detection circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a configuration diagram of a switch circuit according to a first reference example. [Diagram 5] FIG. 5 is a timing chart when an overvoltage anomaly occurs according to the first reference example. [Figure 6] FIG. 6 is a configuration diagram of a switch circuit according to a second reference example. [Figure 7] FIG. 7 is a configuration diagram of a switch circuit according to a third reference example. [Figure 8] FIG. 8 is a configuration diagram of a switch circuit according to a first example of an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing an internal configuration of a driver for an output transistor according to a first example of the embodiment of the present disclosure. [Figure 10]FIG. 10 is a configuration diagram of a switch circuit according to a second embodiment of the present disclosure. [Figure 11] FIG. 11 is a partial configuration diagram of a semiconductor device related to an internal power supply circuit according to a second example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a configuration diagram of a switch circuit according to a third embodiment of the present disclosure. [Figure 13] FIG. 13 is a configuration diagram of a switch circuit according to a third embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground.

[0009] A level refers to a level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal of interest, when the signal is at a high level, the inverted signal of the signal is at a low level, and when the signal is at a low level, the inverted signal of the signal is at a high level.

[0010] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on-state refers to the state where conduction exists between the drain and source of the transistor, and the off-state refers to the state where non-conduction (cut-off state) exists between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0011] Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off. Also, for any transistor, the period during which the transistor is in the on-state is referred to as the on-period, and the period during which the transistor is in the off-state is referred to as the off-period.

[0012] For any signal taking a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage taking a high-level or low-level voltage level.

[0013] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0014] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, and "v1<v2" represents that voltage v1 is lower than voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0015] FIG. 1 is a schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 2 is an external perspective view of the semiconductor device 1. The semiconductor device 1 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the housing CS to the outside of the semiconductor device 1. The semiconductor device 1 is formed by sealing the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the semiconductor device 1 and the type of the housing CS of the semiconductor device 1 shown in FIG. 2 are merely examples, and can be designed arbitrarily. In FIG. 1, an input terminal IN, an output terminal OUT, a ground terminal GND, and an enable terminal EN are shown as some or all of the external terminals provided in the semiconductor device 1. External terminals other than these may also be provided in the semiconductor device 1.

[0016] Incidentally, the wiring provided outside the semiconductor device 1 is particularly referred to as external wiring, and the wiring provided inside the semiconductor device 1 is particularly referred to as internal wiring.

[0017] An input voltage V is applied to an input terminal IN through an external wiring from a voltage source VS provided outside the semiconductor device 1. IN The input voltage V IN has a positive voltage value. OUT An output capacitor C OUT The first end of the output capacitor C OUT The second end of the output terminal OUT is connected to ground. OUT Therefore, the output capacitor C OUT The output voltage V OUT are added. Two or more external terminals functioning as input terminals IN may be provided in the semiconductor device 1. Three or more external terminals functioning as output terminals OUT may be provided in the semiconductor device 1. The ground terminal GND is connected to the ground.

[0018] The semiconductor device 1 includes, as main circuits, a switch circuit 10, an internal power supply circuit 20, and a protection circuit 30. An enable signal S is sent from an external circuit (not shown) to an enable terminal EN of the semiconductor device 1. EN An enable signal S EN is input to the switch circuit 10.

[0019] The switch circuit 10 receives an enable signal S EN When the input terminal IN and the output terminal OUT are connected, in the steady state, the input voltage V IN An output voltage V having substantially the same voltage value as OUT appears at the output terminal OUT, and the output voltage V OUT is supplied to an arbitrary load (not shown) connected to the output terminal OUT. After the input terminal IN and the output terminal OUT are connected, if the input terminal IN and the output terminal OUT are cut off, the output voltage V OUT decreases towards 0V.

[0020] The internal power supply circuit 20 is connected to the input terminal IN via the input voltage V IN The protection circuit 30 detects various abnormalities that may occur in the semiconductor device 1. The detection results of the protection circuit 30 are transmitted to the switch circuit 10. The switch circuit 10 and the protection circuit 30 are driven by any one of the internal power supply voltages generated by the internal power supply circuit 20.

[0021] In this way, the semiconductor device 1 functions as a switch device for establishing or breaking electrical continuity between the input terminal IN and the output terminal OUT. The semiconductor device 1 may be a device classified as an electronic fuse, or may be a high-side switch device inserted into any power bus. The semiconductor device 1 may be used in applications where hot swapping (live insertion and removal) is anticipated. Here, attention is focused on one switch circuit 10, but multiple switch circuits 10 may be provided within the semiconductor device 1.

[0022] Enable signal S ENThe enable signal S has a value of "1" or "0". EN When the enable signal S has a value of "0", the switch circuit 10 cuts off the connection between the input terminal IN and the output terminal OUT. EN When the enable signal S has a value of "1", the switch circuit 10, in principle, brings the input terminal IN and the output terminal OUT into conduction. EN Even if the signal has a value of "1", when a specific abnormality is detected in the protection circuit 30, the switch circuit 10 cuts off the connection between the input terminal IN and the output terminal OUT.

[0023] An example of a specific abnormality is an overvoltage abnormality. An overvoltage abnormality is when the input voltage V IN 3 shows the configuration of an overvoltage detection circuit 31 capable of detecting an overvoltage abnormality. The overvoltage detection circuit 31 can be provided in the protection circuit 30. The overvoltage detection circuit 31 includes resistors 31a and 31b and a comparator 31c. A first end of the resistor 31a is connected to the input terminal IN and detects an input voltage V IN The second end of resistor 31a and the first end of resistor 31b are connected to each other. The second end of resistor 31b is connected to the reference potential end. The voltage at the reference potential end is the voltage VSS. The reference potential end is connected to the ground terminal GND. Therefore, the reference potential end is equivalent to the ground and has a voltage of 0 V. An input voltage V IN Voltage V DIV This occurs.

[0024] Voltage V is applied to the non-inverting input terminal of comparator 31c. DIV is input, and a predetermined judgment reference voltage V OVP The input voltage V IN Or the internal power supply voltage to the reference voltage V OVP The comparator 31c generates a voltage V DIV The reference voltage V OVP and outputs an overvoltage detection signal S according to the comparison result. OVP Generates and outputs an overvoltage detection signal S OVPhas a value of "1" or "0". Here, the high-level overvoltage detection signal S OVP has a value of “1”, and the low-level overvoltage detection signal S OVP shall have a value of "0".

[0025] A hysteresis characteristic is provided in the comparison by the comparator 31c. OVP The initial value of the overvoltage detection signal S OVP Starting from the state where V has a value of “0”, DIV <V OVP "From the state where "V DIV >V OVP When the state transitions to the established state of ", the comparator 31c outputs the overvoltage detection signal S OVP The value of V DIV <(V OVP -ΔV HYS The overvoltage detection signal S OVP The value of “V DIV <(V OVP -ΔV HYS When the above condition is met, the overvoltage detection signal S OVP Switch the value of from “1” to “0”. ΔV HYS is a voltage value that represents the hysteresis width and has a predetermined positive voltage value. HYS = 0”. The overvoltage detection signal S OVP indicates that an overvoltage abnormality has been detected, and the overvoltage detection signal S OVP does not indicate that an overvoltage fault has been detected.

[0026] Overvoltage detection signal S OVP is input to the switch circuit 10. The overvoltage detection signal S OVP When the value of is "0", the operation of the switch circuit 10 is as per the principle. OVP When the enable signal S ENEven if the overvoltage detection signal S has a value of "1", the input terminal IN and the output terminal OUT are immediately disconnected from each other, and thereafter, the input terminal IN and the output terminal OUT are kept disconnected from each other until a predetermined reset condition is satisfied. For example, OVP The reset condition is satisfied simply by the value of the enable signal S returning from "1" to "0". EN After changing the value of from "1" to "0", the enable signal S EN The reset condition may be satisfied by changing the value of "1" again. In addition, the reset condition is arbitrary.

[0027] The specific abnormality described above is not limited to an overvoltage abnormality. For example, an overcurrent abnormality in which the current flowing between the input terminal IN and the output terminal OUT becomes excessively large may also be included in the specific abnormality. In addition, a high temperature abnormality in which the temperature at the temperature detection position in the semiconductor device 1 rises to a predetermined temperature or higher may also be included in the specific abnormality. However, in the following, attention will be given to an overvoltage abnormality as a specific abnormality.

[0028] <<First reference example>> 4 shows a switch circuit 910 according to a first reference example. In the switch circuit 910, a charge pump circuit 911 is used to generate a drive voltage Vbst for turning on the output transistor m1, and an enable signal S EN In response to the control signal CNT, the driver 912 drives the output transistor m1 using the drive voltage Vbst.

[0029] FIG. 5 shows a timing chart of when an overvoltage abnormality occurs according to the first reference example. Starting from a state in which the output transistor m1 is controlled to be on by the high-level control signal CNT, when an overvoltage abnormality is detected ("V IN >Vovp_th”), the control signal CNT is transitioned from high level to low level. The transition of the control signal CNT to low level is transmitted to the driver 912 via the level shifter 913, thereby lowering the gate voltage Vg of the output transistor m1, thereby turning off the output transistor m1. In the process of lowering the gate voltage Vg, the voltage (Vg-V OUTWhen the potential Vth falls below the gate threshold voltage Vth of the output transistor m1, the state of the output transistor m1 switches to the off state.

[0030] The input terminal IN is connected to the input voltage V IN is supplied, the inductance of the cable, etc. IN Therefore, the operation from when an overvoltage abnormality is detected to when the output transistor m1 is turned off must be completed in a short time.

[0031] <<Second reference example>> Fig. 6 shows a switch circuit 920 according to a second reference example. The switch circuit 920 in Fig. 6 is an example of the switch circuit 910 in Fig. 4. A charge pump circuit 921, a driver 922, and a level shifter 923 in Fig. 6 correspond to the charge pump circuit 911, the driver 912, and the level shifter 913 in Fig. 4. However, the driver 922 in Fig. 6 is an inverter circuit.

[0032] In the switch circuit 920, a level shifter 923 has a series circuit of a pull-up resistor 924 and a shift transistor 925. The level shifter 923 shifts the level of the control signal CNT. A voltage v1 at a connection node between the pull-up resistor 924 and the shift transistor 925 is the control signal after the level shift. A driver 922 changes the gate voltage Vg to the level of a drive voltage Vbst or an output voltage V OUT By setting the level of m1, the output transistor m1 is set on or off.

[0033] During a high-level period of the control signal CNT, the level shifter 923 turns on the shift transistor 925 to pass a current through the pull-up resistor 924, and the control signal (v1) after the level shift is set to a low level. In response to this, the driver 922 supplies a high-level gate Vg to the output transistor m1, turning on the output transistor m1. Conversely, during a low-level period of the control signal CNT, a low-level gate Vg is supplied to the output transistor m1 through the off-state of the shift transistor 925, and the output transistor m1 is turned off. In the switch circuit 920, a circuit current (current flowing through the resistor 924 and the shift transistor 925) is generated during an on-period of the output transistor m1, but this circuit current is not generated during an off-period of the output transistor m1, so that power consumption during standby can be suppressed.

[0034] Consider a situation in which the control signal CNT transitions from high level to low level in the switch circuit 920. When the control signal CNT transitions from high level to low level, the shift transistor 925 is switched from on to off, and the voltage v1 rises. The faster the rate at which the voltage v1 rises at this time, the faster the output transistor m1 can be switched from on to off. In other words, when focusing on an overvoltage anomaly, the faster the rate at which the voltage v1 rises, the shorter the time required to turn off the output transistor m1 after the overvoltage anomaly is detected, and therefore it is required to increase the rate at which the voltage v1 rises.

[0035] Here, the rising speed of the voltage v1 is determined by the pull-up resistor 924 and the parasitic capacitance added to the node where the voltage v1 is generated. Therefore, in order to increase the rising speed of the voltage v1, it is necessary to set the value of the pull-up resistor 924 to a small value. However, if the value of the pull-up resistor 924 is reduced, a large current flows through the pull-up resistor 924 during the ON period of the output transistor m1, and therefore it becomes necessary to increase the current capacity of the charge pump circuit 921. This not only leads to an increase in the circuit current, but also leads to an increase in the size of the flying capacitor used in the charge pump circuit 921, resulting in an increase in the circuit area. There is a demand for a technology that can reduce the time required to switch the output transistor from ON to OFF while suppressing the circuit current.

[0036] <<3rd reference example>> FIG. 7 shows a switch circuit 930 according to a third reference example. The switch circuit 930 in FIG. 7 is an example of the switch circuit 910 in FIG. 4. A charge pump circuit 931, a driver 932, and a level shifter 933 in FIG. 7 correspond to the charge pump circuit 911, the driver 912, and the level shifter 913 in FIG. 4. The level shifter 933 in FIG. 7 is formed of four P-channel MOSFET transistors P1 to P4, two N-channel MOSFET transistors N1 and N2, and two resistors r1 and r2, and generates a voltage v1 by level-shifting a control signal CNT. The use of the level shifter 933 can suppress the circuit current and reduce the propagation delay.

[0037] However, the configuration of the level shifter 933 is complicated, and a high power supply voltage is required to operate the level shifter 933 correctly. OUT is applied, the source of the transistor P2 is connected to the gate of the transistor P3, and the driving voltage Vbst is applied to the source of the transistor P3. Therefore, in order to operate the level shifter 933 normally, the driving voltage Vbst must be increased by the sum (2×Vth) of the gate threshold voltage of the transistor P2 and the gate threshold voltage of the transistor P3 to the output voltage V OUTIt is necessary to further improve it (first necessity).

[0038] On the other hand, the current limiting operation that limits the current flowing through the output transistor m1 or the output voltage V OUT A soft start operation that gradually increases the differential voltage (Vg-V OUT ) needs to be controlled to be close to the gate threshold voltage Vth of the output transistor m1 (second necessity). Basically, since the high-level gate voltage Vg has a potential equivalent to the drive voltage Vbst, it is difficult to simultaneously satisfy the first and second necessity. In other words, it is difficult to apply the level shifter 933 to a switch circuit that should meet the above demands. Below, several embodiments that take these circumstances into consideration are shown.

[0039] <<First Example>> A first embodiment will be described. FIG. 8 shows the configuration of a switch circuit 100 according to the first embodiment. The switch circuit 100 can be used as the switch circuit 10 in FIG. 1. The switch circuit 100 includes an output transistor M1 which is an output switching element, a shift transistor M2, a control circuit 110, a charge pump circuit 120, a driver 130 which is an output driver (drive circuit), a driver 140 which is a level shift driver, a capacitor C1, and a pull-up resistor R1. The transistors M1 and M2 are N-channel MOSFETs. The shift transistor M2, the driver 140, and the pull-up resistor R1 form a level shifter LVS1.

[0040] The node ND1 is connected to the input terminal IN. Therefore, the voltage at the node ND1 is equal to the input voltage V IN The node ND2 is connected to the output terminal OUT. Therefore, the voltage at the node ND2 is equal to the output voltage V OUT The nodes ND1 and ND2 may be interpreted as the input terminal IN and the output terminal OUT, respectively. The output transistor M1 is provided between the nodes ND1 and ND2. Specifically, the drain of the output transistor M1 is connected to the node ND1, and the input voltage VIN The source of the output transistor M1 is connected to the node ND2. Therefore, when the output transistor M1 is on, the input terminal IN and the output terminal OUT are electrically connected, and when the output transistor M1 is off, the input terminal IN and the output terminal OUT are electrically disconnected.

[0041] The wirings WR1 to WR3 are internal wirings. The voltage on the wiring WR1 is the driving voltage V BST The wire WR2 is connected to the node ND2. Therefore, the voltage at the wire WR2 is the output voltage V OUT The wiring WR3 is connected to the gate of the output transistor M1. The voltage at the wiring WR3 is the gate voltage V G and corresponds to a drive signal for driving the output transistor M1. The capacitor C1 is inserted between the wirings WR1 and WR2. That is, a first terminal of the capacitor C1 is connected to the wiring WR1, and a second terminal of the capacitor C1 is connected to the wiring WR2.

[0042] A first end of the pull-up resistor R1 is connected to the wiring WR1, and a second end of the pull-up resistor R1 is connected to a node ND3. The voltage at the node ND3 is referred to as a voltage V1. The shifting transistor M2 is connected in series to the pull-up resistor R1. The shifting transistor M2 is inserted between the pull-up resistor R1 and the reference potential end. As described above, the voltage at the reference potential end is the voltage VSS, which here coincides with the ground voltage. Specifically, the drain of the shifting transistor M2 is connected to the node ND3. Although a resistor may be inserted between the source of the shifting transistor M2 and the reference potential end, here, the source of the shifting transistor M2 is directly connected to the reference potential end.

[0043] The control circuit 110 is a logic circuit that operates with the internal power supply voltage VDD as a positive power supply voltage and the voltage VSS as a negative power supply voltage. The internal power supply voltage VDD is one of the internal power supply voltages generated by the internal power supply circuit 20, and has a positive DC voltage value. An enable signal S EN and overvoltage detection signal S OVPThe control circuit 110 receives an enable signal S EN and overvoltage detection signal S OVP The control signal CNT according to the signal is output.

[0044] The control circuit 110 outputs an overvoltage detection signal S OVP has a value of “0”, the enable signal S EN has a value of "1", it outputs a high-level control signal CNT and an enable signal S EN When the overvoltage detection signal S has a value of "0", the control signal CNT is output at a low level. OVP When this is input to the control circuit 110, the control circuit 110 outputs an enable signal S EN Regardless of the value of , the level of the control signal CNT is set to low, and thereafter, the level of the control signal CNT is held at low until the reset condition is met.

[0045] The control signal CNT is a signal (original control signal) that specifies the state of the output transistor M1. A high-level control signal CNT specifies that the output transistor M1 is to be set to an on state, and a low-level control signal CNT specifies that the output transistor M1 is to be set to an off state. Thus, a high-level period of the control signal CNT corresponds to an on-specified period that specifies that the output transistor M1 is on, and a low-level period of the control signal CNT corresponds to an off-specified period that specifies that the output transistor M1 is off. A high-level control signal CNT has substantially the potential of the internal power supply voltage VDD, and a low-level control signal CNT has substantially the ground potential (the potential of the voltage VSS).

[0046] The charge pump circuit 120 is an example of a drive voltage generating circuit that operates or does not operate in response to a control signal CNT from the control circuit 110. The control signal CNT is input to the charge pump circuit 120. During a high-level period of the control signal CNT, the charge pump circuit 120 is in an operating state, and a drive voltage V for turning on the output transistor M1 is applied to the wiring WR1. BSTThe charge pump circuit 120 is composed of a combination of an oscillator circuit, a capacitor, and a diode. When the charge pump circuit 120 is in an operating state, the charge pump circuit 120 supplies charge to the wiring WR1 by a charge pump operation that utilizes the oscillation operation of the oscillator circuit, thereby increasing the potential of the wiring WR1 based on the potential of the wiring WR2. As a result, the voltage (V OUT ) is the driving voltage V BST In the low level period of the control signal CNT, the charge pump circuit 120 is stopped. The charge pump circuit 120 being stopped means that the charge pump circuit 120 is in a stopped state. In the stopped state of the charge pump circuit 120, the oscillation operation of the oscillation circuit is not performed, and no charge is supplied from the charge pump circuit 120 to the wiring WR1.

[0047] The driver 130 is connected to the wirings WR1 to WR3 and also to a node ND3. BST and the output voltage V OUT (in other words, the source voltage of the output transistor M1) is supplied to the driver 130. The driver 130 supplies a driving voltage V BST is the positive power supply voltage and the output voltage V OUT The driver 130 is a buffer circuit that drives the node ND3 using the negative power supply voltage V1. G is supplied to the gate of the output transistor M1 through the wiring WR3, thereby driving the output transistor M1 (in other words, driving the gate of the output transistor M1). By driving the output transistor M1, the output transistor M1 is turned on or off.

[0048] The driver 140 is an inverter circuit that drives the internal power supply voltage VDD1 as a positive power supply voltage and the voltage VSS as a negative power supply voltage. The internal power supply voltage VDD1 is one of the internal power supply voltages generated by the internal power supply circuit 20, and has a positive DC voltage value. The internal power supply voltage VDD1 for the driver 140 and the internal power supply voltage VDD for the control circuit 110 may be a common voltage or may be different voltages. A control signal CNT from the control circuit 110 is input to the input terminal of the driver 140. The output terminal of the driver 140 is connected to the gate of the shift transistor M2. The driver 140 supplies an inverted signal of the control signal CNT to the gate of the shift transistor M2. That is, the driver 140 supplies a low-level gate signal to the gate of the shift transistor M2 during a high-level period of the control signal CNT, and supplies a high-level gate signal during a low-level period of the control signal CNT.

[0049] A high-level gate signal to the gate of the shifting transistor M2 has substantially the potential of the internal power supply voltage VDD1, and the shifting transistor M2 is turned on when it receives a high-level gate signal from the driver 140. A low-level gate signal to the gate of the shifting transistor M2 has substantially the potential of the voltage VSS, and the shifting transistor M2 is turned off when it receives a low-level gate signal from the driver 140.

[0050] When the shifting transistor M2 is off, the voltage V1 at the node ND3 is equal to the driving voltage V BST When the shifting transistor M2 is on, a current flows through the pull-up resistor R1, causing the voltage V1 at the node ND3 to increase to the driving voltage V BST 8, which is substantially 0 V. The level shifter LVS1 converts the control signal CNT into a drive voltage V BSTThe shift control signal is generated by level-shifting using the voltage V1. The voltage V1 is the voltage of the shift control signal. The shift control signal has a high level or a low level. When the shift transistor M2 is off, the shift control signal has a high level, and when the shift transistor M2 is on, the shift control signal has a low level. For example, if "V1>V OUT +(V BST -V OUT ) / 2”, the shift control signal has a high level, and <V OUT +(V BST -V OUT ) / 2″, the shift control signal has a low level.

[0051] When the shift control signal is at a high level, the driver 130 supplies a high level gate voltage V G The output transistor M1 is set to the on state by supplying a high-level gate voltage V G is the driving voltage V BST A voltage based on the driving voltage V BST and the driving voltage V BST In some cases, the difference voltage (V BST -V OUT ) is greater than the gate threshold voltage of the output transistor M1.

[0052] When the shift control signal is at a low level, the driver 130 supplies a low-level gate voltage V G The output transistor M1 is set to the off state by supplying a low-level gate voltage V G is the output voltage V OUT (i.e., a voltage based on the source voltage of the output transistor M1), which is substantially the output voltage V OUT The output voltage V OUT The low-level gate voltage V Gis supplied to the output transistor M1, the gate-source voltage of the output transistor M1 is less than the gate threshold voltage of the output transistor M1.

[0053] As can be understood from the above description, the switch circuit 100 performs control such that the output transistor M1 is turned off when the control signal CNT has a low level, and the output transistor M1 is turned on when the control signal CNT has a high level.

[0054] Here, the switch circuit 920 in FIG. 6 is compared with the switch circuit 100 in FIG. 8. In the switch circuit 920 in FIG. 6, when the control signal CNT has a high level, that is, when the output transistor (m1) is turned on, the shift transistor (925) is turned on to allow a current to flow through the pull-up resistor (924). In contrast, in the switch circuit 100 in FIG. 8, when the control signal CNT has a low level, that is, when the output transistor (M1) is turned off, the shift transistor (M2) is turned on to allow a current to flow through the pull-up resistor (R1). Therefore, in the switch circuit 100, when the output transistor M1 is switched from on to off, the voltage V1 is lowered by utilizing the on of the shift transistor M2, so that the rate at which the voltage V1 falls is increased. In other words, in the switch circuit 100, the gate voltage V of the output transistor M1 is lowered only after the control signal CNT is switched from a high level to a low level. G This shortens the propagation delay until the output transistor M1 switches from a high level to a low level, and allows the output transistor M1 to be quickly turned off when an overvoltage is detected.

[0055] On the other hand, when the output transistor M1 is switched from off to on, the shift transistor M2 is switched from on to off, and the parasitic capacitance added to the node ND3 is charged via the pull-up resistor R1, thereby raising the voltage V1 to a high level. For this reason, the propagation delay when turning on the output transistor M1 (the propagation delay from the time when the control signal CNT is switched from a low level to a high level to the time when the gate voltage V of the output transistor M1 is GThe propagation delay from low level to high level is relatively long. However, even if the propagation delay when turning on the output transistor M1 is somewhat long, this does not cause any problems in terms of application.

[0056] In addition, since no current flows through the pull-up resistor R1 and the shift transistor M2 during the on-period of the output transistor M1 except during a transient response, the charge pump circuit 120 only needs to have the current capacity required to turn on the output transistor M1. This allows the element size of the charge pump circuit 120 to be reduced.

[0057] As a trade-off, when the control signal CNT is at a low level, a current is generated through the pull-up resistor R1 and the shift transistor M2. However, the generation of this current does not lead to an increase in the current capacity of the charge pump circuit 120. This is because the operation of the charge pump circuit 120 is stopped in the first place during the low level period of the control signal CNT. When the control signal CNT switches from a high level to a low level, the charge on the wiring WR1 is pulled out through the pull-up resistor R1 and the shift transistor M2, and the drive voltage V BST When the voltage drops to its lowest point, the circuit current becomes zero, so no problem occurs.

[0058] In addition, the driving voltage V BST During the decrease in output voltage V, the charge in the wiring WR2 flows through the parasitic diode in the driver 130 toward the wiring WR1 (see FIG. 9) and is discharged through the pull-up resistor R1 and the shift transistor M2. OUT 9 shows a part of the internal configuration of the driver 130. The driver 130 has an output stage made up of transistors 131 and 132. The transistor 131 is a P-channel type MOSFET, and the transistor 132 is an N-channel type MOSFET. The parasitic diodes in the driver 130 mentioned above refer to the parasitic diodes of the transistors 131 and 132.

[0059] The source of the transistor 131 is connected to the wiring WR1, the drains of the transistors 131 and 132 are connected to the wiring WR3, and the source of the transistor 132 is connected to the wiring WR2. In the driver 130 of FIG. 9, the transistor 131 is controlled to be on and the transistor 132 is controlled to be off during a high-level period of the shift control signal. BST is supplied to the wiring WR3, and during the low level period of the shift control signal, the transistor 131 is turned off and the transistor 132 is turned on, thereby generating the output voltage V OUT is supplied to the wiring WR3. A parasitic diode having a forward direction from the drain to the source is added to the transistor 131. A parasitic diode having a forward direction from the source to the drain is added to the transistor 132.

[0060] <<Second Example>> The second embodiment will be described. The second embodiment and the third and fourth embodiments described later are based on the first embodiment, and for matters not specifically mentioned in the second to fourth embodiments, the description of the first embodiment also applies to the second to fourth embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third and fourth embodiments described later). As long as there is no contradiction, any combination of the first to fourth embodiments may be used.

[0061] FIG. 10 shows the configuration of a switch circuit 200 according to the second embodiment. The switch circuit 200 can be used as the switch circuit 10 of FIG. 1. The switch circuit 200 differs from the switch circuit 100 of FIG. 8 in that a driver 141 and a shift transistor M3 are added to the switch circuit 100, and except for this addition and unless otherwise noted, has the same configuration as the switch circuit 100. In the switch circuit 200, a level shifter LVS2 is formed by the shift transistors M2 and M3, the drivers 140 and 141, and a pull-up resistor R1. The transistor M3 is an N-channel MOSFET. The configuration and operation of the switch circuit 200 will be described with a focus on the differences from the switch circuit 100.

[0062] The shift transistor M3 is connected in series to the pull-up resistor R1, similar to the shift transistor M2. Specifically, in the switch circuit 200, the drains of the shift transistors M2 and M3 are connected to a node ND3. Although a resistor may be inserted between the source of the shift transistor M2 and the reference potential end, the source of the shift transistor M2 is directly connected to the reference potential end here. Although a resistor may be inserted between the source of the shift transistor M3 and the reference potential end, the source of the shift transistor M3 is directly connected to the reference potential end here.

[0063] The driver 141 is an inverter circuit that drives with the internal power supply voltage VDD2 as a positive power supply voltage and the voltage VSS as a negative power supply voltage. A control signal CNT from the control circuit 110 is input to the input terminal of the driver 141. The output terminal of the driver 141 is connected to the gate of the shift transistor M3. The driver 141 supplies an inverted signal of the control signal CNT to the gate of the shift transistor M3. That is, the driver 141 supplies a low-level gate signal to the gate of the shift transistor M3 during a high-level period of the control signal CNT, and supplies a high-level gate signal during a low-level period of the control signal CNT.

[0064] A high-level gate signal to the gate of the shifting transistor M3 has substantially the potential of the internal power supply voltage VDD2, and the shifting transistor M3 is turned on when it receives a high-level gate signal from the driver 141. A low-level gate signal to the gate of the shifting transistor M3 has substantially the potential of the voltage VSS, and the shifting transistor M3 is turned off when it receives a low-level gate signal from the driver 141.

[0065] When the shifting transistors M2 and M3 are both off, the voltage V1 at the node ND3 is equal to the driving voltage V BSTWhen at least one of the shifting transistors M2 and M3 is on, a current flows through the pull-up resistor R1 and the on-state shifting transistor, causing the voltage V1 at the node ND3 to increase by a factor of 1. BST 10, which is substantially 0 V. The level shifter LVS2 converts the control signal CNT into a drive voltage V BST A shift control signal is generated by level-shifting using the voltage V1. The voltage V1 is the voltage of the shift control signal. The shift control signal has a high level or a low level. When both the shift transistors M2 and M3 are off, the shift control signal has a high level, and when at least one of the shift transistors M2 and M3 is on, the shift control signal has a low level.

[0066] In the switch circuit (100, 200) according to the first or second embodiment, a method is adopted in which the output transistor M1 is turned on when the shifting transistors (M2, M3) are off, so that when the power supply to the driver constituting the level shifter is completely lost, the output transistor M1 is fixed in the on state. This is not desirable for the load connected to the output terminal OUT. In the switch circuit 100 according to the first embodiment (see FIG. 8), the input voltage V IN There is no problem if the internal power supply voltage VDD1 is always generated normally when the internal power supply voltage VDD1 is equal to or higher than a certain voltage. However, when a relatively high current capacity is required, an external capacitor may be connected to the semiconductor device 1, and care must be taken in this case. In the second embodiment, it is assumed that an external capacitor is assigned to the internal power supply voltage VDD1.

[0067] 11 shows a partial configuration of the semiconductor device 1 related to the internal power supply circuit 20. The internal power supply circuit 20 according to the second embodiment operates in response to an input voltage V IN11, the internal power supply voltages VDD, VDD1, and VDD2 are shown separately, but the internal power supply voltage VDD and the internal power supply voltage VDD1 may be a common voltage. It is also possible to make the internal power supply voltage VDD and the internal power supply voltage VDD2 a common voltage. The internal power supply voltage VDD may be generated separately from the internal power supply voltages VDD1 and VDD2.

[0068] The terminal REG is one of the external terminals of the semiconductor device 1. The terminal REG is provided on the semiconductor device 1 (in other words, on the housing CS of the semiconductor device 1) and is a metal terminal exposed from the housing CS of the semiconductor device 1 to the outside of the semiconductor device 1. The internal power supply circuit 20 is connected to the terminal REG and outputs an internal power supply voltage VDD1 to the terminal REG. The terminal REG is connected to a capacitor C REG is connected to the first end of the capacitor C REG The second end of the capacitor C is connected to ground. REG Since the internal power supply voltage VDD1 accumulates charge corresponding to the internal power supply voltage VDD1, the internal power supply voltage VDD1 can be used as a power supply with high current capacity. On the other hand, the internal power supply voltage VDD2 is not output to the outside of the semiconductor device 1. In other words, the semiconductor device 1 does not have an external terminal to which the internal power supply voltage VDD2 is applied. The current capacity of the internal power supply voltage VDD2 is smaller than the current capacity of the internal power supply voltage VDD1.

[0069] Input voltage V IN When the input voltage V is equal to or higher than a predetermined lower limit voltage, the internal power supply circuit 20 generates the internal power supply voltages VDD1 and VDD2. When the internal power supply voltage VDD is generated separately from the internal power supply voltages VDD1 and VDD2, IN When is equal to or greater than a predetermined lower limit voltage, an internal power supply voltage VDD is also generated.

[0070] Input voltage V IN When the input voltage V is equal to or higher than a predetermined lower limit voltage and no short circuit abnormality, which will be described later, occurs, the internal power supply voltage VDD1 has a predetermined positive DC voltage value VAL1. INis equal to or higher than a predetermined lower limit voltage, the internal power supply voltage VDD2 always has a predetermined positive DC voltage value VAL2, regardless of whether or not a short circuit abnormality, which will be described later, occurs. The DC voltage values ​​VAL1 and VAL2 basically match each other, but may differ from each other.

[0071] The above-mentioned short circuit abnormality refers to a state in which the terminal REG is short-circuited to ground. A short circuit abnormality can occur due to unnecessary solder or the like that may be present on the board on which the semiconductor device 1 is mounted. When a short circuit abnormality occurs, the input voltage V IN Since the internal power supply voltage VDD1 is 0 V regardless of the magnitude of the short circuit, the shift transistor M2 is fixed in the off state. However, since the driver 141 operates without being affected by the short circuit anomaly, the shift transistor M3 can be controlled to be on.

[0072] The driver 140, which uses the internal power supply voltage VDD1 with a relatively high current capacity, can operate at a relatively high speed, and when there is no short circuit, the specified contents of the control signal CNT are quickly reflected in the state of the output transistor M1 due to the high-speed operation of the driver 140. The driver 141, which uses the internal power supply voltage VDD2 with a relatively low current capacity, is not suitable for high-speed operation, but even when a short circuit occurs, it can generate a voltage V1 (a low-level shift control signal) for turning off the output transistor M1 by turning on the shift transistor M3. That is, according to the switch circuit 200, when a short circuit occurs, it is possible to safely cut off the connection between the input terminal IN and the output terminal OUT.

[0073] In addition, when the internal power supply voltage VDD and the internal power supply voltage VDD1 are common, the input voltage V IN When a short circuit occurs while the voltage is equal to or higher than a predetermined lower limit voltage, the control signal CNT is fixed at a low level, so that the shift transistor M3 is turned on and the output transistor M1 is fixed at an off state.

[0074] Input voltage V IN When the input voltage V INSince the control signal CNT is at a low level, no problem occurs. IN As the input voltage V IN Since the level shifter LVS2 extracts the charge on the wiring WR1 before the potential drops to its lowest point, the output transistor M1 does not turn on.

[0075] <<Third Example>> A third embodiment will now be described. The switch circuit 100 in Fig. 8 may be modified to a switch circuit 100a in Fig. 12. By adding a resistor R2 and a diode D1 to the switch circuit 100, the switch circuit 100a is obtained.

[0076] The differences between the switch circuits 100 and 100a will be described. In the switch circuit 100a, a resistor R2 is added to the components of the level shifter LVS1. In the switch circuit 100a, the anode of the diode D1 is connected to the wiring WR2, and the cathode of the diode D1 is connected to the node ND3. In the switch circuit 100a, the resistor R2 is inserted between the source of the shift transistor M2 and the reference potential point. That is, in the switch circuit 100a, the source of the shift transistor M2 is connected to the reference potential terminal via the resistor R2.

[0077] In the absence of resistor R2 and diode D1, when the shifting transistor M2 is set to on, a driving voltage V BST This causes a voltage drop of 100mV, so the drive voltage V BST The resistor R1 is required to have a withstand voltage exceeding 1 V. The provision of the resistor R2 and the diode D1 relaxes the withstand voltage requirement for the resistor R1. That is, in the switch circuit 100a, when the shift transistor M2 is set to ON, the current flowing through the resistor R1 is limited by the resistor R2, and the voltage across the resistor R1 is reduced accordingly. In addition, in the switch circuit 100a, the presence of the diode D1 reduces the drop in voltage V1 to a voltage (V OUT-Vf), where Vf represents the forward voltage of the diode D1. Note that since the value of the resistor R2 affects the propagation delay and the fluctuation range of the voltage V1, it is preferable to set the value of the resistor R2 to be sufficiently smaller than the value of the resistor R1.

[0078] Just as the switch circuit 100 is modified into the switch circuit 100a, the switch circuit 200 in Fig. 10 may be modified into the switch circuit 200a in Fig. 13. The switch circuit 200a is obtained by adding resistors R2 and R3 and a diode D1 to the switch circuit 200.

[0079] The differences between the switch circuits 200 and 200a will be described. In the switch circuit 200a, resistors R2 and R3 are added to the components of the level shifter LVS2. In the switch circuit 200a, the anode of the diode D1 is connected to the wiring WR2, and the cathode of the diode D1 is connected to the node ND3. In the switch circuit 200a, a resistor R2 is inserted between the source of the shift transistor M2 and the reference potential point, and a resistor R3 is inserted between the source of the shift transistor M3 and the reference potential point. That is, in the switch circuit 200a, the source of the shift transistor M2 is connected to the reference potential end via the resistor R2, and the source of the shift transistor M3 is connected to the reference potential end via the resistor R3.

[0080] As described for the switch circuit 100a, the withstand voltage requirement for the resistor R1 is relaxed by providing the resistors R2 and R3 and the diode D1. Note that, since the values ​​of the resistors R2 and R3 affect the propagation delay and the fluctuation range of the voltage V1, it is preferable to set the combined resistance value of the resistors R2 and R3 (i.e., the resistance value of the parallel circuit of the resistors R2 and R3) sufficiently smaller than the value of the resistor R1.

[0081] <<Fourth Example>> A fourth embodiment will be described. In the fourth embodiment, applied techniques, modified techniques, or supplementary matters for the above-mentioned items will be described.

[0082] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0083] The channel types of FETs (field effect transistors) shown in each embodiment are merely examples, and the channel type of any FET may be changed between P-channel and N-channel without departing from the spirit of the above.

[0084] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0085] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0086] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0087] A switch circuit (100, 200, 100a, 200a) according to an aspect of the present disclosure includes an output switching element (M1) provided between a first node and a second node, and a drive voltage (V BST a drive voltage generation circuit (120) configured to generate a shift control signal by level-shifting an original control signal (CNT) that specifies the state of the output switching element using the drive voltage, level shifters (LVS1, LVS2) configured to generate a shift control signal by level-shifting an original control signal (CNT) that specifies the state of the output switching element using the drive voltage, and a drive circuit (130) configured to drive the output switching element in accordance with the shift control signal based on the drive voltage, wherein the level shifter has a pull-up resistor (R1) and a shift transistor (e.g., M2) connected in series to the pull-up resistor, and is configured to generate the shift control signal that turns off the output switching element by turning on the shift transistor to flow a current through the pull-up resistor when the original control signal specifies the off of the output switching element (first configuration).

[0088] This makes it possible to reduce the circuit current while shortening the propagation delay when the output switching element is switched from on to off.

[0089] In the switch circuit according to the first configuration, the drive voltage may be supplied to a first terminal of the pull-up resistor, and the level shifter may be configured (second configuration) to generate the shift control signal at a connection node (ND3) between the second terminal of the pull-up resistor and the shift transistor.

[0090] In the switch circuit according to the second configuration, the level shifter may be configured (third configuration) to turn off the shift transistor during an on-designation period in which the original control signal designates the output switching element to be on, and to turn on the shift transistor to cause a current to flow through the pull-up resistor during an off-designation period in which the original control signal designates the output switching element to be off, thereby lowering the voltage of the shift control signal compared to that during the on-designation period.

[0091] In the switch circuit according to any one of the first to third configurations, the output switching element is an output transistor formed of an N-channel type field effect transistor, and the drive voltage and the source voltage (V OUT ) is supplied, and the drive circuit receives the shift control signal when the shift transistor is off and supplies a voltage based on the drive voltage to the gate of the output transistor to turn on the output transistor, and receives the shift control signal when the shift transistor is on and supplies a voltage based on the source voltage to the gate of the output transistor to turn off the output transistor (fourth configuration).

[0092] In the switch circuit according to any of the above first to fourth configurations, the level shifter may have, as the shift transistors, first and second shift transistors (M2, M3) each connected in series to the pull-up resistor, and may be configured to turn on or off the first shift transistor in accordance with the original control signal based on a first power supply voltage (VDD1), turn on or off the second shift transistor in accordance with the original control signal based on a second power supply voltage (VDD2), and generate the shift control signal that turns off the output switching element when at least one of the first shift transistor and the second shift transistor is on (fifth configuration).

[0093] This makes it possible to turn off the output switching element even if either the first power supply voltage or the second power supply voltage is lost.

[0094] In the switch circuit according to the fifth configuration, only one of the first power supply voltage and the second power supply voltage may be output from an external terminal (REG) provided in a housing (CS) that houses the switch circuit and exposed from the housing (sixth configuration).

[0095] In the switch circuit according to any one of the first to sixth configurations, the drive voltage generating circuit may be a charge pump circuit, and the charge pump circuit may be stopped during a period in which the switching element is controlled to be off (seventh configuration). [Explanation of symbols]

[0096] 1 Semiconductor device CS case 10, 910, 920, 930, 100, 200, 100a, 200a Switch circuit 20 Protection circuit 30 Internal power circuit 31 Overvoltage detection circuit 31a, 31b resistance 31c Comparator VS Voltage Source C OUT Output Capacitor IN Input terminal OUT Output terminal GND Ground terminal EN Enable terminal REG terminal V IN Input voltage V OUT Output Voltage S EN Enable Signal S OVP Overvoltage detection signal V DIV Voltage V OVP Judgment Reference Voltage VSS voltage 911, 921, 931 Charge pump circuit 912, 922, 932 Driver 913, 923, 933 Level Shifter 924 Pull-up resistor 925 Shift Transistor P1~P6, N1, N2 transistors r1, r2 resistance CNT Control Signal Vbst drive voltage Vg Gate voltage 110 Control circuit 120 Charge pump circuit 130, 140, 141 Driver 131, 132 Transistors M1 Output transistor M2, M3 Shift transistor R1 Pull-up resistor R2, R3 resistance D1 Diode C1, C REG Capacitor WR1~WR3 wiring ND1~ND3 nodes V BST Driving voltage V G Gate Voltage VDD, VDD1, VDD2 internal power supply voltage

Claims

1. an output switching element provided between the first node and the second node; a drive voltage generating circuit configured to generate a drive voltage for turning on the output switching element; a level shifter configured to generate a shift control signal by level-shifting an original control signal that designates a state of the output switching element using the drive voltage; a drive circuit configured to drive the output switching element in accordance with the shift control signal based on the drive voltage; The level shifter has a pull-up resistor and a shifting transistor connected in series to the pull-up resistor, and generates the shift control signal for turning off the output switching element by turning on the shifting transistor and causing a current to flow through the pull-up resistor when the original control signal specifies turning off the output switching element. , switch circuit.

2. The drive voltage is supplied to a first end of the pull-up resistor; The level shifter generates the shift control signal at a connection node between the second end of the pull-up resistor and the shifting transistor.

2. The switch circuit according to claim 1.

3. The level shifter turns off the shift transistor during an ON designation period in which the original control signal designates the ON of the output switching element, and turns on the shift transistor to cause a current to flow through the pull-up resistor during an OFF designation period in which the original control signal designates the OFF of the output switching element, thereby lowering the voltage of the shift control signal compared to the ON designation period.

3. The switch circuit according to claim 2.

4. the output switching element is an output transistor formed of an N-channel type field effect transistor, the drive voltage and the source voltage of the output transistor are supplied to the drive circuit; The drive circuit receives the shift control signal when the shifting transistor is off and supplies a voltage based on the drive voltage to the gate of the output transistor to turn on the output transistor, and receives the shift control signal when the shifting transistor is on and supplies a voltage based on the source voltage to the gate of the output transistor to turn off the output transistor.

4. A switch circuit according to claim 1.

5. The level shifter has, as the shift transistors, first and second shift transistors each connected in series to the pull-up resistor, turns on or off the first shift transistor in accordance with the original control signal based on a first power supply voltage, turns on or off the second shift transistor in accordance with the original control signal based on a second power supply voltage, and generates the shift control signal for turning off the output switching element when at least one of the first shift transistor and the second shift transistor is on.

4. A switch circuit according to claim 1.

6. Only one of the first power supply voltage and the second power supply voltage is output from an external terminal that is provided in a housing that houses the switch circuit and is exposed from the housing.

6. The switch circuit according to claim 5.

7. the drive voltage generating circuit is a charge pump circuit, The charge pump circuit stops during the period in which the switching element is controlled to be off.

4. A switch circuit according to claim 1.

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