Memory system, access control method, and program

Abstract

To provide a memory access technique that enables performance improvement without increasing the load on a host device side.SOLUTION: A memory system is provided, comprising a non-volatile memory having a plurality of logical areas, and a controller for controlling an access to each logical area of the non-volatile memory, where the controller includes an execution order control unit configured to set the execution order of received commands according to predetermined priority levels assigned to the logical areas specified by the commands.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a memory system, an access control method, and a program. [Background technology]

[0002] For example, there is a memory system equipped with a non-volatile memory such as an SSD (Solid State Drive) that uses NVMe (Non-Volatile Memory Express) as an interface protocol. Such a memory system logically divides and uses the storage area it has. Each divided logical area is called an NS (Name Space).

[0003] As a technique for improving the usability of SSDs, there is a technique in which a host device sets a priority of Atomic Write cancellation for each NS in order to adaptively control the performance of canceling a write request (write command) to the SSD (see, for example, Patent Document 1). According to the technique disclosed in Patent Document 1, a cancellation priority is set for each NS, and the cancellation processing method is changed according to the set priority. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-107318 A Summary of the Invention [Problem to be solved by the invention]

[0005] The following analysis was performed by the inventors.

[0006] In general, in a memory system having an NVMe SSD or the like, the NS is generated for each application. Depending on the application, high speed may or may not be required. For example, in an in-vehicle device, driving information for automatic driving (current location and surrounding information) requires immediacy even at the expense of other information. On the other hand, there is no problem if mileage and remaining fuel information are left for later. Therefore, when such a memory system is used in an in-vehicle device, this information can be stored in different NSs for each application.

[0007] According to the technology disclosed in Patent Document 1, the processing speed of a single command changes depending on the priority set in the NS. However, in such a memory system, commands are processed in the order of issue. Therefore, even if information that requires immediacy is stored in an NS with a high priority, if a command for that information is issued after a command for an NS for which information that does not require immediacy is set, the former will only be executed after the latter has been processed. Furthermore, the technology disclosed in Patent Document 1 only supports cancel commands. However, there are a wide variety of commands from the host device to the memory system, in addition to the cancel command.

[0008] To control the execution order of consecutively issued commands, the host device needs to control the order in which the commands are issued to non-volatile memory such as an NVMe SSD, which requires complex processing in the host device application.

[0009] Thus, currently, when multiple commands are issued in succession, unless complex processing is imposed on the host device, the command execution order cannot be appropriately controlled, resulting in waiting times in processing within the memory system, which prevents the memory system from speeding up processing and prevents the response performance from being fully utilized.

[0010] The present disclosure has been made in consideration of the above circumstances, and has an object to provide a memory access technique that can improve performance without increasing the load on the host device side. [Means for solving the problem]

[0011] According to a first aspect of the present disclosure, The memory system is a non-volatile memory having a plurality of logic regions; and a controller for controlling access to each logical area of ​​the non-volatile memory. The controller includes an execution order control unit that determines an execution order of received commands according to a priority order predetermined for the logic area specified by the command.

[0012] According to a second aspect of the present disclosure, An access control method for controlling access to each logic area in a non-volatile memory having a plurality of logic areas includes the following steps: The execution order of the received commands is determined according to the priority order previously determined for the logic area designated by the command.

[0013] According to a third aspect of the present disclosure, a program causes a controller of a non-volatile memory having a plurality of logical areas to execute the above access control method.

[0014] These programs can be recorded on a computer-readable storage medium. The storage medium can be a non-transient medium such as a semiconductor memory, a hard disk, a magnetic recording medium, an optical recording medium, etc. The present invention can also be embodied as a computer program product. Effect of the Invention

[0015] According to the present disclosure, it is possible to improve the performance of a memory system without increasing the load on the host device side. [Brief description of the drawings]

[0016] [Figure 1] 1A and 1B are diagrams illustrating an example of a configuration and hardware, respectively, of a memory system according to an embodiment of the present disclosure. [Diagram 2] 1A and 1B are diagrams illustrating an example of the configuration of an information processing system and a memory system, respectively, according to an embodiment of the present disclosure. [Diagram 3] 1A to 1C are diagrams for explaining an example of a create command, an MS Management command, and a command issued during operation, respectively, according to an embodiment of the present disclosure. [Figure 4] FIG. 2A is a diagram for explaining an example of an MS table according to an embodiment of the present disclosure, and FIG. 2B is a diagram for explaining an example of execution order control according to an embodiment of the present disclosure. [Diagram 5] 13 is a flowchart of an NS creation process according to an embodiment of the present disclosure. [Figure 6] 11 is a flowchart of a command process according to an embodiment of the present disclosure. [Figure 7] 11A and 11B are diagrams for explaining an example of a command execution order according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an outline of one embodiment of the present disclosure (hereinafter, referred to as the present embodiment) will be described with reference to the drawings. Note that the reference symbols in the drawings are given for convenience to each element as an example to aid in understanding, and are not intended to limit the present disclosure to the illustrated form. Furthermore, the connection lines between blocks in the drawings and the like referred to in the following description include both bidirectional and unidirectional lines. The unidirectional arrows are intended to diagrammatically indicate the flow of the main signal (data), and do not exclude bidirectionality.

[0018] In addition, although there are ports and interfaces at the connection points of input and output of each block in the figure, they are not shown in the figure. In the following explanation, "A and / or B" means A or B, or A and B.

[0019] <<First embodiment>> Hereinafter, one embodiment (first embodiment) of the present disclosure will be described with reference to the drawings.

[0020] The memory system 200 of this embodiment is a system capable of controlling the execution order of commands in a storage area configured with a non-volatile memory, for example, an SSD (Solid State Drive) that employs NVMe (Non-Volatile Memory Express). The memory system 200 operates as a storage device, stores received data, and outputs the stored data in response to a request.

[0021] In this embodiment, the storage area (non-volatile memory) is divided into multiple logical areas (Name Space; NS), and a priority is predefined for each area. Then, received commands are executed in order of the NS priority specified by each command.

[0022] 1A is a configuration diagram of a memory system 200 according to this embodiment. The memory system 200 is implemented, for example, by an NVMe SSD, and includes a controller 210 and a non-volatile memory 220 that functions as a storage area.

[0023] The non-volatile memory 220 is realized by, for example, a NAND flash memory. In this embodiment, the non-volatile memory 220 has a plurality of logical areas that are logically divided. As described above, each logical area is called a Name Space (NS). A priority that determines the execution order of commands is set in advance for each NS.

[0024] 1 illustrates an example in which the non-volatile memory 220 includes NS231, NS232, and NS233. However, the number of NSs may be more than one, and is not limited to three. Hereinafter, when it is not necessary to distinguish between the NSs, they will be represented by NS230.

[0025] The controller 210 exchanges data (signals) with the host device that issues the command, and also controls access to the non-volatile memory 220. The command received from the host device includes information that specifies the NS 230 in which the target data for executing the command is stored.

[0026] The controller 210 includes an execution order control unit 212 that controls the execution order of commands. The execution order control unit 212 of this embodiment determines the execution order of received commands according to a priority order predetermined for the NS 230 specified by the command.

[0027] In the controller 210, unexecuted commands received from the host device are queued in the execution order. When the execution order control unit 212 of this embodiment receives a new command from the host device, it rearranges the commands queued in the execution queue in the order of priority of the NS 230 specified by the command. Specifically, the commands are rearranged so that the command specifying the NS 230 with the higher priority is executed first.

[0028] The controller 210 executes commands according to the execution queue rearranged by the execution order control unit 212. Commands received from the host device include, for example, read, erase, and write.

[0029] Additionally, the controller 210 may detect and correct errors in the non-volatile memory 220. Also, the controller 210 may execute a process of disabling a memory block in which some kind of defect has occurred and allocating a spare block (redundant block) instead. Furthermore, when a NAND flash memory is used for the non-volatile memory 220, the controller 210 may store the number of erase operations for each memory block of the NAND flash memory and perform wear leveling of the number of rewrite operations.

[0030] As described above, according to this embodiment, the memory system 200 sets the command execution priority in advance for each NS 230. Then, the command execution order is controlled according to the priority set for the NS 230 specified by each command. That is, the memory system 200 rearranges the command execution order so that a command specifying an NS 230 with a higher priority is executed preferentially.

[0031] As a result, the memory system 200 of this embodiment can physically control the processing performance on the side of the memory system 200. That is, according to this embodiment, in the memory system 200 in which multiple NSs 230 are set, appropriate priority processing can be realized on the host device side, i.e., without burdening the user.

[0032] This makes it possible to suppress the degradation of NS performance caused by commands with low priority but high load, and according to this embodiment, it is possible to realize a memory system 200 that is highly efficient, fast, and responsive. In other words, it is possible to make the most of the performance of the memory system.

[0033] Furthermore, according to this embodiment, in a system in which IOs (Input / Output; commands) with different performance requirements coexist, command processing can be realized with a simple configuration, at low cost, and with a desired priority order, compared to methods using virtualization, etc. For example, this is particularly useful in data centers and edge areas with a variety of uses.

[0034] <<Second embodiment>> Next, a second embodiment of the present disclosure will be described. In this embodiment, when the controller 210 configures (creates) a logical area (NS230) in the non-volatile memory 220 in accordance with an instruction from the host device, the controller 210 sets the priority of the NS230.

[0035] 2A is a diagram showing the overall configuration of an information processing system 100 according to this embodiment. The information processing system 100 according to this embodiment includes a host device 300 and a memory system 200. The memory system 200 is realized by an SSD or the like, similarly to the first embodiment.

[0036] Hereinafter, in this embodiment, the memory system 200 will be referred to as SSD 200. Furthermore, with regard to the various functions within the SSD 200, those that are the same as those in the first embodiment will be given the same reference numerals.

[0037] The host device 300 issues commands to the SSD 200. The host device 300 is, for example, a PC (Personal Computer), a server, a storage, an Edge device, etc. The host device 300 is not limited to these, and may be any device that is capable of issuing commands to the SSD 200 and transmitting and receiving data to and from the SSD 200.

[0038] In this embodiment, the host device 300 includes, for example, an NVMe device driver, and issues various commands defined by the NVMe specifications to the SSD 200. Specifically, the command issued by the host device 300 to the SSD 200 includes information for identifying the NS 230 to be used.

[0039] When creating an NS 230 in the SSD 200, the host device 300 transmits a create command 310 to the SSD 200. The create command 310 is issued for the number of NSs 230 to be created. For example, when creating three NSs 230, a create command 310 with three NSIDs 311 is issued for each NS 230.

[0040] An example of the create command 310 is shown in Fig. 3(a). The create command 310 comprises an NSID 311, a priority 312, a size 313, and a function 314. The NSID 311 is an identifier (ID) capable of uniquely identifying the NS 230 to be created. The priority 312 is the priority of the NS 230. The size 313 is the size of the logical area of ​​the NS to be created. The function 314 is information indicating the use of the NS 230.

[0041] For example, the priority may be set using an existing NS Management command. An example of an NS Management command 320 is shown in Fig. 3(b). In this case, the priority of the NSID is set in the SSD using a currently reserved bit in the Function Field 321, for example, of the Operation Code (Opcode) of the NS Management command 320. Note that the priority setting is not limited to this, and any reserved bit in the field in the existing command may be used.

[0042] Note that one create command 310 may include the above information for each NS 230 together with the number of divisions.

[0043] A command 330 issued by the host device 300 to the SSD 200 during operation includes a command ID 331 that uniquely identifies the command 330, an NSID 332 of the NS 230 in which the data to be executed (processed) is stored, and the processing content (command processing content) 333 of the command, as shown in FIG. 3(c).

[0044] The SSD 200 basically has the same configuration as in the first embodiment. Hereinafter, components having the same functions as in the first embodiment will be given the same names and reference numerals.

[0045] As shown in FIG. 2( b ), the SSD 200 includes a controller 210, a non-volatile memory 220, and a buffer memory 240.

[0046] As in the first embodiment, the controller 210 functions as an interface with the host device 300 and controls access to the non-volatile memory 220. The controller 210 of this embodiment comprises an NS creation unit 211, an execution order control unit 212, an execution unit 213, a transmission / reception unit 214, and an NS management unit 215.

[0047] The transmission / reception unit 214 transmits and receives data, including commands, to and from the host device 300 .

[0048] When the NS creation unit 211 receives a create command 310 from the host device 300, it generates the designated number of NSs 230 in the non-volatile memory 220. At this time, it sets a priority order for each NS 230. In other words, the NS creation unit 211 also functions as a priority order setting unit.

[0049] Specifically, the NS creation unit 211 divides the non-volatile memory 220 into a designated number of logical areas having a designated size, and each logical area is designated as an NS 230. Note that, before the generation, any existing NS is deleted.

[0050] At this time, the NS creation unit 211 generates an NS table 250 that includes each piece of information specified in the create command 310 and information that associates the generated NS 230 with a physical area (simply referred to as a physical area). The generated NS table 250 is stored in the NS management unit 215. The NS management unit 215 is constructed in, for example, a storage unit or the like of the controller 210. It should be noted that the NS management unit 215 may also be constructed in the non-volatile memory 220.

[0051] 4(a) shows an example of the NS table 250 generated by the NS creation unit 211. The NS table 250 includes, for each generated NS 230, its NSID 251, priority 252, size 253, function 254, and physical area 255.

[0052] The NSID 251, the priority 252, the size 253, and the function 254 are registered with information of the same name in the create command 310 when the NS 230 is generated. The physical area 255 is information that associates each generated NS 230 with a physical utilization area in the non-volatile memory 220.

[0053] As in the first embodiment, the execution order control unit 212 controls the execution order of commands 330 issued by the host device 300. When a command 330 is issued from the host device 300, the execution order control unit 212 queues it in an execution queue. At this time, the execution order control unit 212 compares the priority of the NSID 332 included in the queued command 330 (hereinafter referred to as the command priority) with the priority of a newly received command to be queued, and inserts the command into the execution queue so that it is executed in the order of priority.

[0054] When the execution order control unit 212 receives the command 330 via the transmission / reception unit 214, it extracts the NSID 332 included in the command 330. Then, it refers to the NS table 250 and identifies the priority order 252 associated with the NSID 251 that matches the extracted NSID 332. Then, it inserts the command 330 into the execution queue. At this time, for example, the identified priority order 252 may be added to the command 330.

[0055] A method in which the execution order control unit 212 adds a newly received command 330 to the execution queue will be described with reference to Fig. 4(b). Note that in Fig. 4(b), command processing content 333 of command 330 is omitted. In Fig. 4(b), as an example, it is assumed that command 330 with command ID 331 of "command 08" and specified NSID 332 of "002" has been received.

[0056] Using the above-mentioned method, the execution order control unit 212 assigns the priority 252 to the newly received command 330. In this case, since the NSID 332 is "002", the priority 252 is 2.

[0057] The execution order control unit 212 then determines where in the execution queue 340, which has already been sorted in order of priority, to insert this command 330. Specifically, for example, starting from the top command in the execution queue, the execution order control unit 212 compares the priority 252 of that command with the priority 252 added to the newly received command 330. If the priority 252 added to the newly received command 330 is higher than the priority 252 added to the command 330 in the execution queue that is the target of comparison, the newly received command 330 is inserted immediately before that command 330 that is the target of comparison.

[0058] 4(b), the execution order control unit 212 compares the commands 330 in the execution queue 340 in order from highest priority to lowest, and when comparing it with command 02, the priority 252 of the command 330 received for the first time is higher than the priority 252 of the command 330 being compared. Therefore, the newly received command is inserted immediately before command 02, and the execution queue 340 is updated.

[0059] In addition, if the priority 252 assigned to the newly received command 330 is the lowest among the NS230 priorities set for that SSD 200, the command 330 may be added to the end of the execution queue without performing the comparison process described above.

[0060] The method for determining the insertion position is not limited to this. It is also possible to compare the command from the end of the execution queue, or to use a bisection method or other existing sorting methods.

[0061] The execution unit 213 executes the commands according to the execution queue determined by the execution order control unit 212 .

[0062] The transmitting / receiving unit 214 controls the transmission and reception of data to and from the host device 300 .

[0063] As described above, the NS management unit 215 manages the NS 230. In this embodiment, the NS management unit 215 stores the NS table 250.

[0064] The non-volatile memory 220 includes, for example, a plurality of NAND flash memories. In accordance with an instruction from the controller 210, the non-volatile memory 220 is logically divided to generate one or more logical areas. Each logical area is called an NS 230, as in the first embodiment. Here, NS 231, NS 232, and NS 233 are shown as examples. The number of NSs and the number of NAND flash memories in each NS are not limited to this.

[0065] The buffer memory 240 is configured, for example, with a DRAM (Dynamic Random Access Memory) etc. In this embodiment, it is used as a work area for the controller 210.

[0066] [NS creation process] Next, the flow of the NS creation process by the controller 210 in this embodiment will be described. Fig. 5 shows the process flow of the NS creation process in this embodiment. This process is executed when the NS creation unit 211 receives a create command 310 from the host device 300 via the transmission / reception unit 214.

[0067] The NS creating unit 211 deletes the existing NS 230 in the non-volatile memory 220 (step S1101). Note that if an NS has not been created in the non-volatile memory 220, this process does not need to be performed.

[0068] The NS generating unit 211 generates the number of NSs 230 designated by the host device 300, each of which has a designated size (step S1102).

[0069] Then, the NS creation unit 211 registers information about each NS 230 in the NS table 250 (step S1103), and ends the process. Here, as described above, the NSID 251, the priority 252, the size 253, the function 254, and the physical area 255 are registered.

[0070] [Command Processing] Next, a command processing flow when a command 330 is received from the host device 300 after the NS is generated will be described. Fig. 6 shows the command processing flow of this embodiment. This processing is executed by the execution order control unit 212 and the execution unit 213 every time a command 330 with a priority (with NSID 332) is received from the host device 300 via the transmission / reception unit 214.

[0071] The execution order control unit 212 interprets the received command 330 and extracts the specified NSID 332 (step S1201).

[0072] The execution order control unit 212 refers to the NS table 250 and identifies the priority order 252 registered in association with the NSID 251 that matches the extracted NSID 332 (step S1202). The priority order 252 identified here is represented as PR0.

[0073] Here, the execution order control unit 212 determines whether the identified priority 252 (PR0) is the lowest among the priorities set in the NS 230 (step S1203). If it is the lowest (S1203: Yes), the execution order control unit 212 updates the execution queue 340 by queuing the received command at the end of the execution queue 340 (step S1211).

[0074] Otherwise (S1203: No), the execution order control unit 212 compares the identified priority order 252 with each command in the execution queue 340, starting from the top command, to determine the insertion position and update the execution queue 340. This method is described in detail below. Here, it is assumed that N commands are queued. Also, the nth command from the top of the execution order in the execution queue 340 is called the nth command.

[0075] The execution order control unit 212 initializes a counter n (n=1) (step S1204). If n is greater than N (S1205: Yes), the process proceeds to step S1211.

[0076] Otherwise (S1205: No), the execution order control unit 212 compares the priority (PRn) of the n-th command from the top with the identified priority (PR0). Here, it is determined whether PR0 is higher (greater) than PRn (step S1206).

[0077] If PR0 is higher than PRn (S1206: Yes), the execution order control unit 212 inserts the received command 330 immediately before the n-th command and updates the execution queue (step S1210).

[0078] On the other hand, if PR0 is equal to or less than PRn (S1206: No), n is incremented by 1 (step S1207), and the process returns to step S1205 to repeat the process. That is, the process continues to compare n with the priority of the next command in the execution order until n exceeds N.

[0079] Once execution queue 340 has been updated, execution unit 213 executes commands from the top of execution queue 340 (step S1220), and ends the process.

[0080] As an example of the above embodiment, the execution order when a write command and a read command are issued from the host device 300 will be described below.

[0081] For example, the issuance order and actual execution order when three write commands are issued will be described. Fig. 7(a) is a diagram for explaining the execution order. Here, it is assumed that three write commands IO1, IO2, and IO3 are issued in this order, and NSID:01, NSID:02, and NSID:03 are specified as the NS230 to be executed, respectively.

[0082] In this case, the NS priorities specified in the respective write commands are 1, 2, and 3, respectively, according to the NS table 250 in FIG. 4(a), and therefore the execution order is IO3, IO2, and IO1.

[0083] Similarly, Figure 7(b) shows the execution order when three read commands IO1, IO2, and IO3 are issued in this order. As shown in this figure, the NSs specified in each read command IO1, IO2, and IO3 are NSID:01, NSID:02, and NSID:03, respectively, as above. In this case, the execution order is IO3, IO2, and IO1.

[0084] As described above, according to the information processing system 100 of this embodiment, an execution priority is set for each NS 230 in the memory system 200. Therefore, on the host device 300 side, even if multiple commands conflict, each command is processed in the desired priority by simply specifying the NS 230 to be executed in the command 330. Therefore, the same effect as the first embodiment can be obtained.

[0085] Furthermore, in this embodiment, the priority of each NS 230 is specified by the host device 300 when the NS 230 is created. Since each NS 230 can be set for different purposes, it can be configured so that commands are processed according to the user's desired priority for each purpose.

[0086] Therefore, according to this embodiment, a memory system 200 that is highly efficient, fast, and responsive can be realized.

[0087] [Hardware configuration] The configuration of the controller 210 in each of the above embodiments is shown in Fig. 1(b). As shown in this figure, the controller 210 may include a CPU (Central Processing Unit) 291, a DRAM interface (I / F) 292, a memory I / F 293, and a host I / F 294, which are connected to each other via a bus.

[0088] The CPU 291 is a processor that realizes each of the above-mentioned functions of the controller 210. The CPU 291 realizes each of the above-mentioned functions, for example, by loading a program such as firmware stored in the non-volatile memory 220 or the like onto a RAM such as a DRAM and executing the program.

[0089] The DRAM I / F 292, the memory I / F 293, and the host I / F 294 control data transmission and reception with the RAM such as DRAM, the non-volatile memory 220, and the host device 300, respectively.

[0090] Each function realized by the CPU 291, the DRAM I / F 292, the memory I / F 293, and the host I / F 294 may be realized by dedicated hardware, such as an integrated circuit (IC) dedicated to each process, an application specific integrated circuit (ASIC), a system on chip (SOC), a field programmable gate array (FPGA), or the like.

[0091] <Variation 1> In the above embodiment, the memory system 200 is an SSD. However, the memory system 200 is not limited to an SSD. It may be any storage device equipped with a nonvolatile memory accessible by the Nonvolatile Memory Express (NVMe) protocol. For example, it may be a flash device.

[0092] In addition, a NAND memory has been described as an example of the nonvolatile memory 220 included in the memory system 200. However, the nonvolatile memory 220 is not limited to this. For example, the nonvolatile memory 220 may be various other nonvolatile memories such as a Magnetoresistive Random Access Memory (MRAM), a Phase change Random Access Memory (PRAM), a Resistive Random Access Memory (ReRAM), or a Ferroelectric Random Access Memory (FeRAM).

[0093] <Variation 2> Furthermore, an NVMe device can have multiple controllers, and an NS 230 is assigned to each controller. In the above embodiments, the memory system 200 has one controller 210, but the memory system 200 may have multiple controllers 210. In each controller 210, the priority of commands to the assigned NS 230 may be controlled by the method of the above embodiments.

[0094] <Modification 3> In each of the above embodiments, the command 330 at execution time includes the NSID 332. However, this is not limited to this. For example, if a function is defined for each NS 230, the function may be specified.

[0095] Also, the host device 300 may have a table that associates functions with NS230 (NSID). In this case, the user specifies a function when issuing a command. Then, the host device 300 may refer to the table to identify the NSID that corresponds to the specified function and include it in the command to be issued.

[0096] Alternatively, a function may be predefined for each command. Then, host device 300 may be configured to identify a function for each command, identify the corresponding NSID by referring to a table, and issue command 330.

[0097] <Variation 4> Also, a priority may be specified in the command 330 instead of the NSID 332. In this case, the execution order control unit 212 extracts the priority specified from the command 330, and determines the insertion position of the command 330 in the execution queue 340 according to the priority. Also, the execution order control unit 212 or the execution unit 213 refers to the NS table 250, identifies the NSID 251 corresponding to the matching priority 252, and determines the NS 230 to be processed.

[0098] <Variation 5> Furthermore, in each of the above embodiments, a different priority level 252 is set for each NS 230. However, this is not limiting. For example, the same priority level 252 may be set for multiple NSs 230.

[0099] <Variation 6> Furthermore, in each of the above embodiments, when correspondence information between logical areas and physical areas is stored in advance, information for identifying the logical area may be stored in the NS table 250 instead of the physical area 255 .

[0100] <Variation 7> In addition, in each of the above embodiments, the host device 300 and the memory system (SSD) 200 are independent devices, but this is not limited to the above. The memory system 200 may be built into the host device 300 as a storage device of the host device 300.

[0101] In the flowcharts used in the above description, multiple steps (processes) are described in order, but the order in which each step is performed is not limited to the order described. For example, the order of the steps shown in the drawings can be changed to a degree that does not affect the content, such as performing each process in parallel.

[0102] In addition, the programs stored in the non-volatile memory 220 and implementing the functions of the controller 210 can be provided as program products recorded on a non-transitory computer-readable storage medium. These can be used to store various programs recorded on the non-transitory computer-readable storage medium for the medium to long term.

[0103] Although the embodiments and modifications of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications that can be understood by those skilled in the art can be made. Each embodiment and modification can be appropriately combined with other embodiments. For example, the network configuration and the configuration of each element shown in each drawing are examples to help understand the present disclosure, and are not limited to the configurations shown in these drawings.

[0104] Finally, preferred embodiments of the present disclosure will be summarized. A part or all of the above-described embodiments can be described as follows, but are not limited to the following. (Appendix 1) a non-volatile memory having a plurality of logic regions; a controller for controlling access to each logical area of ​​the non-volatile memory; The controller includes an execution order control unit that determines an execution order of received commands according to a priority order predetermined for the logical area specified by the command. (Appendix 2) In the memory system of claim 1, an execution unit that executes the commands according to an execution queue in which the commands are queued in order of execution, It is preferable that the execution order control unit rearranges the execution queue in descending order of priority of the logical areas specified by each command every time a new command is received. (Appendix 3) In the memory system according to claim 1 or 2, It is preferable that the controller further comprises a priority order setting unit that sets the priorities when dividing the non-volatile memory into the plurality of logical areas. (Appendix 4) In the memory system according to any one of claims 1 to 3, It is desirable that the logic area be set for each purpose. (Appendix 5) 1. An access control method for controlling access to each logic area in a non-volatile memory having a plurality of logic areas, comprising: An access control method, comprising: determining an execution order of received commands according to a priority order predetermined for the logic area specified by the command. (Appendix 6) A controller for a non-volatile memory having a plurality of logic regions, A program for executing the access control method according to claim 5. In addition, the forms of Supplements 5 and 6 can be expanded into the forms of Supplements 2-4, just like Supplement 1.

[0105] The disclosures of the above patent documents and the like are incorporated herein by reference. Within the framework of the entire disclosure (including the scope of claims), modifications and adjustments of the embodiments or modifications are possible based on the basic technical ideas. Furthermore, within the framework of the disclosure, various combinations or selections of the various disclosed elements (including each element of each claim, each element of each embodiment or modification, each element of each drawing, etc.) are possible. In other words, the present disclosure naturally includes various modifications and corrections that a person skilled in the art would be able to make in accordance with the entire disclosure, including the scope of claims, and the technical ideas. In particular, with regard to the numerical ranges described in this specification, any numerical value or subrange included in the range should be interpreted as being specifically described even if not otherwise specified. [Explanation of symbols]

[0106] 100: Information processing systems, 200: memory system, 210: controller, 211: NS creation unit, 212: execution order control unit, 213: execution unit, 214: transmission / reception unit, 215: NS management unit, 220: non-volatile memory, 230: NS (name space), 231: NS, 232: NS, 233: NS, 240: buffer memory (DRAM), 250: NS table, 251: NSID, 252: priority, 253: size, 254: function, 255: physical area, 291: CPU, 292: DRAM I / F, 293: memory I / F, 294: host I / F, 300: host device, 310: create command, 311: NSID, 312: priority, 313: size, 314: function, 320: NS management command, 321: function field, 330: command, 331: command ID, 332: NSID, 333: command processing content, 340: execution queue

Claims

1. a non-volatile memory having a plurality of logic regions; a controller for controlling access to each logical area of ​​the non-volatile memory; The controller includes an execution order control unit that determines an execution order of received commands according to a priority order predetermined for the logical area specified by the command.

2. 2. The memory system of claim 1, an execution unit that executes the commands according to an execution queue in which the commands are queued in order of execution, The execution order control unit rearranges the execution queue in descending order of priority of the logical areas specified by each command, each time a new command is received.

3. 2. The memory system of claim 1, The memory system further comprises a priority setting unit configured to set the priorities when the non-volatile memory is divided into the plurality of logical areas.

4. 2. The memory system of claim 1, A memory system, wherein the logical area is set for each purpose.

5. 1. An access control method for controlling access to each logic area in a non-volatile memory having a plurality of logic areas, comprising: An access control method, comprising: determining an execution order of received commands according to a priority order predetermined for the logic area specified by the command.

6. A controller for a non-volatile memory having a plurality of logic regions, A program for causing execution of the access control method according to claim 5.

Images