Information processing program, information processing method, and information processing device

Abstract

To suppress performance degradation of an application using a hierarchical memory.SOLUTION: A computer comprises a first memory and a processor connected to the first memory. The computer stores address conversion information created for each application, in a cache memory which stores a part of data which each application accesses, so that a plurality of applications access the first memory, and a second memory including a storage region shared among the plurality of computers. The computer monitors a hit ratio of the data in the cache memory, and a continuous page number of the accessed data, for each application. The computer performs first processing in which data size of the address conversion information corresponding to the application is decreased for the application with a lower hit ratio. The computer performs second processing in which the data size of the address conversion information corresponding to the application is increased for the application with a fewer continuous page number.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to an information processing program, an information processing method, and an information processing device. [Background technology]

[0002] There is known a system that includes a plurality of computers that are connected to each other so as to be able to communicate with each other, and a shared memory that includes a storage area shared among the plurality of computers. In this system, an application executed on each computer may utilize a hierarchical memory (which may be called a heterogeneous memory) that combines a local memory of each computer with the shared memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 6-124237 [Patent Document 2] JP 2009-163450 A [Patent Document 3] US Patent Application Publication No. 2004 / 0221090 Summary of the Invention [Problem to be solved by the invention]

[0004] Shared memory may be managed at the user level, for example, at the application level, rather than at the OS (Operating System) level of the computer, in which case an OS-independent management method is used to control the hierarchical memory hierarchy.

[0005] For example, a method is conceivable in which a management table for converting virtual addresses used by an application into addresses of local memory and shared memory is stored in the local memory, and the application accesses the hierarchical memory by referring to the management table. In this method, the management table is referred to each time the application accesses the hierarchical memory, so that the latency of accessing the local memory is added to the access to the hierarchical memory by the application.

[0006] The latency of accessing local memory is, for example, about 50 to 100 ns (nanoseconds). On the other hand, the latency of accessing shared memory is, for example, the latency (100 to 200 ns) + α of accessing remote memory in a NUMA (Non-Uniform Memory Access) type system. For this reason, the penalty of accessing conversion information stored in local memory cannot be ignored compared to the latency of accessing hierarchical memory, and this may cause a decrease in application performance.

[0007] In one aspect, an object of the present invention is to suppress performance degradation of an application that uses a hierarchical memory. [Means for solving the problem]

[0008] In one aspect, an information processing program may cause a computer including a first memory and a processor connected to the first memory to execute the following process. The process may store address translation information for a plurality of applications to access the first memory and a second memory including a storage area shared among the plurality of computers, the address translation information being generated for each of the applications, in a cache memory that stores a portion of data accessed by the plurality of applications. The process may also monitor a hit rate of data in the cache memory and a number of consecutive pages of data accessed for each of the applications. The process may further perform a first process of decreasing a data size of address translation information corresponding to an application having a lower hit rate among the plurality of applications. The process may also perform a second process of increasing a data size of address translation information corresponding to an application having a lower number of consecutive pages among the plurality of applications. Effect of the Invention

[0009] According to one aspect, the present invention can suppress performance degradation of an application that uses a hierarchical memory. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an example of the configuration of a system according to an embodiment; [Diagram 2] FIG. 2 is a block diagram showing an example of a hardware configuration of a node according to an embodiment. [Diagram 3] FIG. 1 is a diagram showing a comparative example for explaining a system according to an embodiment. [Figure 4] FIG. 13 illustrates an example of an address management table. [Diagram 5] FIG. 13 illustrates an example of memory allocation processing; [Figure 6] FIG. 2 is a block diagram showing an example of a software configuration of a node according to an embodiment. [Figure 7] 11 is a diagram for explaining an example of processing by a memory management library; FIG. [Figure 8] FIG. 13 illustrates an example of an application monitoring table. [Figure 9] 11 is a diagram illustrating an example of a process performed by a table size changing unit; FIG. [Figure 10] 11 is a flowchart illustrating an example of an operation of a process at the start of an application of a system according to an embodiment. [Figure 11] 11 is a flowchart illustrating an example of an operation of a process during operation of an application of a system according to an embodiment. [Figure 12] 11 is a flowchart illustrating an example of an operation of a process when an application of a system according to an embodiment is terminated. [Figure 13] 11 is a flowchart illustrating an example of the operation of a table size change process by a table size change unit according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications or application of techniques not specified below. For example, this embodiment can be modified in various ways without departing from the spirit of the invention. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[0012] [A] Example of system configuration according to one embodiment 1 is a block diagram showing an example of the configuration of a system 1 according to an embodiment. The system 1 illustratively includes a plurality of nodes 2, one or more switches 3 (one in the example of FIG. 1), and one or more shared memories 4 (one in the example of FIG. 1).

[0013] The node 2 is an example of a computer or an information processing device. The node 2 may include various devices including, for example, a plurality of (two in the example of FIG. 1) processor boards 20. The processor board 20 may include one or more (one in the example of FIG. 1) processors 2a and one or more (one in the example of FIG. 1) memories 2b.

[0014] The processor 2a is an example of a processing unit that performs various controls and calculations. The processor 2a is connected to the memory 2b.

[0015] The memory 2b is an example of a first memory or main memory (primary storage device) that stores various data, programs, and other information. The memory 2b on the node 2 or the processor board 20 may be positioned as a "local memory" for the processor 2a mounted on the node 2 or the processor board 20. In contrast, in a mode in which the processor 2a can access the memory 2b on another node 2 or another processor board 20 different from the one on which the processor 2a is mounted, the memory 2b on the other node 2 or other processor board 20 may be positioned as a "remote memory."

[0016] A plurality of nodes 2 may be connected to each other by a high-speed interconnect 1a so that they can communicate with each other. The interconnect 1a may include, for example, a switch conforming to the communication standard of the transmission line in addition to a high-speed transmission line. The transmission line may include, for example, a transmission line conforming to a communication standard such as InfiniBand, Myrinet, Ethernet (registered trademark), or optical communication (e.g., FC (Fibre Channel)).

[0017] Each of the multiple nodes 2 and the switch 3 may be connected to each other via a high-speed interconnect 1b so that they can communicate with each other. The interconnect 1b may include a transmission path that complies with a communication standard such as CXL (Compute Express Link) or PCIe (Peripheral Component Interconnect Express). CXL is a communication standard based on PCIe.

[0018] The switch 3 relays communication (access) from each of the multiple nodes 2 to the shared memory 4. For example, if the system 1 includes multiple shared memories 4, the switch 3 may transmit a packet to the shared memory 4 that is the access destination from the node 2. The switch 3 is a switch that complies with the communication standard of the transmission path, and may be a CXL switch, for example, if the shared memory 4 is a CXL shared memory.

[0019] The shared memory 4 is an example of a second memory that stores information such as various data and programs used by multiple nodes 2. The shared memory 4 may be, for example, a shared memory that may be managed at an application level, rather than at an OS level (not managed by the OS). A non-limiting example of the shared memory 4 is a CXL shared memory that complies with CXL (e.g., CXL 3.0) or later standards.

[0020] [B] Example of node hardware configuration Fig. 2 is a block diagram showing an example of a hardware configuration of a node 2 according to an embodiment. As shown in Fig. 2, the node 2 may include, as a HW configuration, a processor 2a, a memory 2b, a graphics processing device 2c, a storage device 2d, a communication IF (Interface) 2e, an IO device 2f, a reading device 2g, and a device IF 2h, as shown in Fig. 1. These devices 2a to 2h may be connected to each other via various buses 2k so as to be able to communicate with each other.

[0021] Examples of the processor 2a include integrated circuits (ICs) such as a CPU, MPU, APU, DSP, ASIC, and FPGA. A CPU is an example of a Central Processing Unit, and MPU is an abbreviation for Micro Processing Unit. APU is an abbreviation for Accelerated Processing Unit. DSP is an abbreviation for Digital Signal Processor. ASIC is an abbreviation for Application Specific Integrated Circuit, and FPGA is an abbreviation for Field Programmable Gate Array.

[0022] The processor 2a may be a combination of two or more of these integrated circuits. The processor 2a may be a multiprocessor including a plurality of processors, a multicore processor having a plurality of processor cores, or a configuration having a plurality of multicore processors.

[0023] The memory 2b may be, for example, a volatile memory such as a dynamic random access memory (DRAM) or a non-volatile memory such as a persistent memory (PM). The memory 2b may be, for example, a memory module equipped with a DRAM chip or a non-volatile memory module such as a PM.

[0024] The graphics processing device 2c controls screen display for an output device such as a monitor of the IO device 2f. The graphics processing device 2c may also have a configuration as an accelerator that executes machine learning processing and inference processing using a machine learning model. Examples of the graphics processing device 2c include various arithmetic processing devices, such as integrated circuits (ICs) such as GPUs (Graphics Processing Units), APUs, DSPs, ASICs, and FPGAs.

[0025] The storage device 2d is an example of hardware that stores various data, programs, and other information. Examples of the storage device 2d include various storage devices such as a magnetic disk device such as a hard disk drive (HDD), a semiconductor drive device such as an SSD, and a non-volatile memory. Examples of the non-volatile memory include a flash memory, a storage class memory (SCM), and a read only memory (ROM).

[0026] The storage device 2d may store a program 2i (information processing program, memory management library 12 (see FIG. 6)) that realizes all or part of the various functions of the node 2.

[0027] For example, the processor 2a of the node 2 can implement the function of the node 2 (for example, the control unit 15 shown in FIG. 6) described later by loading a program 2i stored in the storage device 2d into the memory 2b and executing it.

[0028] The communication IF2e controls connections and communications between the nodes 2, between the node 2 and a host device (not shown) that issues various instructions to the node 2, etc. For example, the communication IF2e may include an adapter that complies with the communication standard of the interconnect 1a shown in Fig. 1. The communication IF2e may be connected to other nodes 2 via the interconnect 1a.

[0029] The program 2i may be downloaded to the node 2 from a network (not shown) via the communication IF 2e and stored in the storage device 2d.

[0030] The IO device 2f may include one or both of an input device and an output device. Examples of the input device include a keyboard, a mouse, a touch panel, and the like. Examples of the output device include a display device such as a monitor, a projector, and a printer, and the like. The IO device 2f may also include a touch panel in which the input device and the output device are integrated. The output device may be connected to the graphics processing device 2c.

[0031] The reading device 2g is an example of a reader that reads out data or program information recorded on the recording medium 2j. The reading device 2g may include a connection terminal or device to which the recording medium 2j can be connected or inserted. Examples of the reading device 2g include an adapter that complies with USB (Universal Serial Bus) or the like, a drive device that accesses a recording disk, and a card reader that accesses a flash memory such as an SD card. The recording medium 2j may store the program 2i, and the reading device 2g may read the program 2i from the recording medium 2j and store it in the storage device 2d.

[0032] Examples of the recording medium 2j include non-transitory computer-readable recording media such as magnetic / optical disks and flash memories. Examples of the magnetic / optical disks include flexible disks, CDs (Compact Discs), DVDs (Digital Versatile Discs), Blu-ray Discs, and HVDs (Holographic Versatile Discs). Examples of the flash memory include semiconductor memories such as USB memories and SD cards.

[0033] The device IF2h controls connections and communications between the node 2 and the switch 3, between the nodes 2, etc. For example, the device IF2h may include an adapter that complies with the communication standard of the interconnect 1b shown in Fig. 1. The device IF2h may be connected to the switch 3 (and one or more shared memories 4) via the interconnect 1b.

[0034] The above-mentioned hardware configuration of the node 2 is an example. Therefore, the hardware in the node 2 may be increased or decreased (for example, adding or deleting any block), divided, integrated in any combination, or added or deleted buses, etc. may be appropriately performed. For example, the node 2 may omit the IO device 2f and the reader 2g, etc.

[0035] [C] Description of a system according to one embodiment Fig. 3 is a diagram showing a comparative example for explaining the system 1 according to an embodiment. Fig. 3 shows an example focusing on one pair of a processor 2a and a memory 2b (local memory) in a certain node 2.

[0036] As shown in FIG. 3, the system 1 employs a management method that is independent of the OS executed by the processor 2a in order to perform hierarchical control of a hierarchical memory (heterogeneous memory) that combines the memory 2b and the shared memory 4.

[0037] For example, the memory 2b stores, for each application 11, an address management table 22 for converting a virtual address used by the application 11 executed by the processor 2a into an address in the memory 2b and the shared memory 4. Hereinafter, "application" may be simply referred to as "app."

[0038] The application 11 refers to the address management table 22 every time an access occurs to the memory 2b and the shared memory 4, but as described above, the access penalty for the address management table 22 stored in the memory 2b is large.

[0039] For example, in order to reduce the above-mentioned access penalty to a level that can be ignored relative to the latency of access to the hierarchical memory, it is possible to store the address management table 22 in a memory faster than the memory 2b. An example of a memory faster than the memory 2b is the cache 21 provided in the processor 2a.

[0040] The cache 21 is an example of a cache memory having a storage area for storing part of data (cache data) used in execution of the application 11 as application data 23. The cache 21 may be, for example, a cache memory different from a TLB (Translation Lookaside Buffer).

[0041] Examples of cache 21 include volatile memories such as SRAM (Static Random Access Memory) that have a faster access speed than memory 2b and shared memory 4, and one example is a CPU's Ln (n is an integer greater than or equal to 1, for example, 1≦n≦3) cache.

[0042] In this way, by storing the address management table 22 in the cache 21, it can be expected that the address management table 22 stored in the cache 21 will be referenced when the application 11 runs. Note that the address management table 22 may be managed by user-level software, such as a library located in a layer between the OS and the application 11.

[0043] 4 is a diagram showing an example of the address management table 22. The address management table 22 may include items of a pointer, a virtual address, and an offset, for example. Hereinafter, the address management table 22 is expressed in a table format, but is not limited to this, and the address management table 22 may be data in various formats including an array.

[0044] The pointer is information for determining whether to use memory 2b or shared memory 4 for each application 11. The virtual address is an address in the virtual address space used by the application 11. The offset (K (kilo) bytes) is information indicating a position in the storage area of ​​memory 2b or shared memory 4, and may indicate, for example, a relative position from the start of the address (e.g., physical address, etc.) of memory 2b or shared memory 4. In the example of FIG. 4, "P_local" indicates the start of the address of memory 2b, and "P_remote" indicates the start of the address of shared memory 4.

[0045] As shown in FIG. 4, the address management table 22 holds a virtual address and an offset in the memory 2b or the shared memory 4 for each pointer.

[0046] For example, the library may divide the virtual address space (memory area) secured for the application 11 equally at a predetermined address management granularity, and set an offset of the memory 2b or the shared memory 4 for each area of ​​the equally divided virtual address space. In the example of Fig. 4, the address management granularity is 64K bytes. Hereinafter, the address management granularity may be simply referred to as "management granularity".

[0047] For example, the address management granularity and the table size may be inversely proportional. As an example, doubling the address management granularity halves the table size, and vice versa.

[0048] Fig. 5 is a diagram showing an example of memory allocation processing. As shown in Fig. 5, the library allocates a storage area of ​​a capacity (size) specified by the application 11 from each of the memory 2b (denoted as "local") and the shared memory 4 (denoted as "remote").

[0049] As shown in FIG. 3, the address management table 22 is generated and managed for each application 11.

[0050] For this reason, as the table size (data size) of the address management table 22 increases, the possibility that an entry of cache data used by the application 11 will be evicted from the cache 21 increases. In other words, as the table size of the address management table 22 increases, the size of the memory area capable of storing the application data 23 may decrease.

[0051] Furthermore, as the table size of the address management table 22 increases, the address management table 22 itself corresponding to at least one application 11 may be evicted from the cache 21.

[0052] In this way, by evicting the cache data in the application data 23 and the address management table 22 from the cache 21, the access penalty to these data increases, and there is a risk that the performance of the application 11 will decrease.

[0053] Also, from the example shown in FIG. 4, increasing the address management granularity of the address management table 22 leads to a reduction in the number of equally divided areas of the virtual address space (the number of entries in the address management table 22), in other words, a reduction in the table size.

[0054] However, if the address management granularity is increased in order to reduce the table size of the address management table 22, the memory 2b and the shared memory 4 will be used roughly, which may result in a decrease in the performance of the application 11.

[0055] In this way, there is a trade-off between increasing the table size of the address management table 22 to improve the performance of the application 11 and suppressing the eviction of application data 23 and the like from the cache 21 due to an increase in the table size.

[0056] In one embodiment, a method for setting an optimal table size of the address management table 22 in such a trade-off relationship will be described. This makes it possible to suppress a decrease in performance of the application 11 that uses a hierarchical memory.

[0057] [D] Software configuration example Fig. 6 is a block diagram showing an example of a software configuration of a node 2 according to an embodiment. As shown in Fig. 6, the node 2 may include a processing unit 10 as a software configuration. The processing unit 10 may be realized by a processor 2a (for example, the processor 2a shown in Fig. 3).

[0058] The processing unit 10 may include, for example, an application 11, a memory management library 12, an OS 13, and a heterogeneous memory unit 14. The application 11, the memory management library 12, and the OS 13 (at least the memory management library 12) are an example of a control unit 15.

[0059] The application 11 is software that runs on the OS 13. Note that a plurality of applications 11 may run on the OS 13.

[0060] The memory management library 12 is user-level software located in a layer between the OS 13 and the application 11, and in one embodiment, controls changes to the table size of the address management table 22.

[0061] The memory management library 12 may execute, for example, access monitoring of the application 11, pointer reference from the application 11 to the heterogeneous memory unit 14 (for example, memory access), memory allocation request to the OS 13, and the like.

[0062] The OS 13 executes the memory management library 12 and the application 11. The OS 13 may allocate memory from the heterogeneous memory unit 14 in response to receiving a memory allocation request from the memory management library 12, for example.

[0063] The heterogeneous memory unit 14 represents a storage area of ​​a hierarchical memory including the memory 2b and the shared memory 4.

[0064] As shown in FIG. 6, the memory management library 12 may include, for example, a cache hit rate monitor 121, a continuous access monitor 122, and a table size change unit 123.

[0065] Fig. 7 is a diagram for explaining an example of processing by the memory management library 12. As illustrated in Fig. 7, the memory management library 12 according to an embodiment stores an application monitoring table 24 in the cache 21 in addition to an address management table 22 and application data 23. Although not shown in Fig. 7, the memory 2b stores an address management table 22 for each application 11 executed by the processor 2a.

[0066] The memory management library 12 manages the application monitoring table 24, for example, through monitoring (see arrows (i) and (ii)) by a cache hit rate monitor 121 and a continuous access monitor 122. The memory management library 12 also changes the table size of the address management table 22 based on the application monitoring table 24 through a table size change process by a table size change unit 123 (see arrow (iii)).

[0067] The application monitoring table 24 is information used to monitor the state of each application 11 and to control changes to the table size of the address management table 22 for each application 11.

[0068] 8 is a diagram showing an example of the application monitoring table 24. The application monitoring table 24 may include, for example, items such as application, address management granularity, table size, Pr, Pi, cache hit rate, average number of consecutive pages, and size change.

[0069] The app is an example of identification information for identifying the application 11 (address management table 22). The address management granularity (K bytes) is the minimum unit (range, width) of allocation of the memory 2b or the shared memory 4 to a virtual address, which is set for each application 11. The table size (K bytes) is the data size of the address management table 22.

[0070] Pr is the priority for reducing the table size, and in the example of Fig. 8, there are three priority levels, high, middle, and low, in descending order of priority. Pi is the priority for increasing the table size, and in the example of Fig. 8, there are three priority levels, high, middle, and low, in descending order of priority.

[0071] The cache hit rate is information or a result of monitoring by the cache hit rate monitor 121. In the example of FIG. 8, the cache hit rate for each application 11 is calculated by H using the identification information (A to C) of the application 11. A ~H C It is expressed as follows.

[0072] The average number of consecutive pages is information during monitoring or a result of monitoring by the consecutive access monitor 122. In the example of FIG. 8, the average number of consecutive pages for each application 11 is calculated by N A ~N C It is expressed as follows.

[0073] The size change is information indicating whether the table size was changed immediately before and whether the change was an increase (enlargement) or decrease (reduction). Note that the immediately before may refer to the previous table size change process (described later) for the application 11.

[0074] The cache hit rate monitor 121 performs cache hit rate monitoring. For example, the cache hit rate monitor 121 monitors the hit rate of data in the cache 21 for each application 11 executed by the processing unit 10, and obtains the cache hit rate H for each application 11 during a predetermined time period as a monitoring result. The predetermined time period may be set in advance, for example.

[0075] The cache hit rate H may be calculated, for example, by dividing the number of cache hits in the cache 21 in a given period by the sum of the number of cache hits and the number of cache misses in the given period.

[0076] Then, the cache hit rate monitor 121 specifies a priority Pr based on the cache hit rate H, and sets the specified priority Pr as Pr in the application monitoring table 24 .

[0077] The priority Pr may be set according to a first policy (first condition) that the table size of the address management table 22 corresponding to an application 11 with a lower cache hit rate is made smaller, in other words, the management granularity is made larger.

[0078] The first policy is a policy that aims to improve the cache hit rate by increasing the capacity of the cache 21 used by the application 11, in other words, the storage area for application data 23, for an application 11 with a lower cache hit rate.

[0079] For example, the cache hit ratio monitor 121 may specify a priority Pr according to the calculated cache hit ratio H for each application 11 in accordance with the following conditions (1) to (3), which are an example of the first policy. Note that in the following conditions (1) to (3), the threshold value (H th1 ) and threshold (H th2 ) may be, for example, a preset threshold value, and the threshold value (H th1 )<threshold(H th2 ) is the threshold (H th1 ) is an example of a first threshold, and the threshold (H th2 ) is an example of a third threshold. H ≦ threshold(H th1 )in the case of Pr=high (1) Threshold (H th1 ) < H ≦ threshold(H th2 )in the case of Pr=middle (2) Threshold (H th2 ) < H Pr=low (3)

[0080] This allows the cache hit rate monitor 121 to detect, for example, an application 11 that meets the above condition (1) as an application 11 whose cache hit rate has decreased due to an increase in table size.

[0081] The cache hit ratio monitor 121 may store the cache hit ratio H used to specify the priority Pr or the monitored information (numerical values) used to calculate the cache hit ratio H in the cache hit ratio item of the application monitoring table 24. Alternatively, when the cache hit ratio monitor 121 stores this information in another storage area, the cache hit ratio item may be omitted in the application monitoring table 24.

[0082] The continuous access monitor 122 performs continuous access monitoring. For example, the continuous access monitor 122 monitors the number of continuous pages of data accessed for each application 11 executed by the processing unit 10, and obtains the average number N of continuous pages of data accessed within a predetermined time for each application 11 as a monitoring result.

[0083] The average number of consecutive pages N may be calculated, for example, by averaging the number of consecutive pages in which each piece of data accessed within a given time is stored in the heterogeneous memory unit 14 (or the cache 21).

[0084] Then, the consecutive access monitor 122 specifies a priority level Pi based on the average consecutive page count N, and sets the specified priority level Pi as Pi in the application monitoring table 24 .

[0085] The priority Pi may be set according to a second policy (second condition) that the table size of the address management table 22 corresponding to an application 11 with a smaller average number of consecutive pages is made larger, in other words, the management granularity is made smaller.

[0086] An application 11 with a small average number of consecutive pages is said to be an application 11 that has a strong tendency to perform random access (a weak tendency to perform sequential access). For example, even if a large management granularity (e.g., 1 M (mega) byte, etc.) is set for such an application 11, if random access is performed in small units (e.g., 4 Kbytes, etc.), there is a large waste of allocation of the heterogeneous memory unit 14.

[0087] The second policy is a policy that aims to reduce the above-mentioned waste by reducing the management granularity of the address management table 22 for applications 11 with smaller average numbers of consecutive pages, while also increasing the table size and improving the cache hit rate.

[0088] For example, the continuous access monitor 122 may specify a priority Pi according to the calculated average number of continuous pages N for each application 11 in accordance with the following conditions (4) to (6), which are an example of the second policy. Note that in the following conditions (4) to (6), the threshold (N th1 ) and threshold (N th2 ) may be, for example, a preset threshold value, and the threshold value (N th1 )<threshold(N th2 ) is the threshold (N th1 ) is an example of a second threshold, and the threshold (N th2 ) is an example of a fourth threshold. N ≦ threshold(N th1 )in the case of Pi=high (4) Threshold (N th1 ) < N ≦ threshold(N th2 )in the case of Pi=middle (5) Threshold (N th2 ) < N Pi=low (6)

[0089] This allows the continuous access monitor 122 to classify applications 11 for which the address management granularity should be reduced from applications 11 for which the address management granularity may be increased by detecting the randomness of access through monitoring the average number of continuous pages.

[0090] The continuous access monitor 122 may store the average number of consecutive pages N used to specify the priority Pi or the monitored information (numerical values) used to calculate the average number of consecutive pages N in the average number of consecutive pages item of the application monitoring table 24. Alternatively, when the continuous access monitor 122 stores this information in another storage area, the average number of consecutive pages item may be omitted in the application monitoring table 24.

[0091] The table size change unit 123 performs a data size change process. For example, the table size change unit 123 refers to the application monitoring table 24 at predetermined intervals, and changes the address management granularity and table size of the address management table 22 based on two priorities Pr and Pi (see FIG. 7).

[0092] For example, the table size change unit 123 performs a first process of suppressing an increase in the table size by dynamically changing the table size of the address management table 22 so that the management granularity is larger for an application 11 with a lower cache hit rate.

[0093] As an example, the table size change unit 123 changes the application 11 having a high priority Pr in the application monitoring table 24, in other words, a cache hit rate lower than the threshold H th1 ) or less. Then, the table size change unit 123 reduces the data size by increasing (for example, doubling) the address management granularity of the first address management table 22 corresponding to the identified first application 11.

[0094] Furthermore, the table size change unit 123 performs a second process of dynamically changing the table size of the address management table 22 so that the management granularity becomes smaller for an application 11 with a smaller average number of consecutive pages (in other words, with more random accesses).

[0095] As an example, the table size change unit 123 identifies an application 11 with a high priority Pi among the applications 11 with a priority Pr other than high (middle or low) in the application monitoring table 24. In other words, the table size change unit 123 determines whether the cache hit rate is greater than or equal to a threshold (H th1 ) and the average number of consecutive pages is greater than the threshold (N th1 ) or less. Then, the table size change unit 123 increases the data size by decreasing (for example, by halving) the address management granularity of the second address management table 22 corresponding to the identified second application 11.

[0096] Fig. 9 is a diagram for explaining an example of the process of the table size change unit 123. Note that in Fig. 9, the items of the cache hit rate, the average number of consecutive pages, and size change in the application monitoring table 24 are omitted from the illustration.

[0097] 9, the table size change unit 123 changes the address management granularity based on Pr and Pi of the application monitoring table 24 updated by the cache hit rate monitor 121 and the continuous access monitor 122. In addition, since the table size changes with the change in address management granularity, the table size change unit 123 may also change the table size of the application monitoring table 24.

[0098] Then, the table size change unit 123 may update the table size of the address management table 22 based on the address management granularity and table size updated in the application monitoring table 24.

[0099] Note that, for an application 11 whose table size has been changed, the table size change unit 123 may set information indicating an increase or decrease in the size change (see FIG. 8) of the application monitoring table 24. Similarly, for an application 11 whose table size has not been changed, the table size change unit 123 may set information indicating no change ("-" in the example of FIG. 8) in the size change (see FIG. 8) of the application monitoring table 24.

[0100] As described above, according to the memory management library 12, the table size of the address management table 22 is dynamically changed based on the application monitoring table 24 updated by monitoring the application 11, as shown by symbol A in FIG.

[0101] For example, the first process can reduce the table size by increasing the management granularity in accordance with the cache hit rate of the application 11.

[0102] This makes it possible to reduce the space occupied by the address management table 22 in the storage area of ​​the cache 21, and it is expected that the reduced space will be added to the space for the application data 23 (see symbol B in FIG. 7). That is, it is expected that a part of the data (cache data) used by the application 11 will be stored in the reduced space. Furthermore, the reduction in the table size of the address management table 22 can reduce the frequency with which data is evicted from the cache 21. Therefore, it is possible to suppress a decrease in performance of the application 11 that uses a hierarchical memory.

[0103] Furthermore, the application 11 is identified based on the priority Pr (in other words, the threshold value) obtained by monitoring, and the data size of the corresponding address management table 22 is increased, enabling high-speed processing using simple logic.

[0104] Furthermore, by using the second process to reduce the management granularity in accordance with the randomness of memory access by the application 11, it is possible to optimize the allocation of hierarchical memory to virtual addresses, and thus it is possible to suppress a decrease in the performance of the application 11.

[0105] Furthermore, the application 11 is identified based on the priorities Pr and Pi (in other words, threshold values) obtained by monitoring, and the data size of the corresponding address management table 22 is reduced, enabling high-speed processing using simple logic.

[0106] [E] Example of operation Next, an example of the operation of the system 1 according to an embodiment will be described. Hereinafter, an example of detailed processing of each process at the start, operation, and end of the application 11, including the above-mentioned processing by the system 1 (e.g., the processing unit 10), and table size change processing will be described with reference to flowcharts.

[0107] [E-1] Examples of processing at the start, end, and termination of an application 10 to 12 are flowcharts illustrating examples of processing operations at the start, operation, and end of the application 11 of the system 1 according to an embodiment.

[0108] First, an example of the operation at the start of the application 11 will be described with reference to Fig. 10. As illustrated in Fig. 10, when the application 11 is started, the application 11 specifies the storage capacity of the memory 2b (local memory) and the storage capacity of the shared memory 4 (step S1).

[0109] The memory management library 12 determines the address management granularity from the storage capacity of the specified memory 2b (step S2). For example, the memory management library 12 can efficiently manage data stored in the small storage capacity of the memory 2b by setting a smaller address management granularity as the storage capacity of the specified memory 2b becomes smaller.

[0110] The memory management library 12 creates the address management table 22 corresponding to the started application 11 according to the address management granularity determined in step S2 (step S3). The address management table 22 may be stored in both the cache 21 and the memory 2b.

[0111] The memory management library 12 adds the information of the created address management table 22 to a new entry in the application monitoring table 24 (step S4), and the process ends.

[0112] Next, an example of operation during operation of the application 11 will be described with reference to Fig. 11. As illustrated in Fig. 11, the cache hit rate monitor 121 of the memory management library 12 performs cache hit rate monitoring for each entry (application 11) registered in the application monitoring table 24 (step S11). The cache hit rate monitor 121 sets the priority Pr identified by the cache hit rate monitoring in the application monitoring table 24.

[0113] The continuous access monitor 122 of the memory management library 12 performs continuous access monitoring for each entry (application 11) registered in the application monitoring table 24 (step S12). The continuous access monitor 122 sets the priority Pi determined by the continuous access monitoring in the application monitoring table 24.

[0114] The table size change unit 123 executes a table size change process based on the application monitoring table 24 updated in steps S11 and S12 (step S13).

[0115] The memory management library 12 determines whether or not the processes of steps S11 to S13 have been executed for all applications 11 registered in the application monitoring table 24 (step S14). If there is an unprocessed application 11 (NO in step S14), the process proceeds to step S11.

[0116] When the processes of steps S11 to S13 have been executed for all applications 11 (YES in step S14), the memory management library 12 waits for a predetermined time (step S15), and the process proceeds to step S11.

[0117] Next, an example of operation when the application 11 is terminated will be described with reference to Fig. 12. As illustrated in Fig. 12, when the application 11 is terminated, the memory management library 12 releases the memory designated (used) by the application 11 (step S21), and deletes the address management table 22 corresponding to the application 11 (step S22). Note that the address management table 22 may be deleted from both the cache 21 and the memory 2b.

[0118] The memory management library 12 acquires the table size of the deleted address management table 22 from, for example, the application monitoring table 24 (step S23).

[0119] The memory management library 12 deletes the entry of the terminated application 11 from the application monitoring table 24 (step S24).

[0120] Here, step S22 creates space in the cache 21 that allows the table sizes of other address management tables 22 to be increased by the table size of the deleted address management table 22. It may be expected that the space will be used as a storage area for application data 23, but by allocating the space to other address management tables 22 (increasing the table sizes), it is also possible to improve the performance of the application 11. The following steps S25 to S29 are an example of a process for allocating the space to other address management tables 22.

[0121] The table size change unit 123 refers to the entry of the application 11 having the smallest table size in the application monitoring table 24 (step S25).

[0122] The table size change unit 123 judges whether or not the priority Pr of the referenced application 11 is high (step S26). If the priority Pr is high (YES in step S26), the process proceeds to step S29.

[0123] If the priority Pr is not high (is low or middle) (NO in step S26), the table size change unit 123 determines whether the priority Pi of the referenced application 11 is low (step S27). If the priority Pi is low (YES in step S27), the process proceeds to step S29.

[0124] If the priority Pi is not low (is middle or high) (NO in step S27), the table size change unit 123 executes a table size change process for the address management table 22 of the referenced application 11 (step S28).

[0125] The table size change unit 123 determines whether the table size increased by the table size change process is less than the free table size (the table size of the deleted address management table 22) (step S29).

[0126] If the increased table size is less than the free table size (YES in step S29), the process proceeds to step S25. On the other hand, if the increased table size is equal to or greater than the free table size (NO in step S29), the process ends.

[0127] In this way, in steps S25 to S29, applications 11 for which the management granularity may be reduced are selected in ascending order of the table size of the address management table 22. Such applications 11 are, for example, applications 11 with a high cache hit rate and a strong tendency for random access, such as applications 11 with a priority Pr of low or middle and a priority Pi of middle or high. The table size change unit 123 repeats the process until the increased table size is equal to or greater than (for example, the same as) the free (deleted) table size. Details of the process in step S28 will be described later.

[0128] [E-2] Example of table size change processing 13 is a flowchart illustrating an example of the operation of the table size change process by the table size change unit 123 according to an embodiment. For example, the table size change process may be executed in step S13 in FIG. 11 and step S28 in FIG.

[0129] 13, the table size change unit 123 refers to the application monitoring table 24 for an entry of the address management table 22 that is the target of the table size change process (step S31). The target address management table 22 is, for example, the address management table 22 in which the priorities Pr and Pi have been updated in step S13 of FIG. 11, and is the address management table 22 with the smallest table size in step S28 of FIG. 12.

[0130] The table size change unit 123 determines whether or not the table size of the address management table 22 was changed last time based on the size change value of the entry (step S32).

[0131] If the table size has not been changed (NO in step S32), the table size change unit 123 determines whether the priority Pr is high (step S33).

[0132] If the priority Pr is high in step S33 (YES in step S33), the table size change unit 123 performs a first process. That is, the table size change unit 123 changes the address management granularity and table size of the application monitoring table 24 to create an address management table 22 with double the address management granularity and half the table size (step S34). The table size change unit 123 may set a value indicating a decrease in the size change of the application monitoring table 24. After completion of step S34, the process ends.

[0133] After the first process is performed, the table size change unit 123 may determine whether or not the cache hit rate is improved for the application 11 for which the table size of the address management table 22 has been reduced. If the cache hit rate is not improved, the table size change unit 123 may further reduce the table size of the address management table 22 for the application 11. These processes are performed in steps S40 to S42.

[0134] If the priority Pr is not high (is low or middle) in step S33 (NO in step S33), the table size change unit 123 determines whether the priority Pi is high or not (step S35). If the priority Pi is not high (is low or middle) (NO in step S35), the current situation is maintained and the process ends.

[0135] If the priority Pi is high in step S35 (YES in step S35), the table size change unit 123 performs the second process.

[0136] Here, the table size is increased in the second process. If the performance of application 11 deteriorates due to the increase in the table size, there is a possibility that the performance of application 11 will be further deteriorated by decreasing the expanded table size.

[0137] Therefore, in the second process, before increasing the table size, the table size change unit 123 secures a temporary table (temporary address management table 22) having the same table size as the address management table 22 in the cache 21 (step S36). Note that the table size change unit 123 may set a value indicating an increase in the size change of the application monitoring table 24. After completion of step S36, the process ends.

[0138] The temporary table is an example of first data of the first data size. The temporary table is a dummy table for simulating a situation in which the table size of the address management table 22 is doubled. For example, the temporary table may be various data as long as the memory management library 12 can recognize that the temporary table is not a valid address management table 22. Note that the first data size of the temporary table may be the same as the table size of the address management table 22, for example, but may be different.

[0139] In step S32, if the table size is changed and increased (YES (increase) in step S32), this means that a temporary table was created in the previous table size change process. In this case, the table size change unit 123 determines whether the cache hit rate of the application 11 has decreased due to the creation of the temporary table, for example, whether the priority Pr is high (step S37).

[0140] If the priority Pr is high in step S37 (YES in step S37), this means that the priority Pr was low or middle in the previous table size change process (NO in step S33), and therefore the cache hit rate has decreased. In this case, since increasing the table size would decrease the performance of the application 11, the table size change unit 123 deletes the temporary table (step S39). Note that the table size change unit 123 sets a value indicating no change in the size change of the application monitoring table 24. After step S39 is completed, the process ends.

[0141] If the priority Pr is not high (is low or middle) in step S37 (NO in step S37), this means that the change in the cache hit rate is small. In this case, the table size change unit 123 changes the address management granularity and table size of the application monitoring table 24 to create an address management table 22 with half the address management granularity and double the table size (step S38). In other words, the table size change unit 123 may increase the address management table 22 by the first data size of the temporary table.

[0142] Furthermore, the table size change unit 123 deletes the temporary table (step S39), and the process ends. Step S39 may be executed before step S38. Note that since the table size was changed in the previous table size change process and has not been changed this time, the table size change unit 123 may set a value indicating no change in the size change of the application monitoring table 24. With the above, the second process (steps S36 to S39) ends.

[0143] In this way, the table size change unit 123 repeatedly executes the second process for an application 11 having a lower average number of consecutive pages. Therefore, the second process can increase the data size of the corresponding address management table 22 for an application 11 having a smaller average number of consecutive pages among the multiple applications 11.

[0144] In step S32, if the table size is changed and decreased (YES (decreased) in step S32), this means that step S34 or S42 was executed in the previous table size change process, in other words, the first process was executed. In this case, the table size change unit 123 determines whether the cache hit rate of the application 11 has decreased due to the decrease in the table size, for example, whether the priority Pr is high or not (step S40).

[0145] If the priority Pr is not high (is low or middle) in step S40 (NO in step S40), this means that the cache hit rate has increased due to the reduction in table size in the previous table size change process. In this case, the performance of application 11 has been improved, and the process ends.

[0146] If the priority Pr is high in step S40 (YES in step S40), this means that the cache hit rate has not improved due to the reduction in table size in the previous table size change process. The table size change unit 123 determines whether the current address management granularity is maximum or not (step S41). The maximum value of the address management granularity is the maximum management granularity that the system 1 can tolerate, and may be set to a predetermined value, for example.

[0147] In step S41, if the management granularity is not maximum (NO in step S41), the table size change unit 123 performs the first process again. That is, the table size change unit 123 changes the address management granularity and table size of the application monitoring table 24 to create the address management table 22 with double the address management granularity and half the table size (step S42). Note that the table size change unit 123 may set a value indicating a decrease in the size change of the application monitoring table 24. After completion of step S42, the process ends.

[0148] In this way, according to the table size change unit 123, the first process is executed more repeatedly for an application 11 having a lower cache hit rate. Therefore, the first process can reduce the data size of the corresponding address management table 22 for an application 11 having a lower cache hit rate among the multiple applications 11.

[0149] In step S41, if the management granularity is maximum (YES in step S41), it means that changing to the maximum allowable address management granularity did not improve the cache hit rate. In this case, it can be said that the application 11 is an application 11 that is not suitable for management by a hierarchical memory (heterogeneous memory). Such an application 11 may be excluded from the objects managed by the memory management library 12 so that it operates by referring to the address management table 22 stored in the memory 2b or the shared memory 4, for example.

[0150] In this case, the table size change unit 123 judges whether the priority Pi is high or not (step S43). If the priority Pi is high (YES in step S43), the application 11 has a strong tendency for random access, and therefore allocates data including the address management table 22 in the memory 2b (step S44).

[0151] If the priority Pi is not high (is low or middle) (NO in step S43), the application 11 has a strong tendency for sequential access, so data including the address management table 22 is allocated in the shared memory 4 (step S45).

[0152] After arranging the data in the memory 2b or the shared memory 4, the table size change unit 123 deletes the address management table 22 of the application 11 from the cache 21 (step S46), and the process ends. Note that the table size change unit 123 may delete the entry of the application 11 from the application monitoring table 24.

[0153] [F] Other The technology according to the above-described embodiment can be modified and changed as follows.

[0154] For example, the cache hit rate monitor 121, the continuous access monitor 122, and the table size change unit 123 included in the memory management library 12 of the processing unit 10 shown in FIG. 6 may be merged in any combination, or each may be divided.

[0155] In addition, the cache hit rate monitor 121 and the continuous access monitor 122 are each configured to specify three levels of priority Pr and Pi by monitoring the application 11, but the number of levels of priority Pr and Pi is not limited to this. The cache hit rate monitor 121 or the continuous access monitor 122 may specify two levels or four or more levels of priority Pr or Pi.

[0156] Furthermore, the change magnification of the address management granularity or table size by the table size change unit 123 is not limited to double or half (1 / 2), and may be various magnifications.

[0157] [G] Notes Regarding the above embodiment, the following supplementary notes are further disclosed.

[0158] (Appendix 1) A computer including a first memory and a processor connected to the first memory, storing address translation information for a plurality of applications to access the first memory and a second memory including a storage area shared among the plurality of computers, the address translation information being generated for each of the applications, in a cache memory that stores a portion of data accessed by the plurality of applications; monitoring, for each of the applications, a hit rate of data in the cache memory and a number of consecutive pages of data accessed; performing a first process of reducing a data size of address translation information corresponding to an application having a lower hit rate among the plurality of applications; performing a second process of increasing a data size of address translation information corresponding to an application having a smaller number of consecutive pages among the plurality of applications; An information processing program that executes processing.

[0159] (Appendix 2) the first process includes a process of reducing the data size by increasing a management granularity of first address translation information corresponding to a first application having a hit rate equal to or less than a first threshold value; 2. An information processing program according to claim 1.

[0160] (Appendix 3) the second process includes a process of increasing the data size by decreasing a management granularity of second address translation information corresponding to a second application in which the hit rate is greater than the first threshold value and the number of consecutive pages is equal to or less than a second threshold value; 2. An information processing program according to claim 1.

[0161] (Appendix 4) The second process includes: storing first data of a first data size in the cache memory; when the hit rate of the second application during a predetermined period after the first data is stored in the cache memory is greater than the first threshold, deleting the first data from the cache memory and increasing a data size of the second address translation information by the first data size. 4. An information processing program according to claim 3.

[0162] (Appendix 5) The second memory is a memory that is not managed by an operating system executed by the processor. An information processing program according to any one of claims 1 to 4.

[0163] (Appendix 6) The second memory is a shared memory conforming to CXL (Compute Express Link), The processor and the second memory are connected via a CXL switch. An information processing program according to any one of claims 1 to 5.

[0164] (Appendix 7) a computer including a first memory and a processor coupled to the first memory, storing address translation information for a plurality of applications to access the first memory and a second memory including a storage area shared among the plurality of computers, the address translation information being generated for each of the applications, in a cache memory that stores a portion of data accessed by the plurality of applications; monitoring, for each of the applications, a hit rate of data in the cache memory and a number of consecutive pages of data accessed; performing a first process of reducing a data size of address translation information corresponding to an application having a lower hit rate among the plurality of applications; performing a second process of increasing a data size of address translation information corresponding to an application having a smaller number of consecutive pages among the plurality of applications; A method for processing information.

[0165] (Appendix 8) the first process includes a process of reducing the data size by increasing a management granularity of first address translation information corresponding to a first application having a hit rate equal to or less than a first threshold value; 8. An information processing method as described in Appendix 7.

[0166] (Appendix 9) the second process includes a process of increasing the data size by decreasing a management granularity of second address translation information corresponding to a second application in which the hit rate is greater than the first threshold value and the number of consecutive pages is equal to or less than a second threshold value; 10. An information processing method as described in Appendix 8.

[0167] (Appendix 10) The second process includes: storing first data of a first data size in the cache memory; when the hit rate of the second application during a predetermined period after the first data is stored in the cache memory is greater than the first threshold, deleting the first data from the cache memory and increasing a data size of the second address translation information by the first data size. 10. An information processing method as described in Supplementary Note 9.

[0168] (Appendix 11) The second memory is a memory that is not managed by an operating system executed by the processor. An information processing method according to any one of Supplementary Notes 7 to 10.

[0169] (Appendix 12) The second memory is a shared memory conforming to CXL (Compute Express Link), The processor and the second memory are connected via a CXL switch. An information processing method according to any one of Supplementary Note 7 to Supplementary Note 11.

[0170] (Appendix 13) A first memory; a processor coupled to the first memory, The processor, storing address translation information for a plurality of applications to access the first memory and a second memory including a storage area shared among the plurality of computers, the address translation information being generated for each of the applications, in a cache memory that stores a portion of data accessed by the plurality of applications; monitoring, for each of the applications, a hit rate of data in the cache memory and a number of consecutive pages of data accessed; performing a first process of reducing a data size of address translation information corresponding to an application having a lower hit rate among the plurality of applications; performing a second process of increasing a data size of address translation information corresponding to an application having a smaller number of consecutive pages among the plurality of applications; Information processing device.

[0171] (Appendix 14) the processor, in the first process, reduces the data size by increasing a management granularity of first address translation information corresponding to a first application having a hit rate equal to or less than a first threshold. 14. The information processing device according to claim 13.

[0172] (Appendix 15) the processor, in the second process, increases the data size by reducing a management granularity of second address translation information corresponding to a second application in which the hit rate is greater than the first threshold and the number of consecutive pages is equal to or less than a second threshold. 15. The information processing device according to claim 14.

[0173] (Appendix 16) In the second process, the processor storing first data of a first data size in the cache memory; when the hit rate of the second application during a predetermined period after the first data is stored in the cache memory is greater than the first threshold, the first data is deleted from the cache memory, and a data size of the second address translation information is increased by the first data size; 16. The information processing device according to claim 15.

[0174] (Appendix 17) The second memory is a memory that is not managed by an operating system executed by the processor. The information processing device according to any one of claims 13 to 16.

[0175] (Appendix 18) The second memory is a shared memory conforming to CXL (Compute Express Link), The processor and the second memory are connected via a CXL switch. The information processing device according to any one of Supplementary claims 13 to 17. [Explanation of symbols]

[0176] 1 System 1a,1b Interconnect 10 Processing section 11 Applications 12 Memory Management Library 121 Cache Hit Rate Monitor 122 Continuous Access Monitor 123 Table size change section 13 OS 14 Heterogeneous Memory Section 15 Control section 2 Node 2a Processor 2b Memory 2c Graphics Processing Unit 2d storage device 2e Communication Interface 2f IO device 2g reader 2h Device IF 2i Program 2j Recording media 2k bus 20 Processor Board 21 Cache 22 Address Management Table 23 App Data 24 App Monitoring Table 3 Switch 4. Shared Memory

Claims

1. A computer including a first memory and a processor connected to the first memory, storing address translation information for a plurality of applications to access the first memory and a second memory including a storage area shared among the plurality of computers, the address translation information being generated for each of the applications, in a cache memory that stores a portion of data accessed by the plurality of applications; monitoring, for each of the applications, a hit rate of data in the cache memory and a number of consecutive pages of data accessed; performing a first process of reducing a data size of address translation information corresponding to an application having a lower hit rate among the plurality of applications; performing a second process of increasing a data size of address translation information corresponding to an application having a smaller number of consecutive pages among the plurality of applications; An information processing program that executes processing.

2. the first process includes a process of reducing the data size by increasing a management granularity of first address translation information corresponding to a first application having a hit rate equal to or less than a first threshold value; The information processing program according to claim 1 .

3. the second process includes a process of increasing the data size by decreasing a management granularity of second address translation information corresponding to a second application in which the hit rate is greater than the first threshold value and the number of consecutive pages is equal to or less than a second threshold value; The information processing program according to claim 2.

4. The second process includes: storing first data of a first data size in the cache memory; when the hit rate of the second application during a predetermined period after the first data is stored in the cache memory is greater than the first threshold, deleting the first data from the cache memory and increasing a data size of the second address translation information by the first data size. The information processing program according to claim 3.

5. the second memory is a memory that is not managed by an operating system executed by the processor; The information processing program according to any one of claims 1 to 4.

6. the second memory is a shared memory conforming to CXL (Compute Express Link), The processor and the second memory are connected via a CXL switch. The information processing program according to any one of claims 1 to 4.

7. a computer including a first memory and a processor coupled to the first memory, storing address translation information for a plurality of applications to access the first memory and a second memory including a storage area shared among the plurality of computers, the address translation information being generated for each of the applications, in a cache memory that stores a portion of data accessed by the plurality of applications; monitoring, for each of the applications, a hit rate of data in the cache memory and a number of consecutive pages of data accessed; performing a first process of reducing a data size of address translation information corresponding to an application having a lower hit rate among the plurality of applications; performing a second process of increasing a data size of address translation information corresponding to an application having a smaller number of consecutive pages among the plurality of applications; A method for processing information.

8. A first memory; a processor coupled to the first memory, The processor, storing address translation information for a plurality of applications to access the first memory and a second memory including a storage area shared among the plurality of computers, the address translation information being generated for each of the applications, in a cache memory that stores a portion of data accessed by the plurality of applications; monitoring, for each of the applications, a hit rate of data in the cache memory and a number of consecutive pages of data accessed; performing a first process of reducing a data size of address translation information corresponding to an application having a lower hit rate among the plurality of applications; performing a second process of increasing a data size of address translation information corresponding to an application having a smaller number of consecutive pages among the plurality of applications; Information processing device.

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