Display device

Abstract

To provide a display device capable of having higher definition.SOLUTION: A display device includes an array substrate in which a plurality of pixels is arranged in a Dx direction and a Dy direction, a plurality of signal lines DTL connected to the pixels arranged in the Dy direction, a signal line selection circuit that supplies a pixel signal in a selection period of the signal line DTL, and a driver IC that supplies a plurality of image signals resulting from time-divisional multiplexing of the image signal and a selection control signal of the signal line DTL to the signal line selection circuit. In the signal line selection circuit, a plurality of switching circuits to select one of the plurality of signal lines DTL is arranged in the Dx direction on the array substrate. Wires that supply the selection control signal to the signal line selection circuit include a first wire SWL1 to which the switching circuits are connected in the Dx direction, a second wire SWL2 provided approximately parallel to the first wire SWL1 and having both end parts connected to the buffer circuit, and a plurality of third wires SWL3 connected to the second wire SWL2 at a plurality of places including both end parts and a central part of the first wire SWL1.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Conventionally, in a display device using a signal line selection drive system, for example, a configuration has been disclosed in which a control line is wired at the center of a substrate in order to reduce the wiring resistance of a control signal to an analog switch circuit (signal line selection circuit) (for example, Patent Document 1). Also, a configuration has been disclosed in which multiple distribution circuits (signal line selection circuits) are provided and control signals are supplied to both ends of each distribution circuit, thereby reducing waveform rounding of the control signal (for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-192928 A [Patent Document 2] JP 2009-216997 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned Patent Document 1, the control line wired at the center is formed to extend toward both ends, so the wiring resistance becomes larger toward both ends, which may make it difficult to sufficiently suppress voltage drop and delay and attenuation of control signals due to the wiring resistance.

[0005] In recent years, there has been a demand for even higher resolution display panels in configurations in which a display image is enlarged using a lens, such as virtual reality (VR), augmented reality (AR), and mixed reality (MR). In the above-mentioned Patent Document 2, a control signal line is connected to both ends of each distribution circuit, so the number of control signal lines wired between the distribution circuits increases. As a result, the interval between the distribution circuits becomes larger than the pixel interval, and there is a possibility that multiple areas of the display panel divided by each distribution circuit are visible.

[0006] An object of the present invention is to provide a display device capable of achieving high resolution. [Means for solving the problem]

[0007] A display device according to an embodiment of the present disclosure includes a substrate having a display area in which a plurality of pixels are aligned in a first direction and a second direction different from the first direction, a plurality of scanning lines connected to the pixels aligned in the first direction, a plurality of signal lines connected to the pixels aligned in the second direction, a gate driver that supplies scanning signals to the scanning lines during a selection period of the scanning lines, a signal line selection circuit that supplies pixel signals to the signal lines during a selection period of the signal lines, and a driver IC that generates a plurality of image signals by time-division multiplexing the pixel signals to be supplied to the plurality of signal lines, respectively, and supplies the image signals to the signal line selection circuit and supplies a selection control signal for the signal line to the signal line selection circuit, wherein the driver IC: The signal line selection circuit is mounted on the substrate along the signal line selection circuit, and the selection control signal is output from buffer circuits provided at both ends of the driver IC in the first direction, and the signal line selection circuit is a plurality of switch circuits arranged side by side in the first direction on the substrate to select one of a plurality of signal lines, and wiring for supplying the selection control signal to the signal line selection circuit includes a first wiring to which the plurality of switch circuits are connected in the first direction, a second wiring arranged approximately parallel to the first wiring and having both ends connected to the buffer circuits, and a plurality of third wirings connected to the second wiring at least at multiple locations including both ends and a center portion of the first wiring. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a display device. [Diagram 2] FIG. 2 is a diagram showing an example of a pixel arrangement in a display region. [Diagram 3] FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device. [Figure 4] FIG. 4 is a plan view showing an example of the configuration of a pixel. [Figure 5A] FIG. 5A is a diagram showing a first example of a cross section taken along line A1-A2 in FIG. [Figure 5B] FIG. 5B is a diagram showing a second example of a cross section taken along line A1-A2 in FIG. [Figure 6] FIG. 6 is a diagram showing an example of a drive circuit configuration. [Figure 7] FIG. 7 is a schematic diagram of a substrate showing an example of connection of selection control lines according to a conventional example. [Figure 8] FIG. 8 is a schematic diagram of a substrate showing an example of connection of selection control lines according to the embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view taken along line B1-B2 in FIG. [Figure 10] FIG. 10 is a diagram showing an example of a selection control signal waveform in the connection example shown in FIG. [Figure 11] FIG. 11 is a diagram showing an example of a selection control signal waveform in the connection example shown in FIG. [Figure 12] FIG. 12 is a schematic diagram of a substrate showing an example of connection of selection control lines according to a modified example of the embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a selection control signal waveform in the connection example shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The form (embodiment) for carrying out the invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiment. The components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] Fig. 1 is a diagram showing an example of a schematic configuration of a display device, and Fig. 2 is a diagram showing an example of a pixel arrangement in a display region.

[0011] The display device 1 according to the present embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. In addition, in the present disclosure, the display device 1 may adopt, for example, a column inversion driving method or a frame inversion method as a driving method. The driving method in the display device 1 is not limited to the column inversion driving method or the frame inversion method.

[0012] The display device 1 has a display area AA provided on a display panel 11, and a drive circuit 40 provided in a peripheral area of ​​the display area AA. The display device 1 is supplied with power from a power supply device 12.

[0013] The drive circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral region of the display area AA. The display control circuit 44 is included in a driver IC4 mounted in the peripheral region of the display area AA. The driver IC4 is connected to the control device 13 via a relay board constituted by, for example, a flexible printed circuit (FPC) board or the like.

[0014] The control device 13 controls the power supply from the power supply device 12 to the display device 1. The control device 13 also controls power on and power off of the display device 1. The power supply device 12 and the control device 13 are mounted, for example, in a device (not shown) in which the display device 1 is mounted.

[0015] The display area AA is provided with a plurality of pixels Pix arranged in the Dx direction (first direction) and the Dy direction (second direction). The display area AA is also provided with scanning lines (gate lines) SCL that supply scanning signals (gate signals) GATE to the pixels Pix, signal lines DTL that supply pixel signals SIG to the pixels Pix, and a common electrode COML that supplies a common potential VCOM to the pixels Pix. In this embodiment, the scanning lines SCL are provided extending in the Dx direction (first direction). In this embodiment, the signal lines DTL are provided extending in the Dy direction (second direction).

[0016] As shown in Fig. 2, each pixel Pix includes a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is configured with a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter also referred to as "n-type TFT"). The source of the pixel transistor Tr is connected to a signal line DTL, the gate is connected to a scanning line (gate line) SCL, and the drain is connected to the pixel electrode PX. A storage capacitance CS is formed between the pixel electrode PX and a common electrode COML.

[0017] A scanning signal (gate signal) GATE (1, 2, . . . , m, . . . , M) is supplied to the gates of the pixel transistors Tr of the pixels Pix arranged in the Dx direction (first direction) via the respective scanning lines (gate lines) SCL, and a pixel signal SIG (1, 2, . . . , n, . . . N) is supplied to the sources of the pixel transistors Tr of the pixels Pix arranged in the Dy direction (second direction) via the respective signal lines DTL. In FIG. 2, an example is shown in which N pixels Pix are arranged in the Dx direction (first direction) and M pixels Pix are arranged in the Dy direction (second direction), but this is not limiting. Hereinafter, a row in which the pixels Pix are arranged in the Dx direction (first direction) is also referred to as a pixel row. Also, a column in which the pixels Pix are arranged in the Dy direction (second direction) is also referred to as a pixel column.

[0018] In the present disclosure, the pixel Pix includes, for example, a red pixel for displaying red (R), a green pixel for displaying green (G), and a blue pixel for displaying blue (B). An example of the pixel arrangement is a stripe arrangement in which RGB pixels are arranged in the Dx direction (first direction), but the pixel arrangement is not limited to the RGB stripe arrangement. Specifically, for example, the pixel Pix may be a white pixel for displaying white (W), a diagonal stripe arrangement having a predetermined angle with respect to the Dx direction (first direction) or the Dy direction (second direction), or an arrangement in which a plurality of pixel groups displaying different colors are periodically arranged in both the Dx direction (first direction) and the Dy direction (second direction).

[0019] The power supply device 12 generates a first power supply voltage signal PSIG1 of a positive value and a second power supply voltage signal PSIG2 of a negative value to be supplied to the display device 1. The first power supply voltage signal PSIG1 is controlled to a first potential (VGH). The second power supply voltage signal PSIG2 is controlled to a second potential (VGL) that is lower than the first potential (VGH). The first potential (VGH) is set to, for example, 6V. The second potential (VGL) is set to, for example, -6V. The first potential (VGH) is not limited to 6V. Furthermore, the second potential (VGL) is not limited to -6V.

[0020] The control device 13 transmits a video signal, which is an original signal of a video to be displayed on the display device 1, to the display device 1. The control device 13 also transmits a control signal for controlling the display device 1 to the display device 1. The control device 13 also transmits a control signal for controlling the power supply from the power supply device 12 to the display device 1 to the power supply device 12.

[0021] The control device 13 includes, for example, a storage device such as a CPU (Central Processing Unit) and a memory. The control device 13 executes a program using these hardware resources such as the CPU and the storage device, thereby realizing the display function of the display device 1. The control device 13 controls the driver IC 4 to handle an image to be displayed on the display device 1 as image input gradation information according to the execution result of the program.

[0022] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives video signals and various control signals from the control device 13. The display control circuit 44 also converts the video signals from the control device 13 into image signals Vsig and outputs them. The image signals Vsig are, for example, signals obtained by time-division multiplexing pixel signals SIG corresponding to the RGB pixel arrangement. The display control circuit 44 also supplies a common potential VCOM to the common electrode COML.

[0023] The display control circuit 44 also functions as an interface (I / F) between the signal line selection circuit 43 and the control device 13, and as a timing generator.

[0024] Next, a schematic structure of the display device 1 according to the embodiment will be described with reference to FIG. 3 to FIG. 5B. FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device. FIG. 4 is a plan view showing a configuration example of a pixel. FIG. 5A is a diagram showing a first example of a cross section taken along line A1-A2 in FIG. 4. In the first example shown in FIG. 5A, a bottom-gate type transistor is used as the pixel transistor Tr. FIG. 5B is a diagram showing a second example of a cross section taken along line A1-A2 in FIG. 4. In the second example shown in FIG. 5B, a top-gate type transistor is used as the pixel transistor Tr.

[0025] The array substrate 2 includes a first substrate 21 made of glass or transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX and the common electrode COML. The plurality of pixel electrodes PX are arranged, for example, in a matrix above the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0026] The pixel electrodes PX are provided corresponding to each pixel Pix. A pixel signal SIG for performing a display operation is supplied to the pixel electrodes PX from a signal line selection circuit 43 via a signal line DTL and a pixel transistor Tr. During a display operation, a common potential VCOM for display, which is a voltage signal, is supplied to the common electrode COML from a driver IC4. The common potential VCOM is preferably a potential different from the GND potential, and is set to, for example, about −0.7V. The set value of the common potential VCOM is set to an optimal value that does not cause flicker in a driving method such as a column inversion driving method or a frame inversion driving method. The common potential VCOM is preferably a fixed potential, but may be configured to have a waveform consisting of an AC rectangular wave.

[0027] The pixel electrodes PX and the common electrode COML are made of a conductive material having light-transmitting properties, such as ITO (Indium Tin Oxide), etc. A polarizing plate 35B is provided on the lower side of the first substrate 21 via an adhesive layer (not shown).

[0028] The counter substrate 3 includes a second substrate 31 made of glass or transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one surface of the second substrate 31. In addition, a polarizing plate 35A is provided on the upper side of the second substrate 31 via an adhesive layer (not shown).

[0029] The array substrate 2 and the counter substrate 3 are disposed opposite to each other with a predetermined gap (cell gap) provided. A liquid crystal layer 6 is provided as a display function layer in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 modulates light passing through the liquid crystal layer 6 by changing the alignment state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between each pixel electrode PX and the common electrode COML. In this embodiment, for example, a liquid crystal suitable for a lateral electric field mode such as IPS (in-plane switching) including FFS (fringe field switching) is used.

[0030] The array substrate 2 includes wiring such as pixel transistors Tr of each pixel Pix, signal lines DTL that supply pixel signals SIG to each pixel electrode PX, and scanning lines (gate lines) SCL that supply gate signals GATE that drive each pixel transistor Tr. The signal lines DTL and the scanning lines (gate lines) SCL extend in a plane parallel to the surface of the first substrate 21.

[0031] 4, a region surrounded by a scanning line (gate line) SCL and a signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip-shaped electrodes 22a and a connecting portion 22b.

[0032] As shown in FIG. 4, the pixel transistor Tr includes a semiconductor 61, a source electrode 62, a drain electrode 63 and a gate electrode 64.

[0033] As shown in FIG. 5A, in a configuration using a bottom-gate type transistor as the pixel transistor Tr, a gate line layer 51 is provided on a first substrate 21. A gate electrode 64 (scanning line (gate line) SCL) is provided on the gate line layer 51. An insulating layer 58a (second insulating layer) is provided on the first substrate 21, covering the gate electrode 64. A semiconductor layer 52 is provided on the insulating layer 58a. A semiconductor 61 is provided on the semiconductor layer 52. A signal line layer 53 is provided on the upper side of the semiconductor layer 52 via an insulating layer 58c (first insulating layer).

[0034] As shown in FIG. 5B, in a configuration using a top-gate transistor as the pixel transistor Tr, a light shield LS is provided on the first substrate 21. A semiconductor layer 52 is provided on the light shield LS via an insulating layer 58f. A semiconductor 61 is provided on the semiconductor layer 52. A gate line layer 51 is provided on the upper side of the semiconductor layer 52 via an insulating layer 58c. A gate electrode 64 is provided on the gate line layer 51. An insulating layer 58a is provided on the insulating layer 58c, covering the gate electrode 64. A signal line layer 53 is provided on the upper side of the gate line layer 51 via the insulating layer 58a.

[0035] A drain electrode 63 and a source electrode 62 (signal line DTL) are provided on the signal line layer 53. An auxiliary wiring layer 54 is provided above the drain electrode 63 and the source electrode 62 (signal line DTL) via an insulating layer 58d (third insulating layer). A common electrode layer 55 is provided above the auxiliary wiring layer 54 via an insulating layer 58e. A common electrode COML is provided on the common electrode layer 55. Note that a configuration in which the auxiliary wiring layer and the common electrode layer overlap without an insulating layer can also be employed. A pixel electrode PX is provided above the common electrode layer 55 via an insulating layer 24.

[0036] As shown in FIG. 4 and FIG. 5A (or FIG. 5B), the pixel electrode PX is connected to a drain electrode 63 of the pixel transistor Tr through a contact hole H11. The drain electrode 63 is connected to a semiconductor 61 through a contact hole H12. The semiconductor 61 intersects with a gate electrode 64 in a plan view. The gate electrode 64 is connected to a scanning line (gate line) SCL and is provided so as to protrude from one side of the scanning line (gate line) SCL. The semiconductor 61 extends to a position where it overlaps with a source electrode 62 and is electrically connected to the source electrode 62 through a contact hole H13. The source electrode 62 is connected to a signal line DTL and protrudes from one side of the signal line DTL.

[0037] The semiconductor 61 may be made of known materials such as polysilicon or oxide semiconductor. For example, the use of TAOS (Transparent Amorphous Oxide Semiconductor) provides a good ability to hold the voltage for image display for a long time (holding rate), improving the display quality. In addition, oxide semiconductors containing TAOS have a small leakage current when the pixel transistor Tr is off.

[0038] The gate electrode 64 (scanning line (gate line) SCL) is made of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof. The drain electrode 63 and the source electrode 62 (signal line DTL) are made of, for example, titanium aluminum (TiAl), which is an alloy of titanium and aluminum.

[0039] Known insulating materials can be used as the material of the insulating layers 24, 58a, 58c, 58d, 58e, and 58f. For example, TEOS (Tetra Ethyl Ortho Silicate) can be used as the material of the insulating layer 58b. For example, silicon oxide film (SiO2) can be used as the material of the insulating layer 58c. An organic insulating film such as acrylic is used as the material of the insulating layer 58d. This allows the surface on which the common electrode COML is provided to be flattened.

[0040] The auxiliary wiring layer 54 is made of a material similar to that of the gate electrode 64 (scanning line (gate line) SCL), such as aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof.

[0041] Fig. 6 is a diagram showing an example of a drive circuit configuration. Fig. 6 shows an example of a circuit configuration corresponding to pixels Pix(n,m) and Pix(n+1,m). Pixel Pix(n,m) indicates the n-th pixel Pix from the left in the figure of pixels Pix arranged in the Dx direction (first direction) and the m-th pixel Pix from the top in the figure of pixels Pix arranged in the Dy direction (second direction) in the pixel array shown in Fig. 2. Also, pixel Pix(n+1,m) indicates the n+1-th pixel Pix from the left in the figure of pixels Pix arranged in the Dx direction (first direction) and the m-th pixel Pix from the top in the figure of pixels Pix arranged in the Dy direction (second direction) in the pixel array shown in Fig. 2.

[0042] Each circuit element constituting the drive circuit 40 operates by receiving a first power supply voltage signal PSIG1 and a second power supply voltage signal PSIG2 from the power supply device 12. The potential of the first power supply voltage signal PSIG1 (first potential VGH) is set to the high potential of the scanning signal (gate signal) GATE(m) supplied to the gate of the pixel transistor Tr. Also, the potential of the second power supply voltage signal PSIG2 (second potential VGL) is set to the low potential of the scanning signal GATE(m) supplied to the gate of the pixel transistor Tr.

[0043] The display control circuit 44 (driver IC4) controls the gate driver 42 and the signal line selection circuit 43. Specifically, the display control circuit 44 (driver IC4) supplies synchronization signals such as a start pulse STV and a shift clock CKV, and a scanning line drive signal ENB to the gate driver 42. The display control circuit 44 (driver IC4) also supplies a selection control signal MUX to the signal line selection circuit 43. The potential of the first power supply voltage signal PSIG1 (first potential VGH) is set to, for example, the high potential of the selection control signal MUX. The potential of the second power supply voltage signal PSIG2 (second potential VGL) is set to, for example, the low potential of the selection control signal MUX. The present disclosure is not limited by the potential of the selection control signal MUX.

[0044] The gate driver 42 is a circuit that generates a scanning signal GATE(m) to be supplied to the gate of the pixel transistor Tr, based on a start pulse STV, a shift clock CKV, and a scanning line driving signal ENB output from a display control circuit 44 (driver IC4).

[0045] Specifically, during a selection period of the scanning line SCL to which the m-th pixel row is connected, the scanning signal GATE(m) is set to a high potential (first potential VGH), thereby turning on the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0046] In addition, during a non-selection period of the scanning line SCL to which the m-th pixel row is connected, the scanning signal GATE(m) is set to a low potential (second potential VGL), thereby turning off the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0047] The signal line selection circuit 43 includes a switch circuit ASW that time-divides a selection period of the scanning line SCL to which the m-th pixel row is connected, and supplies a pixel signal SIG(n) to the pixel Pix(n,m) and a pixel signal SIG(n+1) to the pixel Pix(n+1,m). In the example shown in Fig. 6, the switch circuit ASW includes switch transistors Trn1 and Trn2 formed of n-type TFTs, and switch transistors Trp1 and Trp2 formed of p-type TFTs.

[0048] The signal line selection circuit 43 has a plurality of switch circuits ASW arranged side by side in the Dx direction (first direction) on the array substrate 2. Fig. 6 illustrates an example in which the selection period of the scanning line SCL to which the m-th pixel row is connected is divided into two, and the corresponding pixel signals SIG(n) and SIG(n+1) are selectively output during each selection period of the pixel Pix(n,m) and the pixel Pix(n+1,m). In this configuration, the total number of switch circuits ASW arranged side by side in the Dx direction (first direction) is N / 2.

[0049] Specifically, during a selection period of the signal line DTL to which the pixel Pix(n,m) is connected, the selection control signal MUX1 is set to a high potential (first potential VGH) and the selection control signal xMUX1 is set to a low potential (second potential VGL), whereby the switch transistors Trn1 and Trp1 are controlled to be on, and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n).

[0050] During a selection period of the signal line DTL to which the pixel Pix(n+1,m) is connected, the selection control signal MUX2 is set to a high potential (first potential VGH) and the selection control signal xMUX2 is set to a low potential (second potential VGL), thereby turning on the switch transistors Trn2 and Trp2, and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n+1).

[0051] 6 shows a switch circuit ASW having a CMOS configuration, but is not limited thereto. The switch circuit ASW may be configured, for example, only with n-type TFTs, or only with p-type TFTs.

[0052] 6 shows an example in which the selection period of the scanning line SCL to which the m-th pixel row is connected is divided into two, and the corresponding pixel signals SIG(n) and SIG(n+1) are selectively output during each selection period of the pixels Pix(n,m) and Pix(n+1,m), but the present invention is not limited to this. For example, any other embodiment may be used as long as the selection period of the scanning line SCL to which the m-th pixel row is connected is divided into three or more periods, and the corresponding pixel signals SIG are selectively output during each selection period of each pixel Pix.

[0053] 7 is a schematic diagram of a substrate showing a connection example of a selection control line according to a conventional example. In the following explanation, for ease of explanation, a plurality of wirings transmitting the selection control signals MUX1, xMUX1, MUX2, and xMUX2 are simplified as selection control lines SWL.

[0054] 7, the wirings (signal line DTL, image signal line VsigL, and selection control line SWL) in the signal line layer 53 (first metal layer) on the array substrate 2 are shown by solid lines, and the wirings (image signal line VsigL and selection control line SWL) in the gate line layer 51 (second metal layer) on the array substrate 2 are shown by dashed lines. The wirings on the signal line layer 53 (first metal layer) and the wirings on the gate line layer 51 (second metal layer) are connected by contact holes indicated by black dots. Note that the scanning lines (gate lines) SCL are omitted.

[0055] 7, the driver IC 4 is mounted on the array substrate 2 along the signal line selection circuit 43. The output buffer circuits Buf for the selection control signals are generally provided at both ends of the driver IC 4 in the longitudinal direction.

[0056] In the conventional connection example shown in FIG. 7, the selection control line SWL is connected to both ends of the signal line selection circuit 43 in the Dx direction (first direction).

[0057] Fig. 8 is a substrate schematic diagram showing an example of connection of selection control lines according to the embodiment. Fig. 9 is a schematic cross-sectional view taken along line B1-B2 in Fig. 8. Fig. 9 illustrates a layer configuration similar to that of the first example of the pixel cross section shown in Fig. 5A.

[0058] 8 and 9, the selection control line includes a first wiring SWL1 that connects a plurality of switch circuits ASW of the signal line selection circuit 43 arranged in the Dx direction (first direction) on the array substrate 2, a second wiring SWL2 that is provided substantially parallel to the first wiring SWL1 and has both ends connected to an output buffer circuit Buf of the selection control signal provided at both ends of the driver IC 4 in the Dx direction (first direction), and a third wiring SWL3 that is connected to the second wiring SWL2 at both ends and the center of the first wiring SWL1. Also, in the connection example shown in FIG. 8, the image signal line includes a first image signal line VsigL1 that intersects with the second wiring SWL2, and a second image signal line VsigL2 that is connected to the switch circuit of the signal line selection circuit 43.

[0059] In the connection example according to the embodiment shown in FIG. 8, the first wiring SWL1, the second wiring SWL2, and the third wiring SWL3 are provided in a signal line layer 53 (first metal layer) on the array substrate 2.

[0060] In the connection example according to the embodiment shown in Fig. 8, the second wiring SWL2 is connected to the output buffer circuits Buf of the selection control signal provided at both ends in the Dx direction (first direction) of the driver IC4 via contact holes H21, H22 and wiring provided in the gate line layer 51 (second metal layer) at both ends in the Dx direction (first direction) as shown in Fig. 9. In addition, the second wiring SWL2 intersects with the first image signal line VsigL1 provided in the gate line layer 51 (second metal layer) with insulating layers 58a, 58c sandwiched therebetween as shown in Fig. 9.

[0061] The layer in which the first wiring SWL1, the second wiring SWL2, and the third wiring SWL3 are provided is not limited to the signal line layer 53 (first metal layer). The first wiring SWL1, the second wiring SWL2, and the third wiring SWL3 may be provided in a metal layer other than the gate line layer 51 (second metal layer).

[0062] Fig. 10 is a diagram showing an example of a selection control signal waveform in the connection example shown in Fig. 7. Fig. 11 is a diagram showing an example of a selection control signal waveform in the connection example shown in Fig. 8.

[0063] The on-timing of the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2 varies depending on the potential of the pixel signals SIG(n) and SIG(n+1). In Fig. 10 and Fig. 11, the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2 are turned on in a region where the selection control signal MUX (MUX1, xMUX1, MUX2, xMUX2) is equal to or higher than the potential indicated by the dashed line.

[0064] The on-period of the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2 is longer than the selection period of the pixel Pix(n,m) (the high period under the control of the selection control signal MUX1 and the low period under the control of the selection control signal xMUX1) and the selection period of the pixel Pix(n+1,m) (the high period under the control of the selection control signal MUX2 and the low period under the control of the selection control signal xMUX2) due to the turn-on time and turn-off time caused by the impedance of the selection control line SWL. For this reason, it is necessary to provide an interval time Int between the selection period of the pixel Pix(n,m) and the selection period of the pixel Pix(n+1,m) so that the on-period of the switch transistors Trn1, Trp1 and the on-period of the switch transistors Trn2, Trp2 do not overlap.

[0065] As shown in Fig. 10, in the connection example shown in Fig. 7, the impedance of the selection control line SWL is large, and the turn-on time and turn-off time of the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2 are long. As a result, the effective on-period of the switch transistors Trn1, Trp1 is long compared to the selection period of the pixel Pix(n,m) (the high period under the control of the selection control signal MUX1 and the low period under the control of the selection control signal xMUX1). Also, the effective on-period of the switch transistors Trn2, Trp2 is long compared to the selection period of the pixel Pix(n+1,m) (the high period under the control of the selection control signal MUX2 and the low period under the control of the selection control signal xMUX2). As a result, it is necessary to set the interval time Int provided between the selection period of the pixel Pix(n,m) and the selection period of the pixel Pix(n+1,m) long.

[0066] In the connection example (FIG. 8) of the selection control line SWL according to the embodiment, the impedance of the selection control line SWL is lower than that of the conventional example (FIG. 7) due to an increase in the supply point P of the selection control signal to the signal line selection circuit 43. As a result, as shown in FIG. 11, the turn-on time and turn-off time of the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2 can be shortened compared to the conventional example shown in FIG. 10. As a result, the substantial on-period of the switch transistors Trn1, Trp1 for the selection period of the pixel Pix(n,m) and the substantial on-period of the switch transistors Trn2, Trp2 for the selection period of the pixel Pix(n+1,m) are shortened. As a result, the interval time Int provided between the selection period of the pixel Pix(n,m) and the selection period of the pixel Pix(n+1,m) can be shortened. Furthermore, by shortening the turn-on times of the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2, it is possible to shorten the selection period of the pixel Pix(n,m) (the high period under the control of the selection control signal MUX1 and the low period under the control of the selection control signal xMUX1) and the selection period of the pixel Pix(n+1,m) (the high period under the control of the selection control signal MUX2 and the low period under the control of the selection control signal xMUX2). This shortens the selection period (1 horizontal period = 1H period) of the scanning line SCL to which the m-th pixel row is connected, making it possible to display a higher resolution than in the conventional example at the same frame rate.

[0067] (Modification) Fig. 12 is a schematic diagram of a substrate showing a connection example of a selection control line according to a modified example of the embodiment, and Fig. 13 is a diagram showing an example of a selection control signal waveform in the connection example shown in Fig. 12.

[0068] In the modification shown in Fig. 12, the number of supply points P of the selection control signal to the signal line selection circuit 43 is further increased compared to Fig. 8. Specifically, in the connection example of the selection control line according to the modification of the embodiment shown in Fig. 12, the selection control line includes a third wiring SWL3 connected to the second wiring SWL2 at multiple points including both ends and the center of the first wiring SWL1.

[0069] As a result, as shown in Fig. 13, the turn-on time and turn-off time of the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2 can be further shortened compared to the connection example according to the embodiment shown in Fig. 11. As a result, the substantial on-period of the switch transistors Trn1, Trp1 for the selection period of the pixel Pix(n,m) and the substantial on-period of the switch transistors Trn2, Trp2 for the selection period of the pixel Pix(n+1,m) are further shortened, and as a result, the interval time Int provided between the selection period of the pixel Pix(n,m) and the selection period of the pixel Pix(n+1,m) can be further shortened. In addition, the turn-on time of the switch transistors Trn1, Trp1 and the switch transistors Trn2, Trp2 is further shortened, so that the selection period of the pixel Pix(n,m) and the selection period of the pixel Pix(n+1,m) can be further shortened. This further shortens the selection period (1 horizontal period=1H period) of the scanning line SCL to which the m-th pixel row is connected, enabling a higher resolution display at the same frame rate.

[0070] The position of the supply point P of the selection control signal to the signal line selection circuit 43 and the layer in which the third wiring SWL3 extending from the second wiring SWL2 to the signal line selection circuit 43 is provided may be appropriately set according to the arrangement and wiring conditions of the display control circuit 44 (driver IC4) and the signal line selection circuit 43. Specifically, for example, in the connection example shown in Fig. 12, it is preferable to provide the supply point P of the selection control signal to the signal line selection circuit 43 at a position where the wiring direction changes between adjacent image signal lines VsigL. In this way, it is possible to prevent the width in the Dy direction (second direction) between the signal line selection circuit 43 and the driver IC4 from becoming wider.

[0071] The display device 1 is not limited to a liquid crystal display device, and may be, for example, an organic EL display using organic light emitting diodes (OLEDs) as display elements. The display device 1 may also be an inorganic EL display using inorganic light emitting diodes (micro LEDs) as display elements. The display device 1 may also be an electrophoretic display (EPD), or may even be a transparent display that displays an image on a transparent display surface.

[0072] Although the preferred embodiment of the present disclosure has been described above, the present disclosure is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally belong to the technical scope of the present disclosure. [Explanation of symbols]

[0073] 1 Display device 4 Driver IC 11 Display Panel 12 Power supply 13 Control device 40 Drive circuit 42 Gate Driver 43 Signal line selection circuit 44 Display control circuit 51 Gate line layer (second metal layer) 53 Signal line layer (first metal layer) AA display area ASW Switch circuit COML Common electrode CS retention capacity DTL signal line ENB Scan line drive signal GATE Scan signal (gate signal) MUX, MUX1, MUX2, xMUX1, xMUX2 selection control signal Pix, Pix(n,m), Pix(n+1,m) pixels PSIG1 First power supply voltage signal PSIG2 Second power supply voltage signal PX pixel electrode SCL Scan line (gate line) SIG Pixel signal SWL Selection control line Tr Pixel transistor Trn1, Trn2, Trp1, Trp2 switch transistors VCOM common potential VGH First potential VGL 2nd potential Vsig Image signal VsigL Image signal line

Claims

1. a substrate having a display area in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction; A plurality of scanning lines connected to pixels aligned in the first direction; A plurality of signal lines connected to pixels arranged in the second direction; a gate driver for supplying a scanning signal to the scanning line during a selection period of the scanning line; a signal line selection circuit that supplies a pixel signal to the signal line during a selection period of the signal line; a driver IC that generates a plurality of image signals by time-division multiplexing pixel signals to be supplied to a plurality of signal lines, respectively, and supplies the image signals to the signal line selection circuit, and also supplies a selection control signal for the signal lines to the signal line selection circuit; Equipped with The driver IC includes: mounted on the substrate along the signal line selection circuit; The selection control signal is The signal is output from buffer circuits provided at both ends of the driver IC in the first direction, The signal line selection circuit includes: a plurality of switch circuits for selecting one of a plurality of signal lines are arranged side by side in the first direction on the substrate; The wiring for supplying the selection control signal to the signal line selection circuit is a first wiring to which the plurality of switch circuits are connected in the first direction; a second wiring provided substantially parallel to the first wiring, both ends of the second wiring being connected to the buffer circuit; a plurality of third wirings connected to the second wiring at a plurality of locations including at least both ends and a center portion of the first wiring; Including, Display device.

2. The substrate is a first metal layer on which the signal line is provided; a second metal layer different from the first metal layer; having the first wiring, the second wiring, and the third wiring are provided in the first metal layer; The wiring for supplying the image signal to the signal line selection circuit is a first image signal line provided in the second metal layer and intersecting the second wiring; a second image signal line provided in the first metal layer and connected to the switch circuit; Including, The display device according to claim 1 .

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