Storage device, host device, and information processing system

Abstract

To provide a storage device, a host device, and an information processing system which can improve average latency and throughput.SOLUTION: According to an embodiment of the present invention, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory has a first region where data readout can be performed with the number of times of voltage application of one or two and a second region where the data readout can be performed with the number of times of voltage application of 3 or more. The controller has readout frequency information including information showing the number of times of issuance of a read command for each of segments of a readout request unit. The controller executes, on the basis of the readout frequency information, write control of a first segment of the number of times of issuance of a predetermined reference value or more into the first region or the second region and write control of a second segment of the number of times of issuance of less than the predetermined reference value into the second region.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a storage device, a host device, and an information processing system. [Background technology]

[0002] With the development of mass media, especially the spread of the Internet, the amount of information available to people is increasing at an accelerating rate. With the development of sensing technology using IoT and the active use of large-scale data, such as deep learning, the amount of information accumulated every day is becoming increasingly huge. By managing this data in a hierarchical manner based on update frequency, the performance of writing data to file systems and databases has improved significantly. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0076753 [Patent Document 2] US Patent Application Publication No. 2012 / 0297121 [Patent Document 3] U.S. Patent No. 7,859,932 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a storage device, a host device, and an information processing system that can improve average latency and throughput. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a storage device includes a non-volatile memory and a controller, the non-volatile memory has a first area from which data can be read with one or two voltage applications, and a second area from which data can be read with three or more voltage applications, the controller has read frequency information including information indicating the number of times a read command is issued for each segment of a read request unit, and based on the read frequency information, the controller controls the writing of a first segment whose issuance count is equal to or greater than a predetermined reference value to the first area or the second area, and controls the writing of a second segment whose issuance count is less than the predetermined reference value to the second area. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a hardware configuration of an information processing system according to a first embodiment of the present invention. [Diagram 2] 1 is a block diagram showing a functional configuration of an information processing system according to a first embodiment of the present invention. [Diagram 3] FIG. 2 is a block diagram showing a modified example of the functional configuration of the information processing system according to the first embodiment of the present invention. [Figure 4] 2 is a block diagram showing a configuration of a host memory in the information processing system according to the first embodiment of the present invention. FIG. [Diagram 5] 3 is a diagram showing a data structure of a read count map of the information processing system according to the first embodiment of the present invention. FIG. [Figure 6] 1 is a diagram showing an overview of division of a write area in a non-volatile memory of an information processing system according to a first embodiment of the present invention. [Figure 7] 2 is a diagram showing an example of a bit arrangement of 4-4-3-4 Gray coding in the non-volatile memory of the information processing system according to the first embodiment of the present invention; FIG. [Figure 8] 2 is a diagram showing an example of a bit arrangement of 1-4-5-5 Gray coding in a non-volatile memory of the information processing system according to the first embodiment of the present invention; FIG. [Figure 9]3 is a diagram showing a threshold region after data programming in the nonvolatile memory according to the first embodiment of the present invention; FIG. [Figure 10] 13 is a diagram showing an example of a voltage waveform applied to a word line when reading data of a lower page in a cell written in 4-4-3-4 Gray coding in a non-volatile memory. FIG. [Figure 11] 13 is a diagram showing an example of a voltage waveform applied to a word line when reading data of a lower page in a cell written in 1-4-5-5 Gray coding in a non-volatile memory. FIG. [Figure 12] 5 is a flowchart showing a command processing operation of the information system according to the first embodiment of the present invention. [Figure 13] 5 is a flowchart illustrating an example of an initialization operation of the storage device according to the first embodiment of the present invention. [Figure 14] 11 is a flowchart illustrating an example of an operation of registering Read Cold data in a garbage collection candidate segment list according to the first embodiment of the present invention. [Figure 15] 10 is a flowchart showing an example of an operation of receiving a copy command including Read Hot data in the storage device according to the first embodiment of the present invention. [Figure 16] 10 is a flowchart showing an example of an operation of receiving a copy command including Read Cold data in the storage device according to the first embodiment of the present invention. [Figure 17] 5 is a flowchart showing an example of an operation of garbage collection by a CPU according to the first embodiment of the present invention. [Figure 18] 13 is a flowchart illustrating an example of an operation of garbage collection according to the second embodiment of the present invention. [Figure 19] 13 is a flowchart showing an example of a movement operation of Read Cold data in a cleaning process according to the second embodiment of the present invention. [Figure 20] 13 is a flowchart showing an example of a copy operation of Read Hot data according to the third embodiment of the present invention. [Figure 21]13 is a flowchart illustrating an example of a copy operation of Read Cold data according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] In the following description, data with a high read frequency is called "Read Hot" and data with a low read frequency is called "Read Cold". In addition, the classification of "Read Hot" and "Read Cold" is called Hot Cold separation. In the information processing system of the embodiment, data with a high read frequency is arranged in a page (area where the number of voltage applications is 1 or 2) where the number of voltage applications is small when data is read in the gray coding of QLC (Quad Level Cell) or NAND with more multi-valued than QLC. Similarly, in the information processing system of the embodiment, data with a low read frequency is arranged in a page (area where the number of voltage applications is 3 or more) where the number of voltage applications is large when data is read in the gray coding of QLC or NAND with more multi-valued than QLC. Here, gray coding is an encoding method that encodes data so that the Hamming distance between adjacent codes is always 1. When a gray coded code changes from a certain value to an adjacent value, only one bit always changes.

[0008] The storage device in the information processing system according to the embodiment further comprises an interface for receiving information indicating that the data is Read Hot from the host, and an interface for allowing the host to specify the size of the area in which the Read Hot data is to be allocated.

[0009] (First embodiment) The information processing system of the first embodiment performs hot / cold separation based on the read frequency of a segment. Based on the result of the hot / cold separation, the information processing system stores data with a high read frequency in an area of ​​the storage device with high read speed (SLC area), and stores data with a low read frequency in an area of ​​the storage device with low read speed (QLC area).

[0010] 1 shows the configuration of an information processing system 101 according to the first embodiment. The information processing system 101 according to the first embodiment includes a host 102 and a storage device 105.

[0011] The host 102 is an information processing device, such as a server, a personal computer, an in-vehicle device, or a mobile device. The host 102 issues a predetermined command and transmits it to the storage device 105.

[0012] The storage device 105 is a device that permanently stores data using a non-volatile memory. The storage device 105 is an embedded flash memory or SSD that complies with the UFS standard, the eMMC standard, the NVMe standard, or the like. The storage device 105 is communicably connected to the host 102. The storage device 105 functions as an external storage device for the host 102. The storage device 105 writes, reads, erases, copies, and the like of data in response to received commands.

[0013] The host 102 includes a host controller 103 and a host memory 104 .

[0014] The host controller 103 is hardware that connects to the storage device 105. The host controller 103 may be implemented as, for example, an SoC. The host controller 103 has a CPU (not shown) and performs processing for issuing commands to the storage device 105.

[0015] The host memory 104 is, for example, a volatile memory such as a DRAM, etc. The host memory 104 stores data used in the processing of the host controller 103.

[0016] The storage device 105 includes a controller 106 , a buffer memory 111 , and a non-volatile memory 112 .

[0017] The controller 106 is hardware that realizes access to the non-volatile memory 112. The controller 106 executes data processing upon receiving a command from the host 102. The controller 106 may receive a command from the host 102 requesting a write process (hereinafter referred to as a "write command").

[0018] The buffer memory 111 is a volatile memory such as an SRAM or a DRAM. The buffer memory 111 functions as a memory that temporarily holds write data input from the host 102. The buffer memory 111 also functions as a memory that temporarily holds read data read from the non-volatile memory 112 before transferring the read data to the host 102.

[0019] The non-volatile memory 112 is a memory element capable of retaining stored contents even without external power supply. The non-volatile memory 112 may be configured, for example, by a NAND type flash memory. The non-volatile memory 112 has a flash controller and a plurality of flash memory chips (not shown). The flash controller is a functional unit that controls writing, reading, and erasing of data to the flash memory chips. The flash memory chip is an element configured to be able to write bit data to a number of memory cells arranged in the chip, read written data, or erase written data in blocks.

[0020] The controller 106 includes a host interface 107 , a buffer interface 108 , a memory interface 109 , and a CPU 110 .

[0021] The host interface 107 is a controller that controls communication with the host 102. The host interface 107 functions as an interface that connects to the host 102.

[0022] The buffer interface 108 is a controller that controls access to the buffer memory 111 by the controller 106 .

[0023] The memory interface 109 is a controller that controls communication with the non-volatile memory 112. The memory interface 109 is connected to the non-volatile memory 112 via a bus.

[0024] The CPU 110 is a central processing unit that interprets and executes commands received by the host interface 107.

[0025] (Functional configuration) The functional configuration of the information processing system 101 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a block diagram showing the functional configuration of the information processing system. As described above, the information processing system 101 according to the first embodiment includes a host 102 and a storage device 105.

[0026] First, a description will be given of the functions of the host 102. The host 102 has an application 201 and an OS 202 as its functions.

[0027] The application 201 is a functional unit that accesses data from the storage device 105. To execute the data access, the application 201 issues a VFS call to the OS 202. The VFS call is a communication requesting the execution of a read, write, or the like to a virtual file system (VFS) (described later) which is one function of the OS 202.

[0028] The OS 202 is a functional unit that constitutes the core system of the host 102. The OS 202 manages device operations and process operations. The OS 202 has a VFS 203 as one of its functions.

[0029] The VFS 203 is a functional unit that constitutes a virtual file system that mediates between the application 201 and an actual file system. The VFS 203 receives a VFS call issued by the application 201.

[0030] The VFS 203 includes a VFS call processor 204 , an I / O transmitter 205 , a write area manager 206 a , and an I / O completion processor 209 .

[0031] The VFS call processor 204 is a functional unit that processes a VFS call issued by the application 201. The VFS call includes, for example, commands such as read and write.

[0032] The I / O transmitting unit 205 is a functional unit that generates a transmission command based on the VFS call processed by the VFS call processing unit 204. The I / O transmitting unit 205 transmits the generated transmission command to the storage device 105.

[0033] The write area management unit 206a is a functional unit that manages data stored in areas such as LBA (Logical Block Addressing), Stream, and Zone of the storage device 105 in segments of write, read, or data deletion units. The data indicated by the LBA and the data size of the segment may be the same. In the example shown in Fig. 2, the write area management unit 206a is illustrated as a function in the OS 202, but is not limited to this. It may also be implemented as a functional unit of an application 201 such as a database.

[0034] The I / O completion processing unit 209 is a functional unit that receives a command processing completion notification sent from the storage device 105 and notifies the application 201 of the completion of the VFS call.

[0035] The write area management unit 206a includes a read count map 207a and a bitmap 208a.

[0036] The read count map 207a is a functional unit that holds a count value of the number of times a read command is executed for a segment. The read count map 207a is referenced when data movement occurs due to garbage collection or wear leveling, and can be used to classify data based on read frequency.

[0037] The bitmap 208a is a functional section that manages valid data contained in a segment, and can be used to select an area to which data is moved during garbage collection or wear leveling.

[0038] Next, a description will be given of the functions of the storage device 105. The storage device 105 has, as its functions, a host interface unit 210, a memory conversion layer 211, a memory interface unit 212, and a non-volatile memory unit 213.

[0039] The host interface unit 210 is a functional unit that interprets the transmission command transmitted by the I / O transmission unit 205, and executes storage and acquisition of data in the non-volatile memory unit 213. After executing the contents of the transmission command, the host interface unit 210 issues a notification of completion of command processing.

[0040] The memory conversion layer 211 of the CPU 110 is a functional unit that converts between logical addresses and physical addresses.

[0041] The memory interface unit 212 is a functional unit that executes access to the non-volatile memory unit 213 based on the physical address converted by the memory conversion layer 211 .

[0042] The non-volatile memory unit 213 is a functional unit that stores data.

[0043] (Modification of Information Processing System) Here, the functional configuration of a modified example of the information processing system 101 of the embodiment will be described with reference to Fig. 3. Fig. 3 is a block diagram showing a modified example of the functional configuration of the information processing system. The information processing system 101a of this modified example includes a write area management unit 206b as a function of the CPU 110 in the storage device 105, instead of the write area management unit 206a of the VFS 203 in the host 102. In the following description, elements common to the information processing system 101 are denoted by the same reference numerals, and duplicated description will be omitted.

[0044] As shown in FIG. 3, in an information processing system 101a according to the modified embodiment, the CPU 110 of the storage device 105 includes a write area management unit 206b.

[0045] The write area management unit 206b corresponds to the write area management unit 206a in Fig. 2 and is a functional unit having common functions. The write area management unit 206b manages data stored in areas such as LBA, Stream, and Zone by segments in units of writing, reading, or data erasure.

[0046] The write area management unit 206b includes a read count map 207b and a bitmap 208b. The read count map 207b and the bitmap 208b correspond to the read count map 207a and the bitmap 208a, and have common functions.

[0047] The information processing system 101a may include both a write area management unit 206a on the VFS 203 and 206b on the CPU 110. In this case, depending on the interface (for example, PCIe) used, either the host 102 or the storage device 105 may function as the master.

[0048] An example of the functional configuration of the host memory 104 of the host 102 will be described in detail with reference to Fig. 4. Fig. 4 is a block diagram showing the configuration of the host memory 104 of the information processing system of the embodiment. The host memory 104 has an I / O command transmit queue 301, an I / O command completion queue 302, and a data buffer area 303. The functional configuration of the host memory 104 shown in Fig. 4 is an example, and the I / O command transmit queue 301 and the I / O command completion queue 302 can be implemented by hardware independent of the host memory 104.

[0049] The I / O command transmission queue 301 temporarily stores commands transmitted by the I / O transmitting unit 205. The I / O command transmission queue 301 is, for example, a memory realized by a ring buffer. The I / O command transmission queue 301 enqueues issued commands. The I / O command transmission queue 301 has entries. The entries can be managed by two variables, a head and a tail. The storage device 105 can identify the reference location of each queue based on the head pointer and the tail pointer. For example, the location of newly enqueued command information can be identified.

[0050] The I / O command completion queue 302 temporarily stores VFS call completion notifications notified by the I / O completion processing unit 209. The I / O command completion queue 302 is a memory realized by, for example, a ring buffer. The I / O command completion queue 302 enqueues the VFS completion notifications to be notified. The I / O command completion queue 302 has entries. The entries can be managed by two variables, a head and a tail. The host 102 can identify the reference location of each queue based on the head pointer and the tail pointer. For example, the location of a newly enqueued VFS completion notification can be identified.

[0051] The data buffer 303 temporarily stores data to be written to the storage device 105 and data to be read from the storage device 105 .

[0052] 5 shows a specific example of the data structure of the read count map 207a included in the write area management unit 206a. The read count map 207a is information (read frequency information) that associates a segment number 401, a read count 402, and a read flag 403. The read count map 207a may have a two-dimensional data structure. For example, the read count map 207a may have a data string of the read count 402 and a data string of the read flag 403.

[0053] Similarly, the write area management unit 206b includes a read count map 207b. The read count map 207b has a common configuration with the read count map 207a.

[0054] The segment number 401 is an entry that identifies a segment. In the example shown in Fig. 5, the segment number 401 has "1" as the top entry 404a, and "2" to "4" as the subsequent entries 404b to 404d. That is, the segment number 401 has a unique value for each entry.

[0055] The read count 402 is an entry that holds the count result of the number of times a read command is issued for each segment. In the example shown in Fig. 5, the read count 402 has values ​​of "100" for the top entry 404a, and values ​​of "2", "5", and "10" for the subsequent entries 404b to 404d.

[0056] The read flag 403 is an entry that holds the result of a determination made by the write area management unit 206a or 206b based on the data held in the column of the read count 402. In the example shown in Fig. 5, "Hot" indicating hot data is entered as the determination result in the entry 404a, and "Cold" indicating cold data is entered in the entry 404b.

[0057] In other words, the read count maps 207a, 207b, which constitute read frequency information, may include information indicating the number of times a read command was issued for each segment, and information indicating either Hot data or Cold data corresponding to the number of times the read command was issued (information indicating the read frequency).

[0058] 5, in entry 404d, read count 402 indicating the number of reads is 10. If the reference value for determining whether data is hot or cold is set to, for example, 8, the data stored in the segment of entry 404d may be determined to be Read Hot data. If entry 404d is determined to be Read Hot data and data movement occurs due to garbage collection or wear leveling, the data of the segment is stored in the storage device 105 as Read Hot data. Additionally, a "Hot" flag is stored in the read count map 207a or 207b as the entry for read flag 403 of entry 404d.

[0059] (Non-volatile memory write area) With reference to FIG. 6, the division of the write area of ​​the non-volatile memory 112 and the corresponding data attributes will be described. FIG. 6 is a diagram showing an overview of the division of the write area of ​​the non-volatile memory 112. As shown in FIG. 6, the non-volatile memory 112 is a NAND type flash memory that may include an SLC area 501 and a QLC area 504. That is, the non-volatile memory 112 may include areas with different numbers of bits written per cell. The SLC area 501 is an area of ​​the SLC method that stores one bit per cell. The QLC area as a multi-valued cell area is an area of ​​the QLC method that stores four bits per cell.

[0060] As shown in Fig. 6, the SLC area 501 can store Read Hot data 502a, which is frequently read, and Write Hot data 503, which is frequently overwritten. Writing these data to the SLC area improves write performance while there is free space in the SLC area, and also improves data read performance. On the other hand, frequent data transfer from the SLC area 501 to the QLC area 504 not only reduces I / O performance, but also speeds up the write / erase cycle of the NAND flash memory. This causes an increase in cells with a high data error rate.

[0061] 6, Write Cold data 505, which is infrequently overwritten, can be stored in the QLC area 504. The Write Cold data 505 can be further classified into Read Hot data 502b and Read Cold data 506. The Read Hot data 502b is stored in a Read Hot data storage area 507.

[0062] That is, the Read Hot data 502a and 502b related to the first segment, whose read command issuance count per segment is equal to or greater than a predetermined reference value (high read frequency), are written to cells (first cells) in the SLC area 501 (first area) and the QLC area 504 (second area). The Read Cold data 506 related to the second segment, whose read command issuance count per segment is less than a predetermined reference value (lower read frequency than the Read Hot data 502a and 502b), is written to cells (second cells) in the QLC area 504 (second area).

[0063] (Data writing and coding method selection) When writing multi-value data to one cell of a NAND flash memory, an appropriate gray coding is selected depending on the error rate during reading and the read speed. Taking the QLC method as an example, in order to guarantee the QoS of the storage device 105, it is desirable that there is no difference in the read latency of each page in the QLC method.

[0064] FIG. 7 is a diagram showing an example of bit arrangement when 4-4-3-4 coding is adopted. In FIG. 7, S0 to S15 are threshold distributions in a threshold region. The bit arrangement after writing to a cell can be expressed in 16 ways from S0 to S15 depending on the state of the threshold distribution. The 4-4-3-4 coding is a coding that distributes 15 boundaries between 16 threshold regions to 4 pages, with 4 boundaries distributed to the Lower page, 4 to the Middle page, 3 to the Upper page, and 4 to the Top page. This coding distributes the number of boundaries between pages with less bias.

[0065] As shown in Fig. 7, bits are assigned to each threshold distribution for the Top, Upper, Middle, and Lower pages. When reading data only from the Lower page, bit inversions occur between S0 and S1, S3 and S4, S5 and S6, and S10 and S11 in the threshold distribution, so at least four determinations must be made to determine the bit state.

[0066] 8 is a diagram showing an example of bit allocation when 1-4-5-5 coding is adopted. In the 1-4-5-5 coding, when distributing 15 boundaries between 16 threshold regions to four pages, one boundary is distributed to the Lower page, four to the Middle page, five to the Upper page, and five to the Top page.

[0067] For example, when data is read only from the Lower page, bit inversion occurs only between S7 and S8 of the threshold distribution, so at least one judgment is required to determine the bit state. By adopting 1-4-5-5 coding, it is possible to significantly reduce the number of judgments required to determine the bit. By writing Read Hot data 502b to the Lower page, high-speed data reading and writing is achieved. On the other hand, by writing Read Cold data 506 to the Top page, Upper page, and Middle page, the overall system performance is less susceptible to the slight increase in read time.

[0068] In addition, SLC randomization is performed on the lower pages, and TLC randomization is performed on the other pages from S0 to S7 and S8 to S15, which prevents writing from being concentrated in a specific threshold distribution and equalizes the lifespan of the NAND cells.

[0069] In the description of this embodiment, 1-4-5-5 coding has been exemplified, but the present invention is not limited to this coding, and the same effect can be achieved as long as the coding allows data to be read with one or two judgments (voltage applications).

[0070] Fig. 9 is a diagram showing an example of a threshold region when writing data in the QLC method to a NAND flash memory. In Fig. 9, "(T1)" indicates an erased state, and "(T2)" indicates a state in which QLC data has been written. The threshold distributions S0 to S15 in Fig. 9 correspond to S0 to S15 shown in Figs. 7 and 8.

[0071] By setting threshold voltages Vread1 to Vread15 between the respective distributions and determining the threshold distribution, the value written to the page is determined in conjunction with the bit allocation by the coding of Figures 7 and 8. For example, if a threshold voltage Vread8 is applied and a current flows through the bit line, it is determined that the distribution is S0 to S7, and if no current flows through the bit line, it is determined that the distribution is S8 to S15. When the 1-4-5-5 coding of Figure 8 is adopted, it becomes possible to complete the data read of the Lower page by applying the threshold voltage Vread8 once.

[0072] Fig. 10 is a diagram showing an example of a voltage waveform applied to a word line when reading data of the Lower page when using the 4-4-3-4 coding shown in Fig. 7. In Fig. 10, the time t when the storage device 105 receives the command is 0. In Fig. 10, the time from receiving the command to applying the voltage is the setup time for address transfer, etc. ("setup" in the diagram). Thereafter, threshold voltages at the boundaries where bits are inverted in the Lower page of Fig. 7 are applied in order, Vread1, Vread4, Vread6, and Vread11, to read the data.

[0073] 11 is a diagram showing an example of a voltage waveform applied to a word line when reading data of the Lower page when the 1-4-5-5 coding shown in FIG. 8 is used. In FIG. 11, the time t when the storage device 105 receives the command is also 0. After setup ("setup" in the diagram), data is read by applying a threshold voltage Vread8 that corresponds to the boundary where the bit is inverted in the Lower page of FIG. 8. That is, compared to the example shown in FIG. 10, the time for applying voltage during reading is significantly reduced, enabling high-speed reading of the Read Hot data 502b.

[0074] (Command processing operation) Next, a command processing operation of the information system of the embodiment will be described with reference to Fig. 12. Fig. 12 is a flowchart showing a command processing operation of the information system.

[0075] The application 201 issues a VFS call (S800). The VFS call may include a command request such as read, write, delete, or copy.

[0076] When the VFS call processor 204 receives a VFS call, it issues a corresponding command (S801).

[0077] The issued command is enqueued in the I / O command transmission queue 301 (S802).

[0078] The I / O transmission unit 205 notifies the storage device 105 of the command issuance (S803).

[0079] Upon receiving the notification, the host interface unit 210 accesses the I / O command transmission queue 301 and acquires the command (S804).

[0080] The host interface unit 210 interprets the received command (S805).

[0081] The host interface unit 210 acquires data write area information (S806). If the command is a read command or a delete command, the write area information is information about the area of ​​the non-volatile memory 112 where the data is written. If the command is a write command or a copy command, the write area information is included in the write destination information of the command.

[0082] The host interface unit 210 drives command processing based on the write area information (S807).

[0083] The memory conversion layer 211 converts addresses related to command processing by the host interface unit 210 (S808).

[0084] The memory interface unit 212 reads, writes, and deletes data from the non-volatile memory 112 (S809). If the command is a read command, the memory interface unit 212 transmits data to the data buffer area 303. If the command is a write command, the memory interface unit 212 obtains data from the data buffer area 303.

[0085] When the execution of the command is completed, the host interface unit 210 creates a CQE including write area information (S810).

[0086] The host interface unit 210 accesses the I / O command completion queue 302 and enqueues the CQE (S811). The host interface unit 210 notifies the I / O completion processing unit 209 of the completion of the command.

[0087] The I / O completion processing unit 209 notifies the application 201 of the completion of the VFS call based on the received notification. The application 201 can obtain the completion of command execution by checking the I / O command completion queue 302 (S812).

[0088] (Initialization operation) Next, an initialization operation of the storage device 105 will be described with reference to Fig. 13. Fig. 13 is a flowchart showing an example of the initialization operation of the storage device 105. In the initialization operation, the size of the Read Hot data storage area 507 can also be set.

[0089] The host 102 acquires a device handle of the storage device 105 (S901).

[0090] When the device handle is acquired, the host 102 generates a namespace management command including allocation information of the QLC area for Read Hot (S902).

[0091] The host 102 transmits the generated namespace management command (S903) to the storage device 105. The storage device 105, which has received the namespace management command, sets a QLC data area for Read Hot.

[0092] (Registering Read Cold data) Next, an operation of the write area management unit 206a to register Read Cold data in a garbage collection (GC) candidate segment list will be described with reference to Fig. 14. Fig. 14 is a flowchart showing an example of an operation of registering Read Cold data in a garbage collection candidate segment list.

[0093] The write area management unit 206a determines GC candidate segments based on the time when data was written to the non-volatile memory 112 and the bitmap 208a. Garbage collection has two main purposes: one is to stop I / O processing of the host 102 and perform it in the foreground to secure free space, and the other is to perform it in the background at a time when there are few I / O requests to improve the performance of the storage device 105. Segments registered in the GC candidate segment list can be used for the latter garbage collection to improve the performance of the storage device. However, they can also be used for the former garbage collection.

[0094] The write area management unit 206a creates a GC candidate segment list based on the read count map 207a. The write area management unit 206a refers to the read count map 207a and extracts segments that include static read cold data with a cold flag set (S1001).

[0095] The write area management unit 206a refers to the read count map 207a and determines that, among the segments for which the Cold flag is not set, the number of reads of which is less than a reference value, is a segment that includes dynamic Read Cold data (S1002).

[0096] The write area management unit 206a extracts segments for which a predetermined time has passed since they were written, based on the file creation time or the write time information into the non-volatile memory 112, which is included in the metadata area of ​​the storage device (S1003).

[0097] If the amount of valid data in the extracted segment is greater than a predetermined reference value (no in S1004), the process ends. If the amount of valid data in the extracted segment is less than a predetermined reference value (yes in S1004), the segment is registered in the GC candidate segment list of the Read Cold data (S1005).

[0098] The same operation is performed when a write area management unit 206b is provided instead of or in addition to the write area management unit 206a. The write area management unit 206b refers to the read count map 207b and the bitmap 208b and performs the same process.

[0099] (Read Hot Data Write Command Reception Operation) Next, an operation when the host interface 107 receives a write or copy command for Read Hot data will be described with reference to Fig. 15. Fig. 15 is a flowchart showing an example of an operation of the storage device 105 when receiving a copy command including Read Hot data.

[0100] The host interface 107 accesses the I / O command send queue 301 and receives a command including a flag indicating Read Hot data (S1101). In the example shown in Fig. 5, this corresponds to the data of segment number 1 (first segment).

[0101] The host interface 107 interprets the command and determines whether it is a copy command or not (S1102).

[0102] If the command is a copy command (yes in S1102), the memory interface 109 reads the Read Hot data from the non-volatile memory 112 based on the source information included in the command (S1103).

[0103] If the command is not a copy command (no in S1102), the host interface 107 accesses the host memory 104 and receives the Read Hot data from the host (S1104).

[0104] The CPU 110 determines whether or not the GC candidate segment of the Read Cold data (the fourth segment) is registered in the GC candidate segment list of the Read Cold data (S1105).

[0105] If the data is registered in the GC candidate segment list of the Read Cold data (yes in S1105), the memory interface 109 reads data from the GC candidate segment of the Read Cold data (S1106).

[0106] The CPU 110 creates a data block to be made nonvolatile by using the Read Hot data and the Read Cold data (S1107).

[0107] The memory interface 109 writes the data to the QLC area 504 (second area) using the unbalanced coding shown in FIG. 8 (S1108).

[0108] If the Read Cold data is not registered in the GC candidate segment list (no in S1105), the CPU 110 writes the Read Hot data to the SLC area 501 (first area) (S1109).

[0109] When the data writing is completed, the CPU 110 updates the address management map included in the memory conversion layer 211 and the read count map 207 included in the write area management unit 206 (S1110). The CPU 110 registers the address information of the newly written data, then invalidates the original data that was moved by garbage collection, and sets a flag for Hot / Cold data.

[0110] According to the information processing system 101 of the embodiment, it is not necessary to wait until the host writes the Read Cold data required to configure a block.

[0111] (Read Cold data write command reception operation) Next, an operation when the host interface 107 receives a write or copy command for Read Cold data will be described with reference to Fig. 16. Fig. 16 is a flowchart showing an example of an operation when a copy command including Read Cold data is received in a storage device.

[0112] The host interface 107 accesses the I / O command send queue 301 and receives a command including a flag indicating Read Cold data (S1201). In the example shown in Fig. 5, this corresponds to the data of segment number 2 (the second segment).

[0113] The host interface 107 interprets the command and determines whether it is a copy command or not (S1202).

[0114] If the command is a copy command (yes in S1202), the memory interface 109 reads Read Cold data from the non-volatile memory 112 based on the source information of the command (S1203).

[0115] If the command is not a copy command (no in S1202), the host interface 107 accesses the host memory 104 and receives Read Cold data from the host (S1204).

[0116] The CPU 110 determines whether data (third segment) that is Write Cold and Read Hot exists in the SLC area 501 (S1205).

[0117] If it exists (yes in S1205), the Read Hot data is read from the SLC area 501 (S1206).

[0118] The CPU 110 creates a data block to be made nonvolatile by using the Read Hot data and the Read Cold data (S1207).

[0119] The memory interface 109 writes the data to the QLC area 504 (second area) using the unbalanced coding shown in FIG. 8 (S1208).

[0120] If it does not exist (no in S1205), the Read Cold data is written to the QLC area 504 (second area) (S1209).

[0121] Once the data writing is complete, the address management map included in the memory conversion layer 211 and the read count map 207 included in the write area management unit 206 are updated (S1210), the address information of the newly written data is registered, the original data moved by garbage collection is invalidated, and a Hot / Cold flag is set.

[0122] According to the information processing system 101 of the embodiment, it is not necessary to wait until the host writes the Read Hot data required to configure a block.

[0123] (Separation behavior based on read frequency) 17, the operation of garbage collection that realizes Hot / Cold separation based on the read frequency by the CPU 110 will be described. FIG 17 is a flowchart showing an example of the operation of garbage collection in the CPU 110.

[0124] The CPU 110 refers to the read count map 207 and extracts Read Hot segments (S1301).

[0125] Furthermore, the CPU 110 extracts, from among the Read Hot segments, segments for which Hot / Cold separation has not been performed, as Read Hot GC candidate segments (S1302).

[0126] The CPU 110 determines whether or not a long time has passed since the Read Hot GC candidate segment was written, or whether or not there is little valid data (S1303).

[0127] If the condition is not met (no in S1303), the process ends. If the condition is met (yes in S1303), the CPU 110 determines whether a Read Cold GC candidate segment exists (S1304).

[0128] If it does not exist (no in S1304), the process ends. If it does exist (yes in S1304), the CPU 110 executes a garbage collection flow.

[0129] The memory interface 109 reads data from the Read Hot GC candidate segment (S1305).

[0130] Furthermore, the CPU 110 reads the Read Cold data from the Read Cold GC candidate segment (S1306).

[0131] The CPU 110 creates a data block to be made nonvolatile by using the Read Hot data and the Read Cold data (S1307).

[0132] The memory interface 109 writes the data to the QLC area 504 using the unbalanced coding shown in FIG. 8 (S1308).

[0133] Once the data writing is complete, the CPU 110 updates the address management map included in the memory conversion layer 211 and the read count map 207 included in the write area management unit 206 (S1309), registers the address information of the newly written data, invalidates the original data that was moved by garbage collection, and sets the Hot / Cold flag.

[0134] The information processing system according to the embodiment of the present invention can achieve high-speed reading without shortening the NAND write / erase cycle.

[0135] Furthermore, the storage device in the information processing system according to the embodiment of the present invention realizes Hot / Cold separation based on the read frequency in cooperation between the host and the storage device.

[0136] The information processing system according to the embodiment of the present invention can improve the average latency and throughput. The information processing system according to the embodiment has a region with a high read speed and a region with a low read speed in the same cell of a non-volatile memory.

[0137] According to the write area management unit in the embodiment of the present invention, the storage device can determine whether it is hot or cold, and achieve separation by garbage collection and wear leveling, even if the host does not explicitly specify the data read frequency.

[0138] According to the information processing system 101 of the embodiment, the hot data is arranged in an area with a small read latency. Although the hot data is written in a QLC area, it is possible to realize a read latency equivalent to that of a pseudo SLC that uses a multi-level NAND as an SLC.

[0139] According to the information processing system 101 of the embodiment, it is possible to reduce the processing time required for receiving a command and creating a data block in garbage collection that is processed in the background.

[0140] According to the information processing system 101 of the embodiment, it is possible to improve the average latency and throughput for a read command after background garbage collection is completed.

[0141] According to the information processing system 101 of the embodiment, it is possible to suppress deterioration of average latency and throughput by allocating Read Cold data to a page that employs unbalanced coding. Also, according to the information processing system 101 of the embodiment, it is possible to prevent an extreme increase in tail latency by employing 1-4-5-5 coding or the like as unbalanced coding.

[0142] Second embodiment Next, the operation of the second embodiment will be described in detail with reference to FIG. 18. FIG. 18 is a flowchart showing an example of the operation of garbage collection according to the second embodiment. In the second embodiment, garbage collection may be performed on the host side. For example, in LSF (Log Structured Filesystem), garbage collection performed on the host is called "Cleaning." Hereinafter, garbage collection processing performed on the host will be referred to as cleaning processing. In addition, in the following description, elements common to the first embodiment are denoted by common reference numerals, and duplicated description will be omitted.

[0143] The write area management unit 206a of the host 102 refers to the read count map 207a and extracts Read Hot segments (S1401).

[0144] The write area management unit 206a extracts, from among the Read Hot segments, segments for which Hot / Cold separation has not been performed, as Read Hot GC candidate segments (S1402).

[0145] The write area management unit 206a judges whether a predetermined time has passed since writing to the Read Hot GC candidate segment, and whether there is little valid data (S1403).

[0146] If the condition is not met (no in S1403), the write area management unit 206a ends the process. If the condition is met (yes in S1403), the host 102 executes the cleaning flow. The host 102 issues an I / O and reads the Read Hot GC candidate segment from the storage device 105 (S1404).

[0147] The host 102 creates a data block to be made nonvolatile from the read Read Hot data (S1405).

[0148] The host 102 sets a flag indicating Read Hot data, generates a write command for the storage device 105, and transmits the data (S1406).

[0149] The host 102 registers the address information of the newly written data accompanying the data movement, updates the address management map and the read count map 207a, and sets the Read Hot flag (S1407).

[0150] After updating the address management map, the host 102 sends a delete command for the Read Hot GC candidate segment to the storage device 105, and releases the area that was being used (S1408).

[0151] Next, the movement of Read Cold data in the cleaning process will be described with reference to Fig. 19. Fig. 19 is a flowchart showing an example of the movement operation of Read Cold data in the cleaning process according to the second embodiment.

[0152] The host 102 issues an I / O to the storage device 105 and reads out a Read Cold GC candidate segment (S1501).

[0153] The host 102 creates a data block to be made nonvolatile from the read Read Hot data (S1502).

[0154] The host 102 sets a flag indicating Read Cold data, and issues a write command to the storage device 105 to transmit the data (S1503).

[0155] The host 102 registers the address information of the newly written data accompanying the data movement, updates the address management map and the read count map 207, and sets a Read Cold flag (S1504).

[0156] After updating the address management map, the host 102 sends a delete command for the Read Cold GC candidate segment to the storage device 105, and releases the area that was being used (S1505).

[0157] According to the information processing system 101 of the embodiment, even in an information processing system using write-once storage such as Zoned Storage or in which the host takes the lead in performing GC, such as LSF, hot and cold separation of reads is possible, making it possible to improve the average read latency and throughput.

[0158] Third embodiment Next, the operation of the third embodiment will be described in detail with reference to Fig. 20. Fig. 20 is a flowchart showing an example of a Read Hot data copy operation according to the third embodiment. The third embodiment is an example in which a data copy command is implemented in an information processing system 101 in which garbage collection is performed by the host. In the following description, elements common to the first and second embodiments are denoted by common reference numerals, and duplicated descriptions will be omitted.

[0159] 20 shows the operation of moving Read Hot data by issuing a copy command. The write area management unit 206a of the host 102 refers to the read count map 207 and extracts a Read Hot segment (S1601).

[0160] Furthermore, the write area management unit 206a extracts, from among the Read Hot segments, segments for which Hot / Cold separation has not been performed, as Read Hot GC candidate segments (S1602).

[0161] The host 102 judges whether a predetermined time has passed since writing to the Read Hot GC candidate segment, and whether there is little valid data (S1603).

[0162] If the condition is not met (no in S1603), the process ends. If the condition is met (yes in S1603), the host 102 executes a cleaning flow using a copy command. The host 102 sets a flag indicating Read Hot data, generates a copy command including a bitmap of valid data in the source segment and destination segment information, and sends it to the storage device 105 (S1604).

[0163] The host 102 registers the address information of the newly written data accompanying the data movement, updates the address management map and the read count map 207, and sets the Read Hot flag (S1605).

[0164] After updating the address management map, the host 102 sends a delete command for the Read Hot GC candidate segment to the storage device 105, and releases the area that was being used (S1606).

[0165] Next, an operation of moving Read Cold data by issuing a copy command will be described with reference to Fig. 21. Fig. 21 is a flowchart showing an example of a copy operation of Read Cold data according to the third embodiment.

[0166] The host 102 sets a flag indicating Read Cold data, generates a copy command including a bitmap of valid data in the source segment and destination segment information, and transmits it to the storage device 105 (S1701).

[0167] The host 102 registers the address information of the newly written data accompanying the data movement, updates the address management map and the read count map 207, and sets a Read Cold flag (S1702).

[0168] After updating the address management map, the host 102 sends a delete command for the Read Cold GC candidate segment to the storage device 105, and releases the area that was being used (S1703).

[0169] According to the information processing system 101 of the embodiment, it is possible to reduce the amount of data transfer in I / O during GC processing, reduce the memory usage of the host, and shorten the processing time.

[0170] The embodiments are illustrative and the scope of the invention is not limited thereto. [Explanation of symbols]

[0171] 101, 101a…Information processing system 102…Host 103...Host controller 104…Host memory 105...Storage devices 106…Controller 107...Host interface 108...Buffer interface 109...Memory interface 110…CPU 111...Buffer memory 112...Non-volatile memory 201…Application 202...Operating system (OS) 203...Virtual File System (VFS) 204…VFS call processing unit 205…I / O transmission unit 206a, 206b...Writing area management section 207a, 207b…Read count map 208a, 208b...Bitmap 209...I / O completion processing section 210...host interface unit 211…Memory conversion layer 212...Memory interface unit 213...Non-volatile memory section 301...I / O command send queue 302...I / O command completion queue 303...Data buffer area 401...Column recording segment number 402…Column recording the number of reads 403…Column that records a flag indicating Read Hot or Cold 404…Read Count Map Entry 501…SLC area 502a…Read Hot data stored in the SLC area 502b…Read Hot data stored in the QLC area 503...Write Hot data stored in the SLC area 504…QLC area 505…Write Cold data stored in the QLC area 506...Read Cold data stored in the QLC area 507: Area for placing Read Hot data

Claims

1. A storage device including a non-volatile memory and a controller, The non-volatile memory includes: a first region from which data can be read by applying a voltage once or twice; a second region from which data can be read by applying a voltage three or more times; The controller: read frequency information including information indicating the number of times a read command is issued for each segment of a read request unit; The controller, based on the read frequency information, writing the first segment, the number of times of which is equal to or greater than a predetermined reference value, into the first area or the second area; writing the second segment, the number of times of which is less than a predetermined reference value, into the second area; Storage device.

2. The controller: The read frequency information is generated for each of the segments, determining whether to move a third segment stored in a third area different from the first area and the second area and having an issue count equal to or greater than a predetermined reference value to the first area or the second area, and whether to move a fourth segment stored in a fourth area different from the first area to the third area and having an issue count less than a predetermined reference value to the second area, based on the read frequency information; writing valid data of the third segment into the first area or the second area, and writing valid data of the fourth segment into the second area; The storage device according to claim 1.

3. The controller: The read frequency information included in a data write command is configured to be retained, and configured to perform garbage collection or wear leveling based on the retained read frequency information. The storage device according to claim 2.

4. The controller: The read frequency information included in the received command is interpretable, when the first segment is received, reading the fourth segment from the fourth area, writing the first segment to the first area or the second area, and writing the fourth segment to the second area; The storage device according to claim 2.

5. The controller: The read frequency information included in the received command is interpretable, when the second segment is received, reading the third segment from the third area, writing the third segment to the first area or the second area, and writing the second segment to the second area; The storage device according to claim 2.

6. The non-volatile memory includes: A first cell; a second cell; The first cell comprises: The first region and the second region are included, The second cell comprises: The second region is included in the first region and the second region, The controller: A namespace setting command including allocation information of the first cell and the second cell is received. The first cell and the second cell are configured to be allocated to the non-volatile memory based on the setting command. The storage device according to claim 1.

7. A host device connectable to the storage device according to claim 1, a module capable of generating said read frequency information; a host controller capable of transmitting a command including the read frequency information to the storage device and capable of transmitting a setting command for a namespace of the storage device; A host device comprising:

8. The host controller Transmitting a command including the read frequency information to the storage device, and causing the storage device to write valid data of the first segment to the first area.

8. The host device of claim 7.

9. The host controller Transmitting a command including the read frequency information to the storage device, and causing the storage device to write valid data of the second segment to the second area.

8. The host device of claim 7.

10. The storage device according to claim 1 ; A host device according to claim 7; An information processing system comprising:

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