Allocation control program, allocation control method, and information processing device

Abstract

To speed up parallel processing of multiple processes for sharing data.SOLUTION: A storage part 11 includes processors 21 to 24 connected to different memories, and stores speed information 13 indicating a communication speed between different two processors for a system 20 to which the processors 21 to 24 are connected via a relay device 29. A control part 12 calculates a communication load 14 between the processors 21, 23 allocated to a process group including processes 15, 16 sharing data, and changes the processor allocated to the process group among the processors 21 to 24 based on the speed information 13 and the communication load 14.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an allocation control program, an allocation control method, and an information processing device. [Background technology]

[0002] Information processing systems include parallel processing systems that use multiple processors to execute multiple processes in parallel. One type of parallel processing system is a distributed memory type parallel processing system in which multiple processors each have their own local memory. The multiple processors are connected via relay devices such as switches.

[0003] In a distributed memory parallel processing system, a processor may request data from another processor because different processes may refer to the same data. For this reason, two processors may communicate with each other and perform a data sharing process in which data is copied between the two processors. For example, one processor writes data to its local memory, and the other processor reads data from the local memory.

[0004] A resource balancing method has been proposed in which the hardware resources of an information processing system are divided into multiple logical partitions and an operating system (OS) is run in each logical partition. The proposed resource balancing method receives throughput information from the logical partitions, determines resource allocation based on the throughput information, and instructs the OS kernel of the partition to allocate resources. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2002 / 073397 Summary of the Invention [Problem to be solved by the invention]

[0006] In a distributed memory parallel processing system, the hardware performance of multiple processors is not necessarily uniform, and the speed of the communication links of relay devices is not necessarily uniform. Therefore, the communication speed may differ depending on the processor pair.

[0007] On the other hand, depending on the process group including multiple processes that share data, there may be a lot of data sharing between processors. When there are a lot of data sharing processes, the overhead of parallel processing may become large and the execution time may become long. Therefore, in one aspect, the present invention aims to speed up parallel processing of multiple processes that share data. [Means for solving the problem]

[0008] In one embodiment, there is provided an allocation control program that causes a computer to execute the following processes: For a system including a plurality of processors connected to different memories, the plurality of processors being connected via one or more relay devices, speed information indicating a communication speed between two different processors among the plurality of processors is acquired; A communication load between two or more processors among the plurality of processors that are assigned to a process group including two or more processes that share data is calculated; Two or more processors among the plurality of processors that are assigned to the process group are changed based on the speed information and the communication load.

[0009] According to another aspect, there is provided an allocation control method executed by a computer. According to another aspect, there is provided an information processing device having a storage unit and a control unit. Effect of the Invention

[0010] On the one hand, it speeds up parallel processing among multiple processes that share data. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating an information processing device according to a first embodiment. [Diagram 2] FIG. 11 illustrates an example of hardware of an information processing apparatus according to a second embodiment. [Diagram 3] FIG. 2 is a block diagram showing an example of hardware of a CPU connection network. [Figure 4] FIG. 2 is a diagram illustrating an example of a process executed by a CPU. [Diagram 5] FIG. 11 illustrates a first example of CPU allocation to workloads. [Figure 6] FIG. 13 is a diagram illustrating an example of a table included in the management panel. [Figure 7] FIG. 11 illustrates a second example of CPU to workload allocation. [Figure 8] FIG. 13 illustrates a third example of allocation of CPUs to workloads. [Figure 9] FIG. 13 illustrates a fourth example of allocation of CPUs to workloads. [Figure 10] FIG. 13 illustrates a fifth example of allocation of CPUs to workloads. [Figure 11] FIG. 2 is a block diagram showing an example of functions of the information processing device; [Figure 12] 13 is a flowchart illustrating an example of a CPU allocation procedure. [Figure 13] 13 is a flowchart showing an example of a procedure for CPU allocation (continuation). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the present embodiment will be described with reference to the drawings. [First embodiment] A first embodiment will be described.

[0013] FIG. 1 is a diagram illustrating an information processing apparatus according to a first embodiment. The information processing device 10 of the first embodiment controls parallel processing using a system 20. The system 20 may be external to the information processing device 10 or may be included in the information processing device 10. The system 20 may be called a parallel processing system. The information processing device 10 may be a client device or a server device. The information processing device 10 may be called a computer, a scheduler, or an allocation control device.

[0014] The information processing device 10 includes a storage unit 11 and a control unit 12. The storage unit 11 may be a volatile semiconductor memory such as a random access memory (RAM), or may be a non-volatile storage such as a hard disk drive (HDD) or a flash memory.

[0015] The control unit 12 is, for example, a processor such as a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP). However, the control unit 12 may include an electronic circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The processor executes a program stored in a memory such as a RAM (which may be the storage unit 11). A collection of processors may be called a multiprocessor or simply a "processor."

[0016] The system 20 is a parallel processing system in which each processor has a local memory. The system 20 has processors 21, 22, 23, 24, memories 25, 26, 27, 28, and a relay device 29. The processors 21, 22, 23, 24 are, for example, CPUs. The memories 25, 26, 27, 28 are, for example, RAMs. The processor 21 is connected to the memory 25. The processor 22 is connected to the memory 26. The processor 23 is connected to the memory 27. The processor 24 is connected to the memory 28.

[0017] The relay device 29 connects the processors 21, 22, 23, and 24. The relay device 29 may be a switch that transfers data between a source processor and a specified destination processor. The system 20 may have two or more relay devices connected to each other by a communication link. In that case, each of the processors 21, 22, 23, and 24 is connected to one of the two or more relay devices.

[0018] In the system 20, a Compute Express Link (CXL) may be used for connections between processors and local memories and between processors. The relay device 29 may be called a CXL switch. CXL is a bus interface standard used for communication between a CPU and memory and between a CPU and peripheral devices. CXL is implemented on a Peripheral Component Interconnect Express (PCIe). CXL is sometimes used in high-performance computers such as data center computers.

[0019] The system 20 may be a heterogeneous system in which the hardware capabilities or topology are not uniform. Thus, the processors 21, 22, 23, and 24 may have different hardware capabilities. The hardware capabilities may include the clock frequency for executing instructions, the size and speed of cache memory, the speed of the memory bus between the processors and the local memory, etc.

[0020] Furthermore, relay device 29 may have communication ports with different communication performance. Furthermore, when system 20 has two or more relay devices, the communication performance of the communication ports may differ depending on the relay device. Furthermore, when system 20 has two or more relay devices, the number of relay devices through which communication passes may differ depending on the pair of processors communicating.

[0021] Therefore, in the system 20, the communication speed may differ depending on the pair of communicating processors. For example, the communication speed between the processors 21 and 22 may differ from the communication speed between the processors 23 and 24. The communication speed between the processors is affected by the lowest communication performance among the communication performance determined by the hardware performance of one processor, the communication performance determined by the hardware performance of the other processor, and the communication performance of the communication link via which the communication is carried out.

[0022] While parallel processing using the system 20 is being performed, the topology of the system 20 may change dynamically. A new processor and memory pair may be added to the system 20. A new relay device may be added to the system 20. An existing processor and memory pair may be removed from the system 20. An existing relay device may be removed from the system 20.

[0023] Processors 21, 22, 23, and 24 can execute processes in parallel. In the first embodiment, a process group including processes 15 and 16 is executed in system 20. Processes 15 and 16 share data and may refer to common data. Processors 21 and 23 are assigned to this process group. Processor 21 executes process 15, and processor 23 executes process 16.

[0024] A process group is a collection of processes that belong to the same application. A process group is sometimes called a job or a workload. The processes in a process group may be started by the same program. The processes may share data.

[0025] In principle, each processor processes information using data stored in its own local memory. However, a process may refer to data held by other processes in the same process group. Therefore, a processor may request data stored in the local memory of another processor assigned to the same process group. Therefore, two processors assigned to the same process group may communicate with each other via relay device 29 to copy data.

[0026] The above inter-processor communication is sometimes called a data sharing operation. For example, the processor 21 writes data to the memory 25 connected to the processor 21. The processor 23 reads the data written to the memory 25. The processor 23 accesses the memory 25 via, for example, a memory controller included in the processor 21. The address of the memory area where the data is written is shared by the processes 15 and 16 through communication between the processes 15 and 16. The address may be shared before or after the data is written.

[0027] The storage unit 11 stores speed information 13 for the system 20. The speed information 13 indicates a communication speed between two different processors among a plurality of processors included in the system 20. For example, the speed information 13 indicates the communication speed between processors 21 and 22, the communication speed between processors 21 and 23, the communication speed between processors 21 and 24, the communication speed between processors 22 and 23, the communication speed between processors 22 and 24, and the communication speed between processors 23 and 24.

[0028] The communication speed indicated by the speed information 13 may be the execution speed of the above-mentioned data sharing process, or may indicate the number of times the data sharing process can be executed per unit time (for example, per second). The control unit 12 may acquire the speed information 13 from outside the information processing device 10. The control unit 12 may also measure the communication speed between the processors by having the processors 21, 22, 23, and 24 execute a certain information process such as a data sharing process. In this case, the control unit 12 may measure the communication speed periodically. The control unit 12 may also measure the communication speed when the topology of the system 20 changes.

[0029] The control unit 12 calculates the communication load 14 between the processors 21, 23 assigned to the process group. The communication load 14 may be the number of executions of the data sharing process within a certain period of time. The communication load 14 may also be the average execution number obtained by dividing the number of executions of the data sharing process within a certain period of time by the number of processors assigned to the process group.

[0030] The control unit 12 may periodically calculate the communication load 14. The control unit 12 may also periodically receive information on the communication load 14 from a representative processor of the processors 21, 23 assigned to the process group. When two or more process groups are running, the control unit 12 may calculate the communication load 14 for each process group.

[0031] Then, the control unit 12 changes which of the processors 21, 22, 23, and 24 in the system 20 are assigned to the process group based on the speed information 13 and the communication load 14. It is preferable that the control unit 12 assigns a combination of processors having a higher communication speed to the process group as the communication load 14 increases. However, the control unit 12 may not change the number of processors assigned to the process group.

[0032] For example, when the communication load 14 exceeds a threshold, the control unit 12 may assign a processor pair whose communication speed exceeds a threshold to a process group. Also, when the communication load 14 exceeds a threshold, the control unit 12 may preferentially assign a processor pair whose communication speed is high to a process group. When the communication load 14 does not exceed a threshold, the control unit 12 may randomly assign free processors to process groups.

[0033] Furthermore, when multiple process groups are running, the control unit 12 may preferentially assign a processor pair whose communication speed exceeds a threshold to a process group with a high communication load 14. Furthermore, the control unit 12 may preferentially assign a processor pair whose communication speed is high to a process group with a high communication load 14. As an example, when the communication speed between the processors 23 and 24 is the highest, the control unit 12 changes the processors to be assigned to the above process group from the processors 21 and 23 to the processors 23 and 24.

[0034] As described above, the information processing device 10 of the first embodiment acquires speed information 13 indicating the communication speed between two different processors for a system 20 including a plurality of processors connected to different memories. The information processing device 10 calculates a communication load 14 between two or more processors assigned to a process group including two or more processes that share data. Then, the information processing device 10 changes the processor to be assigned to the process group based on the speed information 13 and the communication load 14.

[0035] This allows the information processing device 10 to assign a combination of processors with high communication speeds to a process group with a lot of inter-processor communication. This reduces communication overhead for multiple processes that share data, and speeds up parallel processing. In addition, the information processing device 10 can optimize processor allocation in response to changes in the topology of the system 20, increases and decreases in process groups, changes in communication load 14, and the like.

[0036] When the communication load 14 of a process group is higher than that of other process groups, the information processing device 10 may preferentially assign a pair of processors having a high communication speed to the process group. This enables the information processing device 10 to reduce a decrease in efficiency of parallel processing due to inter-processor communication.

[0037] The communication speed indicated by the speed information 13 may be the execution speed of a data sharing process. The data sharing process may be a process in which one processor writes data to a memory connected to the one processor, and the other processor reads data from the memory. This allows the relationship between the execution efficiency of a process group that shares data and the processors to be assigned to the process group to be evaluated with high accuracy.

[0038] The communication load 14 may be an average execution count calculated by dividing the number of executions of the data sharing process within a certain period of time by the number of processors assigned to the process group. This allows for accurate evaluation of the relationship between the execution efficiency of the process group that shares data and the processors assigned to the process group.

[0039] Furthermore, when there is an available processor in the system 20, the information processing device 10 may add the available processor to a process group to which a processor having the highest communication speed with the available processor is assigned. This makes it possible to utilize the communication performance of the available processor and to shorten the execution time of a process group with a high communication load 14.

[0040] [Second embodiment] Next, a second embodiment will be described. FIG. 2 illustrates an example of hardware of an information processing apparatus according to the second embodiment.

[0041] The information processing device 100 of the second embodiment executes parallel processing using multiple CPUs. The information processing device 100 may be a client device or a server device. The information processing device 100 may be called a computer or a parallel processing device. The information processing device 100 corresponds to the information processing device 10 of the first embodiment.

[0042] The information processing device 100 has multiple CPUs including a CPU 101 , multiple memories including a memory 102 , a storage device 111 , a GPU 112 , an input interface 113 , a media reader 114 , and a communication interface 115 .

[0043] The CPU 101 is a processor that executes program instructions. The CPU 101 loads the programs and data stored in the storage device 111 into the memory 102 and executes the programs. The memory 102 is a volatile semiconductor memory that temporarily stores the programs executed by the CPU 101 and data used by the CPU 101 for calculations. The memory 102 is, for example, a RAM. However, the information processing device 100 may have a type of volatile memory other than a RAM.

[0044] The storage device 111 is a non-volatile storage that stores software programs and other data. The software includes an OS, firmware, middleware, application software, etc. The storage device 111 is, for example, an HDD or an SSD (Solid State Drive).

[0045] The GPU 112 performs image processing in cooperation with the CPU 101, and outputs an image to a display device 116 connected to the information processing device 100. The display device 116 is, for example, a CRT (Cathode Ray Tube) display, a liquid crystal display, an organic EL (Electro Luminescence) display, or a projector. Other types of output devices, such as a printer, may be connected to the information processing device 100.

[0046] The GPU 112 may be used as a general purpose computing on graphics processing unit (GPGPU). The GPU 112 may execute a program in response to an instruction from the CPU 101. The information processing device 100 may include a volatile semiconductor memory other than the memory 102 as a GPU memory.

[0047] The input interface 113 receives an input signal from an input device 117 connected to the information processing device 100. The input device 117 is, for example, a mouse, a touch panel, or a keyboard. A plurality of input devices may be connected to the information processing device 100.

[0048] The medium reader 114 is a reading device that reads the program and data recorded on the recording medium 118. The recording medium 118 is, for example, a magnetic disk, an optical disk, or a semiconductor memory. The magnetic disk includes a flexible disk (FD) and a HDD. The optical disk includes a compact disc (CD) and a digital versatile disc (DVD). The medium reader 114 copies the program and data read from the recording medium 118 to another recording medium such as the memory 102 or the storage device 111. The read program may be executed by the CPU 101.

[0049] The recording medium 118 may be a portable recording medium. The recording medium 118 may be used to distribute programs and data. The recording medium 118 and the storage device 111 may also be referred to as computer-readable recording media.

[0050] The communication interface 115 is connected to a network 119 and communicates with other information processing devices via the network 119. The communication interface 115 may be a wired communication interface that is connected to a wired communication device such as a router via a cable. The communication interface 115 may also be a wireless communication interface that is connected to a wireless communication device such as a base station or an access point.

[0051] FIG. 3 is a block diagram showing an example of hardware of a CPU connection network. The multiple CPUs and multiple memories of the information processing device 100 are connected according to CXL. As an example, the information processing device 100 has CPUs 101a, 101b, 101c, 101d, 101e, 101f, 101g, 101h, 101i, 101j, 101k, and 101l. The information processing device 100 also has memories 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h, 102i, 102j, 102k, and 102l. The information processing device 100 also has switches 103a, 103b, and 103c. The switches 103a, 103b, and 103c are CXL switches that transfer data from a source CPU to a destination CPU.

[0052] The CPUs 101a, 101b, 101c, and 101d correspond to the processors 21, 22, 23, and 24 in the first embodiment. The memories 102a, 102b, 102c, and 102d correspond to the memories 25, 26, 27, and 28 in the first embodiment. The switch 103a corresponds to the relay device 29 in the first embodiment.

[0053] CPU 101a is connected to memory 102a. CPU 101b is connected to memory 102b. CPU 101c is connected to memory 102c. CPU 101d is connected to memory 102d. CPU 101e is connected to memory 102e. CPU 101f is connected to memory 102f. CPU 101g is connected to memory 102g. CPU 101h is connected to memory 102h. CPU 101i is connected to memory 102i. CPU 101j is connected to memory 102j. CPU 101k is connected to memory 102k. CPU 101l is connected to memory 102l.

[0054] The switches 103a, 103b, and 103c are connected to each other via a communication link. The CPUs 101a, 101b, 101c, and 101d are connected to the switch 103a. The CPUs 101e, 101f, 101g, and 101h are connected to the switch 103b. The CPUs 101i, 101j, 101k, and 101l are connected to the switch 103c. Thus, two CPUs can communicate via one or two switches.

[0055] FIG. 4 illustrates an example of a process executed by the CPU. As an example, the CPU 101l executes an administration panel (administrator panel) 121 and a scheduler 122. The CPU 101a executes a process 123a. The CPU 101b executes a process 123b. The CPU 101g executes a process 123c. The CPU 101h executes a process 123d. The CPU 101i executes a process 123e.

[0056] Processes 123a and 123b belong to the same workload. Processes 123c, 123d, and 123e belong to the same workload. A workload in the second embodiment is a set of processes started for the same application. A workload corresponds to a process group in the first embodiment, and may be called a job.

[0057] Processes belonging to the same workload may share data and may refer to common data during parallel processing. Thus, two CPUs assigned to the same workload may perform data-sharing operations, in which one CPU generates and stores data that the other CPU reads.

[0058] For example, the CPU 101a writes data to the memory 102a. The CPU 101b reads the data from the memory 102a via the memory controller of the CPU 101a according to the memory address shared between the CPUs 101a and 101b. In this case, the CPUs 101a and 101b communicate with each other via the switch 103a.

[0059] The CPU system of the information processing device 100 is a heterogeneous system in which the speed of data sharing processing differs depending on the pair of CPUs. The speed of the data sharing processing is expressed, for example, by the number of times the data sharing processing can be executed per second. The speed of the data sharing processing depends on the hardware performance of the two CPUs. The speed of the data sharing processing also depends on the communication performance of the switch connecting the two CPUs.

[0060] Typically, the speed of data sharing processing between two CPUs is the smallest of the achievable speed of one CPU, the achievable speed of the other CPU, and the achievable speed of the switch on the path between the two CPUs. For example, the speed between switches 103a and 103b is 70 times per second. The speed between switches 103a and 103c is 60 times per second. The speed between switches 103b and 103c is 80 times per second.

[0061] The management panel 121 is a control module that collects information indicating the execution status of each workload and determines the allocation of processors to each workload. The management panel 121 is included in, for example, the firmware or device driver of CXL. A representative CPU that executes a representative process is determined for each workload. The management panel 121 periodically receives information from the representative CPU of each workload.

[0062] The scheduler 122 is a control module that performs scheduling according to the CPU allocation determined by the management panel 121 and causes the CPU of the information processing device 100 to execute a process. The scheduler 122 is included in, for example, an OS or a device driver.

[0063] The management panel 121 and the scheduler 122 are executed by a specific CPU that is not assigned to any workload. However, the management panel 121 and the scheduler 122 may be executed by different CPUs. The CPU 101l corresponds to the control unit 12 in the first embodiment. The memory 102l corresponds to the storage unit 11 in the first embodiment.

[0064] As described above, in the information processing device 100, the speed of data sharing processing differs depending on the CPU pair. Meanwhile, the frequency of data sharing processing differs depending on the workload. Furthermore, during operation of the information processing device 100, the topology of the CPU system may change due to the addition of a new CPU or a new switch. Furthermore, the frequency of data sharing processing of a certain workload may change during execution of the workload.

[0065] Therefore, the information processing device 100 dynamically changes the allocation of CPUs to workloads in order to efficiently utilize the multiple CPUs possessed by the information processing device 100. Each time the topology of the CPU system changes, the information processing device 100 executes a speed test to measure the speed of data sharing processing between the CPUs. In addition, the information processing device 100 periodically collects information indicating the frequency of data sharing processing from each workload. The information processing device 100 determines CPU allocation such that a combination of CPUs with higher speeds is assigned to a workload with a higher frequency of data sharing processing.

[0066] FIG. 5 is a diagram illustrating a first example of allocation of CPUs to workloads. As an example, the information processing device 100 includes CPUs 104a, 104b, 104c, and 104d and switches 106a and 106b. The CPUs 104a and 104b are connected to the switch 106a. The CPUs 104c and 104d are connected to the switch 106b. The switches 106a and 106b are connected to each other via a communication link.

[0067] Regarding data sharing processing, the maximum speed of CPU 104a is 100 times per second. The maximum speed of CPU 104b is 105 times per second. The maximum speed of CPU 104c is 130 times per second. The maximum speed of CPU 104d is 135 times per second. The communication speed between switches 106a and 106b is equivalent to 50 times per second.

[0068] Therefore, the speed between CPUs 104a and 104b is 100 times per second. The speed between CPUs 104a and 104c is 50 times per second because they cross switches 106a and 106b. The speed between CPUs 104a and 104d is 50 times per second. The speed between CPUs 104b and 104c is 50 times per second. The speed between CPUs 104b and 104d is 50 times per second. The speed between CPUs 104c and 104d is 130 times per second.

[0069] These CPUs are executing workloads 1 and 2. CPUs 104a and 104d are assigned to workload 1. The representative CPU for workload 1 is CPU 104a. CPUs 104b and 104c are assigned to workload 2. The representative CPU for workload 2 is CPU 104b.

[0070] The management panel 121 receives a data share value for workload 1 from CPU 104a. The management panel 121 also receives a data share value for workload 2 from CPU 104b. The data share value indicates the frequency of data share processing in the most recent fixed period. The data share value is the average number of data shares obtained by dividing the number of data share processes executed within a workload in a fixed period by the number of CPUs assigned to the workload.

[0071] For example, suppose a workload is assigned three CPUs, 12 data sharing operations are performed between the first and second CPUs, 1 data sharing operation is performed between the first and third CPUs, and 2 data sharing operations are performed between the second and third CPUs, then the data sharing value is (12+1+2)÷3=5.

[0072] Here, the number of data share processes for workload 1 is 10, and the data share value is 10÷2=5. Additionally, the number of data share processes for workload 2 is 16, and the data share value is 16÷2=8. Therefore, workload 2 has a larger data share value than workload 1. Note that each workload may notify the management panel 121 of the number of data share processes, and the management panel 121 may calculate the data share value.

[0073] The management panel 121 sorts the workloads in descending order of data sharing value. The management panel 121 also sorts the CPU pairs in descending order of data sharing processing speed. The management panel 121 assigns the same number of CPUs as before the change, starting with the workload with the highest data sharing value. At this time, the management panel 121 selects a combination of CPUs with high speeds from a set of free CPUs whose assignment destination workloads have not been determined.

[0074] Here, the management panel 121 first selects workload 2 with the largest data sharing value. The management panel 121 selects CPUs 104c and 104d, which are the CPU pair with the largest speed, and assigns CPUs 104c and 104d to workload 2. Since the number of CPUs in workload 2 before the change was 2, CPU assignment to workload 2 is completed.

[0075] Next, the management panel 121 selects workload 1, which has the next largest data sharing value. From the CPU pair, both of which are free CPUs, the management panel 121 selects CPUs 104a and 104b, which have the fastest speed, and assigns CPUs 104a and 104b to workload 1. Since the number of CPUs in workload 1 before the change was 2, the CPU assignment to workload 1 is terminated. As a result, CPUs 104a and 104b are assigned to workload 1, and CPUs 104c and 104d are assigned to workload 2.

[0076] With regard to data sharing processing, the minimum speed of workload 1 before the change was 50 times per second. In contrast, the minimum speed of workload 1 after the change was 100 times per second. Furthermore, the minimum speed of workload 2 before the change was 50 times per second. In contrast, the minimum speed of workload 2 after the change was 130 times per second. Thus, the change in CPU allocation has increased the speed of data sharing processing for both workloads 1 and 2. Furthermore, workload 2, which performs data sharing processing more frequently, is faster than workload 1.

[0077] FIG. 6 is a diagram showing an example of a table included in the management panel. To perform the above CPU allocation, the management panel 121 generates a CPU speed table 124 , a workload table 125 and a CPU pair list 126 .

[0078] The CPU speed table 124 indicates the number of executable data sharing processes per unit time for each pair of CPUs. In the second embodiment, the data sharing process is symmetric. It is assumed that the speed at which one CPU refers to the data of the other CPU is equal to the speed at which the other CPU refers to the data of the one CPU. Therefore, when the information processing device 100 has n CPUs, the CPU speed table 124 indicates n(n-1) / 2 different speeds.

[0079] The workload table 125 associates a workload ID, a data share value, and the number of CPUs. The workload ID is an identifier for identifying a workload. The data share value indicates the frequency of data share processing performed within a workload in a recent fixed period of time. The number of CPUs is the number of CPUs assigned to a workload. In the workload table 125, multiple workload IDs are sorted in descending order of data share value.

[0080] The CPU pair list 126 is generated from the CPU speed table 124. The CPU pair list 126 associates a CPU pair with a speed. In the CPU pair list 126, a plurality of CPU pairs are sorted in descending order of speed.

[0081] Next, another example of CPU allocation will be described. FIG. 7 illustrates a second example of CPU allocation to workloads. As an example, the information processing device 100 includes CPUs 105a, 105b, 105c, 105d, 105e, 105f, 105g, 105h, 105i, 105j, 105k, and 105l, and switches 106a and 106b. The CPUs 105a, 105b, 105c, 105d, 105e, and 105f are connected to the switch 106a. The CPUs 105g, 105h, 105i, 105j, 105k, and 105l are connected to the switch 106b. The switches 106a and 106b are connected by a communication link.

[0082] For data sharing processing, the maximum speed of CPU 105a is 100 times per second. The maximum speed of CPU 105b is 105 times per second. The maximum speed of CPU 105c is 110 times per second. The maximum speed of CPU 105d is 115 times per second. The maximum speed of CPU 105e is 120 times per second. The maximum speed of CPU 105f is 125 times per second.

[0083] The maximum speed of CPU 105g is 130 times per second. The maximum speed of CPU 105h is 135 times per second. The maximum speed of CPU 105i is 140 times per second. The maximum speed of CPU 105j is 145 times per second. The maximum speed of CPU 105k is 150 times per second. The maximum speed of CPU 105l is 155 times per second.

[0084] Workloads 1, 2, and 3 are being executed on these CPUs. CPUs 105b, 105c, and 105g are assigned to workload 1. The representative CPU for workload 1 is CPU 105c. CPUs 105a, 105i, 105j, 105k, and 105l are assigned to workload 2. The representative CPU for workload 2 is CPU 105a. CPUs 105d, 105e, 105f, and 105h are assigned to workload 3. The representative CPU for workload 3 is CPU 105e.

[0085] The management panel 121 receives a data share value for workload 1 from CPU 105c. The data share value for workload 1 is 5. The management panel 121 also receives a data share value for workload 2 from CPU 105a. The data share value for workload 2 is 8. The management panel 121 also receives a data share value for workload 3 from CPU 105e. The data share value for workload 3 is 2.

[0086] FIG. 8 is a diagram illustrating a third example of allocation of CPUs to workloads. The management panel 121 first selects workload 2, which has the largest data sharing value. The management panel 121 selects CPUs 105k and 105l, which are the CPU pair with the largest speed, and assigns CPUs 105k and 105l to workload 2. From among the free CPUs, the management panel 121 selects CPU 105j, which has the largest speed compared to the CPU already assigned to workload 2, and assigns CPU 105j to workload 2. In the same manner, the management panel 121 assigns CPUs 105h and 105i to workload 2. As a result, the same five CPUs as before the change are assigned to workload 2.

[0087] Next, the management panel 121 selects workload 1 with the next largest data sharing value. From the CPU pair, both of which are free CPUs, the management panel 121 selects CPUs 105e and 105f, which have the highest speed, and assigns CPUs 105e and 105f to workload 1. From the free CPUs, the management panel 121 selects CPU 105d, which has the highest speed compared to the CPU already assigned to workload 1, and assigns CPU 105d to workload 1. As a result, the same three CPUs as before the change are assigned to workload 1.

[0088] Next, the management panel 121 selects workload 3, which has the next largest data sharing value. From the CPU pair, both of which are free CPUs, the management panel 121 selects CPUs 105b and 105c, which have the fastest speed, and assigns CPUs 105b and 105c to workload 3. From the free CPUs, the management panel 121 selects CPU 105a, which has the fastest speed compared to the CPUs already assigned to workload 3, and assigns CPU 105a to workload 3. In a similar manner, the management panel 121 assigns CPU 105g to workload 3. As a result, the same four CPUs as before the change are assigned to workload 3.

[0089] With regard to data sharing processing, the minimum speed of workload 1 before the change was 50 times per second. In contrast, the minimum speed of workload 1 after the change was 115 times per second. Furthermore, the minimum speed of workload 2 before the change was 50 times per second. In contrast, the minimum speed of workload 2 after the change was 135 times per second. The minimum speed of workload 3 was 50 times per second both before and after the change. Thus, the change in CPU allocation has increased the speed of data sharing processing for workloads 1 and 2. Furthermore, workload 2, which performs data sharing processing more frequently, is faster than workload 1.

[0090] Next, yet another example of CPU allocation will be described. FIG. 9 is a diagram illustrating a fourth example of allocation of CPUs to workloads. Here, a CPU 105m is dynamically added, changing the topology from the CPU allocation state shown in Fig. 8. The CPU 105m is connected to the switch 106a. The maximum speed of the CPU 105m is 160 times per second.

[0091] The representative CPU for workload 1 is CPU 105e. The representative CPU for workload 2 is CPU 105k. The representative CPU for workload 3 is CPU 105a. The management panel 121 receives the data share value for workload 1 from CPU 105e. In addition, the management panel 121 receives the data share value for workload 2 from CPU 105k. In addition, the management panel 121 receives the data share value for workload 3 from CPU 105a. These data share values ​​are unchanged from FIG. 7.

[0092] FIG. 10 is a diagram illustrating a fifth example of allocation of CPUs to workloads. The management panel 121 first selects the workload 2 having the largest data sharing value. The management panel 121 assigns the CPUs 105h, 105i, 105j, 105k, and 105l to the workload 2 according to the procedure described with reference to FIG.

[0093] Next, the management panel 121 selects workload 1, which has the next largest data sharing value. From the CPU pair, both of which are free CPUs, the management panel 121 selects CPUs 105f and 105m, which have the fastest speed, and assigns CPUs 105f and 105m to workload 1. The management panel 121 selects CPU 105e, which has the fastest speed compared to the CPUs already assigned to workload 1, and assigns CPU 105e to workload 1.

[0094] Next, the management panel 121 selects workload 3. From the CPU pair in which both CPUs are free, the management panel 121 selects the CPUs 105c and 105d, which have the fastest speed, and assigns the CPUs 105c and 105d to workload 3. In a similar manner, the management panel 121 assigns the CPUs 105a and 105b to workload 3.

[0095] If the same number of CPUs as before the change were assigned to workloads 1, 2, and 3, CPU 105g would remain free. From the viewpoint of CPU usage efficiency, it is preferable that each CPU is used by one of the workloads. Therefore, the management panel 121 assigns the remaining free CPU to the same workload as the other CPU with a higher speed than the free CPU.

[0096] Here, the CPUs with the highest speeds relative to CPU 105g are CPUs 105h, 105i, 105j, 105k, and 105l. CPUs 105h, 105i, 105j, 105k, and 105l are assigned to workload 2. Therefore, management panel 121 additionally assigns CPU 105g to workload 2. This utilizes the performance of the data sharing process of CPU 105g. Note that workload 2 with an increased number of CPUs may increase the number of processes executed in parallel. The behavior of a workload when the number of CPUs is increased depends on the application.

[0097] Next, the functions and processing procedures of the information processing device 100 will be described. FIG. 11 is a block diagram illustrating an example of functions of the information processing device. The information processing device 100 includes a topology storage unit 131, a workload storage unit 132, an information collection unit 133, an optimization unit 134, and a scheduler 135. The topology storage unit 131 and the workload storage unit 132 are implemented, for example, using the memory 102l or the storage device 111. The information collection unit 133, the optimization unit 134, and the scheduler 135 are implemented, for example, using the CPU 101l and a program.

[0098] The topology storage unit 131 stores speed information indicating the speed of data sharing processing measured between a CPU pair. For example, the above-mentioned CPU speed table 124 is stored in the topology storage unit 131. The workload storage unit 132 stores load information indicating the execution status of the data sharing processing of each of a plurality of workloads. For example, the above-mentioned workload table 125 is stored in the workload storage unit 132.

[0099] The information collector 133 generates speed information and stores it in the topology storage unit 131. The information collector 133 also generates load information and stores it in the workload storage unit 132. Regarding the speed information, the information collector 133 monitors the topology of the CPU system. When the topology changes, the information collector 133 causes some or all of the CPU pairs to execute data sharing processing and measures the speed of the data sharing processing. Regarding the load information, the information collector 133 periodically receives a data sharing value from the representative CPU of each workload.

[0100] The optimization unit 134 determines a CPU to be allocated to each workload based on the speed information stored in the topology storage unit 131 and the load information stored in the workload storage unit 132. The optimization unit 134 monitors the data share value of each workload, and changes the CPU allocation when a change in the data share value occurs. The optimization unit 134 may change the CPU allocation when a topology change occurs, such as the addition of a CPU or a switch. The optimization unit 134 notifies the scheduler 135 of the determined CPU allocation.

[0101] The scheduler 135 schedules multiple processes to be executed in parallel on multiple CPUs according to the CPU allocation notified by the optimization unit 134. The scheduler 135 distributes multiple processes included in a workload to the multiple CPUs allocated to the workload. When a new workload is started, the scheduler 135 allocates free CPUs to the new workload. When there is a shortage of free CPUs, the scheduler 135 may secure free CPUs by reducing the CPUs of existing workloads.

[0102] When changing the CPU that executes a certain process, for example, scheduler 135 saves data in the local memory of the CPU before the change to the shared memory or storage device 111. Scheduler 135 loads the saved data into the local memory of the CPU after the change.

[0103] The information processing device 100 may output information on the optimized CPU allocation. The information processing device 100 may store the information on the CPU allocation in the storage device 111, may display the information on the display device 116, or may transmit the information to another information processing device.

[0104] FIG. 12 is a flowchart showing an example of a CPU allocation procedure. For example, the process of FIG. 12 is executed periodically. (S10) The information collection unit 133 checks the topology of the CPU system.

[0105] (S11) The information collecting unit 133 compares the previous topology and determines whether a new switch has been added. If a new switch has been added, the process proceeds to step S12. If no switch has been added, the process proceeds to step S13.

[0106] (S12) The information collection unit 133 comprehensively executes speed tests between all CPU pairs, and updates the measured speed values ​​of all CPU pairs. Then, the process proceeds to step S15. (S13) The information collection unit 133 compares the topology with the previous topology and determines whether a new CPU has been added. If a new CPU has been added, the process proceeds to step S14. If no CPU has been added, the process proceeds to step S15.

[0107] (S14) The information collection unit 133 executes a speed test between the new CPU and each of the other CPUs, and updates the measured speed value of the corresponding CPU pair. At this time, the information collection unit 133 does not need to execute a speed test between existing CPU pairs.

[0108] (S15) The information collection unit 133 receives a data share value from the representative CPU of each workload. The received data share value is a numerical value obtained by dividing the number of data share processes executed within the workload in the most recent fixed period by the number of CPUs used by the workload. The information collection unit 133 may calculate the data share value from the number of data share processes.

[0109] (S16) The optimization unit 134 determines whether there is any workload whose data share value has changed since the previous time. If the data share value of at least one workload has changed, the process proceeds to step S17. If the data share value of none of the workloads has changed, the optimization unit 134 ends the current CPU allocation process and waits for the next execution time.

[0110] (S17) The optimization unit 134 sorts the CPU pairs in descending order of speed. (S18) The optimization unit 134 calculates the number of CPUs for each workload. The number of CPUs is the number of CPUs currently being used by the workload.

[0111] (S19) The optimization unit 134 sorts the workloads in descending order of data sharing value. FIG. 13 is a flowchart (continuation) illustrating an example of a procedure for CPU allocation. (S20) The optimization unit 134 determines whether a CPU has been assigned to all the workloads. If a CPU has been assigned to all the workloads, the process proceeds to step S28. If there is a workload to which a CPU has not been assigned, the process proceeds to step S21.

[0112] (S21) The optimization unit 134 selects the workload with the largest data sharing value from among the workloads to which a CPU has not yet been assigned. (S22) The optimization unit 134 selects a CPU pair with the highest speed from among free CPU pairs in which both CPUs are not assigned to any workload. The optimization unit 134 assigns the two CPUs included in the selected CPU pair to a workload of interest.

[0113] (S23) The optimization unit 134 determines whether the number of CPUs assigned to the workload of interest has reached the number of CPUs of the workload. If the assigned number has reached the number of CPUs, the process returns to step S20; otherwise, the process proceeds to step S24.

[0114] (S24) The optimization unit 134 selects a CPU pair having the second highest speed after the CPU pair already selected for the workload of interest. (S25) The optimization unit 134 determines whether one of the CPUs in the CPU pair selected in step S24 is assigned to the workload of interest. If one of the CPUs is assigned to the workload, the process proceeds to step S26; otherwise, the process returns to step S23.

[0115] (S26) The optimization unit 134 determines whether the other CPU included in the CPU pair selected in step S24 is assigned to a workload other than the workload of interest. If the other CPU is assigned to a workload other than the workload of interest, the process returns to step S23; otherwise, the process proceeds to step S27.

[0116] (S27) The optimization unit 134 allocates the other CPU to the workload of interest, and then the process returns to step S23. (S28) The optimization unit 134 determines whether or not there is a free CPU remaining that is not assigned to any workload. If there is a free CPU remaining, the process proceeds to step S29. If there is no free CPU remaining, the process proceeds to step S31.

[0117] (S29) The optimization unit 134 selects the CPU pair with the highest speed from among the CPU pairs each including an available CPU as one of the CPUs. (S30) The optimization unit 134 identifies a workload to which the other CPU included in the CPU pair selected in step S29 has been assigned. The optimization unit 134 additionally assigns a free CPU to the identified workload.

[0118] (S31) The optimization unit 134 notifies the scheduler 135 of the changed CPU allocation. The scheduler 135 performs scheduling to cause multiple CPUs to execute multiple processes in parallel in accordance with the notified CPU allocation.

[0119] As described above, the information processing apparatus 100 according to the second embodiment measures the speed of data sharing between CPUs and calculates the frequency of data sharing for each workload. The information processing apparatus 100 changes CPU allocation so that the speed between the multiple CPUs assigned to a workload with a higher frequency of data sharing is higher.

[0120] This reduces the overhead of parallel processing of multiple processes that refer to common data, and speeds up parallel processing. Also, in a heterogeneous CPU system in which communication performance differs depending on the CPU and switch, CPU resources are used efficiently. Also, the information processing device 100 can flexibly change CPU allocation in accordance with changes in the topology of the CPU system and changes in the frequency of data sharing processing of the workload.

[0121] Furthermore, the information processing device 100 measures the number of times data sharing processing can be executed per unit time as the speed between the CPU pair. Furthermore, the information processing device 100 calculates the average number of executions by dividing the number of data sharing processing executed in a certain period by the number of CPUs assigned to the workload as the frequency of each workload. This allows the speed and frequency of data sharing processing to be appropriately evaluated, improving the accuracy of CPU allocation optimization.

[0122] Furthermore, when an available CPU remains, the information processing device 100 additionally assigns the available CPU to the same workload as the CPU with the highest speed with respect to the available CPU. This makes it possible to utilize the communication performance of the available CPU and to further speed up parallel processing of a workload with a high frequency of data sharing processing. [Explanation of symbols]

[0123] 10. Information processing device 11 Storage section 12 Control section 13 Speed ​​information 14 Communication Load 15,16 Process 20 Systems 21,22,23,24 Processors 25,26,27,28 Memory 29 Relay Device

Claims

1. a system including a plurality of processors connected to different memories, the plurality of processors being connected via one or more relay devices, and acquiring speed information indicating a communication speed between two different processors among the plurality of processors; Calculating a communication load between two or more processors assigned to a process group including two or more processes sharing data among the plurality of processors; changing the two or more processors to be assigned to the process group among the plurality of processors based on the speed information and the communication load; An allocation control program that causes a computer to execute a process.

2. the change includes, when the communication load is higher than other communication loads calculated for other process groups, a process of preferentially allocating the two different processors having the higher communication speed to the process group over the other process groups; 2. The allocation control program according to claim 1.

3. the communication speed is an execution speed of a data sharing process in which one of the two different processors writes data to a memory connected to the one processor, and the other of the two different processors reads the written data from the connected memory; 2. The allocation control program according to claim 1.

4. The communication load is an average number of executions calculated by dividing the number of executions within a certain period of time of a data sharing process in which one of the two or more processors writes data to a memory connected to the one processor and another of the two or more processors reads the written data from the connected memory, by the number of processors assigned to the process group.

2. The allocation control program according to claim 1.

5. the change includes, when a free processor is present among the plurality of processors, a process of adding the free processor to a process group to which a processor having the highest communication speed with the free processor is assigned among a plurality of process groups.

2. The allocation control program according to claim 1.

6. a system including a plurality of processors connected to different memories, the plurality of processors being connected via one or more relay devices, and acquiring speed information indicating a communication speed between two different processors among the plurality of processors; Calculating a communication load between two or more processors assigned to a process group including two or more processes sharing data among the plurality of processors; changing the two or more processors to be assigned to the process group among the plurality of processors based on the speed information and the communication load; An allocation control method for causing a computer to execute a process.

7. a storage unit that stores speed information indicating a communication speed between two different processors among a plurality of processors in a system including a plurality of processors connected to different memories and in which the plurality of processors are connected via one or more relay devices; a control unit that calculates a communication load between two or more processors among the plurality of processors that are assigned to a process group including two or more processes that share data, and changes the two or more processors among the plurality of processors that are assigned to the process group based on the speed information and the communication load; An information processing device having the above configuration.

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