SRAM circuit

Abstract

To provide an SRAM circuit that performs read and write operations in one cycle of a basic clock.SOLUTION: An SRAM circuit 11 including: a single-port SRAM cell 13; a word line decoder circuit 15 that selects a word line WL of the SRAM cell 13 in response to each of a read word address line WLRAD and a write word address line WLWAD; and a first internal timing generation circuit 17 that generates both a first read timing signal SRD1 and a first write timing signal SWR1 in one cycle of a basic clock CLK and provides the first read timing signal SRD1 and the first write timing signal SWR1 to the word line decoder circuit 15, in which the first internal timing generation circuit 17 generates the first read timing signal SRD1 and the first write timing signal SWR1 by a delay amount capable of being trimmed by the delay from either rising or falling of the basic clock CLK.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to SRAM circuits. [Background technology]

[0002] Patent Document 1 discloses a semiconductor memory device. This semiconductor memory device uses two types of column selectors. These column selectors arbitrarily connect single-port memory cells to a single port of a sense amplifier and a port of a write buffer by a first address and a second address. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-297073 Summary of the Invention [Problem to be solved by the invention]

[0004] Single-port static random access memory (SRAM) is used for temporary data storage in semiconductor integrated circuits. Single-port SRAM contains six transistors. In some product fields, dual-port SRAM is required to perform write and read operations within one cycle. Dual-port SRAM contains eight transistors, and there is a limit to how much the area of ​​one cell can be reduced. On the other hand, the demand for faster operating speeds in semiconductor integrated circuits is increasing. Accordingly, there is a demand to perform write and read operations within one cycle of the base clock.

[0005] An object of the present invention is to provide an SRAM circuit that can perform write and read operations within one cycle of a basic clock. [Means for solving the problem]

[0006] An SRAM circuit according to a first aspect of the present invention is an SRAM circuit that operates in synchronization with a basic clock, the SRAM circuit comprising: a single-port SRAM cell connected to a single word line and a pair of bit lines; a word line decoder circuit having an output connected to the word line of the SRAM cell, and a read word address input and a write word address input connected to a read word address line and a write word address line, respectively; and a first internal timing generation circuit that generates both a first read timing signal and a first write timing signal within one cycle of the basic clock and provides the first read timing signal and the first write timing signal to the word line decoder circuit, wherein the first internal timing generation circuit generates the first read timing signal and the first write timing signal with a delay that can be trimmed by a delay from either the rising or falling edge of the basic clock. Effect of the Invention

[0007] According to the above aspect, it is possible to provide an SRAM circuit that can perform write and read operations within one cycle of a base clock. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an SRAM circuit according to the present embodiment. [Diagram 2] FIG. 2 is a diagram showing a circuit of an SRAM cell of the SRAM circuit according to this embodiment. [Diagram 3] FIG. 3 is a diagram showing the operation timing of the SRAM circuit according to this embodiment. [Figure 4] FIG. 4 is a diagram illustrating an exemplary internal timing generation circuit of the SRAM circuit according to the present embodiment. [Diagram 5] FIG. 5 is a schematic diagram of an individual word line decoder circuit of a word line decoder circuit of an SRAM circuit according to an embodiment of the present invention. [Figure 6]FIG. 6 is a diagram illustrating an individual R / W circuit of the SRAM circuit according to the present embodiment. [Figure 7] FIG. 7 is a diagram illustrating an SRAM circuit (further including a second internal timing generation circuit) according to the present embodiment. [Figure 8] FIG. 8 is a diagram showing operation timings related to the second internal timing generation circuit of the SRAM circuit according to the present embodiment. [Figure 9] FIG. 9 is a diagram illustrating a second internal timing generation circuit of the SRAM circuit according to the present embodiment. [Figure 10] FIG. 10 is a schematic diagram of an SRAM circuit (which further includes a control circuit for setting the SRAM circuit in a test mode). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar parts are designated by the same or similar reference numerals, and duplicated description will be omitted.

[0010] Fig. 1 is a diagram showing a schematic diagram of an SRAM circuit according to the present embodiment. Fig. 2 shows a circuit of an SRAM cell of the SRAM circuit according to the present embodiment. Fig. 3 shows the operation timing of the SRAM circuit according to the present embodiment.

[0011] The SRAM circuit 11 includes one or more single-port SRAM cells 13, a word line decoder circuit 15, and a first internal timing generation circuit 17. The SRAM circuit 11 (static random access memory) operates in synchronization with a basic clock CLK, as shown in FIG.

[0012] The SRAM cell 13 has a single word line and a pair of bit lines and includes six transistors, a so-called 6Tr-SRAM, which is shown in Fig. 2. However, the SRAM cell 13 may include a so-called resistive-load 4Tr-SRAM. Referring to Fig. 1, the SRAM cells 13 are arranged in rows and columns to form an SRAM array ARY.

[0013] The word line decoder circuit 15 has an output 15b, a read word address input 15c and a write word address input 15d. In the word line decoder circuit 15, the output 15b is connected to the word line WL of the SRAM cell 13. The read word address input 15c and the write word address input 15d are connected to a read word address line WLRAD and a write word address line WLWAD, respectively. The read word address line WLRAD provides an address that defines a word line of the SRAM array ARY to be selected in a read operation. The write word address line WLWAD provides an address that defines a word line of the SRAM array ARY to be selected in a write operation.

[0014] The word line decoder circuit 15 is capable of receiving a read address and a write address independently of each other.

[0015] The first internal timing generation circuit 17 receives the basic clock CLK at an input 17b, and generates a first read timing signal SRD1 and a first write timing signal SWR1 as shown in Fig. 3. Specifically, the first read timing signal SRD1 and the first write timing signal SWR1 can be generated with a delay amount that can be trimmed by delaying from either the rising edge or the falling edge of the basic clock CLK. The first read timing signal SRD1 and the first write timing signal SWR1 are output from a first output 17c and a second output 17d, respectively.

[0016] The SRAM circuit 11 performs a read operation during a read period ("TRD0" in FIG. 3), which is determined by a read signal SRD. The SRAM circuit 11 performs a write operation during a write period ("TWR0" in FIG. 3), which is determined by a write signal SWR. The read period ("TRD0" in FIG. 3) is, for example, the length from the rising time of the first read timing signal SRD1 to the rising time of the first write timing signal SWR1. The write period ("TWR0" in FIG. 3) is, for example, the length from the rising time of the first write timing signal SWR1 to the rising time of the next first read timing signal SRD1. The read period ("TRD0") and the write period ("TWR0") are within one cycle of the basic clock CLK, except for a slight time shift from the basic clock CLK. The sum of the read period ("TRD0") and the write period ("TWR0") is substantially equal to the period of one cycle of the basic clock CLK.

[0017] The first read timing signal SRD1 and the first write timing signal SWR1 are located in a read period ("TRD0") and a write period ("TWR0"), respectively. The first read timing signal SRD1 and the first write timing signal SWR1 can be, for example, exclusive periods.

[0018] The first read timing signal SRD1 and the first write timing signal SWR1 are provided to a word line decoder circuit 15. For example, the word line decoder circuit 15 selects a certain word line WL according to an address signal from a read word address line WLRAD during the period of the first read timing signal SRD1 (period of logical value "H"). Also, the word line decoder circuit 15 selects a certain word line WL according to an address signal from a write word address line WLWAD during the period of the first write timing signal SWR1 (period of logical value "H").

[0019] FIG. 4 is a diagram illustrating an exemplary internal timing generation circuit of the SRAM circuit according to the present embodiment.

[0020] The exemplary first internal timing generation circuit 17 may include a first delay circuit 30. The exemplary first delay circuit 30 may include at least one first RD delay circuit 35 and at least one first WR delay circuit 37.

[0021] The exemplary first delay circuit 30 receives a basic clock CLK. The exemplary first delay circuit 30 generates a first RD delay signal SDRD1 and a first WR delay signal SDWR1, which are generated with a trimmable delay amount by delaying from either the rising edge or the falling edge of the basic clock CLK. The trimmable delay amount can be adjusted by data in a plurality of non-volatile writable storage elements 38, such as fuse elements. The fuse elements are included in a data storage circuit 39. The trimming value of the data storage circuit 39 is loaded at the time of power-on and stored in a holding circuit 30b in the first delay circuit 30.

[0022] The exemplary first delay circuit 30 can generate delay signals with delay amounts D1, D2, D3, and D4, for example, as shown in Fig. 3. The delay amount D1 can be used to generate a read period ("TRD0") (or a write period ("TWR0")) from the basic clock CLK. The delay amounts D2 and D4 allow the read operation / write operation to be read out stably, respectively.

[0023] The delays D1 and D2 can be used to generate a first read timing signal SRD1, and the delays D3 and D4 can be used to generate a first write timing signal SWR1, which can also be generated from the delays D5 and D6.

[0024] The first RD delay circuit 35 receives the basic clock CLK and generates the first RD delay signal SDRD1 (delay amounts D1 and D2). The first WR delay circuit 37 receives the basic clock CLK and generates the first WR delay signal SDWR1 (delay amounts D3 and D4, or delay amounts D5 and D6).

[0025] The first read timing signal SRD1 and the first write timing signal SWR1 are provided to the word line decoder circuit 15. In this embodiment, the first internal timing generation circuit 17 outputs a first RD delay signal SDRD1 as the first read timing signal SRD1, and outputs a first WR delay signal SDWR1 as the first write timing signal SWR1.

[0026] According to this SRAM circuit 11, the first internal timing generation circuit 17 generates the first read timing signal SRD1 and the first write timing signal SWR1 from the basic clock CLK. This generation is performed using the first RD delay signal SDRD1 and the first WR delay signal SDWR1, which are generated with a trimmable delay amount. Therefore, the first internal timing generation circuit 17 enables reading and writing of the single-port SRAM cell 13 within the period of one basic clock.

[0027] The word line decoder circuit 15 separately receives the read word address signal from the read word address line WLRAD and the write word address signal from the write word address line WLWAD, thereby making it possible to avoid the complication of timing adjustments for receiving two types of word address signals (WLRAD and WLWAD).

[0028] The read signal SRD and the write signal SWR are exclusive except for their respective transition periods. Also, the first read timing signal SRD1 and the first write timing signal SWR1 are exclusive. That is, the read period TRD1 defined by the first read timing signal SRD1 and the write period TWR1 defined by the first write timing signal SWR1 do not substantially overlap each other.

[0029] As shown in FIG. 1, an exemplary word line decoder circuit 15 may include multiple individual word line decoder circuits 16 connected to each word line WL.

[0030] FIG. 5 is a schematic diagram of an individual word line decoder circuit of a word line decoder circuit of an SRAM circuit according to an embodiment of the present invention.

[0031] The exemplary individual word line decoder circuit 16 includes a first RD decoder circuit 41 and a first WR decoder circuit 43. The first RD decoder circuit 41 is connected to a read word address line WLRAD and is responsive to an address signal from the read word address line WLRAD to select a word line WL for a read operation. The first WR decoder circuit 43 is connected to a write word address line WLWAD and is responsive to an address signal from the write word address line WLWAD to select a word line WL for a write operation.

[0032] According to this SRAM circuit 11, the first RD decoder circuit 41 of the individual word line decoder circuit 16 operates in response to a read address word signal from the read word address line WLRAD. Also, the first WR decoder circuit 43 of the individual word line decoder circuit 16 operates in response to a write word address signal from the write word address line WLWAD. Therefore, the first RD decoder circuit 41 and the first WR decoder circuit 43 can operate independently of each other. The SRAM circuit 11 does not need to adjust the input timing of the read address word signal and the write word address signal.

[0033] The exemplary individual word line decoder circuit 16 further includes a first conflict avoidance circuit 45. The first conflict avoidance circuit 45 has an output 45b connected to the word line WL of the SRAM cell 13. The first conflict avoidance circuit 45 also has a first input 45c and a second input 45d, which are connected to the output 41b of the first RD decoder circuit 41 and the output 43b of the first WR decoder circuit 43, respectively.

[0034] The first conflict avoidance circuit 45 provides a word line signal from either the output 41b of the first RD decoder circuit 41 or the output 43b of the first WR decoder circuit 43 to the word line WL of the individual word line decoder circuit 16. The first read timing signal SRD1 and the first write timing signal SWR1 are used for this conflict avoidance. Therefore, during the selection period of the first read timing signal SRD1 shown in FIG. 3, the first RD decoder circuit 41 of the individual word line decoder circuit 16 is coupled to the word line WL, and the first WR decoder circuit 43 is disconnected from the word line WL. Also, during the selection period of the first write timing signal SWR1 shown in FIG. 3, the first WR decoder circuit 43 of the individual word line decoder circuit 16 is coupled to the word line WL, and the first RD decoder circuit 41 is disconnected from the word line WL. For example, a tri-state buffer can be used for conflict avoidance.

[0035] 1 is arranged on one side of the array ARY. However, the first RD decoder circuit 41 and a part of the first conflict avoidance circuit 45 may be arranged on one of the two opposing sides of the array ARY, and the first WR decoder circuit 43 and the first conflict avoidance circuit 45 may be arranged on the other side. In this SRAM circuit 11 as well, the first conflict avoidance circuits 45 on both sides serve to avoid conflicts between the RD word select signal and the WR word select signal.

[0036] 1, the SRAM circuit 11 may include a read / write circuit 53. The read / write circuit 53 reads and writes selected SRAM cells 13. In particular, the read / write circuit 53 may include multiple individual R / W circuits 18.

[0037] 6 is a diagram showing an individual R / W circuit of the SRAM circuit according to the present embodiment. In the SRAM circuit 11, the individual R / W circuit 18 may further include a write circuit 55 and a read circuit 57.

[0038] 1 and 6, the write circuit 55 is connected to the bit line BLP of the SRAM cell 13 and receives write data DWD (see FIG. 6) via a write line LWR (see FIG. 1). The read circuit 57 is connected to the bit line BLP of the SRAM cell 13 and provides read data DRD (see FIG. 6) to an output line LRD (see FIG. 1).

[0039] In this SRAM circuit 11, the write circuit 55 provides write data DWD from the write line LWR to a pair of bit lines BLP. A selected SRAM cell 13 is written in accordance with the write data DWD on the pair of bit lines BLP. The stored value of the selected SRAM cell 13 also changes the potentials of the pair of bit lines BLP. The change in the bit line potentials is detected by the read circuit 57.

[0040] 3, within one cycle of the basic clock CLK, the read period defined by the first read timing signal SRD1 precedes the write period defined by the first write timing signal SWR1. According to this SRAM circuit 11, within one cycle, the read operation is performed before the write operation. That is, the data before rewriting is read. However, this is defined by the specifications of the SRAM circuit 11.

[0041] The write circuit 55 can be activated by a signal (SWR and / or SWR1) shown in Fig. 3. The read circuit 57 can be activated by a signal (SRD and / or SRD1) shown in Fig. 3.

[0042] 1 and 6, the SRAM circuit 11 may further include a precharge circuit 51 connected to each of the bit lines BLP (BL, BLB) of the array ARY of the SRAM cells 13.

[0043] According to this SRAM circuit 11, the precharge circuit 51 can precharge the pair of bit lines BLP of the SRAM cell 13, specifically, the bit line BL and the bit line BLB, prior to at least one or both of a read and write operation.

[0044] Specifically, the precharge circuit 51 precharges the pair of bit lines BLP in the same manner prior to writing to the SRAM cell 13 using the write circuit 55. In this SRAM circuit 11, the write circuit 55 changes the potentials of the precharged pair of bit lines BLP in accordance with the write data DWD from the write line LWR.

[0045] Furthermore, the precharge circuit 51 precharges the pair of bit lines BLP prior to reading the SRAM cell 13 using the read circuit 57. According to the SRAM circuit 11, the SRAM cell 13 changes the potentials of the precharged pair of bit lines BLP in accordance with the stored value of the SRAM cell 13. The read circuit 57 detects the change in the bit line potentials.

[0046] Referring again to FIG. 1, the SRAM circuit 11 may further include a column selector 61 and a column line decoder circuit 63.

[0047] The column selector 61 is connected between the write circuit 55 and the read circuit 57 and the bit line BLP.

[0048] The column line decoder circuit 63 has an output 63b connected to the column selector 61, a read column address input 63c and a write column address input 63d. In the column line decoder circuit 63, the read column address input 63c and the write column address input 63d are connected to the read column address line CLRAD and the write column address line CLWAD, respectively.

[0049] The column line decoder circuit 63 may further have a first control input 63e and a second control input 63f. In the exemplary column line decoder circuit 63, the first control input 63e and the second control input 63f receive a first read timing signal SRD1 and a first write timing signal SWR1, respectively.

[0050] In response to activation of the first read timing signal SRD1, the column line decoder circuit 63 provides a selection signal defined by an address signal from the read column address line CLRAD to the column selector 61. In addition, in response to activation of the first write timing signal SWR1, the column line decoder circuit 63 provides a selection signal defined by an address signal from the write column address line CLWAD to the column selector 61.

[0051] An exemplary column line decoder circuit 63 may include circuitry similar to the word line selection circuitry shown in Figure 5. An exemplary individual column line decoder circuit may include a second RD decoder circuit, a second WR decoder circuit, and a second contention avoidance circuit. The second RD decoder circuit, the second WR decoder circuit, and the second contention avoidance circuit may be provided with functionality similar to the second RD decoder circuit 41, the second WR decoder circuit 43, and the second contention avoidance circuit 45, respectively.

[0052] In this SRAM circuit 11, the column selector 61 couples a desired bit line BLP to the write circuit 55 or the read circuit 57. In addition, the column line decoder circuit 63 receives address signals from the read column address line CLRAD and the write column address line CLWAD independently, which makes it possible to avoid complication in the timing of switching the column address between the read operation and the write operation.

[0053] FIG. 7 is a schematic diagram of a modified SRAM circuit according to the present embodiment.

[0054] The SRAM circuit 11a may further include a second internal timing generation circuit 20. Due to the addition of the second internal timing generation circuit 20, the first internal timing generation circuit 17 is not connected to the first control input 63e and the second control input 63f of the column line decoder circuit 63. Instead, the second internal timing generation circuit 20 is connected to the first control input 63e and the second control input 63f of the column line decoder circuit 63. The first internal timing generation circuit 17 controls the operation of the word line decoder circuit 15, while the second internal timing generation circuit 20 controls the operation of the column line decoder circuit 63 and the read / write circuit 53.

[0055] The second internal timing generation circuit 20 can be configured to generate a delay suitable for controlling the operation of the column line decoder circuit 63 and the read / write circuit 53. The first internal timing generation circuit 17 can be configured to generate a delay suitable for controlling the operation of the word line decoder circuit 15.

[0056] Next, the second internal timing generating circuit 20 will be described.

[0057] 8 is a diagram showing operation timings related to the second internal timing generation circuit of the SRAM circuit according to the present embodiment. FIG. 9 is a diagram showing the second internal timing generation circuit of the SRAM circuit according to the present embodiment.

[0058] The second internal timing generation circuit 20 receives the basic clock CLK at the input 20b, and generates a second read timing signal SRD2 and a second write timing signal SWR2 as shown in FIG. 8. Specifically, the second read timing signal SRD2 and the second write timing signal SWR2 can be generated with a delay amount that can be trimmed by delaying from either the rising edge or the falling edge of the basic clock CLK. The second read timing signal SRD2 and the second write timing signal SWR2 are output from the first output 20c and the second output 20d, respectively. The second read timing signal SRD2 and the second write timing signal SWR2 are provided to a column line decoder circuit 63. The column line decoder circuit 63 receives the second read timing signal SRD2 and the second write timing signal SWR2 at a first control input 63e and a second control input 63f. The column line decoder circuit 63 operates in response to the second read timing signal SRD2 and the second write timing signal SWR2. In this embodiment, the second internal timing generation circuit 20 outputs a second RD delay signal SDRD2 as the second read timing signal SRD2, and outputs a second WR delay signal SDWR2 as the second write timing signal SWR2.

[0059] For example, the column line decoder circuit 63 selects a single column line CL in response to an address signal from the read column address line CLRAD during the period of the second read timing signal SRD2 (period of logical value "H"), and also selects a single column line CL in response to an address signal from the write column address line CLWAD during the period of the second write timing signal SWR2 (period of logical value "H").

[0060] A signal line from the first internal timing generation circuit 17 is connected to the read / write circuit 53 and the second internal timing generation circuit 20. The second internal timing generation circuit 20 can receive, for example, a read signal SRD and a write signal SWR. Also, the second read timing signal SRD2 and the second write timing signal SWR2 can be provided to the read / write circuit 53. The read / write circuit 53 operates in response to the second read timing signal SRD2 and the second write timing signal SWR2. In this embodiment, the second internal timing generation circuit 20 is connected to receive a signal from the first internal timing generation circuit 17. However, the second internal timing generation circuit 20 does not have to be connected to the first internal timing generation circuit 17, and can receive, for example, the read signal SRD and the write signal SWR.

[0061] 8, the activation period (TRD2) of the second read timing signal SRD2 and the activation period (TWR2) of the second write timing signal SWR2 are located within the read period ("TRD0") and the write period ("TWR0"), respectively. The second read timing signal SRD2 and the second write timing signal SWR2 can be, for example, exclusive periods.

[0062] 9, the second internal timing generation circuit 20 may have a similar configuration to the first internal timing generation circuit 17. Specifically, the exemplary second internal timing generation circuit 20 may include a second delay circuit 70. The exemplary second delay circuit 70 may include at least one second RD delay circuit 75 and at least one second WR delay circuit 77.

[0063] The exemplary second delay circuit 70 receives the basic clock CLK and generates a second RD delay signal SDRD2 and a second WR delay signal SDWR2. The second RD delay signal SDRD2 and the second WR delay signal SDWR2 are generated with a trimmable delay amount by delaying from either the rising edge or the falling edge of the basic clock CLK. The trimmable delay amount can be adjusted by data in a plurality of non-volatile writable storage elements 78, such as fuse elements. The fuse elements are included in a data storage circuit 79. The trimming value of the data storage circuit 79 is loaded at the time of power-on and stored in a holding circuit 70b in the second delay circuit 70.

[0064] The exemplary second delay circuit 70 can generate delay signals with delay amounts D7, D8, D9, and D10, for example, as shown in FIG.

[0065] The delays D7 and D8 can be used to generate a second read timing signal SRD2, and the delays D9 and D10 can be used to generate a second write timing signal SWR2, which can also be generated from the delays D11 and D12.

[0066] The second RD delay circuit 75 receives the basic clock CLK and generates the second RD delay signal SDRD2 (delay amounts D7 and D8). The second WR delay circuit 77 receives the basic clock CLK and generates the second WR delay signal SDWR2 (delay amounts D9 and D10, or delay amounts D11 and D12).

[0067] The second read timing signal SRD2 and the second write timing signal SWR2 are provided to a column line decoder circuit 63.

[0068] In this SRAM circuit 11, the second internal timing generation circuit 20 generates the second read timing signal SRD2 and the second write timing signal SWR2 using the second RD delay signal SDRD2 and the second WR delay signal SDWR2, which have trimmable delay amounts. Therefore, the second internal timing generation circuit 20 enables reading and writing of the single-port SRAM cell 13 within the period of the basic clock.

[0069] FIG. 10 is a diagram showing a control circuit of the SRAM circuit according to the present embodiment.

[0070] The SRAM circuit 11b may further include a control circuit 81 that sets the SRAM circuit 11 in a test mode in response to an external test mode signal from the pad electrode 10.

[0071] Moreover, the first internal timing generation circuit 17 may further include a switching circuit 40. In response to the SRAM circuit 11 being set to the test mode, the switching circuit 40 switches the connection between the delay circuit 30 and the word line decoder circuit 15 to the connection between the control circuit 81 and the word line decoder circuit 15.

[0072] According to this SRAM circuit 11, in the test mode, for read and write operations, the word line decoder circuit 15 operates in response to an external test signal from the control circuit 81, independent of the delay amount of the first delay circuit 30. The test mode can also be applied to the column line decoder circuit 63 and the read / write circuit 53. The column line decoder circuit 63 and the read / write circuit 53 can also operate in response to an external test signal from the control circuit 81.

[0073] The operating speed of the SRAM circuit 11 can be increased by adjusting the amount of delay in the internal timing generation circuits (17, 20) to speed up the write timing, thereby enabling the SRAM circuit 11 to perform a series of write / read operations in a short time.

[0074] However, the operating speed of the SRAM circuit 11 depends on the process finish. The adjustment of the delay amount of the SRAM circuit 11 can be determined from the measurement results of the operating characteristics of another circuit, such as a test circuit or a product circuit (oscillator circuit characteristics, standby current value of a semiconductor chip), which is fabricated on the same semiconductor wafer as the SRAM circuit 11. Alternatively, the adjustment of the delay amount of the SRAM circuit 11 can be determined from the measurement results of a speed test in a test mode.

[0075] These measurements can be used to identify data to write to a trim element (eg, a fuse element), and this value can be written to the trim element.

[0076] Operating the device faster than required by the product specifications can reduce test time. For example, testing at 1.2 times the operating speed reduces test time by 0.83 (=1 / 1.2) times, resulting in reduced test costs.

[0077] The operating speed of the SRAM circuit 11 can be slowed down by writing data to a trimming element (for example, a fuse element), and the operating margin of the SRAM circuit 11 becomes large.

[0078] The test mode of the SRAM circuit 11 can be used for failure analysis purposes.

[0079] In the test mode, the stored value of the delay amount in the internal timing generation circuit (17, 20) can be provided from the outside.

[0080] When testing the SRAM circuit 11, the detection rate of delay faults can be increased by increasing the operating speed in the test mode. As semiconductors become finer, manufacturing defects appear as delays, making delay fault testing an important technical issue. Increasing the operating speed makes it possible to discover various potential process defects as delay faults.

[0081] According to this embodiment, it is possible to provide an SRAM circuit that can perform write and read operations within one cycle of the base clock.

[0082] As described above, the present embodiment has various aspects.

[0083] A first aspect according to this embodiment is an SRAM circuit that operates in synchronization with a basic clock, the SRAM circuit comprising: a single-port SRAM cell connected to a single word line and a pair of bit lines; a word line decoder circuit having an output connected to the word line of the SRAM cell, and a read word address input and a write word address input connected to a read word address line and a write word address line, respectively; and a first internal timing generation circuit that generates both a first read timing signal and a first write timing signal within one cycle of the basic clock and provides the first read timing signal and the first write timing signal to the word line decoder circuit, wherein the first internal timing generation circuit is capable of generating the first read timing signal and the first write timing signal with a delay that can be trimmed by a delay from either the rising edge or the falling edge of the basic clock.

[0084] In a second aspect according to the first aspect, the word line decoder circuit includes a first RD decoder circuit and a first WR decoder circuit, the first RD decoder circuit decodes a read word address signal from the read word address input to generate a RD word select signal, and the first WR decoder circuit decodes a write word address signal from the write word address input to generate a WR word select signal.

[0085] In a third aspect according to the second aspect, the word line decoder circuit includes a first conflict avoidance circuit that connects either an output of the first RD decoder circuit or an output of the first WR decoder circuit to the word line in response to the first read timing signal and the first write timing signal from the first internal timing generation circuit, and the first conflict avoidance circuit can be connected to the word line of the SRAM cell.

[0086] A fourth aspect according to any one of the first to third aspects may further include a precharge circuit connected to each of the bit lines of the SRAM cells.

[0087] A fifth aspect according to the fourth aspect may further include a write circuit connected to the bit line of the SRAM cell and receiving write data via a write line, and a read circuit connected to the bit line of the SRAM cell and providing read data to an output line.

[0088] A sixth aspect according to the fifth aspect may further include a column selector connected between the write circuitry and the read circuitry and the bit lines, and a column line decoder circuit having an output connected to the column selector, and read and write column address inputs connected to read and write column address lines, respectively.

[0089] In a seventh aspect according to any one of the first to sixth aspects, within one cycle of the basic clock, a read period defined by the first read timing signal can precede a write period defined by the first write timing signal.

[0090] In an eighth aspect according to the seventh aspect, the first read timing signal and the first write timing signal are provided to the column line decoder circuit, and the column line decoder circuit can operate in response to the first read timing signal and the first write timing signal.

[0091] In a ninth aspect according to any one of the first to eighth aspects, the first internal timing generation circuit may include a first delay circuit that receives the basic clock and generates a first RD delay signal and a first WR delay signal generated with a trimmable delay amount by delaying from either the rising or falling edge of the basic clock.

[0092] In a tenth aspect according to the ninth aspect, the first internal timing generation circuit further includes a rewritable first storage circuit connected to the first delay circuit and storing values ​​for the delay amount of the first RD delay signal and the first WR delay signal, and the first delay circuit may include a first holding circuit that holds the value from the first storage circuit.

[0093] An eleventh aspect according to the ninth or tenth aspect further includes a control circuit that sets the SRAM circuit to a test mode in response to an external test mode signal, and a first switching circuit that switches a connection between the first delay circuit and the word line decoder circuit to a connection between the control circuit and the word line decoder circuit in response to the SRAM circuit being set to the test mode, and the first internal timing generation circuit can provide an external test signal from the control circuit to the word line decoder circuit.

[0094] In a twelfth aspect according to any one of the first to eleventh aspects, the SRAM cell may have a 6Tr-SRAM configuration.

[0095] In a thirteenth aspect according to the seventh aspect, the semiconductor memory device further includes a second internal timing generation circuit that generates both a second read timing signal and a second write timing signal within one cycle of the basic clock and provides the second read timing signal and the second write timing signal to the column line decoder circuit, and the column line decoder circuit can operate in response to the second read timing signal and the second write timing signal.

[0096] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0097] 10···pad electrode, 11, 11a, 11b···SRAM circuit, 13···SRAM cell, 15···word line decoder circuit, 15b···output, 15c···read word address input, 15d···write word address input, 16···individual word line decoder circuit, 17···first internal timing generation circuit, 18···individual R / W circuit, 20···second internal timing generation circuit, 30···first delay circuit, 30b···first hold circuit, 35···first RD delay circuit, 37···first WR delay circuit, 38···memory element, 39...data storage circuit, 40...switching circuit, 41...first RD decoder circuit, 43...first WR decoder circuit, 45...first conflict avoidance circuit, 51...precharge circuit, 53...read / write circuit, 55...write circuit, 57...readout circuit, 61...column selector, 63...column line decoder circuit, 70...second delay circuit, 70b...second hold circuit, 75...second RD delay circuit, 77...second WR delay circuit, 78...memory element, 79...data storage circuit, and 81...control circuit.

Claims

1. An SRAM circuit that operates in synchronization with a basic clock, a single-port SRAM cell connected to a single word line and a pair of bit lines; a word line decoder circuit having an output connected to the word line of the SRAM cell, and read and write word address inputs connected to read and write word address lines, respectively; a first internal timing generating circuit that generates both a first read timing signal and a first write timing signal within one cycle of the basic clock and provides the first read timing signal and the first write timing signal to the word line decoder circuit; Equipped with the first internal timing generation circuit generates the first read timing signal and the first write timing signal with a delay amount that can be trimmed by delaying from either a rising edge or a falling edge of the basic clock; SRAM circuit.

2. the word line decoder circuit includes a first RD decoder circuit and a first WR decoder circuit; the first RD decoder circuit decodes a read word address signal from the read word address input to generate a RD word select signal; the first WR decoder circuit decodes a write word address signal from the write word address input to generate a WR word select signal; 2. The SRAM circuit of claim 1.

3. the word line decoder circuit includes a first conflict avoidance circuit that connects either an output of the first RD decoder circuit or an output of the first WR decoder circuit to the word line in response to the first read timing signal and the first write timing signal from the first internal timing generation circuit; the first conflict avoidance circuit is connected to the word line of the SRAM cell; 3. The SRAM circuit of claim 2.

4. a precharge circuit connected to each of the bit lines of the SRAM cells; 2. The SRAM circuit of claim 1.

5. a write circuit connected to the bit line of the SRAM cell and receiving write data via a write line; a read circuit connected to the bit lines of the SRAM cells and providing read data on an output line; Further comprising:

5. The SRAM circuit of claim 4.

6. Within one cycle of the basic clock, a read period defined by the first read timing signal precedes a write period defined by the first write timing signal.

2. The SRAM circuit of claim 1.

7. a column selector connected between the write circuit and the read circuit and the bit lines; a column line decoder circuit having an output connected to the column selector, and read and write column address inputs connected to read and write column address lines, respectively; Further comprising:

6. The SRAM circuit of claim 5.

8. the first read timing signal and the first write timing signal are provided to the column line decoder circuit; the column line decoder circuit operates in response to the first read timing signal and the first write timing signal; 8. The SRAM circuit of claim 7.

9. The first internal timing generation circuit includes: a first delay circuit that receives the basic clock and generates a first RD delay signal and a first WR delay signal that are generated with a trimmable delay amount based on a delay from either a rising edge or a falling edge of the basic clock; 9. An SRAM circuit according to claim 1.

10. The first internal timing generation circuit includes: a rewritable first storage circuit connected to the first delay circuit and configured to store values ​​for the delay amounts of the first RD delay signal and the first WR delay signal; the first delay circuit includes a first holding circuit that holds the value from the first storage circuit; 10. The SRAM circuit of claim 9.

11. a control circuit for setting the SRAM circuit to a test mode in response to an external test mode signal; a first switching circuit for switching a connection between the first delay circuit and the word line decoder circuit to a connection between the control circuit and the word line decoder circuit in response to the SRAM circuit being set to the test mode; Further comprising: the first internal timing generation circuit provides an external test signal from the control circuit to the word line decoder circuit; 10. The SRAM circuit of claim 9.

12. The SRAM cell has a 6Tr-SRAM configuration.

2. The SRAM circuit of claim 1.

13. a second internal timing generation circuit that generates both a second read timing signal and a second write timing signal within one cycle of the basic clock and provides the second read timing signal and the second write timing signal to the column line decoder circuit; the column line decoder circuit operates in response to the second read timing signal and the second write timing signal; 8. The SRAM circuit of claim 7.

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