Display unit and display system

Abstract

To provide a display unit and a display system that can reduce power consumption in a period during which control processing in a pause mode is under execution.SOLUTION: A display unit comprises a timing control circuit 2 and a power conversion circuit 4. When receiving a control signal for making a transition from a display mode to a pause mode from a host controller 102, the timing control circuit 2 transmits a pause signal B1 to the power control circuit 4. In a display mode before receiving the pause signal B1, the power control circuit 4 converts input voltage V1 into output voltage V2 at a switching frequency f1, and in a pause mode after receiving the pause signal B1 from the timing control circuit 2, converts the input voltage V1 into the output voltage V2 at a switching frequency f2 lower than the switching frequency f1.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a display device and a display system. [Background technology]

[0002] Patent Document 1 discloses a power supply circuit for driving liquid crystal used in a display device. The power supply circuit for driving includes a capacitor and a switch. The power supply circuit for driving applies an input voltage to a capacitor to store an electric charge in the capacitor, and converts the input voltage into a voltage having a voltage value used for driving the liquid crystal by switching a switch connected to the capacitor at a predetermined switching frequency.

[0003] The display device described in Patent Document 2 executes control processing in either a normal operation mode in which an image is displayed on the display panel, or a sleep mode in which an image is not displayed on the display panel. The display device is configured to transition to the sleep mode if there is no touch operation for a certain period of time in the normal operation mode. The display device is also configured to transition to the normal operation mode if there is a touch operation in the sleep mode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2002-268610 A

[0005] [Patent Document 2] JP 2017-91224 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the sleep mode (pause mode) described in Patent Document 2, it is necessary to continue supplying power to at least some of the circuits in the display device, and therefore it is not possible to sufficiently reduce power consumption.

[0007] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a display device and a display system that are capable of reducing power consumption during the period when control processing is being executed in sleep mode. [Means for solving the problem]

[0008] In order to solve the above problem, a display device according to a first aspect of the present disclosure includes a display panel, a display drive circuit that supplies a drive signal to the display panel, a timing control circuit that supplies an image signal to the display panel and a timing signal to the display drive circuit, and a power conversion circuit that converts an input voltage, which is the voltage of an input power, into an output voltage and supplies power having the output voltage to at least one of the display panel, the display drive circuit, and the timing control circuit, wherein the timing control circuit transmits a pause signal to the power conversion circuit when it receives a control signal from a host controller to transition from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, and the power conversion circuit converts the input voltage to the output voltage at a first switching frequency in the display mode before receiving the pause signal, and converts the input voltage to the output voltage at a second switching frequency lower than the first switching frequency in the pause mode after receiving the pause signal from the timing control circuit.

[0009] Further, a display system according to a second aspect is a display system comprising: a display device having a display panel; and a host controller that transmits a control signal to the display device to switch from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped. The display device comprises: a display drive circuit that supplies a drive signal to the display panel; a timing control circuit that supplies an image signal to the display panel and supplies a timing signal to the display drive circuit; and a power conversion circuit that converts an input voltage, which is the voltage of input power, into an output voltage and supplies power having the output voltage to at least one of the display panel, the display drive circuit, and the timing control circuit. When the timing control circuit receives a control signal from the host controller to transition from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, the timing control circuit transmits a pause signal to the power conversion circuit. In the display mode before receiving the pause signal, the power conversion circuit converts the input voltage to the output voltage at a first switching frequency, and in the pause mode after receiving the pause signal from the timing control circuit, the power conversion circuit converts the input voltage to the output voltage at a second switching frequency lower than the first switching frequency. Effect of the Invention

[0010] Here, the lower the switching frequency of the power conversion, the lower the power consumption in the power conversion. According to the above configuration, during the period in which the control process in the pause mode is being executed, the power conversion by the power conversion circuit can be performed at a switching frequency lower than that in the display mode. Therefore, during the period in which the control process in the pause mode is being executed, the power consumption can be reduced. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a display system 100 according to the first embodiment. [Diagram 2] FIG. 2 is a schematic diagram for explaining the configuration of the display panel 1. As shown in FIG. [Diagram 3] FIG. 3 is a schematic diagram showing the configuration of a pixel 10a in the display panel 1. As shown in FIG. [Figure 4] FIG. 4 is a functional block diagram of the timing control circuit 2 and the power control circuit 4. [Diagram 5] FIG. 5 is a schematic circuit diagram of the circuit power supply unit 42a. [Figure 6] FIG. 6 is a schematic circuit diagram of the level shifter power supply unit 42c. [Figure 7] FIG. 7 is a timing chart for explaining the operation of the display system 100 in the first embodiment. [Figure 8] FIG. 8 is a block diagram showing the configuration of a display system 200 according to the second embodiment. [Figure 9] FIG. 9 is a block diagram showing the configuration of a display system 300 according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present disclosure will be described based on the drawings. Note that the present disclosure is not limited to the following embodiments, and appropriate design changes can be made within the scope of the configuration of the present disclosure. In the following description, the same parts or parts having similar functions are commonly designated by the same reference numerals in different drawings, and repeated description thereof will be omitted. In addition, each configuration described in the embodiment and the modified example may be appropriately combined or modified within the scope of the gist of the present disclosure. In addition, in order to make the description easier to understand, in the drawings referred to below, the configuration is shown simplified or schematic, and some components are omitted.

[0013] [First embodiment] (Overall configuration of the display device) 1 is a block diagram showing a schematic configuration of a display system 100 in the first embodiment. The display system 100 includes a display device 101 and a host controller 102. The display system 100 is, for example, a personal computer, a tablet terminal, a smartphone, or a television device. The host controller 102 transmits an image signal A1 (video signal) to the display device 101, and also transmits a control signal D1 to the display device 101. The host controller 102 is connected to the display device 101 via an I2C bus, and performs serial communication with the display device 101. The display device 101 displays an image based on the image signal A1 from the host controller 102.

[0014] The control signal D1 also includes a signal for commanding the display mode, in which the display panel 1 of the display device 101 performs display, to be switched to a pause mode, in which the display panel 1 stops display. For example, the host controller 102 transmits the control signal D1 including a signal for transitioning from the display mode to the pause mode when no operation is input from the user for a predetermined period during the period during which the control process in the display mode is being performed, or when the user is not present within the range of photography by a camera (not shown) for a predetermined period. The host controller 102 also transmits the control signal D1 including a signal for commanding the transition from the pause mode to the display mode when an operation is input from the user during the period during which the control process in the pause mode is being performed, or when the user appears within the range of photography by the camera. Here, in the first embodiment, the host controller 102 supplies the voltage V1 to the power control circuit 4 regardless of whether the control process in the display mode or the pause mode is being performed.

[0015] The "pause mode" is a state in which display by the display panel 1 is stopped (paused) to reduce power consumption. The pause of display by the display panel 1 in the pause mode continues until the display mode is changed to (paused over multiple frames). Stopping the display means stopping the supply of signals (gate signals and source signals) from the gate drive circuit 11 and the source drive circuit 12 to the display unit 10 on the display panel 1. The "display mode" is a state in which signals (gate signals and source signals) are supplied from the gate drive circuit 11 and the source drive circuit 12 to the display unit 10, and an image is displayed on the display panel 1. Note that the transmission of signals and the supply of power indicated by dotted arrows in Figs. 1, 4, 8, and 9 are performed only in the display mode. The transmission of signals and the supply of power indicated by solid arrows in Figs. 1, 4, 8, and 9 are performed in both the display mode and the pause mode.

[0016] (Display Device Configuration) 1, a display device 101 includes a display panel 1, a timing control circuit 2, a level shifter circuit 3, and a power control circuit 4. The level shifter circuit 3 is an example of the "display driver circuit" of the present disclosure.

[0017] Display Panel Configuration FIG. 2 is a schematic diagram for explaining the configuration of the display panel 1. The display panel 1 is a panel that displays an image. The display panel 1 is, for example, a liquid crystal display panel, an organic EL panel, or a micro LED panel. As shown in FIG. 2, the display panel 1 includes a display section 10, a gate drive circuit 11, and a source drive circuit 12. The display panel 1 includes a substrate 1a on which a plurality of gate lines 11a, a plurality of source lines 12a, and a plurality of terminals 13 are formed. The plurality of gate lines 11a intersect with the plurality of source lines 12a in a plan view. The display section 10 is a portion on the substrate 1a on which pixels 10a (see FIG. 3) are formed, and is an area that displays an image.

[0018] The gate drive circuit 11 sequentially supplies the gate signal G1, which is supplied from the level shifter circuit 3, to the multiple gate lines 11a. The gate drive circuit 11 is a circuit (GDM: Gate Driver Monolithic) formed (monolithically) on the substrate 1a.

[0019] The source driving circuit 12 is supplied with an image signal A1 (digital signal) from the timing control circuit 2. The source driving circuit 12 is also supplied with a positive voltage Vp, a negative voltage Vn, and a reset signal R1 from the power control circuit 4. The source driving circuit 12 generates a source signal using the positive voltage Vp and the negative voltage Vn based on the image signal A1 (digital signal). The source driving circuit 12 supplies the source signal to a plurality of source lines 12a. The source driving circuit 12 is an integrated circuit mounted on the substrate 1a.

[0020] The multiple terminals 13 are connected to a flexible printed circuit board (not shown). The multiple terminals 13 are connected to the timing control circuit 2, the level shifter circuit 3, and the power control circuit 4 via the flexible printed circuit board. The multiple terminals 13 are also connected to the gate drive circuit 11, the source drive circuit 12, and a common electrode wiring (not shown).

[0021] 3 is a schematic diagram showing a configuration of a pixel 10a in the display panel 1. As shown in FIG. 3, the pixel 10a is formed in an area defined by a plurality of gate lines 11a and a plurality of source lines 12a. The pixel 10a is provided with a thin film transistor 14 and a pixel electrode 15. The gate line 11a is connected to a gate electrode of the thin film transistor 14. The source line 12a is connected to a source electrode of the thin film transistor 14. The pixel electrode 15 is connected to a drain electrode of the thin film transistor 14. As a result, when a gate signal is input from the gate line 11a to the gate electrode of the thin film transistor 14, a source signal is supplied to the pixel electrode 15, and the pixel electrode 15 is charged (an image is written).

[0022] (Configuration of Timing Control Circuit) 1, the timing control circuit 2 receives a control signal D1 and an image signal A1 from a host controller 102. Then, the timing control circuit 2 supplies the image signal A1 to the display panel 1, and supplies a timing signal C1 to the level shifter circuit 3. The timing control circuit 2 is formed of, for example, an integrated circuit.

[0023] 4 is a functional block diagram of the timing control circuit 2 and the power control circuit 4. As shown in FIG. 4, the timing control circuit 2 includes a receiving unit 21, a level shifter control unit 22, an image signal control unit 23, a return operation control unit 24, and a pause signal transmitting unit 25. The receiving unit 21 receives an image signal A1 and a control signal D1 from the host controller 102. The level shifter control unit 22 transmits a timing signal C1 to the level shifter circuit 3 based on the image signal A1. The timing signal C1 includes a synchronization signal (e.g., a vertical synchronization signal) and a clock signal. The image signal control unit 23 transmits the image signal A1 to the source driving circuit 12 of the display panel 1.

[0024] When the receiving unit 21 receives a control signal D1 including a signal for transitioning from the display mode to the pause mode, the return operation control unit 24 stops the operation of the level shifter control unit 22 and stops the operation of the image signal control unit 23. This causes the supply of the timing signal C1 from the level shifter control unit 22 to stop. As the supply of the timing signal C1 stops, the gate driving circuit 11 stops outputting the gate signal. Also, the supply of the image signal A1 from the image signal control unit 23 stops. This causes the source driving circuit 12 to stop outputting the source signal. Then, the return operation control unit 24 transmits a signal to the pause signal transmitting unit 25 to instruct it to transmit the pause signal B1.

[0025] Furthermore, when the receiving unit 21 receives a control signal D1 including a signal for transitioning from the pause mode to the display mode, the return operation control unit 24 causes the level shifter control unit 22 to start (resume) operation and the image signal control unit 23 to start (resume) operation. This causes the level shifter control unit 22 to start supplying a timing signal C1. As a result of the start of supplying the timing signal C1, the gate driving circuit 11 starts outputting a gate signal. Also, the image signal control unit 23 starts supplying an image signal A1. This causes the source driving circuit 12 to start outputting a source signal. Then, the return operation control unit 24 transmits a signal to the pause signal transmitting unit 25 to instruct it to stop transmitting the pause signal B1.

[0026] The pause signal transmitting unit 25 transmits the pause signal B1 to the power control circuit 4 based on a command from the recovery operation control unit 24. For example, the pause signal transmitting unit 25 transmits the pause signal B1 by setting the level of the voltage applied to the signal line connected to the power control circuit 4 to High. Furthermore, the pause signal transmitting unit 25 stops transmitting the pause signal B1 by setting the level of the voltage applied to the signal line connected to the power control circuit 4 to Low based on a command from the recovery operation control unit 24.

[0027] (Configuration of Level Shifter Circuit) In the display mode, the level shifter circuit 3 generates a gate signal G1 based on the timing signal C1 from the timing control circuit 2, using the voltages VGH and VHL supplied from the power control circuit 4. The level shifter circuit 3 transmits the gate signal G1, which is a pulsed signal having the voltage VGH, to the multiple gate lines 11a in sequence via the gate drive circuit 11. The level shifter circuit 3 applies the voltage VGL to the multiple gate lines 11a other than the gate line 11a to which the gate signal G1 is being supplied.

[0028] (Configuration of power control circuit) The power control circuit 4 is a circuit that controls a state in which power is supplied and a state in which power supply is stopped for each of the display panel 1, the timing control circuit 2, and the level shifter circuit 3. As shown in FIG. 4, the power control circuit 4 includes a voltage detection unit 41, a power conversion unit 42, a reset signal control unit 43, and a power supply circuit control unit 44.

[0029] The voltage detection unit 41 detects the voltage V1 (voltage level is High) supplied from the host controller 102. Then, when the supply of the voltage V1 from the host controller 102 is stopped (when the voltage level becomes Low), the voltage detection unit 41 causes the reset signal control unit 43 to stop outputting the reset signal R1. Furthermore, when the supply of the voltage V1 from the host controller 102 is stopped, the voltage detection unit 41 causes the power conversion unit 42 to stop outputting the voltage. The supply of the voltage V1 from the host controller 102 is stopped, for example, when the power supply of the display system 100 is turned off and the supply of power to the host controller 102 is stopped.

[0030] The power conversion unit 42 converts the input voltage V1 into voltages V2, V3, VGH, VGL, Vp, Vn, and Vc, and supplies power having the converted voltages to the display panel 1, the level shifter circuit 3, the source driving circuit 12, and the timing control circuit 2. The power conversion unit 42 includes a switching element. The power conversion unit 42 turns on and off the input voltage at a switching frequency to generate a voltage having a predetermined voltage value. The power conversion unit 42 is, for example, a switching regulator of a pulse width modulation type.

[0031] The power conversion unit 42 includes a circuit power supply unit 42a, a timing control circuit power supply unit 42b, a level shifter power supply unit 42c, a source drive circuit power supply unit 42d, a common electrode power supply unit 42e, and a switching frequency control unit 42f. The switching frequency of the power conversion unit 42 is variable, and is determined based on a command from the switching frequency control unit 42f. For example, the switching frequency control unit 42f sets the switching frequency in the power conversion unit 42 to f1 in a display mode before the power supply circuit control unit 44 receives the pause signal B1 from the timing control circuit 2. Also, the switching frequency control unit 42f sets the switching frequency to f2, which is a frequency lower than f1, in a pause mode after the power supply circuit control unit 44 receives the pause signal B1 from the timing control circuit 2. That is, the switching frequency control unit 42f changes the switching frequency from f1 to f2 in response to receiving the pause signal B1. Also, the switching frequency control unit 42f changes the switching frequency from f2 to f1 in response to stopping the reception of the pause signal B1.

[0032] 5 is a schematic circuit diagram of the circuit power supply unit 42a. The circuit power supply unit 42a converts the voltage V1 output from the host controller 102 into a voltage V2 for operating the display panel 1, the timing control circuit 2, and the level shifter circuit 3. The circuit power supply unit 42a outputs the voltage V2 to the display panel 1, the timing control circuit 2, and the level shifter circuit 3. As an example of the voltage value, the voltage V1 is 3.3V, and the voltage V2 is 1.8V. The circuit power supply unit 42a includes, for example, switching elements SW1 and SW2, an inductor L1 connected to the output side of the switching elements SW1 and SW2, and a capacitor Ca1. The circuit power supply unit 42a generates a pulse width modulation signal (PWM signal) of a switching frequency set by the switching frequency control unit 42f, and switches the switching elements SW1 and SW2 based on the PWM signal. The switched voltage V1 is smoothed by the inductor L1 and the capacitor Ca1 to become the voltage V2.

[0033] The timing control circuit power supply unit 42b converts the voltage V1 output from the host controller 102 into a voltage V3 for operating the timing control circuit 2. Then, the timing control circuit power supply unit 42b outputs the voltage V3 to the timing control circuit 2. The voltage V3 has a different voltage value from the voltage V2. The circuit configuration of the timing control circuit power supply unit 42b is similar to that of the circuit power supply unit 42a, and therefore a description thereof will be omitted.

[0034] 6 is a schematic circuit diagram of the level shifter power supply unit 42c. The level shifter power supply unit 42c converts the voltage V1 output from the host controller 102 into voltages VGH and VGL used when the level shifter circuit 3 generates the gate signal G1. The level shifter power supply unit 42c outputs the voltages VGH and VGL to the level shifter circuit 3. The level shifter power supply unit 42c includes, for example, switching elements SW3 and SW4, an inductor L2 connected to the input sides of the switching elements SW3 and SW4, and a capacitor Ca2. The level shifter power supply unit 42c generates a pulse width modulation signal (PWM signal) having a switching frequency set by the switching frequency control unit 42f, and switches the switching elements SW3 and SW4 based on the PWM signal. Here, since the voltage V1 is input to the inductor L2, energy is stored in the inductor L1 during a period when the switching element SW3 is off and the switching element SW4 is on. As a result, when the switching element SW3 is on and the switching element SW4 is off, a voltage having a higher voltage value than the voltage V1 is output, and the voltage having a higher voltage value than the voltage V1 is smoothed to generate the voltage VGH. Although not shown, a portion of the level shifter power supply unit 42c that generates the voltage VGL generates a voltage with the polarity inverted with respect to the voltage VGH as the voltage VGL.

[0035] The source driving circuit power supply unit 42d converts the voltage V1 output from the host controller 102 into a positive voltage Vp and a negative voltage Vn used when the source driving circuit 12 generates a source signal. Then, the source driving circuit power supply unit 42d outputs the positive voltage Vp and the negative voltage Vn to the source driving circuit 12. The circuit configuration of the source driving circuit power supply unit 42d is similar to that of the level shifter power supply unit 42c, and therefore a description thereof will be omitted.

[0036] The common electrode power supply unit 42e converts the voltage V1 output from the host controller 102 into a voltage Vc to be applied to the common electrode of the display panel 1. Then, the common electrode power supply unit 42e outputs the voltage Vc to the display panel 1. The circuit configuration of the common electrode power supply unit 42e is similar to that of the level shifter power supply unit 42c, and therefore a description thereof will be omitted.

[0037] The reset signal control unit 43 outputs the reset signal R1 based on a command from the voltage detection unit 41. The level shifter circuit 3 and the source drive circuit 12 stop operating when the voltage level of the reset signal R1 changes from High to Low (OFF). That is, the level shifter circuit 3 (gate drive circuit 11) outputs a gate signal when the voltage level of the reset signal R1 is High, and stops outputting the gate signal when the voltage level of the reset signal R1 is Low. The source drive circuit 12 outputs a source signal when the voltage level of the reset signal R1 is High, and stops outputting the source signal when the voltage level of the reset signal R1 is Low.

[0038] The power supply circuit control unit 44 causes the switching frequency control unit 42f to change the switching frequency from f1 to f2 when the power supply circuit control unit 44 receives the pause signal B1 from the timing control circuit 2. Furthermore, when the power supply circuit control unit 44 stops receiving the pause signal B1 from the timing control circuit 2, the power supply circuit control unit 44 causes the switching frequency control unit 42f to change the switching frequency from f2 to f1.

[0039] Furthermore, when the power supply circuit control unit 44 receives the pause signal B1 from the timing control circuit 2, it stops the supply of power from the level shifter power supply unit 42c, the source driving circuit power supply unit 42d, and the common electrode power supply unit 42e while maintaining the supply of power from the circuit power supply unit 42a and the timing control circuit power supply unit 42b of the power conversion unit 42. As a result, the level shifter circuit 3 stops the operation (output of the gate signal) as the supply of power from the level shifter power supply unit 42c stops. Furthermore, the supply of power to the common electrode in the display panel 1 stops. Furthermore, the supply of power from the level shifter power supply unit 42c stops the operation of the source driving circuit 12 (output of the source signal). Furthermore, the supply of power to the timing control circuit 2 is maintained. As a result, the time required to start the timing control circuit 2 when the display panel 1 is resumed (when switching from the pause mode to the display mode) can be omitted, and the time required for the display panel 1 to resume display from the paused state can be shortened.

[0040] (Display system operation) Next, the operation of the display system 100 according to the first embodiment will be described.

[0041] In the first embodiment, as shown in Fig. 7, the supply of voltage V1 from the host controller 102 to the power control circuit 4 is performed in both the pause mode and the display mode. Here, in the pause mode before time point t1, the power control circuit 4 converts the input voltage V1 into voltages V2 and V3 by performing switching at a switching frequency f2. Then, in the pause mode, the voltages V2 and V3 are output. Also, in the pause mode, the output of the voltages Vp, Vn, Vc, VGH, and VGL, and the reset signal R1 is stopped.

[0042] Then, at time t1, when the mode transitions from the pause mode to the display mode, the host controller 102 transmits a control signal D1 including a signal for transitioning from the pause mode to the display mode to the timing control circuit 2. Then, the timing control circuit 2 starts supplying a timing signal C1 to the level shifter circuit 3, and starts supplying an image signal A1 to the source driving circuit 12.

[0043] Also, at time t1, the timing control circuit 2 stops supplying the pause signal B1 to the power control circuit 4. Also, even in the pause mode, the voltage V1 is applied to the power control circuit 4, and the output of the voltages V2 and V3 from the power control circuit 4 is maintained, so that at time t11, the voltages V2 and V3 are being output. Also, since the voltage V1 is applied to the power control circuit 4, the power control circuit 4 starts outputting the voltages Vp, Vn, Vc, VGH, and VGL, and the reset signal R1 after time t1, and the display panel 1 starts displaying at time t2. As a result, according to the first embodiment, display on the display panel 1 can be started in a short period from time t1, when the control signal D1 including the signal for transitioning from the pause mode to the display mode is received.

[0044] Then, at time t1, the switching frequency of the power conversion by the power control circuit 4 is changed from f2 to f1. This allows power conversion at a switching frequency higher than that in the sleep mode, so that even if the load fluctuates during display, it is possible to respond quickly. In addition, the high switching frequency reduces the effect of ripples on the display.

[0045] Also, at time t3, when the display mode is switched to the pause mode, the host controller 102 transmits a control signal D1 including a signal for switching from the display mode to the pause mode to the timing control circuit 2. Then, the switching frequency of the power conversion by the power control circuit 4 is changed from f1 to f2. As a result, in the pause mode, the power conversion by the power control circuit 4 can be performed at a lower switching frequency. Therefore, it is possible to reduce power consumption during the period when the control process in the pause mode is being executed. Furthermore, by performing the power conversion at a low switching frequency, it is possible to suppress the generation of noise in the pause mode. Furthermore, by performing the power conversion at a low switching frequency, it is possible to improve the power conversion efficiency in the power conversion in the pause mode.

[0046] [Second embodiment] Next, the configuration of a display system 200 according to a second embodiment will be described with reference to Fig. 8. In the first embodiment, an example was shown in which the pause signal B1 was transmitted by changing the voltage level of one signal line to High or Low, but in the second embodiment, the pause signal B1 is transmitted by a command. Note that the same components as those in the first embodiment are given the same reference numerals and will not be described.

[0047] As shown in FIG. 8, the display system 200 includes a display device 201. The display device 201 includes a timing control circuit 202 and a power control circuit 204. The timing control circuit 202 according to the second embodiment is connected to the power control circuit 204 via an I2C bus and performs serial communication with the power control circuit 204. The pause signal transmission unit 225 of the timing control circuit 202 transmits a pause signal B1 as a command in the serial communication. When the power supply circuit control unit 244 of the power control circuit 204 receives the command, it changes the switching frequency from f1 to f2. When the power supply circuit control unit 244 receives the command, it stops the supply of power from the level shifter power supply unit 42c, the source drive circuit power supply unit 42d, and the common electrode power supply unit 42e while maintaining the supply of power from the circuit power supply unit 42a and the timing control circuit power supply unit 42b of the power conversion unit 42. Other configurations and effects are the same as those of the first embodiment.

[0048] [Third embodiment] Next, the configuration of a display system 300 according to a third embodiment will be described with reference to Fig. 9. In the third embodiment, when a power control circuit 204 receives a pause signal B1, the power control circuit 204 not only maintains the supply of power to the timing control circuit 202, but also maintains the supply of power to the display panel 1, the level shifter circuit 3, and the source driving circuit 12. Note that the same components as those in the first embodiment are denoted by the same reference numerals and will not be described.

[0049] 9, a display system 300 includes a display device 301. The display device 301 includes a power control circuit 304. The power control circuit 304 includes a power conversion unit 342 and a power supply circuit control unit 344. The power conversion unit 342 according to the third embodiment includes a level shifter circuit 342c, a source drive circuit 342d, a common electrode power supply unit 342e, and a switching frequency control unit 342f.

[0050] When the switching frequency control unit 342f receives a pause signal B1 from the timing control circuit 2, it changes the switching frequency from f1 to f2. Then, the level shifter circuit 342c, the source drive circuit 342d, and the common electrode power supply unit 342e perform power conversion at a switching frequency of f2. Then, the level shifter circuit 342c outputs voltages VGH and VGL even in the pause mode. Also, the source drive circuit 342d outputs voltages Vp and Vn even in the pause mode. Also, the common electrode power supply unit 342e outputs Vc even in the pause mode. Here, since the timing control circuit 2 does not output the timing signal C1 and the image signal A1 in the pause mode, no image is displayed on the display panel 1 (display is paused) even if the voltages VGH and VGL are output from the power conversion unit 342. The other configurations and effects are the same as those of the first embodiment.

[0051] [Variations] Although the embodiment of the invention has been described above, the above-mentioned embodiment is merely an example for carrying out the invention. Therefore, the present invention is not limited to the above-mentioned embodiment, and can be appropriately modified and carried out without departing from the spirit of the invention. Below, a modified example of the above-mentioned embodiment will be described.

[0052] (1) In the above first to third embodiments, the host controller supplies the voltage V1 to the power control circuit, but the present disclosure is not limited to this. That is, the voltage V1 may be supplied to the power control circuit from a power supply circuit other than the host controller.

[0053] (2) In the first to third embodiments, the switching frequency of all the power conversions by the power conversion unit is set to f2 in the pause mode, but the present disclosure is not limited to this. That is, in the pause mode, only the switching frequency of some of the power conversions by the power conversion unit (for example, the switching frequency when converting from voltage V1 to voltage V2) may be changed to f2, and the switching frequency of the other power conversions may be set to f1.

[0054] (3) In the above first to third embodiments, the display panel is provided with a GDM, but the present disclosure is not limited to this. An integrated circuit (gate driver) including a level shifter circuit may be mounted on the substrate.

[0055] (4) In the above first to third embodiments, the display driver circuit of the present disclosure is configured as a level shifter circuit, but the present disclosure is not limited to this. A driver circuit that sequentially supplies gate signals to a plurality of gate lines may be configured without using a level shifter circuit.

[0056] The above-mentioned configuration can also be explained as follows.

[0057] A display device according to a first configuration includes a display panel, a display drive circuit that supplies a drive signal to the display panel, a timing control circuit that supplies an image signal to the display panel and a timing signal to the display drive circuit, and a power conversion circuit that converts an input voltage, which is the voltage of an input power, into an output voltage and supplies power having the output voltage to at least one of the display panel, the display drive circuit, and the timing control circuit. When the timing control circuit receives a control signal from a host controller to transition from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, the timing control circuit transmits a pause signal to the power conversion circuit, and in the display mode before receiving the pause signal, the power conversion circuit converts the input voltage to the output voltage at a first switching frequency, and in the pause mode after receiving the pause signal from the timing control circuit, converts the input voltage to the output voltage at a second switching frequency lower than the first switching frequency (first configuration).

[0058] Here, the power consumption in the power conversion can be reduced as the switching frequency is lower. According to the first configuration, during the period in which the control process in the pause mode is being executed, the power conversion by the power conversion circuit can be performed at a lower switching frequency. Therefore, during the period in which the control process in the pause mode is being executed, the power consumption can be reduced. Furthermore, by performing the power conversion at a low switching frequency, the generation of noise in the pause mode can be suppressed. Furthermore, by performing the power conversion at a low switching frequency, the power conversion efficiency in the power conversion in the pause mode can be improved. Furthermore, during the period in which the display panel is performing display, the input voltage can be converted into an output voltage at a switching frequency higher than that in the pause mode, so that even if the load fluctuates during display, a quick response can be made. Furthermore, the high switching frequency can reduce the effect of ripples on the display.

[0059] In a first configuration, the power conversion circuit may be configured to supply power to the timing control circuit, the display panel, and the display driving circuit in the display mode, and when the pause signal is received, to stop a portion of the power supply to the display panel and the display driving circuit while maintaining the supply of power to the timing control circuit, and to convert the output voltage of the power supplied from the input voltage to the timing control circuit using the second switching frequency in the pause mode (second configuration).

[0060] According to the second configuration, since power is supplied to the timing control circuit even during the control process in the pause mode, it is not necessary to start up the timing control circuit when changing from the pause mode to the display mode, and therefore the time required to change from the pause mode to the display mode can be shortened.

[0061] In the second configuration, the power conversion circuit may be configured, when it receives the pause signal, to stop the supply of power to the display panel and the display driving circuit while maintaining the supply of power to the timing control circuit (third configuration).

[0062] According to the third configuration, during the period when the control process in the pause mode is being executed, the supply of power to the display panel and the display drive circuit is stopped, thereby making it possible to further reduce power consumption.

[0063] A display system according to a fourth configuration is a display system including a display device having a display panel, and a host controller that transmits a control signal to the display device to switch from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, the display device including a display drive circuit that supplies a drive signal to the display panel, a timing control circuit that supplies an image signal to the display panel and supplies a timing signal to the display drive circuit, and a timing control circuit that converts an input voltage, which is the voltage of input power, into an output voltage and supplies power having the output voltage to at least one of the display panel, the display drive circuit, and the timing control circuit. and a power conversion circuit that supplies a power to the display panel, wherein the timing control circuit, when receiving a control signal from a host controller to transition from a display mode in which the display panel displays data to a pause mode in which the display panel stops displaying data, transmits a pause signal to the power conversion circuit, and the power conversion circuit, in the display mode before receiving the pause signal, converts the input voltage to the output voltage at a first switching frequency, and in the pause mode after receiving the pause signal from the timing control circuit, converts the input voltage to the output voltage at a second switching frequency lower than the first switching frequency (fourth configuration).

[0064] According to the fourth configuration, it is possible to provide a display system capable of reducing power consumption during the period when the control process in the sleep mode is being executed. [Explanation of symbols]

[0065] 1: display panel, 2, 202: timing control circuit, 3: level shifter circuit, 4, 204, 304: power control circuit, 10: display unit, 10a: pixel, 11: gate drive circuit, 11a: gate line, 12: source drive circuit, 12a: source line, 13: terminal, 14: thin film transistor, 15: pixel electrode, 21: receiving unit, 22: level shifter control unit, 23: image signal control unit, 24: recovery operation control unit, 25, 225: pause signal transmission unit, 41: voltage detection unit, 42, 342: power conversion unit, 42a: circuit power supply unit, 42b: timing control circuit power supply unit, 42c, 342c: level shifter power supply unit, 42d, 342d: source drive circuit power supply unit, 42e, 342e: common electrode power supply unit, 42f, 342f: switching frequency control unit, 43: reset signal control unit, 44, 244, 344: power supply circuit control unit, 100, 200, 300: display system, 101, 201, 301: display device, 102: host controller, A1: image signal, B1: pause signal, C1: timing signal, D1: control signal

Claims

1. A display panel; a display drive circuit for supplying a drive signal to the display panel; a timing control circuit for supplying an image signal to the display panel and a timing signal to the display drive circuit; a power conversion circuit that converts an input voltage, which is a voltage of an input power, into an output voltage and supplies power having the output voltage to at least one of the display panel, the display drive circuit, and the timing control circuit; the timing control circuit, when receiving from a host controller a control signal for transitioning from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, transmits a pause signal to the power conversion circuit; The power conversion circuit includes: converting the input voltage to the output voltage at a first switching frequency in the display mode before receiving the pause signal; The display device converts the input voltage to the output voltage at a second switching frequency lower than the first switching frequency in the sleep mode after receiving the sleep signal from the timing control circuit.

2. The power conversion circuit includes: In the display mode, power is supplied to the timing control circuit, the display panel, and the display drive circuit; when the pause signal is received, a part of the power supply to the display panel and the display drive circuit is stopped while maintaining the power supply to the timing control circuit; 2 . The display device according to claim 1 , wherein in the sleep mode, an output voltage of power supplied from the input voltage to the timing control circuit is converted at the second switching frequency.

3. 3 . The display device according to claim 2 , wherein the power conversion circuit, when receiving the pause signal, stops the supply of power to the display panel and the display drive circuit while maintaining the supply of power to the timing control circuit.

4. A display device having a display panel; a host controller that transmits a control signal to the display device to switch from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, The display device includes: a display drive circuit for supplying a drive signal to the display panel; a timing control circuit that supplies an image signal to the display panel and a timing signal to the display drive circuit; a power conversion circuit that converts an input voltage, which is a voltage of an input power, into an output voltage and supplies power having the output voltage to at least one of the display panel, the display drive circuit, and the timing control circuit; the timing control circuit, when receiving from a host controller a control signal for transitioning from a display mode in which display is performed by the display panel to a pause mode in which display by the display panel is stopped, transmits a pause signal to the power conversion circuit; The power conversion circuit includes: converting the input voltage to the output voltage at a first switching frequency in the display mode before receiving the pause signal; The display system converts the input voltage to the output voltage at a second switching frequency lower than the first switching frequency in the sleep mode after receiving the sleep signal from the timing control circuit.

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