Semiconductor device

Abstract

To provide a technique that can suppress heat generation in a first semiconductor switching element and a second semiconductor switching element.SOLUTION: A semiconductor device includes a gate driving circuit that drives each of a first semiconductor switching element and a second semiconductor switching element based on an input signal. The gate driving circuit turns off the first semiconductor switching element after turning off the second semiconductor switching element regardless of the input signal when a first gate voltage applied to a first gate for turning on the first semiconductor switching element is lower than a first threshold value.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of inexpensive Si (silicon) have been commonly used as power elements for inverter devices for driving motors, etc. On the other hand, in recent years, the use of high-efficiency power elements made of SiC (silicon carbide) or GaN (gallium nitride), which are WGB (wide band gap) semiconductors, has been increasing.

[0003] However, because WGB semiconductors are expensive, they have not been widely used in cost-conscious consumer devices. Therefore, for applications that require long periods of low-current operation, such as the drive motors of compressors in home air conditioners, it has been proposed to use parallel circuits in products that are configured by connecting small-sized SiC-MOSFETs and Si-IGBTs in parallel (for example, Patent Document 1). Such products are expected to reduce costs due to the small size of SiC-MOSFETs, and improve efficiency (i.e., reduce losses) due to the good DC characteristics of SiC-MOSFETs at low currents. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6544316 Summary of the Invention [Problem to be solved by the invention]

[0005] When the gate voltage applied to the gate to turn on the power element decreases, the on-voltage increases (i.e., the DC characteristics deteriorate). As a result, the loss increases and the heat generated by the power element increases, which may cause a malfunction of the power element. Therefore, a configuration has been proposed in which a protection circuit is provided to suppress heat generation by the power element by turning off the power element when the gate voltage falls below a specified value.

[0006] However, for example, when the gate voltage of the Si-IGBT in the parallel circuit described above drops and the Si-IGBT of the power element is turned off, if the SiC-MOSFET connected in parallel is on, all the current flows in, causing high heat generation and causing a malfunction in the SiC-MOSFET.

[0007] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a technology that can suppress heat generation from a first semiconductor switching element and a second semiconductor switching element such as a Si element and a SiC element. [Means for solving the problem]

[0008] The semiconductor device disclosed herein comprises a first semiconductor switching element having a first gate; a second semiconductor switching element connected in parallel to the first semiconductor switching element, having a second gate, having a larger band gap than the first semiconductor switching element and a lower current carrying capacity than the first semiconductor switching element; and a gate drive circuit that drives each of the first semiconductor switching element and the second semiconductor switching element based on an input signal, wherein when a first gate voltage applied to the first gate to turn on the first semiconductor switching element is lower than a first threshold value, the gate drive circuit turns off the second semiconductor switching element and then the first semiconductor switching element regardless of the input signal. Effect of the Invention

[0009] According to the present disclosure, when the first gate voltage is lower than the first threshold, the gate drive circuit turns off the second semiconductor switching element and then the first semiconductor switching element regardless of the input signal. With this configuration, heat generation in the first semiconductor switching element and the second semiconductor switching element can be suppressed. [Brief description of the drawings]

[0010] [Figure 1] 1 is a perspective view showing an external configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view showing an internal configuration of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a diagram showing an application example of the semiconductor device according to the first embodiment; [Figure 4] 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment; [Diagram 5] 1 is a timing chart showing an operation of a related semiconductor device. [Figure 6] 4 is a timing chart showing an operation of the semiconductor device according to the first embodiment. [Figure 7] FIG. 11 is a diagram showing a change in current when the first gate voltage remains unchanged and the second gate voltage decreases. [Figure 8] 1 is a timing chart illustrating a specific situation. [Figure 9] FIG. 11 is a diagram showing a configuration of a semiconductor device according to a second embodiment. [Figure 10] 10 is a timing chart showing an operation of the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a diagram showing a configuration of a semiconductor device according to a third embodiment. [Figure 12] FIG. 13 is a diagram showing a configuration of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a waveform output from the semiconductor device according to the fourth embodiment. [Figure 14] FIG. 11 is a diagram showing a change in current when the second gate voltage increases without changing the first gate voltage. [Figure 15] FIG. 13 is a diagram showing a configuration of a semiconductor device according to a fifth embodiment. [Figure 16] 13 is a timing chart showing the operation of the semiconductor device according to the fifth embodiment. [Figure 17] FIG. 13 is a diagram showing a configuration of a semiconductor device according to a fifth embodiment. [Figure 18] 13 is a timing chart showing the operation of the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In the following description, the same or similar reference numerals are used to denote similar components in multiple embodiments, and different components will be mainly described.

[0012] <Embodiment 1> Fig. 1 is a perspective view showing an external configuration of a semiconductor device according to the present embodiment 1, and Fig. 2 is a plan view showing an internal configuration of the semiconductor device. As shown in Fig. 2, the semiconductor device according to the present embodiment 1 includes a parallel circuit 1, a gate drive circuit 2, a lead frame 6, and a sealing member 7.

[0013] The parallel circuit 1 includes a first semiconductor switching element having a first gate and a second switching element having a second gate, and the first semiconductor switching element and the second switching element are connected in parallel.

[0014] In the present embodiment 1, the first semiconductor switching element is a Si element 1a made of Si (silicon). In the following description, the Si element 1a is an IGBT, but is not limited to an IGBT and may be an RC-IGBT (Reverse Conducting - IGBT) or a MOSFET.

[0015] In the present embodiment 1, the second semiconductor switching element is a SiC element 1b made of SiC (silicon carbide). However, the second semiconductor switching element is not limited to this as long as it has a larger band gap than the first semiconductor switching element, a small size and a low current carrying capacity. For example, the second semiconductor switching element may be an element made of a WBG (Wide Band Gap) semiconductor such as GaN or diamond. The SiC element 1b made of SiC can improve efficiency, that is, reduce losses.

[0016] In the following description, the SiC element 1b is assumed to be a MOSFET which is particularly effective at low current and low loss, but the SiC element 1b is not limited to this and may be an IGBT or the like.

[0017] The fact that the SiC element 1b has a lower current carrying capacity than the Si element 1a corresponds to, for example, the saturation current value of the SiC element 1b being smaller than the saturation current value of the Si element 1a for an applied gate voltage. By lowering the current carrying capacity of the SiC element 1b, the size of the SiC element 1b can be made smaller than the size of the Si element 1a, so that the cost of the semiconductor device can be reduced. Even if the current carrying capacity is reduced, the on-voltage of the SiC element 1b made of a WBG semiconductor at low current can be made lower than the on-voltage of the Si element 1a, so that loss can be reduced.

[0018] The gate drive circuit 2 is connected to the first gate of the Si element 1a and the second gate of the SiC element 1b, and drives each of the Si element 1a and the SiC element 1b as described below. The lead frame 6 is electrically connected to the parallel circuit 1 and the gate drive circuit 2. As shown in Figures 1 and 2, the sealing member 7 covers the parallel circuit 1, the gate drive circuit 2, and the lead frame 6 with a part of the lead frame 6 exposed.

[0019] 2, the number of parallel circuits 1 is six and the number of gate drive circuits 2 is two, but this is not limited thereto. For example, as shown in FIG. 3, a three-phase motor drive circuit may be configured by connecting six parallel circuits 1 and six gate drive circuits 2 to a drive motor 8 that drives a compressor of a home appliance such as an air conditioner. For convenience of explanation, the following description will be given taking as an example a configuration in which one gate drive circuit 2 is provided for one parallel circuit 1.

[0020] FIG. 4 is a diagram showing the configuration of the semiconductor device according to the present embodiment 1, specifically, a diagram showing the detailed configurations of the parallel circuit 1 and the gate drive circuit 2 according to the present embodiment 1.

[0021] The collector and emitter of the Si element 1a are connected to the drain and source of the SiC element 1b, respectively, to form a parallel circuit 1. The first gate of the Si element 1a and the second gate of the SiC element 1b are connected to a gate drive circuit 2.

[0022] An outline of the gate drive circuit 2 will be given before a detailed description thereof. An input signal that can be selectively turned on or off is input to the gate drive circuit 2 from an external controller such as a microcomputer (not shown).

[0023] The gate drive circuit 2 drives each of the Si element 1a and the SiC element 1b based on an input signal. In the present embodiment 1, the gate drive circuit 2, in principle, turns on the Si element 1a and the SiC element 1b when the input signal is on, and turns off the Si element 1a and the SiC element 1b when the input signal is off.

[0024] However, as an exception to the above operation, when the first gate voltage is lower than the first threshold, the gate drive circuit 2 turns off the SiC element 1b and then the Si element 1a regardless of the input signal. The first gate voltage is a voltage applied to the first gate of the Si element 1a to turn on the Si element 1a. The second gate voltage, which will be described later, is a voltage applied to the second gate of the SiC element 1b to turn on the SiC element 1b.

[0025] Next, the gate drive circuit 2 will be described in detail. The gate drive circuit 2 includes a buffer circuit 2a, a control circuit 2b, a first buffer circuit 2c, a second buffer circuit 2d, and a power supply voltage drop protection circuit 2e. Each of the buffer circuit 2a, the control circuit 2b, the first buffer circuit 2c, the second buffer circuit 2d, and the power supply voltage drop protection circuit 2e is a logic circuit.

[0026] The buffer circuit 2a maintains the logical value of the input signal and outputs it.

[0027] The control circuit 2b turns on the Si element 1a and the SiC element 1b when the input signal inputted through the buffer circuit 2a is switched on, and turns off the Si element 1a and the SiC element 1b when the input signal is switched off. As an example, the control circuit 2b may turn on the Si element 1a and then turn on the SiC element 1b when the input signal is switched on, and turn off the Si element 1a and then turn off the SiC element 1b when the input signal is switched off. That is, the control circuit 2b may be configured to provide a time difference between the ON of the Si element 1a and the SiC element 1b, and to provide a time difference between the OFF of the Si element 1a and the SiC element 1b. As a result, the current flowing only through the Si element 1a that was turned on first is diverted to the SiC element 1b at a ratio according to the difference in DC characteristics between the elements.

[0028] When the control circuit 2b turns on the Si element 1a, the first buffer circuit 2c applies the voltage V1 supplied from the outside to the first gate of the Si element 1a. As a result, the first gate voltage is substantially the same as the voltage V1, and therefore may be referred to as the first gate voltage V1 in the following description. For example, a voltage of about 15V is used as the first gate voltage V1, but a voltage of another value may be used depending on the characteristics of the Si element 1a.

[0029] When the control circuit 2b turns on the SiC device 1b, the second buffer circuit 2d applies the voltage V2 supplied from the outside to the second gate of the SiC device 1b. As a result, the second gate voltage is substantially the same as the voltage V2, and therefore may be referred to as the second gate voltage V2 in the following description. For example, a voltage of about 15V is used as the second gate voltage V2, but a voltage of another value may be used depending on the characteristics of the SiC device 1b.

[0030] In the above configuration in which voltages V1 and V2 are supplied from the outside, if voltages V1 and V2 drop for some reason, such as an abnormality, the on-voltage of the Si element 1a and the SiC element 1b rises (i.e., DC characteristics deteriorate). As a result, loss increases and heat generation in these elements increases, which may cause malfunctions in the Si element 1a and the SiC element 1b. Therefore, the control circuit 2b and the power supply voltage drop protection circuit 2e have a protection function for suppressing heat generation in the Si element 1a and the SiC element 1b. Next, this protection function will be described.

[0031] The power supply voltage drop protection circuit 2e according to the first embodiment includes a first comparator 2e1. The first comparator 2e1 compares the first gate voltage V1 with a threshold voltage Vth1 corresponding to a predefined first threshold. The threshold voltage Vth1 is, for example, a voltage lower than the standard first gate voltage V1 in normal operation by a certain voltage (for example, 2 to 3 V) and higher than the gate threshold of the Si element 1a, and may be changed to a voltage of an appropriate value according to the characteristics of the Si element 1a. The first comparator 2e1 outputs different output signals to the control circuit 2b when the first gate voltage V1 is equal to or higher than the threshold voltage Vth1 and when it is lower than the threshold voltage Vth1. For example, a comparator is used as the first comparator 2e1.

[0032] When the control circuit 2b receives an output signal from the first comparator 2e1 in which the first gate voltage V1 is lower than the threshold voltage Vth1, the control circuit 2b turns off the SiC device 1b and then turns off the Si device 1a regardless of the input signal.

[0033] 5 is a timing chart showing the operation of a related semiconductor device related to the semiconductor device according to the first embodiment. When the first gate voltage V1 is lower than the threshold voltage Vth1, the related semiconductor device turns off the Si element 1a and keeps the SiC element 1b on. With this configuration, the Si element 1a, which has become high in loss due to a drop in the first gate voltage V1, is stopped, so that heat generation by the Si element 1a can be suppressed.

[0034] However, when the Si element 1a is stopped, the current that had been flowing through the Si element 1a flows through the SiC element 1b, which may increase heat generation in the SiC element 1b and cause a malfunction in the SiC element 1b. This possibility is particularly high in compressor drive motors for home appliances such as home air conditioners, in which the size of the SiC element 1b is reduced to reduce the cost of the semiconductor device and the DC characteristics of the SiC element 1b are improved to reduce losses.

[0035] 6 is a timing chart showing the operation of the semiconductor device according to the first embodiment. When the first gate voltage V1 is lower than the threshold voltage Vth1, the semiconductor device according to the first embodiment turns off the SiC element 1b and then the Si element 1a regardless of the input signal. With this configuration, not only can heat generation in the Si element 1a be suppressed, but also heat generation in the SiC element 1b can be suppressed. In FIG. 6, the on-current of the SiC element 1b is smaller than the on-current of the Si element 1a, reflecting the fact that the SiC element 1b has a lower current carrying capacity than the Si element 1a.

[0036] Incidentally, the semiconductor device according to the first embodiment protects the Si element 1a and the SiC element 1b by monitoring a drop in the first gate voltage V1 using the power supply voltage drop protection circuit 2e and the control circuit 2b, but does not monitor a drop in the second gate voltage V2. The reason for this will be explained below.

[0037] 7 is a diagram showing changes in current flowing through the Si element 1a and the SiC element 1b when the second gate voltage V2 decreases while the first gate voltage V1 remains unchanged. The horizontal axis indicates the voltage applied between the collector and emitter of the Si element 1a and between the drain and source of the SiC element 1b (hereinafter referred to as "voltage across both ends"), and the vertical axis indicates the on-current of the Si element 1a and the SiC element 1b.

[0038] The dotted line in Fig. 7 indicates the relationship between the voltage across both ends (i.e., on-voltage) and on-current of the Si element 1a, and the thin solid line and two-dot chain line in Fig. 7 indicate the relationship between the voltage across both ends and on-current of the SiC element 1b. The thick solid line and two-dot chain line in Fig. 7 indicate the relationship between the voltage across both ends and on-current of the parallel circuit 1, which essentially corresponds to the sum of the relationship between the voltage across both ends and on-current of the Si element 1a and the relationship between the voltage across both ends and on-current of the SiC element 1b. The two-dot chain line indicates the relationship between the voltage across both ends and on-current before the second gate voltage V2 is lowered, and the solid line indicates the relationship between the voltage across both ends and on-current after the second gate voltage V2 is lowered.

[0039] Before the second gate voltage V2 is lowered, the voltages across the Si element 1a and the SiC element 1b are V on1and the on-current of the Si element 1a is I A1 and the on-current of the SiC element 1b is I B1 and the on-current of the parallel circuit 1 is I T (=I A1 +I B1 ) The on-current of the Si element 1a and the on-current of the SiC element 1b are significantly different between FIG. 6 and FIG. 7. This is because in FIG. T This is because the relationship when I is a large current is shown in Figure 7 for convenience. T This is because the relationship in the case of a small current is illustrated.

[0040] When the second gate voltage V2 decreases, the current does not easily flow through the SiC element 1b, so the slope of the thin solid line decreases from the thin double-dashed line. Even if the second gate voltage V2 decreases, the on-current (I T ) is maintained, the voltage across the on1 From big V on2 As a result, the on-current of the Si element 1a is changed to I A1 From I A2 However, the on-current of the SiC element 1b is I B1 From I B2 and I T =I A2 +I B2 holds true.

[0041] Since the current carrying capacity of the Si element 1a is higher than that of the SiC element 1b, and the allowable current of the Si element 1a is larger than that of the SiC element 1b, no problem occurs in the Si element 1a even if the on-current of the Si element 1a becomes slightly larger. Therefore, although the efficiency deteriorates somewhat, the system can continue to operate by monitoring the decrease in the on-current of the parallel circuit 1 without monitoring the decrease in the second gate voltage V2.

[0042] <Summary of the first embodiment> According to the semiconductor device of the first embodiment as described above, when the first gate voltage is lower than the first threshold, the gate drive circuit 2 turns off the SiC element 1b and then the Si element 1a, regardless of the input signal. With this configuration, heat generation in the Si element 1a and the SiC element 1b can be suppressed, and defects caused in the Si element 1a and the SiC element 1b due to the heat can be suppressed. Furthermore, in the first embodiment, a circuit for monitoring the decrease in the second gate voltage V2 is not required, and therefore simplification, miniaturization, and cost reduction of the semiconductor device can be expected.

[0043] <Embodiment 2> In the first embodiment, a drop in the second gate voltage V2 does not cause a problem in system operation, so the gate drive circuit 2 protects the Si device 1a and the SiC device 1b by monitoring only a drop in the first gate voltage V1.

[0044] However, a drop in the second gate voltage V2 may cause a specific undesirable situation. For example, as shown in FIG. 8, the specific situation may be a situation in which the second gate voltage V2 drops to the gate threshold of the SiC element 1b, and the SiC element 1b repeats insufficient on and off due to the second gate voltage V2 dropping to the gate threshold and rising and falling repeatedly around the gate threshold in a short period of time. In this case, gate oscillation or the like may occur, which may lead to a malfunction of the semiconductor device. Therefore, the semiconductor device according to the second embodiment is configured to protect the Si element 1a and the SiC element 1b by monitoring the drop in the second gate voltage V2 in order to avoid the specific situation, as described below.

[0045] 9 is a diagram showing the configuration of a semiconductor device according to the present embodiment 2, specifically, a diagram showing in detail the configurations of the parallel circuit 1 and the gate drive circuit 2 according to the present embodiment 2. The configuration in FIG. 9 is similar to the configuration in FIG. 4 in which a second comparator 2e2 is added to the power supply voltage drop protection circuit 2e.

[0046] The second comparator 2e2 compares the second gate voltage V2 with a threshold voltage Vth2 corresponding to a predefined second threshold. The threshold voltage Vth2 is, for example, a voltage lower than the standard second gate voltage V2 in normal operation by a certain voltage (for example, 2 to 3 V) and is a voltage higher than the gate threshold of the SiC element 1b, and may be changed to a voltage of an appropriate value according to the characteristics of the SiC element 1b. The second comparator 2e2 outputs different output signals to the control circuit 2b when the second gate voltage V2 is equal to or higher than the threshold voltage Vth2 and when it is lower than the threshold voltage Vth2. For example, a comparator is used as the second comparator 2e2.

[0047] As shown in FIG. 10, when the control circuit 2b receives an output signal from the second comparator 2e2 when the second gate voltage V2 is lower than the threshold voltage Vth2, the control circuit 2b turns off the SiC element 1b regardless of the input signal. In the second embodiment, the control circuit 2b turns off the SiC element 1b when the second gate voltage V2 is lower than the threshold voltage Vth2, but continues to drive the Si element 1a based on the input signal. In this case, the current that flowed through the SiC element 1b flows through the Si element 1a. However, since the current carrying capacity of the Si element 1a is higher than that of the SiC element 1b, and the allowable current of the Si element 1a has a margin larger than that of the SiC element 1b, even if the on-current of the Si element 1a becomes somewhat large, no problem occurs in the Si element 1a.

[0048] <Summary of the second embodiment> According to the semiconductor device of the second embodiment as described above, the gate drive circuit 2 turns off the SiC device 1b regardless of the input signal when the second gate voltage is lower than the second threshold value. With this configuration, it is possible to avoid the specific situation as shown in FIG.

[0049] <Embodiment 3> In the first embodiment, the gate drive circuit 2 continues the operation of the system even when the second gate voltage V2 drops. However, when the second gate voltage V2 drops, the efficiency of the system deteriorates, so it is preferable to notify the user of the occurrence of an abnormality and urge the user to repair the system. Therefore, the semiconductor device according to the third embodiment is configured to perform such a notification as described below.

[0050] 11 is a diagram showing the configuration of a semiconductor device according to the present embodiment 3, specifically, a diagram showing in detail the configurations of the parallel circuit 1 and the gate drive circuit 2 according to the present embodiment 3. The configuration in FIG. 11 is similar to the configuration in FIG. 4 in which a power supply voltage drop detection circuit 2f is added to the gate drive circuit 2.

[0051] When the second gate voltage V2 is lower than a threshold voltage Vth2 corresponding to a predefined second threshold, the power supply voltage drop detection circuit 2f outputs a first abnormality signal from an output terminal 2g1 to an external controller. The power supply voltage drop detection circuit 2f includes a comparator similar to the second comparator 2e2 described in the second embodiment.

[0052] When the control circuit 2b detects an abnormality different from the first abnormality signal in the semiconductor device and stops operation of the system, it outputs a second abnormality signal indicating the abnormality different from the first abnormality signal from the output terminal 2g2 to an external controller.

[0053] <Summary of the Third Embodiment> According to the semiconductor device of the third embodiment, the gate drive circuit 2 outputs a first abnormality signal to an external controller when the second gate voltage is lower than the second threshold. With this configuration, it is possible to urge a user to repair the device by notifying the external controller that the second gate voltage is low while continuing the operation of the system.

[0054] <Fourth embodiment> 12 is a diagram showing the configuration of a semiconductor device according to the present embodiment 4, specifically, a diagram showing in detail the configurations of the parallel circuit 1 and the gate drive circuit 2 according to the present embodiment 4. The configuration in FIG. 12 is similar to the configuration in FIG. 11 in which an abnormality signal output circuit 2h is added to the gate drive circuit 2.

[0055] The abnormality signal output circuit 2h outputs the first abnormality signal from the power supply voltage drop detection circuit 2f and the second abnormality signal from the control circuit 2b in mutually distinguishable waveforms from one output terminal 2g3.

[0056] Fig. 13 is a diagram showing an example of a waveform output from the abnormality signal output circuit 2h. Fig. 13 (1) shows a waveform when the power supply voltage drop detection circuit 2f does not detect the first abnormality and the control circuit 2b detects the second abnormality (e.g., a drop in the first gate voltage V1). In this case, a second abnormality signal with an output level L2 is output. Although not shown, when the power supply voltage drop detection circuit 2f does not detect the first abnormality and the control circuit 2b does not detect the second abnormality, a steady signal with an output level L0 is output to the external controller.

[0057] (2) and (3) in FIG. 13 show waveforms when the control circuit 2b does not detect the second abnormality and the power supply voltage drop detection circuit 2f detects the first abnormality (the second gate voltage V2 lower than the threshold voltage Vth2).

[0058] 13(2), when the power supply voltage drop detection circuit 2f detects a first abnormality, a first abnormality signal having an output level L1 different from the output level L2 of the second abnormality signal is output. In this case, the external controller can distinguish between the first abnormality signal and the second abnormality signal based on the difference in output level.

[0059] 13(3), when the power supply voltage drop detection circuit 2f detects a first abnormality, a first abnormality signal having the same output level as the output level L2 of the second abnormality signal is output intermittently for an output time T1. In this case, the external controller can distinguish between the first abnormality signal and the second abnormality signal based on the difference in output time.

[0060] FIG. 13(4) shows waveforms when the power supply voltage drop detection circuit 2f and the control circuit 2b detect the first and second abnormalities, respectively. In the case of FIG. 13(4), since the second abnormality is detected after the first abnormality, the abnormality signal transitions from the first abnormality signal having the output level L1 indicating the first abnormality state to the second abnormality signal having the output level L2 indicating the second abnormality state. Since the second abnormality is an abnormality in which both the Si element 1a and the SiC element 1b are turned off and the system stops, the output of the second abnormality signal is continued with priority over the output of the first abnormality signal. Although not shown here, even when the first abnormality is detected after the second abnormality, the output of the second abnormality signal is continued with priority over the output of the first abnormality signal.

[0061] <Summary of the fourth embodiment> According to the semiconductor device of the fourth embodiment, the gate drive circuit 2 outputs the first abnormality signal and the second abnormality signal from one output terminal 2g3 to the outside with mutually distinguishable waveforms. With such a configuration, the number of output terminals of the gate drive circuit 2 can be reduced, and therefore the gate drive circuit 2 can be expected to be made more compact.

[0062] <Embodiment 5> In the first embodiment, the gate drive circuit 2 continues the operation of the system even when the second gate voltage V2 drops. On the other hand, when the second gate voltage V2 rises, the heat generation of the SiC element 1b increases. This will be described below.

[0063] Fig. 14 is a diagram showing changes in current flowing through the Si element 1a and the SiC element 1b when the second gate voltage V2 increases without changing the first gate voltage V1, and is similar to Fig. 7. However, in Fig. 14, the two-dot chain line shows the relationship between the voltage across both ends and the on-current before the second gate voltage V2 increases, and the solid line shows the relationship between the voltage across both ends and the on-current after the second gate voltage V2 increases.

[0064] Before the second gate voltage V2 rises, the voltages across the Si element 1a and the SiC element 1b are Von1 and the on-current of the Si element 1a is I A1 and the on-current of the SiC element 1b is I B1 and the on-current of the parallel circuit 1 is I T (=I A1 +I B1 ).

[0065] When the second gate voltage V2 increases, the current flows more easily through the SiC element 1b, and the slope of the solid thin line increases from the thin double-dashed line. Even if the second gate voltage V2 increases, the on-current (I T ) is maintained, the voltage across the on1 From small V on3 As a result, the on-current of the Si element 1a is changed to I A1 From I A3 However, the on-current of the SiC element 1b is I B1 From I B3 It grows to I T =I A3 +I B3 holds true.

[0066] In this way, when the on-current of the SiC element 1b increases, the heat generation of the SiC element 1b increases, and there is a possibility that a malfunction occurs in the SiC element 1b. Therefore, the semiconductor device according to the fifth embodiment is configured to perform protection when the second gate voltage V2 increases, as described below.

[0067] Fig. 15 is a diagram showing the configuration of a semiconductor device according to the fifth embodiment, specifically, a diagram showing the configurations of the parallel circuit 1 and the gate drive circuit 2 according to the fifth embodiment in detail. The configuration of Fig. 15 is similar to the configuration of Fig. 9. However, the second comparator 2e2 outputs different output signals to the control circuit 2b when the second gate voltage V2 is higher than a threshold voltage Vth3 corresponding to a predefined third threshold and when it is lower than the threshold voltage Vth3.

[0068] As shown in FIG. 16, when the control circuit 2b receives an output signal from the second comparator 2e2 in which the second gate voltage V2 is higher than the threshold voltage Vth3, the control circuit 2b turns off the SiC device 1b regardless of the input signal. In the fifth embodiment, the control circuit 2b turns off the SiC device 1b, but drives the Si device 1a based on the input signal. In this case, the current that flowed through the SiC device 1b flows through the Si device 1a. However, since the current carrying capacity of the Si device 1a is higher than that of the SiC device 1b, the allowable current of the Si device 1a has a larger margin than the allowable current of the SiC device 1b, even if the on-current of the Si device 1a becomes somewhat large, no problem occurs in the Si device 1a.

[0069] Fig. 17 is a diagram showing another configuration of the semiconductor device according to the present embodiment 5. The configuration in Fig. 17 is similar to the configuration in Fig. 15 in which a voltage reduction circuit 2i is added to the gate drive circuit 2.

[0070] As shown in FIG. 18, when the voltage reduction circuit 2i receives an output signal from the second comparator 2e2 via the control circuit 2b in which the second gate voltage V2 is higher than the threshold voltage Vth3, the voltage reduction circuit 2i reduces the second gate voltage V2 to within a range equal to or higher than the gate threshold voltage of the SiC element 1b.

[0071] <Summary of the fifth embodiment> According to the semiconductor device of the fifth embodiment as described above, when the second gate voltage V3 is higher than the third threshold, the gate drive circuit 2 turns off the SiC element 1b or reduces the second gate voltage V2. With this configuration, even if the second gate voltage V2 rises, heat generation in the SiC element 1b can be suppressed, and therefore defects caused in the SiC element 1b due to the heat can be suppressed. The fifth embodiment may be combined with any of the first to fourth embodiments.

[0072] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0073] Various aspects of the present disclosure are summarized below as appendices.

[0074] (Appendix 1) a first semiconductor switching element having a first gate; a second semiconductor switching element connected in parallel with the first semiconductor switching element, having a second gate, having a band gap larger than that of the first semiconductor switching element, and having a current carrying capacity lower than that of the first semiconductor switching element; a gate drive circuit for driving each of the first semiconductor switching element and the second semiconductor switching element based on an input signal; Equipped with The gate drive circuit includes: A semiconductor device which, when a first gate voltage applied to the first gate to turn on the first semiconductor switching element is lower than a first threshold, turns off the second semiconductor switching element and then turns off the first semiconductor switching element regardless of the input signal.

[0075] (Appendix 2) 2. The semiconductor device according to claim 1, The gate drive circuit includes: A semiconductor device that turns off the second semiconductor switching element regardless of the input signal when a second gate voltage applied to the second gate to turn on the second semiconductor switching element is lower than a second threshold.

[0076] (Appendix 3) The semiconductor device according to claim 1 or 2, The gate drive circuit includes: the semiconductor device outputs a first abnormality signal to an external device when a second gate voltage applied to the second gate to turn on the second semiconductor switching element is lower than a second threshold value.

[0077] (Appendix 4) 4. The semiconductor device according to claim 3, The gate drive circuit includes: the first abnormality signal and a second abnormality signal indicating an abnormality different from the first abnormality signal are output from one output terminal to the outside in mutually distinguishable waveforms.

[0078] (Appendix 5) 2. The semiconductor device according to claim 1, The gate drive circuit includes: A semiconductor device which, when a second gate voltage applied to the second gate to turn on the second semiconductor switching element is higher than a third threshold, turns off the second semiconductor switching element or reduces the second gate voltage.

[0079] (Appendix 6) A semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 4, The gate drive circuit includes: When the second gate voltage is higher than a third threshold, the second semiconductor switching element is turned off or the second gate voltage is reduced. [Explanation of symbols]

[0080] 1a Si element, 1b SiC element, 2 Gate drive circuit, 2g3 Output terminal.

Claims

1. a first semiconductor switching element having a first gate; a second semiconductor switching element connected in parallel with the first semiconductor switching element, having a second gate, having a band gap larger than that of the first semiconductor switching element, and having a current carrying capacity lower than that of the first semiconductor switching element; a gate drive circuit for driving each of the first semiconductor switching element and the second semiconductor switching element based on an input signal; Equipped with The gate drive circuit includes: A semiconductor device which, when a first gate voltage applied to the first gate to turn on the first semiconductor switching element is lower than a first threshold, turns off the second semiconductor switching element and then turns off the first semiconductor switching element, regardless of the input signal.

2. 2. The semiconductor device according to claim 1, The gate drive circuit includes: A semiconductor device that turns off the second semiconductor switching element regardless of the input signal when a second gate voltage applied to the second gate to turn on the second semiconductor switching element is lower than a second threshold value.

3. 2. The semiconductor device according to claim 1, The gate drive circuit includes: the semiconductor device outputs a first abnormality signal to an external device when a second gate voltage applied to the second gate to turn on the second semiconductor switching element is lower than a second threshold value.

4. 4. The semiconductor device according to claim 3, The gate drive circuit includes: The semiconductor device outputs the first abnormality signal and a second abnormality signal indicating an abnormality different from the first abnormality signal from a single output terminal to the outside in mutually distinguishable waveforms.

5. 2. The semiconductor device according to claim 1, The gate drive circuit includes: a second gate voltage applied to the second gate to turn on the second semiconductor switching element is higher than a third threshold, the second semiconductor switching element is turned off or the second gate voltage is reduced.

6. 5. The semiconductor device according to claim 2, The gate drive circuit includes: When the second gate voltage is higher than a third threshold value, the second semiconductor switching element is turned off or the second gate voltage is reduced.

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