Information processing device, robot controller and information processing method

Abstract

To provide an information processing device, a robot controller and an information processing method which are capable of accelerating information processing including signature verification of a program, while reducing power consumption.SOLUTION: An information processing device comprises: a first CPU core; a second CPU core having an operating frequency higher than that of the first CPU core; and a program storage unit which stores a first module, a second module, a third module having a capacity size greater than that of the second module, an electronic signature for the second module, and an electronic signature for the third module. The first CPU core performs second module verification processing which verifies the second module on the basis of the electronic signature for the second module, by executing the first module. The second CPU core performs third module verification processing which verifies the third module on the basis of the electronic signature for the third module, by executing the second module.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an information processing device, a robot controller, and an information processing method. [Background technology]

[0002] An information processing device is being considered that stores a signed program and verifies the signature of the program each time it is started. Signature verification makes it possible to detect whether the program has been tampered with.

[0003] For example, Patent Document 1 discloses an information processing device that sequentially starts a plurality of modules following the startup of a first module, the information processing device including a first module, a second module, and a third module that are started sequentially. The first module detects tampering with the second module and the third module using verification information that verifies the signature of the second module that is to be started next. After being started by the first module, the second module starts the third module that is to be started next.

[0004] This configuration provides a mechanism for detecting tampering in the system because the sequential activation of multiple modules requires successful signature verification. Also, since tampering of multiple modules is detected using the verification information stored in the first module, memory resources can be used more efficiently. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-175000 A Summary of the Invention [Problem to be solved by the invention]

[0006] The information processing device described in Patent Document 1 has a problem in that it takes a long time to start up because it starts up multiple modules sequentially. Also, while the start-up time can be shortened by increasing the operating speed of the CPU provided in the information processing device, this also poses a problem in that it consumes more power. [Means for solving the problem]

[0007] An information processing device according to an application example of the present invention includes: a first CPU core; a second CPU core having an operating frequency higher than that of the first CPU core; a program storage unit that stores a first module, a second module, a third module having a larger capacity than the second module, a digital signature for the second module, and a digital signature for the third module; Equipped with the first CPU core executes the first module to perform a second module verification process for verifying the second module based on the second module digital signature; The second CPU core executes the second module to perform a third module verification process for verifying the third module based on the digital signature for the third module.

[0008] A robot controller according to an application example of the present invention includes: A robot controller for controlling the operation of a robot, a first CPU core; a second CPU core having an operating frequency higher than that of the first CPU core; a program storage unit that stores a first module, a second module, a third module having a larger capacity than the second module, a digital signature for the second module, and a digital signature for the third module; Equipped with the first CPU core executes the first module to perform a second module verification process for verifying the second module based on the second module digital signature; The second CPU core executes the second module to perform a third module verification process for verifying the third module based on the digital signature for the third module.

[0009] An information processing method according to an application example of the present invention includes: a first CPU core; a second CPU core; a program storage unit that stores the first module, the second module, the third module, the digital signature for the second module, and the digital signature for the third module; A method for processing information using the second CPU core has an operating frequency higher than that of the first CPU core; the third module has a larger capacity than the second module; the first CPU core executes the first module to perform a second module verification process for verifying the second module based on the second module digital signature; The second CPU core executes the second module to perform a third module verification process for verifying the third module based on the digital signature for the third module. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a conceptual diagram illustrating an example of the configuration of a robot system. [Figure 2] FIG. 2 is a block diagram showing an example of the hardware configuration of the robot controller shown in FIG. 1. [Figure 3] 3 is a block diagram showing an example of the hardware configuration of the processor shown in FIG. 2. [Figure 4] FIG. 3 is a functional block diagram showing functions of the main board shown in FIG. 2. [Figure 5] This is a memory map of the program storage section of the main board shown in Figure 2. [Figure 6] 3 is a flowchart for explaining a method for starting up the main board shown in FIG. 2 (an information processing method according to an embodiment); [Figure 7] FIG. 10 is a conceptual diagram for explaining signature verification for an IPL (first module) by a boot loader. [Figure 8] FIG. 10 is a conceptual diagram for explaining signature verification for a deployment program (second module) by IPL. [Figure 9] FIG. 10 is a conceptual diagram for explaining signature verification for a compressed file (third module) by a decompression program. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing device, a robot controller, and an information processing method according to the present invention will be described in detail below based on preferred embodiments shown in the accompanying drawings.

[0012] 1.Robot System First, a robot system including a robot controller according to an embodiment will be described. FIG. 1 is a conceptual diagram showing an example of the configuration of a robot system 1.

[0013] The robot system 1 shown in FIG. 1 includes a robot 100, a robot controller 200 (robot controller according to the embodiment), a teach pendant 300, and a computer 350.

[0014] 1.1.Robots The robot 100 shown in FIG. 1 includes a base 120 and a robot arm 130. The robot arm 130 includes six arms connected in order from the base 120 side, and six joints J1 to J6 that connect the base 120 to the arms and between the arms themselves. Of the six joints J1 to J6 shown in FIG. 1, three joints J2, J3, and J5 are bending joints, and the other three joints J1, J4, and J6 are torsion joints. Each of the joints J1 to J6 also includes a motor as a drive source and an encoder for detecting the amount of rotation of the motor, i.e., position information of the motor, although not shown. In this specification, the motor and encoder are collectively referred to as a servo motor.

[0015] An arm end 132 is provided at the tip of the robot arm 130, that is, the end of the robot arm 130 opposite the base 120. An end effector 160 is attached to the arm end 132. The end effector 160 is attached in a detachable manner. Examples of the end effector 160 include a hand that grips a workpiece and a suction tool that sucks the workpiece.

[0016] 1.2.Robot Controller 1 includes a main board 220 (an information processing device according to an embodiment), a first sub-board 240, and a second sub-board 260. These boards are capable of communicating with each other via a communication interface 280.

[0017] 1.2.1.Main board FIG. 2 is a block diagram showing an example of the hardware configuration of the robot controller 200 shown in FIG.

[0018] 2 (information processing device according to the embodiment) includes a processor 222, an external bus 224, a RAM 226, a ROM 228, an input / output port 232, and a memory card interface 234. The RAM is a random access memory, and the ROM is a read-only memory.

[0019] The processor 222 shown in FIG. 2 executes programs loaded in the RAM 226 and programs stored in the ROM 228 to realize various functions.

[0020] FIG. 3 is a block diagram showing an example of the hardware configuration of the processor 222 shown in FIG.

[0021] The processor 222 shown in FIG. 3 is a system-on-a-chip (SoC) element. An SoC element is an element in which a CPU core and other devices are integrated on a single chip (die). The processor 222 shown in FIG. 3 includes a first CPU core 291, a second CPU core 292, a RAM 293, a ROM 294, and an internal bus 295. The CPU is a central processing unit. Using such an SoC element as the processor 222 can further reduce the power consumption of the main board 220 and achieve size and cost reduction. The RAM 293 and the ROM 294 may be provided as needed and may be omitted. The processor 222 does not necessarily have to be an SoC element. For example, the processor 222 may be a system-in-a-package (SiP), or the first CPU core 291 and the second CPU core 292 may be independent elements.

[0022] The second CPU core 292 has a higher operating frequency than the first CPU core 291. On the other hand, when the operating frequency is high, power consumption also tends to be high. In light of this, by mounting CPU cores with different operating frequencies together on the main board 220 and appropriately selecting the programs to be executed by each CPU core, it is possible to increase the speed of information processing on the main board 220 while suppressing the amount of power consumption of the main board 220.

[0023] The number of CPU cores included in one processor 222 is not limited to two as shown in FIG. 3, but may be three or more.

[0024] Furthermore, the operating frequency of the second CPU core 292 may be higher than the operating frequency of the first CPU core 291, but is preferably 1.5 times or more, and more preferably 2.0 times or more. This ensures sufficient speedup for modules executed by the second CPU core 292. On the other hand, the upper limit of the operating frequency of the second CPU core 292 does not need to be particularly set, but taking into consideration the balance with power consumption, it is preferably 5.0 times or less the operating frequency of the first CPU core 291, and more preferably 3.0 times or less.

[0025] Furthermore, the power consumption of the first CPU core 291 is lower than that of the second CPU core 292, but this difference often corresponds to the difference in operating frequency. For example, the power consumption of the first CPU core 291 is preferably 50% or less of the power consumption of the second CPU core 292, more preferably 30% or less, and even more preferably 10% or less. On the other hand, the lower limit of the power consumption of the first CPU core 291 does not need to be particularly set, but taking into account the balance with the operating frequency, it is preferably 1% or more of the power consumption of the second CPU core 292.

[0026] The RAM 293 temporarily stores programs to be executed by the processor 222, read data, etc. The RAM 293 may be, for example, a dynamic random access memory (DRAM).

[0027] The ROM 294 stores programs to be executed by the processor 222, other data, etc. Examples of the ROM 294 include a mask ROM, an antifuse PROM (Programmable Read-Only Memory), an EEPROM (registered trademark) (Electrically Erasable Programmable Read-Only Memory), and a Flash ROM (Flash Read-Only Memory).

[0028] The external bus 224 is a transmission path that connects the processor 222 with the RAM 226 and ROM 228, enabling mutual communication.

[0029] The RAM 226 temporarily stores programs to be executed by the processor 222, read data, etc. The RAM 226 may be, for example, a DRAM.

[0030] The ROM 228 stores programs to be executed by the processor 222, other data, etc. Examples of the ROM 228 include an EEPROM (registered trademark), a Flash ROM, etc. The ROM 228 may be an external storage element.

[0031] The above-mentioned ROM 294 and the above-mentioned ROM 228 constitute a "program storage unit 230."

[0032] The input / output port 232 is an interface for communication between each part of the main board 220 and other devices. Examples of the input / output port 232 include a digital input / output port such as a USB (Universal Serial Bus), an Ethernet (registered trademark) port, and a video output port. The input / output port 232 may be configured to download programs and data from the Internet.

[0033] The memory card interface 234 is an interface into which a memory card (not shown) can be attached and detached, and which writes to and reads from the memory card. The memory card interface 234 may be provided as needed, and may be omitted.

[0034] 1.2.2. First sub-board The first sub-board 240 shown in FIG. 2 includes a processor 242, an external bus 244, a RAM 246, and a ROM 248.

[0035] The processor 242 realizes various functions by executing programs loaded in the RAM 246 and programs stored in the ROM 248. Examples of the processor 242 include a microprocessor and an SoC element. Furthermore, the processor 242 may be partially or entirely configured with a device such as an ASIC or FPGA.

[0036] The external bus 244 enables communication between the processor 242 and the RAM 246 and ROM 248. The RAM 246 temporarily stores programs to be executed by the processor 242, read data, etc. The ROM 248 stores programs to be executed by the processor 242, other data, etc. The RAM 246 and ROM 248 may, for example, be the elements listed above as the RAM 226 and ROM 228.

[0037] 1.2.3. Second sub-board The second sub-board 260 shown in FIG. 2 includes a processor 262, an external bus 264, a RAM 266, and a ROM 268.

[0038] The processor 262 realizes various functions by executing programs loaded in the RAM 266 and programs stored in the ROM 268. Examples of the processor 262 include a microprocessor and an SoC element. The processor 262 may be partially or entirely configured with a device such as an ASIC or FPGA.

[0039] The external bus 264 enables communication between the processor 262 and the RAM 266 and ROM 268. The RAM 266 temporarily stores programs to be executed by the processor 262, read data, etc. The ROM 268 stores programs to be executed by the processor 262, other data, etc. The RAM 266 and ROM 268 may, for example, be the elements listed above as the RAM 226 and ROM 228.

[0040] 1.2.4.Communication Interface The communication interface 280 is a transmission path for transmitting programs, data, etc., and is, for example, a serial communication interface such as PCI or PCI Express (registered trademark).

[0041] Although an example of the hardware configuration of the robot controller 200 has been described above, the hardware configuration is not limited to this. For example, the first sub-board 240 and the second sub-board 260 may be provided as needed, and may be omitted.

[0042] 1.2.5. Functional Section FIG. 4 is a functional block diagram showing the functions of the main board 220 shown in FIG.

[0043] 4 has, as functional units, an interface control unit 312, a language analysis unit 314, an input / output control unit 316, and an interrupt control unit 318. The functions of these functional units are realized by the processor 222 executing a program loaded in the RAM 226 of the main board 220 or a program stored in the ROM 228. Note that the above-described functional units are an example when the main board 220 is used in the robot controller 200. Therefore, the functional units are selected appropriately depending on the application of the main board 220.

[0044] The interface control unit 312 controls, for example, communication between the main board 220, the first sub-board 240, and the second sub-board 260.

[0045] The language analysis unit 314 reads and analyzes the robot language that describes the operation of the robot 100. It receives an operation program for the robot 100 from the computer 350 via the input / output control unit 316 (described later), analyzes the operation program, and acquires target position information for the robot arm 130. The target position information is information about a target position, which is a target point to which the control point of the robot arm 130 is to be moved, and is, for example, data indicating the coordinates of the target position.

[0046] The input / output control unit 316 controls connections with the teach pendant 300, computer 350, and other peripheral devices connected to the main board 220.

[0047] The interrupt control unit 318 controls processing (interrupt processing) for branching from a currently running program to another program.

[0048] Fig. 5 is a memory map of the program storage unit 230 of the main board 220 shown in Fig. 2. Note that the memory map shown in Fig. 5 is an example and is not limiting.

[0049] 5, the program storage unit 230 of the main board 220 includes memory spaces 410, 420, 430, and 440. These memory spaces 410, 420, 430, and 440 are address spaces that can be accessed by the processor 222. These memory spaces 410, 420, 430, and 440 may be divided and allocated to multiple devices, for example, ROM 294 and ROM 268. Furthermore, each of the memory spaces 410, 420, 430, and 440 may also be divided into multiple parts and allocated to multiple devices.

[0050] The memory space 410 stores a boot loader 412 and a first module key 416. Since the memory space 410 stores the boot loader 412 that is started first after the main board 220 is powered on, it is preferable that the memory space 410 be allocated to a non-rewritable device.

[0051] The memory space 420 stores an initial program loader 422 (first module), a digital signature for the first module 424, and a key for the second module 426. In this application, the initial program loader is also referred to as an "IPL."

[0052] The memory space 430 stores a decompression program 432 (second module), a digital signature 434 for the second module, and a key 436 for the third module.

[0053] The memory space 440 stores a compressed file 442 (third module) and a digital signature for the third module 444. Note that the third module may include elements other than the compressed file 442.

[0054] The boot loader 412 is executed by the processor 222 immediately after power is applied to the main board 220. The boot loader 412 has a function of verifying the signature of the IPL 422.

[0055] The IPL 422 is executed by the processor 222 after the boot loader 412. The IPL 422 has a function of verifying the signature of the deployment program 432.

[0056] The decompression program 432 is executed by the processor 222 after the IPL 422. The decompression program 432 has a function of verifying the signature of the compressed file 442, and a function of decompressing the compressed file 442 and decompressing it in the RAM 226.

[0057] The boot loader 412, IPL 422, and expansion program 432 described above are all programs required for booting up the main board 220. When these programs are executed by the processor 222, booting up (secure booting) of the main board 220 is completed.

[0058] The compressed file 442 is a file in which the OS (operating system), applications, root file system, etc. are compressed. The compressed file 442 is usually a binary file. The programs, etc. stored in the compressed file 442 are programs, etc. necessary for information processing. When these programs expanded in the RAM 226 are executed by the processor 222, the functions of each of the functional units described above that the main board 220 has are realized.

[0059] The compressed file 442 has a larger capacity than the decompression program 432. In other words, the capacity of the decompression program 432 is smaller than the compressed file 442. The capacity refers to the space (file size) occupied in the program storage unit 230.

[0060] 1.3.How to start the main board Next, a method for starting up the main board 220 shown in FIG. 2 (an information processing method according to an embodiment) will be described.

[0061] Fig. 6 is a flowchart for explaining a method for starting up the main board 220 shown in Fig. 2 (an information processing method according to an embodiment). Note that Fig. 6 separately illustrates a flow shared by the first CPU core 291 and a flow shared by the second CPU core 292.

[0062] The method for starting up the main board 220 shown in FIG. 6 includes steps S102 to S122.

[0063] After the power is turned on to the main board 220, the process proceeds to step S102. In step S102, the first CPU core 291 executes the boot loader 412 stored in the memory space 410.

[0064] In step S104, the executed boot loader 412 performs a first module verification process. In the first module verification process, the signature of the IPL 422 (first module) stored in the memory space 420 is verified based on the first module key 416 stored in the memory space 410 and the first module digital signature 424 stored in the memory space 420.

[0065] FIG. 7 is a conceptual diagram for explaining the signature verification of the IPL 422 (first module) by the boot loader 412. In FIG.

[0066] When the first CPU core 291 executes the boot loader 412, the executed boot loader 412 applies the IPL 422 to a hash function, thereby obtaining a hash value 423. A hash function is a function that returns fixed-length output data (hash value) from data of any length, and examples of such a function include SHA-256, SHA-384, and SHA-512.

[0067] Meanwhile, the boot loader 412 decrypts the first module digital signature 424 using the first module key 416. This results in a hash value 425. The first module key 416 may be a common key or a public key.

[0068] Then, boot loader 412 compares hash value 423 with hash value 425. If the two values ​​are the same, the integrity and authenticity of IPL 422 have been confirmed, and it is determined that signature verification for IPL 422 has been successful. On the other hand, if the two values ​​are different, it is determined that signature verification for IPL 422 has failed.

[0069] The first CPU core 291 may directly read the IPL 422 stored in the program storage unit 230, or may copy the IPL 422 to the RAM 226 and then read it from the RAM 226. In the latter case, although it takes extra time to copy, it is useful because the signature verification for the IPL 422 may be performed in a shorter time due to good accessibility to the RAM 226.

[0070] Furthermore, although the boot loader 412 may be omitted, in this embodiment, the boot loader 412 is configured to verify the signature of the IPL 422. This makes it possible to confirm the integrity and authenticity of the IPL 422, and to start up the main board 220 while ensuring higher security. Furthermore, by providing both the boot loader 412 and the IPL 422, flexibility in the startup program can be ensured.

[0071] In step S106, if the signature verification in step S104 is successful, the flow branches to step S108. On the other hand, if the signature verification in step S104 is unsuccessful, the flow branches to step S110. In step S110, the startup of the main board 220 is stopped.

[0072] In step S108, the first CPU core 291 executes the IPL 422 (first module).

[0073] In step S112, the executed IPL 422 performs a second module verification process. In the second module verification process, the signature of the deployment program 432 (second module) stored in the memory space 430 is verified based on the second module key 426 stored in the memory space 420 and the second module digital signature 434 stored in the memory space 430.

[0074] FIG. 8 is a conceptual diagram for explaining signature verification for the expansion program 432 (second module) by the IPL 422. In FIG.

[0075] When the first CPU core 291 executes the IPL 422, the executed IPL 422 applies a hash function to the decompression program 432. As a result, a hash value 433 is obtained.

[0076] On the other hand, the IPL 422 decrypts the second module digital signature 434 using the second module key 426. This results in a hash value 435. The second module key 426 may be a common key or a public key.

[0077] IPL 422 then compares hash value 433 with hash value 435. If the two values ​​are the same, the integrity and authenticity of decompression program 432 can be confirmed, and it is determined that signature verification for decompression program 432 has been successful. On the other hand, if the two values ​​are different, it is determined that signature verification for decompression program 432 has failed.

[0078] As mentioned above, the volume size of the decompression program 432 is smaller than that of the compressed file 442. Therefore, even if the first CPU core 291, which has a relatively low operating frequency, is used in signature verification of the decompression program 432, the required time does not become too long. On the other hand, the power consumption of the first CPU core 291 is lower than that of the second CPU core 292. Therefore, the power consumption in signature verification of the decompression program 432 can be kept low.

[0079] Furthermore, the first CPU core 291 may directly read the decompression program 432 stored in the program storage unit 230, or may copy the decompression program 432 to the RAM 226 and then read it from the RAM 226. In the latter case, although it takes extra time to copy, it is useful because it may be possible to perform signature verification on the decompression program 432 in a shorter time due to good accessibility to the RAM 226.

[0080] In step S114, if the signature verification in step S112 is successful, the flow branches to step S116. On the other hand, if the signature verification in step S112 is unsuccessful, the flow branches to step S110. In step S116, the second CPU core 292 executes the expansion program 432.

[0081] In step S118, the executed decompression program 432 performs a third module verification process. In the third module verification process, the signature of the compressed file 442 (third module) stored in the memory space 440 is verified based on the third module key 436 stored in the memory space 430 and the third module digital signature 444 stored in the memory space 440.

[0082] FIG. 9 is a conceptual diagram for explaining signature verification for the compressed file 442 (third module) by the decompression program 432. In FIG.

[0083] When the second CPU core 292 executes the decompression program 432, the executed decompression program 432 applies a hash function to the compressed file 442. As a result, a hash value 443 is obtained.

[0084] Meanwhile, the decompression program 432 decrypts the third module digital signature 444 using the third module key 436. This results in a hash value 445. The third module key 436 may be a common key or a public key.

[0085] Then, decompression program 432 compares hash value 443 with hash value 445. If the two values ​​are the same, the integrity and authenticity of compressed file 442 can be confirmed, and it is determined that signature verification for compressed file 442 has been successful. On the other hand, if the two values ​​are different, it is determined that signature verification for compressed file 442 has failed.

[0086] As mentioned above, the volume size of the compressed file 442 is larger than that of the decompression program 432. However, since the second CPU core 292, which has a relatively high operating frequency, is used in signature verification of the compressed file 442, the required time is not so long. Furthermore, although the power consumption of the second CPU core 292 is higher than that of the first CPU core 291, the power consumption of the second CPU core 292 can be kept low because the time required for signature verification of the compressed file 442 is shorter. Therefore, the main board 220 can speed up information processing, including signature verification, while suppressing power consumption.

[0087] The second CPU core 292 may directly read the compressed file 442 stored in the program storage unit 230, or may copy the compressed file 442 to the RAM 226 and then read it from the RAM 226. In the latter case, although it takes additional time to copy, it is useful because it may be possible to perform signature verification on the compressed file 442 in a shorter time due to good accessibility to the RAM 226.

[0088] In step S120, if the signature verification in step S118 is successful, the flow branches to step S122. On the other hand, if the signature verification in step S118 is unsuccessful, the flow branches to step S110.

[0089] In step S122, the executed decompression program 432 decompresses the compressed file 442 and decompresses it in RAM 226. Because the decompression program 432 is executed by the second CPU core 292, the decompression and decompression processes can be performed in a short time and power consumption can be reduced. In this manner, the main board 220 can be started up.

[0090] According to the information processing method described above, it is possible to increase the speed of information processing, including program signature verification, while suppressing power consumption. It is also possible to realize a main board 220 (information processing device) and a robot controller 200 that can increase the speed of information processing, including program signature verification, while suppressing power consumption. This contributes to reducing the environmental impact of the robot system 1. Furthermore, when the robot system 1 operates on power from a battery (storage battery), it is possible to contribute to extending the operating time of the robot controller 200 while suppressing a decrease in the information processing capability of the robot controller 200.

[0091] Furthermore, according to the above information processing method, the boot loader 412, the IPL 422, and the deployment program 432 are configured to sequentially verify the signature of the next program to be executed. This makes it possible to prevent the execution of a program whose integrity and authenticity have not been confirmed, and to start up the main board 220 while ensuring a higher level of safety.

[0092] Although the same key may be used for the first module key 416, the second module key 426, and the third module key 436, in this embodiment, since they are individually prepared, different keys can be used for each. This further increases the security of each signature verification.

[0093] 2. Effects of the above embodiment As described above, the main board 220 serving as the information processing device according to the embodiment includes the first CPU core 291, the second CPU core 292, and the program storage unit 230. The second CPU core 292 has a higher operating frequency than the first CPU core 291. The program storage unit 230 stores the IPL 422 (first module), the decompression program 432 (second module), the compressed file 442 (third module) that is larger in capacity than the decompression program 432, the digital signature for the second module 434, and the digital signature for the third module 444.

[0094] Then, the first CPU core 291 executes the IPL 422 to perform a second module verification process for verifying the decompression program 432 based on the second module digital signature 434 .

[0095] Furthermore, the second CPU core 292 executes the decompression program 432 to perform a third module verification process for verifying the compressed file 442 based on the third module digital signature 444 .

[0096] According to this configuration, the capacity size of the decompression program 432 is smaller than that of the compressed file 442. Therefore, even if the first CPU core 291, which has a relatively low operating frequency, is used in the second module verification process, the required time does not become so long. On the other hand, the power consumption of the first CPU core 291 is lower than that of the second CPU core 292. Therefore, the power consumption in the second module verification process can be kept low. Furthermore, the capacity size of the compressed file 442 is larger than that of the decompression program 432. Therefore, by using the second CPU core 292, which has a relatively high operating frequency, the required time does not become so long in the third module verification process. On the other hand, although the power consumption of the second CPU core 292 is higher than that of the first CPU core 291, the required time is shorter, so the power consumption can be kept low. Therefore, the main board 220 can speed up information processing, including signature verification, while suppressing power consumption.

[0097] In the embodiment, the RAM 226 is provided, and the second CPU core 292 performs processing to expand the compressed file 442 included in the third module into the RAM 226 .

[0098] According to this configuration, the process of decompressing and expanding the compressed file 442 can be completed in a short time, and power consumption can also be reduced.

[0099] In the embodiment, the program storage unit 230 further stores a boot loader 412 and a first module digital signature 424. The first CPU core 291 then executes the boot loader 412 to perform the first module verification process before the second module verification process. In the first module verification process, the IPL 422 (first module) is verified based on the first module digital signature 424.

[0100] With this configuration, the integrity and authenticity of the IPL 422 (first module) can be confirmed, and higher safety can be ensured while booting the main board 220. Furthermore, by providing both the boot loader 412 and the IPL 422, flexibility in the boot program can be ensured.

[0101] In the embodiment, the first module includes an initial program loader 422 (IPL), the second module includes an extraction program 432, and the third module includes a compressed file 442 extracted by the extraction program 432.

[0102] With this configuration, the IPL 422 and the deployment program 432 sequentially verify the signature of the next program to be executed. This prevents the execution of a program whose integrity and authenticity have not been confirmed, ensuring higher security when starting up the main board 220.

[0103] In the embodiment, the first CPU core 291 and the second CPU core 292 are integrated into an SoC element.

[0104] With this configuration, it is possible to further reduce the amount of power consumed by the main board 220, and also to achieve size reduction and cost reduction.

[0105] The robot controller 200 according to the embodiment is a robot controller that controls the operation of the robot 100, and includes a first CPU core 291, a second CPU core 292, a RAM 226, and a program storage unit 230. The second CPU core 292 has a higher operating frequency than the first CPU core 291. The program storage unit 230 stores an IPL 422 (first module), a decompression program 432 (second module), a compressed file 442 (third module) that is larger in capacity than the decompression program 432, a digital signature 434 for the second module, and a digital signature 444 for the third module.

[0106] Then, the first CPU core 291 executes the IPL 422 to perform a second module verification process for verifying the decompression program 432 based on the second module digital signature 434 .

[0107] Furthermore, the second CPU core 292 executes the decompression program 432 to perform a third module verification process for verifying the compressed file 442 based on the third module digital signature 444 .

[0108] With this configuration, it is possible to obtain a robot controller 200 that reduces power consumption while increasing the speed of information processing, including signature verification.

[0109] The information processing method according to the embodiment is a method of performing information processing using a first CPU core 291, a second CPU core 292, a RAM 226, and a program storage unit 230. The program storage unit 230 stores an IPL 422 (first module), a decompression program 432 (second module), a compressed file 442 (third module), a digital signature for the second module 434, and a digital signature for the third module 444. The second CPU core 292 has a higher operating frequency than the first CPU core 291. The compressed file 442 has a larger capacity than the decompression program 432.

[0110] Then, the first CPU core executes the IPL 422 to perform a second module verification process for verifying the decompression program 432 based on the second module digital signature 434 .

[0111] Furthermore, the second CPU core 292 executes the decompression program 432 to perform a third module verification process for verifying the compressed file 442 based on the third module digital signature 444 .

[0112] According to this configuration, it is possible to reduce power consumption while increasing the speed of information processing including signature verification.

[0113] Although the information processing device, robot controller, and information processing method of the present invention have been described above based on the illustrated embodiments, the present invention is not limited to these.

[0114] For example, the information processing device and robot controller of the present invention may have the components of the above-described embodiments replaced with any other components having similar functions, or may have any other components added. Furthermore, the information processing device of the present invention may be used for purposes other than controlling the operation of a robot. For example, the information processing device of the present invention may be used in a copier, a multifunction device, etc. Furthermore, the information processing method of the present invention may have any additional steps added to the above-described embodiments. [Explanation of symbols]

[0115] 1...Robot system, 100...Robot, 120...Base, 130...Robot arm, 132...Arm end, 160...End effector, 200...Robot controller, 220...Main board, 222...Processor, 224...External bus, 226...RAM, 228...ROM, 230...Program storage unit, 232...Input / output port, 234...Memory card interface, 240...First sub-board, 242...Processor, 244...External bus, 246...RAM, 248...ROM, 260...second sub-board, 262...processor, 264...external bus, 266...RAM, 268...ROM, 280...communication interface, 291...first CPU core, 292...second CPU core, 293...RAM, 294...ROM, 295...internal bus, 300...teach pendant, 312...interface control unit, 314...language analysis unit, 316...input / output control unit, 318...interrupt control unit, 350...computer , 410...Memory space, 412...Boot loader, 416...Key for first module, 420...Memory space, 422...Initial program loader (IPL), 423...Hash value, 424...Digital signature for first module, 425...Hash value, 426...Key for second module, 430...Memory space, 432...Extraction program, 433...Hash value, 434...Digital signature for second module, 435...Hash value, 436...Key for third module, 44 0...Memory space, 442...Compressed file, 443...Hash value, 444...Digital signature for third module, 445...Hash value, J1...Joint, J2...Joint, J3...Joint, J4...Joint, J5...Joint, J6...Joint, S102...Step, S104...Step, S106...Step, S108...Step, S110...Step, S112...Step, S114...Step, S116...Step, S118...Step, S120...Step, S122...Step

Claims

1. A first CPU core; a second CPU core having an operating frequency higher than that of the first CPU core; a program storage unit that stores a first module, a second module, a third module having a capacity size larger than that of the second module, an electronic signature for the second module, and an electronic signature for the third module; Equipped with the first CPU core executes the first module to perform a second module verification process for verifying the second module based on the second module electronic signature; The information processing apparatus, characterized in that the second CPU core performs a third module verification process for verifying the third module based on the electronic signature for the third module by executing the second module.

2. A RAM is provided. The information processing apparatus according to claim 1 , wherein the second CPU core performs a process of expanding a compressed file included in the third module into the RAM.

3. the program storage unit further stores a boot loader and a digital signature for a first module; 3. The information processing device according to claim 1, wherein the first CPU core performs a first module verification process to verify the first module based on an electronic signature for the first module by executing the boot loader prior to the second module verification process.

4. the first module includes an initial program loader; the second module includes a deployment program; The information processing apparatus according to claim 3 , wherein the third module includes a compressed file that is decompressed by the decompression program.

5. 3. The information processing device according to claim 1, wherein the first CPU core and the second CPU core are mounted on a SoC device.

6. A robot controller for controlling an operation of a robot, A first CPU core; a second CPU core having an operating frequency higher than that of the first CPU core; a program storage unit that stores a first module, a second module, a third module having a capacity size larger than that of the second module, an electronic signature for the second module, and an electronic signature for the third module; Equipped with the first CPU core executes the first module to perform a second module verification process for verifying the second module based on the second module electronic signature; A robot controller characterized in that the second CPU core performs a third module verification process to verify the third module based on the electronic signature for the third module by executing the second module.

7. A first CPU core; A second CPU core; and a program storage unit that stores a first module, a second module, a third module, a digital signature for the second module, and a digital signature for the third module; A method for processing information using the second CPU core has an operating frequency higher than that of the first CPU core; the third module has a larger capacity than the second module; the first CPU core executes the first module to perform a second module verification process for verifying the second module based on the second module electronic signature; An information processing method, comprising the steps of: the second CPU core executing the second module to perform a third module verification process for verifying the third module based on the electronic signature for the third module.

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