Information processing device

Abstract

To provide an information processing device that the inputting of the signal with a higher voltage than an operation voltage into a host system is avoided.SOLUTION: A host system is connected to the other end of a rectifier element. A socket comprises a first signal end into which a first signal is input from a peripheral device and a second signal end into which a second signal is input. The first signal end is connected to one end of the rectifier element. The first signal has a higher voltage than a reference potential. A second signal has a higher second voltage than the reference potential when the first voltage becomes below the operation voltage of the host system, and has the second voltage with no significant difference from the reference potential when the first voltage is the operation potential or more of the host system. An information processing device has a circuit configuration that brings the potential at one end closer to the reference potential when the first voltage is higher than the operation voltage of the host system.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to output control of a sideband signal from an information processing device, for example, a solid-state memory device. [Background technology]

[0002] The functions of information processing devices such as PCs (Personal Computers) are expanded by adding various devices. Typically, information processing devices include storage devices. Examples of auxiliary storage devices include SSDs (Solid State Drives). A host system, which is the core of an information processing device, detects devices included in the device itself and controls the operation of the detected devices. Each device outputs an output signal to the host system in accordance with a predetermined input / output method to notify the host system of information such as its presence, specifications, operating state, and operating environment. For example, Patent Document 1 describes an information processing device that includes a storage device and enables the host system to control the storage device in accordance with a predetermined internal bus interface standard.

[0003] A voltage higher than the reference voltage may be applied to the output signal of each device (pull-up). The applied voltage may be equal to the operating voltage of the device that outputs the output. On the other hand, the operating voltage of the host system and each device may differ individually. If the operating voltage of the device is higher than that of the host system, the voltage of the output signal will also be higher than that of the host system, which may cause a failure or malfunction of the host system. For this reason, devices with an operating voltage equal to that of the host system are sometimes adopted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-028934 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, the operating voltage of the processor constituting the host system may be fixed to a certain value. The information processing device includes a socket that allows some devices, including an SSD, to be attached and detached, and a device having an operating voltage higher than that of the host system may be attached. In this case, an output signal having a voltage higher than that of the host system may be input from the device attached to the host system. For example, when an SSD having an operating voltage of 3.3V is connected to a CPU whose operating voltage can be switched between 1.8V and 3.3V, even if the SSD is replaced with an SSD having an operating voltage of 1.8V, a signal having a voltage higher than that of the operating voltage is not input from the replaced SSD to the CPU. On the other hand, when an SSD having an operating voltage of 3.3V is connected to a CPU whose operating voltage is fixed at 1.8V, a signal having a voltage higher than that of the operating voltage may be input to the CPU. [Means for solving the problem]

[0006] The present application has been made to solve the above-mentioned problems, and an information processing device according to one aspect of the present application comprises a host system, a rectifying element that outputs a signal input to one end to the other end, and a socket to which a peripheral device can be connected, wherein the host system is connected to the other end, and the socket comprises a first signal end to which a first signal is input from the peripheral device when connected to the peripheral device, and a second signal end to which a second signal is input, wherein the first signal end is connected to the one end, and the first signal has a first voltage higher than a reference potential, and the second signal has a second voltage higher than the reference potential when the first voltage is equal to or lower than an operating voltage of the host system, and when the first voltage is higher than the operating voltage of the host system, has a second voltage that is not significantly different from the reference potential, and when the first voltage is higher than the operating voltage of the host system, the information processing device has a circuit configuration that brings the potential of the one end closer to the reference potential.

[0007] In the above information processing device, the circuit configuration may be characterized in that the second signal terminal is short-circuited to the first signal terminal.

[0008] The above-mentioned information processing device may include a power supply circuit that enables power to be supplied to the peripheral device when an operation control signal having a voltage higher than the reference potential is input, and a power switch that outputs an operation instruction signal indicating whether or not the information processing device needs to operate depending on whether the voltage is higher than the reference potential, and the circuit configuration may include a logical AND circuit that outputs an operation control signal having a voltage higher than the reference potential when the voltage of the operation instruction signal and the second voltage are each higher than the reference potential, and has a voltage that is not significantly different from the reference potential when at least one of the voltage of the operation instruction signal and the second voltage is not significantly different from the reference potential.

[0009] In the above information processing device, the peripheral device may be a solid-state storage device.

[0010] In the above information processing device, the first voltage and the second voltage higher than the reference potential may each be equal to an operating voltage of the peripheral device.

[0011] In the above information processing device, the first signal may be a sideband signal indicating an operating status of the peripheral device, and the second signal may be a voltage setting signal indicating an operating voltage of the peripheral device.

[0012] In the above-mentioned information processing device, the sideband signal may be a power loss notification signal indicating whether or not a power loss has occurred in the peripheral device, and the voltage setting signal may indicate whether or not the operating voltage of the peripheral device is equal to the operating voltage of the host system. Effect of the Invention

[0013] According to the embodiment of the present application, input of a signal having a voltage higher than the operating voltage to the host system is avoided. [Brief description of the drawings]

[0014] [Figure 1] 1 is a schematic block diagram illustrating an example of a hardware configuration of an information processing device according to an embodiment of the present invention. [Diagram 2] 1 is a schematic block diagram showing an example of a circuit configuration of an information processing device according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a schematic block diagram showing a first example of a usage state of the information processing device according to the embodiment. [Figure 4] FIG. 11 is a schematic block diagram showing a second example of a usage state of the information processing device according to the embodiment. [Diagram 5] FIG. 11 is a schematic block diagram showing another example of the circuit configuration of the information processing device according to the embodiment. [Figure 6] FIG. 11 is a schematic block diagram showing a third example of a usage state of the information processing device according to the embodiment. [Figure 7] FIG. 11 is a schematic block diagram showing a fourth example of a usage state of the information processing device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present application will be described with reference to the drawings. First, an overview of an information processing device 1 according to the present embodiment will be described. The information processing device 1 includes a host system, a rectifying element that outputs a signal input to one end to the other end, and a socket that allows a peripheral device to be connected. The information processing device 1 is, for example, a PC (Personal Computer). The information processing device 1 may have any form, such as a clamshell type PC or a desktop type PC. The information processing device 1 may be realized as any type of electronic device, such as a tablet terminal device or a mobile phone.

[0016] A host system of the information processing device 1 is connected to the other end of the rectifying element, and the socket has at least a first signal end and a second signal end. When a peripheral device is connected to the socket, a first signal is input from the peripheral device to the first signal end, and a second signal is input to the second signal end. The first signal has a first voltage higher than a reference voltage, and the second signal has a second voltage that is equal to or higher than the reference voltage when the first voltage is equal to or lower than the operating voltage of the host system, and has a second voltage equal to the reference voltage when the first voltage is equal to or higher than the operating voltage of the host system. The information processing device 1 has a circuit configuration that brings the voltage of one end closer to the reference voltage when the first voltage is equal to or higher than the operating voltage of the host system.

[0017] Next, an example of the hardware configuration of the information processing device 1 according to the present embodiment will be described. 1 is a schematic block diagram showing an example of a hardware configuration of an information processing device 1 according to this embodiment. The information processing device 1 includes a CPU 11, a main memory 12, a chipset 21, a BIOS (Basic Input Output System) memory 22, a socket 23, an audio system 24, a video system 25, a WLAN (Wireless Local Area Network) card 26, a USB (Universal Serial Bus) connector 27, an EC (Embedded Controller) 31, an input device 32, a power supply circuit 33, a battery 34, an AC (Alternating Current) adapter 37, and a power button 38.

[0018] The CPU 11 is a processor that is the core of a system device included in the information processing device 1. The CPU 11 is a processor that can execute various arithmetic processes instructed by commands written in various programs. The CPU 11 executes processes instructed by various programs, such as an OS (Operating System), a BIOS, firmware, and application programs (referred to as "apps" in this application). The CPU 11 executes the OS and provides functions such as resource management, execution management of various programs, input / output control, and file management in the computer system that constitutes the core of the information processing device 1, i.e., the host system. Note that executing a process instructed by a command written in a program is sometimes called "executing a program" or "running a program."

[0019] The main memory 12 is a writable memory used as a read area for the execution program of the CPU 11 or as a work area for writing processing data for the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. The execution programs include an OS, various drivers for operating hardware such as peripheral devices, various services / utilities, applications, etc.

[0020] The chipset 21 includes one or more bus controllers and can be connected to multiple peripheral devices to input and output various data. The bus controller may be, for example, any one of USB, Serial ATA (Advanced Technology Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, and LPC (Low Pin Count), or any combination thereof. The multiple peripheral devices to be connected include, for example, the BIOS memory 22, SSD 23s, audio system 24, video system 25, WLAN card 26, and EC 31.

[0021] The CPU 11, the main memory 12, and the chipset 21 correspond to system devices constituting the host system 10h. The host system 10h functions as a computer system that constitutes the core of the information processing device 1. The host system 10h includes a system device as hardware, and software such as an OS and a schedule task.

[0022] The BIOS memory 22 stores firmware for controlling the operation of peripheral devices such as the SSD 23s, the audio system 24, the video system 25, the WLAN card 26, the EC 31, and the like in addition to the BIOS. The BIOS is firmware for performing basic input and output of system devices. In this application, the BIOS may also refer to firmware defined according to the specifications prescribed in the Unified Extensible Firmware Interface (UEFI). The BIOS memory 22 includes an electrically rewritable non-volatile memory. As such a non-volatile memory, for example, an Electrically Erasable Programmable Read Only Memory (EEPROM) and a flash Read Only Memory (FLASH ROM) can be used.

[0023] The socket 23 is configured according to a predetermined standard and is a connector for connecting various peripheral devices by wire. The socket 23 has a plurality of terminals and allows various signals to be input and output between the terminals and the peripheral devices connected thereto. The socket 23 is, for example, an M.2 socket configured according to the M.2 standard. In the example of FIG. 1, the socket 23 is connected to an SSD 23s.

[0024] The SSD (Solid State Drive, solid-state storage device) 23s is an example of a peripheral device connected to the chipset 21 using the socket 23. The SSD 23s is an example of an auxiliary storage device that stores various data continuously and in a readable and writable manner. The stored data includes various programs that can be executed by the CPU 11, parameters, data used in various processes, and data acquired by various processes. The SSD 23s is configured to include various nonvolatile memories. For example, a flash memory is used as the nonvolatile memory. The various programs may include, for example, any one of an OS, a driver, firmware, an application, and the like, or any combination thereof.

[0025] A microphone (not shown) and a speaker (not shown) are connected to the audio system 24, and the audio system 24 is capable of recording, reproducing, and outputting audio data. The microphone and the speaker may be built into the information processing device 1, or may be separate from the information processing device 1, for example.

[0026] The video system 25 processes drawing commands input from the CPU 11, and writes drawing information obtained by the processing to a video memory (not shown). The video system 25 reads the drawing information from the video memory, and configures a display screen including the read drawing information (image processing). The video system 25 outputs display data showing the display screen to the display 25d. The display 25d displays a display screen based on display data input from the video system 25. The display 25d may be, for example, any of a liquid crystal display (LCD) and an organic light emitting diode (OLED) display.

[0027] A wideband local area network (WLAN) card 26 is capable of connecting to a wireless LAN or to other devices via a wireless LAN, and transmitting various types of data to and from the connected device. The USB connector 27 is a separate connector for connecting various peripheral devices by wire to the socket 23. The USB 27 uses the USB system as an input / output system for the connected peripheral devices.

[0028] The EC31 is a one-chip microcomputer that monitors and controls the status of various devices (peripheral devices, sensors, etc.) regardless of the operating state of the host system 10h. The EC31 includes a processor separate from the CPU 11, a RAM separate from the main memory 12, a ROM, an A / D (Analog-to-Digital) input terminal for multiple channels, a D / A (Digital-to-Analog) output terminal, a timer, and an input / output interface (not shown). The EC31 executes a predetermined firmware to perform its functions.

[0029] To the input / output interface of the EC 31, devices such as an input device 32, a power circuit 33, and a power button 38 are connected by wires. The EC 31 can control the operations of these devices. The input / output interface may be connected to various devices so as to be able to transmit and receive data wirelessly. The input device 32 may be connected wirelessly to the EC 31. The input device 32 may achieve wireless connection using, for example, a short-range wireless communication method defined in IEEE802.15.1. To the EC 31, a device that is used regardless of the operating status of the host system 10h or a device that has a data transmission speed slower than that of the chipset 21 is connected.

[0030] The input device 32 detects a user's operation and outputs an operation signal generated in response to the detected operation to the EC 31. The input device 32 corresponds to, for example, a keyboard and a touch pad. The input device 32 may further include a touch sensor. The touch sensor may overlap the display 25d and be configured as a touch panel.

[0031] The power supply circuit 33 supplies power required for the operation of each device included in the information processing device 1 under the control of the EC 31. The power supply circuit 33 may also supply power required for the operation of peripheral devices connected to the information processing device 1 by wire. The operating voltage of each device may differ from one device to another. The various devices may include devices that require multiple voltage stages. The multiple voltage stages may include a reference voltage in addition to the operating voltage.

[0032] The power supply circuit 33 includes a converter that converts the voltage of the power supplied to the power supply circuit 33 itself, and a power supply device that supplies the voltage-converted power to the battery 34. When DC power is supplied from an AC (Alternating Current) adapter 37, the power supply device supplies the remaining power that is not consumed in each device to the battery 34. When no power is supplied from the AC adapter 37, or when the power supplied from the AC adapter 37 is insufficient to cover the power consumed by each device, the power discharged from the battery 34 is supplied to each device as operating power.

[0033] As the converter, for example, one or more DC / DC (Direct Current / Direct Current) converters are used. The multiple DC / DC converters may be used separately for each voltage after conversion. For example, some of the DC / DC converters may be connected to a system device or a device whose operating state may vary depending on the operating mode of the system device. The some of the DC / DC converters may control the power they supply based on the operating mode notified by the EC31. The other DC / DC converters may be connected to a device that operates regardless of the operating mode of the system device. The other DC / DC converters are capable of steadily supplying a constant power.

[0034] For example, the DC / DC converter may be used as a power supply for supplying power to each device. In the following description, a power supply that supplies power to a peripheral device may be referred to as a "peripheral device power supply." Among the peripheral device power supplies, a power supply that supplies power to the SSD 23s may be referred to as an "SSD power supply." The power consumption of the host system 10h may account for a large portion of the power consumption of the information processing device 1. The power consumption of the host system 10h differs significantly depending on the operation mode. There are at least a standard mode and a power saving mode. The standard mode is an operation mode in which the power consumption of the CPU 11 is standard. The power saving mode is an operation mode in which the power consumption is less than that of the standard mode. In the power saving mode, the operation of some peripheral devices is stopped. In the power saving mode, the peripheral devices that are stopped from operating include, for example, the display 25d.

[0035] The power button 38 accepts a press on itself and outputs a signal indicating whether or not the information processing device 1 is to operate to the EC 31 as an operation instruction signal. The power button 38 switches between whether or not the operation is required (Power ON / OFF) each time it detects a press. The EC 31 controls the power circuit 33 to supply power to each device based on the operation instruction signal input from the power button 38. The operation instruction signal is, for example, a binary signal having either a high voltage (H: High) significantly higher than a reference potential or a low voltage (L: Low) that has no significant difference from the reference potential. In this application, being significantly high or low, or having a significant difference, means having a substantial difference, for example, being larger than an error or noise.

[0036] When the host system 10h is not operating and an operation instruction signal indicating a need for operation is acquired, the EC 31 causes the power supply circuit 33 to start supplying power to the host system 10h. The host system 10h executes a startup process according to the above firmware.

[0037] The battery 34 stores the power supplied from the power supply circuit 33 under the control of the power supply circuit 33. The battery 34 discharges a part of the stored power to the power supply circuit 33. A secondary battery is used as the battery 34. The secondary battery is a storage battery that can be charged and discharged. The secondary battery is, for example, a lithium ion battery.

[0038] The AC adapter 37 converts AC power supplied from an external power source into DC power with a constant voltage, and supplies the converted power to the power supply circuit 33. The AC adapter 37 includes a mounting fixture that allows the AC adapter 37 to be detachably attached to a housing of the information processing device 1 including the power supply circuit 33. The mounting fixture includes an interface that can transmit both power and data according to a predetermined standard. For example, USB Type-C can be used as the predetermined standard.

[0039] Next, an example of a circuit configuration according to the present embodiment will be described with reference to FIGS. 2 to 4. In the example of FIGS. 2 to 4, it is assumed that the SSD 23s is connected to the socket 23. The SSD 23 corresponds to an example of a peripheral device. The socket 23 has a plurality of terminals. Each terminal is electrically connected to the chipset 21 (FIG. 1) and can input and output various electric signals. As described above, the chipset 21 is a component of the host system 10h. The information processing device 1 has a rectifying element D01. The rectifying element D01 has, for example, a diode. One terminal (sometimes referred to as a "first signal terminal" in this application) among a plurality of terminals provided on the socket 23 is connected to the chipset 21 via the rectifying element D01. The rectifying element D01 passes an input signal input to one end and outputs it from the other end, blocks a signal input to the other end, and does not output it to the one end. Another terminal of the socket 23 (sometimes referred to as a "second signal terminal" in the present application) is electrically shorted to the first signal terminal. The second signal terminal is also electrically connected to one terminal of the rectifying element D01.

[0040] When an operating SSD 23s is connected to the socket 23, a first signal and a second signal are input from the SSD 23s to a first signal terminal and a second signal terminal, respectively. As the first signal, an electrical signal having a voltage (sometimes referred to as a "first voltage" in the present application) significantly higher than a reference potential of the information processing device 1 can be input. In the examples of FIGS. 2 to 4, a power loss notification signal (PLN#: Power Loss Notification) is applied as the first signal. The power loss notification signal is an example of a sideband signal indicating the operating status of the SSD 23. The power loss notification signal is a binary signal that has a high voltage that is significantly different from a reference potential when power is normally supplied to the SSD 23s, and has a low voltage that is not significantly different from the reference potential when power is not normally supplied to the SSD 23s. The first voltage is 1.8V in the example of FIG. 3, and 3.3V in the example of FIG. 4. In these examples, the first voltage is pulled up inside the SSD 23s so as to be equal to the operating voltage of the SSD 23s.

[0041] As the second signal, a signal having a voltage that is equal to or higher than the reference potential of the information processing device 1 when the first voltage is equal to or lower than the operating voltage of the host system 10h, and having a voltage that is not significantly different from the reference potential when the first voltage is higher than the operating voltage of the host system 10h, is input. In the present application, the voltage of the second signal may be called the "second voltage". In the examples of Figs. 2 to 4, a voltage setting signal (vio_cfg, I / O voltage configuration) is applied as the second signal. The voltage setting signal is a signal that indicates the operating voltage of the SSD 23 by its voltage. In the example of Fig. 3, the second voltage is 1.8V. This second voltage is equal to the operating voltage of the SSD 23s and the first voltage when the SSD 23s is operating. In contrast, in the example of Fig. 4, the second voltage is 0V, which is equal to the reference potential. At this time, the output terminal of the second signal of the SSD 23s is connected to the reference point (GND) of the potential. The potential at the reference point corresponds to the reference potential. Therefore, the voltage setting signal can also be considered as a binary signal indicating whether the operating voltage of the SSD 23s is equal to the operating voltage of the host system 10h.

[0042] The information processing device 1 illustrated in FIGS. 2 to 4 has a configuration in which, when the first voltage is higher than the operating voltage of the host system 10h, the potential of the first signal terminal is brought closer to the reference potential. More specifically, the second signal terminal is shorted to the first signal terminal. As illustrated in FIG. 3, it is assumed that an SSD 23s having an operating voltage of 1.8V is connected to the socket 23. In this case, a first signal having a first voltage of 1.8V and a second signal having a second voltage of 1.8V are input to the socket 23. The potential at one end of the rectifying element D01 becomes 1.8V. This potential becomes equal to 1.8V, which is the operating voltage of the host system 10h. In addition, when the power supply to the SSD 23s is stopped, the first voltage and the second voltage become equal to the reference voltage. Therefore, a signal having a voltage higher than the operating voltage is not input to the host system 10h.

[0043] On the other hand, assume that an SSD 23s with an operating voltage of 3.3V is connected as illustrated in Fig. 4. In this case, a first signal with a first voltage of 3.3V and a second signal with a second voltage of 0V are input to the socket 23. In the SSD 23s, the output terminal of the second signal is connected to the reference point and the second output terminal and the first output terminal are shorted, so that the potential of one terminal of the rectifier element D01 becomes 0V. Therefore, the first signal having a voltage exceeding the operating voltage of 1.8V is not input to the host system 10h.

[0044] In this case, the host system 10h recognizes that the power supply to the SSD 23s has been stopped, and does not need to perform input / output with the SSD 23s. In reality, the SSD 23s, which has a higher operating voltage than the operating voltage of the host system 10h, should not be connected to the socket 23. Therefore, there is no particular problem with the host system 10h not performing input / output with the SSD 23s. In addition, since the reverse flow of current from the other end to one end of the rectifier element D01 is prevented, the operating voltage of the host system 10h is maintained at 1.8V.

[0045] Next, another example of the circuit configuration according to the present embodiment will be described with reference to FIGS. 5 to 7. In the following description, differences from the examples of FIGS. 2 to 4 will be mainly described, and the descriptions of FIGS. 2 to 4 will be used unless otherwise specified. The information processing device 1 illustrated in FIGS. 5 to 7 includes a host system 10h, a socket 23, an SSD power supply 23p, and an AND circuit AG01. In the examples of FIGS. 5 to 7, the first signal terminal is connected to the host system 10h via a rectifying element D01 using a first signal line. In contrast, the second signal terminal is connected to the host system 10h in parallel with the first signal line using a second signal line. The second signal terminal is insulated from the first signal terminal without being short-circuited. The other end of the second signal line is connected to a GPIO (General Purpose Input / Output) interface provided in the host system 10h. The GPIO interface is a general terminal provided in an integrated circuit, a computer board, etc. A voltage significantly higher than the reference potential is applied to the GPIO interface (pull-up). In the examples of FIGS. 5 to 7, the voltage applied to the GPIO interface is 1.8 V, which corresponds to the operating voltage of the host system 10h.

[0046] The logical product circuit AG01 has two input terminals and one output terminal, and performs a logical product between a first logical value represented by a first binary signal input to one input terminal (sometimes referred to as a "first input terminal" in this application) and a second logical value represented by a second binary signal input to the other input terminal (sometimes referred to as a "second input terminal" in this application). The logical product circuit AG01 is also called an AND circuit or an AND gate. The logical product circuit AG01 outputs an output signal representing the obtained logical product from the output terminal.

[0047] In the examples of FIGS. 5 to 7, the second signal is input as the first binary signal. The second signal line branches between the socket 23 and the host system 10h and is connected to a first input terminal of the AND circuit AG01. The second signal is a binary signal having a high voltage (1.8V in the examples of FIGS. 5 to 7) higher than the reference potential when the operating voltage of the SSD 23s is equal to or lower than the operating voltage of the host system 10h, and having a low voltage that has no significant difference from the reference potential when the operating voltage of the SSD 23s exceeds the operating voltage of the host system 10h. An operation instruction signal (B_ON) is input to the second input terminal from the power button 38 as the second binary signal. An output signal having a high voltage significantly higher than the reference potential or a low voltage that has no significant difference from the reference potential is output from the output terminal of the AND circuit AG01 to the SSD power supply 23p as the AND of the first logical value and the second logical value.

[0048] The SSD power supply 23p is a power supply circuit capable of supplying power required for the operation of the SSD 23s. The SSD power supply 23p includes a control end EN, to which an output signal output from the AND circuit AG01 is input as an operation control signal for the SSD 23s. The control end EN is sometimes called an enable terminal, and the operation control signal is sometimes called an enable signal.

[0049] When an operation control signal having a voltage significantly higher than the reference potential is input, the SSD power supply 23p supplies power having a predetermined operating voltage VCC3_SSD to the SSD 23s (SSD power on). At this time, the SSD 23s operates by consuming the power supplied from the SSD power supply 23p. During operation, the SSD 23s applies a predetermined first voltage to the output terminal of the first signal (pull-up) and outputs a first signal having the first voltage as a signal voltage to the first signal terminal.

[0050] When the operating voltage of the SSD 23s becomes equal to or lower than the operating voltage of the host system 10h, the SSD 23s applies (pull-up) a second voltage significantly higher than the reference voltage to the output terminal of the second signal, and outputs the second signal having the second voltage to the second signal terminal. Since the second voltage becomes equal to or lower than the operating voltage of the host system 10h, the second signal higher than the operating voltage of the host system 10h is not input to the host system 10h. The SSD 23s, whose operating voltage is higher than that of the host system 10h, outputs a second signal having a second voltage that is not significantly different from the reference voltage to the second output terminal even if the SSD 23s is operating. Since the second voltage is lower than the operating voltage of the host system 10h, the second signal higher than the operating voltage of the host system 10h is not input to the host system 10h.

[0051] When an operation control signal having a low voltage that is not significantly different from the reference potential is input, the SSD power supply 23p does not supply power to the SSD 23s (SSD power off). The SSD 23s does not operate because no power is supplied from the SSD power supply 23p. Therefore, the first signal having a predetermined first voltage is not output from the first signal terminal from the SSD 23s. Furthermore, since the SSD 23s does not operate, a second signal higher than the operating voltage of the host system 10h is not input to the host system 10h.

[0052] 5 to 7, an AND circuit AG01 is provided to which the operation signal and the second signal are input. When the voltage of the operation signal and the second voltage are each significantly higher than the reference potential, the AND circuit AG01 outputs to the SSD power supply 23p an operation control signal having a high voltage significantly higher than the reference potential and having a low voltage in which either the voltage of the operation signal or the second voltage is not significantly different from the reference potential. The SSD power supply 23p can control whether or not to supply power to the SSD 23 depending on whether the voltage of the operation control signal is significantly higher than the reference potential.

[0053] As illustrated in FIG. 6, assume that an SSD 23s with an operating voltage of 1.8V is connected to the socket 23. In this case, a first signal with a first voltage of 1.8V and a second signal with a second voltage of 1.8V are input to the socket 23 by an internal pull-up in the SSD 23s. The potential at one end of the rectifying element D01 becomes 1.8V. The potential at the first input end of the AND circuit AG01 becomes 1.8V, which is significantly higher than the reference potential. Since an operation instruction signal having a high voltage significantly higher than the reference potential is input from the power button 38, the AND circuit AG01 outputs an operation control signal having a high voltage significantly higher than the reference potential to the SSD power supply 23p. The SSD power supply 23p supplies power to the SSD 23s in response to the operation control signal having a high voltage significantly higher than the reference potential being input to the AND circuit AG01. In this case, the potential at the second signal end also becomes 1.8V. Therefore, the first and second signals having a voltage exceeding the operating voltage of 1.8V are not input to the host system 10h.

[0054] Next, as illustrated in FIG. 7, assume that an SSD 23s with an operating voltage of 3.3V is connected. Even if the SSD 23s operates, a first signal with a first voltage of 3.3V may be input to the socket 23. The potential at the first input terminal of the AND circuit AG01 is equal to 0V and the reference potential. Even if an operation instruction signal having a high voltage significantly higher than the reference potential is input from the power button 38, the AND circuit AG01 outputs an operation control signal having a low voltage that is not significantly different from the reference potential to the SSD power supply 23p. The SSD power supply 23p does not supply power to the SSD 23s because an operation control signal having a high voltage significantly higher than the reference potential is not input to the AND circuit AG01. In this case, the SSD 23s does not operate, so the internal pull-up in the SSD 23s does not function. Therefore, the first signal having an operating voltage of 3.3V is not input to the first signal terminal. Even if the SSD 23s operates, the second voltage of the second signal output from the second signal terminal will be 0 V. Therefore, the first signal and the second signal exceeding the operating voltage of 1.8 V will not be input to the host system 10h.

[0055] The SSD power supply 23p may be configured as a part of the power supply circuit 33, or may be configured as a part of the SSD 23s. The first signal may be an electrical signal other than the power loss notification signal PLN#, for example, any sideband signal such as a clock request signal CLKREQ#, a reset signal PERST#, a wake-up signal WAKE#, etc. The first signal may be any other electrical signal having a first voltage significantly higher than the reference potential during normal operation of the SSD 23s. As the second signal, another type of electrical signal other than the voltage setting signal vio_cfg may be used, which has a second voltage that is significantly higher than the reference potential when the first voltage is equal to or lower than the operating voltage of the host system 10h, and has a second voltage that is not significantly different from the reference potential when the first voltage is higher than the operating voltage of the host system 10h.

[0056] Furthermore, the peripheral device is not limited to the SSD 23s. The peripheral device may be another type of device that can output electrical signals having characteristics similar to the above-mentioned first signal and second signal to the first signal terminal and second signal terminal, respectively, and can be attached and detached by applying an external force to the socket 23. The other type of device may be, for example, a hard disk drive (HDD), a network interface card, an input / output interface card, a video module, an audio module, etc. The rectifying element D01 is not limited to a diode, but may be a thyristor, a metal-oxide-semiconductor field-effect transistor (MOSFET), or the like.

[0057] As described above, the information processing device 1 according to the present embodiment includes a host system 10h, a rectifying element D01 that outputs a signal input to one end to the other end, and a socket 23 that allows a peripheral device to be connected. The host system 10h is connected to the other end of the rectifying element D01, and the socket 23 includes a first signal end to which a first signal is input from the peripheral device when the host system 10h is connected to the peripheral device, and a second signal end to which a second signal is input. The first signal end is connected to one end of the rectifying element D01. The first signal has a first voltage higher than the reference potential, and the second signal has a second voltage higher than the reference potential when the first voltage is equal to or lower than the operating voltage of the host system 10h, and has a second voltage equal to the reference potential when the first voltage is higher than the operating voltage of the host system 10h. When the first voltage is higher than the operating voltage of the host system 10h, the circuit has a potential at one end of the rectifying element D01 that approaches the reference potential. The first voltage and the second voltage when higher than the reference potential can be equal to the operating voltage of the peripheral device, respectively. The peripheral device is, for example, an SSD 23s. The first signal may be a sideband signal indicating an operating status of the peripheral device, and the second signal may be a voltage setting signal vio_cfg indicating an operating voltage of the peripheral device. The sideband signal may be a power loss notification signal PLN# indicating whether or not a power loss has occurred in the peripheral device.

[0058] According to this configuration, the operating voltage of the peripheral device is applied as the first voltage, and when the operating voltage of the peripheral device is higher than the operating voltage of the host system 10h, the potential of one end of the rectifying element D01 drops. When a peripheral device having an operating voltage higher than the operating voltage of the host system 10h is connected, input of a signal having a voltage higher than the operating voltage of the host system 10h is avoided. Therefore, unintended failure of the host system 10h can be prevented.

[0059] The above-mentioned circuit configuration may be characterized in that the second signal terminal is short-circuited to the first signal terminal. With this configuration, the potentials of the first signal terminal and the second signal terminal are the reference potential, and the potential of one terminal of the rectifying element D01 is also the reference potential. Therefore, even if an operating voltage of the peripheral device higher than the operating voltage of the host system 10h is applied to the first signal terminal, the input of the first signal higher than any operating voltage to the host system 10h is avoided.

[0060] The information processing device 1 may include a power supply circuit (e.g., SSD power supply 23p) that can supply power to a peripheral device when an operation control signal having a voltage higher than the reference potential is input, and a power switch (e.g., power button 38) that outputs an operation instruction signal indicating whether or not the operation of the information processing device 1 is required depending on whether or not the voltage is higher than the reference potential. The above circuit configuration may include a logical AND circuit AG01 that outputs an operation control signal having a voltage higher than the reference potential when the voltage of the operation instruction signal and the second voltage are each higher than the reference potential, and having a voltage that is not significantly different from the reference potential when at least one of the voltage of the operation instruction signal and the second voltage is not significantly different from the reference potential to the power supply circuit. With this configuration, when a peripheral device having an operating voltage higher than the operating voltage of the host system 10h is connected and the operation of the information processing device 1 is requested by the power switch, an operation control signal having a voltage that is not significantly different from the reference potential is input from the logical AND circuit AG01 to the power supply circuit. At this time, the power supply circuit does not supply power to the peripheral device, so even if the power supply circuit has a configuration for applying the operating voltage of the peripheral device as the first voltage, the operating voltage is not applied. This prevents a signal having a voltage higher than the operating voltage of the host system 10h from being input from one end of the rectifying element D01.

[0061] Although the embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to the above embodiment, and the present invention also includes designs that do not deviate from the gist of the present invention. The configurations described in the above embodiment can be combined in any combination. [Explanation of symbols]

[0062] 1...information processing device, 10h...host system, 11...CPU, 12...main memory, 21...chipset, 22...BIOS memory, 23...socket, 24...audio system, 25...video system, 26...WLAN card, 27...USB connector, 31...EC, 32...input device, 33...power supply circuit, 38...power button, D01...rectifier element, AG01...logical AND circuit

Claims

1. A host system; A rectifying element that outputs a signal input to one end to the other end; A socket for connecting a peripheral device; the host system is connected to the other end; The socket is a first signal terminal to which a first signal is input from the peripheral device when the peripheral device is connected, and a second signal terminal to which a second signal is input, the first signal terminal being connected to the one terminal; the first signal has a first voltage greater than a reference potential; the second signal has a second voltage higher than the reference potential when the first voltage is equal to or lower than an operating voltage of the host system, and has a second voltage not significantly different from the reference potential when the first voltage is higher than the operating voltage of the host system; When the first voltage is higher than the operating voltage of the host system, the potential of the one end is brought closer to the reference potential. Information processing device.

2. The circuit configuration is The second signal terminal is short-circuited to the first signal terminal. The information processing device according to claim 1 .

3. a power supply circuit capable of supplying power to the peripheral device when an operation control signal having a voltage higher than the reference potential is input; a power switch that outputs an operation instruction signal indicating whether or not the information processing device needs to operate depending on whether or not the power switch has a voltage higher than the reference potential; Equipped with The circuit configuration is When the voltage of the operation instruction signal and the second voltage are higher than the reference potential, the voltage is higher than the reference potential; a logical AND circuit configured to output, to the power supply circuit, an operation control signal having a voltage that is not significantly different from the reference potential when at least one of the voltage of the operation instruction signal and the second voltage is not significantly different from the reference potential; The information processing device according to claim 1 .

4. The peripheral device is a solid-state memory device. The information processing device according to claim 1 .

5. The first voltage and the second voltage higher than the reference potential are each equal to an operating voltage of the peripheral device. The information processing device according to claim 1 .

6. the first signal is a sideband signal indicating an operation status of the peripheral device; The second signal is a voltage setting signal indicating an operating voltage of the peripheral device. The information processing device according to claim 1 .

7. the sideband signal is a power loss notification signal that indicates whether or not a power loss has occurred in the peripheral device; The voltage setting signal indicates whether the operating voltage of the peripheral device is equal to the operating voltage of the host system. The information processing device according to claim 6.

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