Imaging apparatus and method for controlling the same, program, and storage medium

Abstract

To provide an imaging apparatus that can smoothly switch between modes, while selecting horizontal scanning periods more suitable for a plurality of operation modes.SOLUTION: An imaging apparatus comprises: a pixel array in which a plurality of pixels are arranged in matrix; a reading unit that can execute the operation of a first mode for reading signals from the pixels a first number of times in one horizontal scanning period, and the operation of a second mode for reading signals from the pixels a second number of times in one horizontal scanning period; and a control unit that sets one horizontal scanning period to a first integral multiple of the cycle of a predetermined basic synchronous signal when in the first mode, and sets one horizontal scanning period to a second integral multiple of the cycle of the basic synchronous signal when in the second mode.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an imaging apparatus and a control method thereof. [Background technology]

[0002] Some electronic devices with camera functions, such as digital cameras and smartphones (hereinafter collectively referred to as imaging devices), have a live view (LV) function. The LV function is a function that captures moving images and displays the obtained images on a display member such as a viewfinder in parallel with the shooting. By checking the displayed live view image, the user can adjust the shooting range for still image shooting or video shooting (hereinafter, this operation of adjusting the shooting range is referred to as framing).

[0003] In order for users to take pictures as they intend, it is important that they be able to frame the image. The indicator of how easy it is to frame the image is called framing performance. For example, when taking a still image after framing a moving image, there is a problem that the acquisition of the moving image stops before and after taking the still image.

[0004] This is because it takes time to switch between video and still image shooting modes before and after capturing a still image, so it takes time to read out the video after capturing a still image. In such cases, the image to be displayed as live view cannot be captured, so the live view display stops before and after capturing a still image, resulting in poor framing performance. In order to improve framing performance, it is important to have a process that allows smooth mode switching between capturing still images and capturing video images.

[0005] For example, Patent Document 1 discloses a method in which the time required to read out one unit of pixel (horizontal scanning period) is set to an integer multiple between multiple modes, and a reset scan of one mode is started before the read scan of the other mode is completed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2021-34963 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the technology disclosed in the above-mentioned Patent Document 1, since it is necessary to align the horizontal scanning periods between the multiple modes to an integer multiple relationship, it is not possible to set the horizontal scanning period optimized for each mode. Therefore, for example, in the case of an image sensor having two operation modes, a situation occurs in which the horizontal scanning period of one operation mode must be extended to match the horizontal scanning period of the other operation mode. In such a case, problems such as an increase in readout time and an associated increase in power consumption occur.

[0008] The present invention has been made in consideration of the above-mentioned problems, and its object is to provide an imaging device that can smoothly switch between multiple operating modes while selecting a more appropriate horizontal scanning period for each mode. [Means for solving the problem]

[0009] An imaging device according to the present invention is characterized in comprising: a pixel array in which a plurality of pixels are arranged in a matrix; readout means capable of executing a first mode operation in which a signal is read out from the pixel a first number of times in one horizontal scanning period; and a second mode operation in which a signal is read out from the pixel a second number of times in one horizontal scanning period; and control means for setting the one horizontal scanning period to a first integer multiple of a period of a predetermined basic synchronization signal in the first mode, and for setting the one horizontal scanning period to a second integer multiple of the period of the basic synchronization signal in the second mode. Effect of the Invention

[0010] According to the present invention, it is possible to provide an imaging device that can smoothly switch between a plurality of operation modes while selecting a horizontal scanning period that is more suitable for the plurality of operation modes. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing the configuration of an imaging apparatus according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing the configuration of an imaging element. [Diagram 3] 4 is a timing chart showing the operation of the imaging element. [Figure 4] FIG. 4 is a diagram showing two ways of reading out a unit pixel. [Diagram 5] 11 is a timing chart showing the relationship between read scanning and reset scanning. [Figure 6] FIG. 11 is a circuit diagram of an image sensor according to a second embodiment. [Figure 7] 6 is a timing chart showing the relationship between a first readout scan and a second readout scan. [Figure 8] 10 is a timing chart showing the operation of an image sensor according to a third embodiment. [Figure 9] FIG. 1 is a circuit diagram of a pixel circuit having a sample and hold circuit. [Figure 10] 10 is a timing chart showing the operation of an image sensor according to a third embodiment. [Figure 11] 10 is a timing chart showing the operation of an image sensor according to a fourth embodiment. [Figure 12] A pixel array with a pupil divided into four and its circuit diagram. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0013] (First embodiment) Fig. 1 is a block diagram showing the configuration of an image pickup device 150 according to a first embodiment of the present invention. In Fig. 1, a first lens 100 is disposed at the tip of an image pickup optical system 104. An aperture 101 adjusts the aperture diameter to adjust the amount of light during image pickup. A second lens 102 and a third lens 103 are driven by a focus actuator 118 (described later) and move forward and backward in the optical axis direction to adjust the focus of the image pickup optical system 104.

[0014] The focal plane shutter 105 has a function of adjusting the exposure time when capturing a still image. The optical low-pass filter 106 is used to reduce false colors and moire in the captured image. The image sensor 107 photoelectrically converts the optical image of the subject formed by the photographing optical system 104 into an electric signal. The DSP 108 receives the image signal output from the image sensor 107 and performs image processing. In addition to image processing, the DSP 108 also calculates information used to drive the focus lenses (second lens 102, third lens 103) based on information from the image sensor 107.

[0015] The RAM 109 has both a function of storing image data processed by the DSP 108 and a function as a work memory when the CPU 110 (described later) operates. In this embodiment, these functions are realized using the RAM 109, but other types of memory can be used as long as the access speed is sufficiently fast and does not cause any operational problems. In this embodiment, the RAM 109 is disposed outside the DSP 108 and the CPU 110, but some or all of the functions may be built into the DSP 108 and the CPU 110.

[0016] The CPU 110 comprehensively controls the operation of the imaging device 150. The CPU 110 executes a program for controlling each part of the imaging device 150. The CPU 110 performs various settings on an SSG (Sync Signal Generator: synchronization signal generation circuit) 111, thereby making it possible for the SSG 111 to periodically output a synchronization signal to the imaging element 107. The CPU 110 has a function of controlling reset scanning timing and read scanning timing, as described below, by directly performing settings on the imaging element 107 and outputting a synchronization signal via the SSG 111.

[0017] In this embodiment, the SSG 111 is described as being external to the image sensor 107, but the present invention is not limited to this and the SSG 111 may be built into the image sensor 107. Furthermore, the image sensor 107 does not necessarily need to be controlled by a synchronization signal, and can be replaced with something like a counter as long as the mechanism operates the sensor based on a predetermined cycle.

[0018] In addition, in this embodiment, the SSG 111 is described as being controlled by the CPU 110, but this is not limiting. For example, the camera itself may be provided with a synchronization signal input terminal, and the SSG 111 may be configured to be controlled by input of a synchronization signal from outside the camera. In this case, the SSG 111 is a synchronization signal output device outside the camera, and the synchronization signal output device and the camera together constitute an imaging device.

[0019] The CPU 110 also has a function of controlling a focus driving circuit 117 (to be described later) using the calculation results output from the DSP 108, and adjusting the focus of the photographing optical system 104. The operation unit 112 has operation members such as buttons and levers. When a user operates the operation unit 112, photographing is performed under the control of the CPU 110. This operation unit 112 includes a still image shooting start button. When it is detected that the user has pressed the still image shooting start button, a still image is shot after a certain time has passed.

[0020] The display unit 113 displays still images, moving images, menus, etc. processed by the DSP 108. The display unit 113 includes an electronic viewfinder (EVF) in addition to a display. The recording medium 114 is a removable recording medium for recording still image data and moving image data. The ROM 115 stores programs that the CPU 110 loads and executes to control the operation of each unit.

[0021] The shutter driving circuit 116 drives and controls the focal plane shutter 105. The focus driving circuit 117 is a focal position changing means for changing the focal position of the photographing optical system 104. Specifically, the focus actuator 118 is controlled based on the output of the CPU 110, and the focus lens (second lens 102, third lens 103) is driven forward and backward in the optical axis direction to adjust the focal position. The aperture driving circuit 119 controls the aperture actuator 120 to control the opening diameter of the aperture 101.

[0022] Next, the configuration of the image sensor 107 will be described with reference to Fig. 2. Fig. 2(a) shows a pixel array (pixel region) in which unit pixels of the image sensor 107 are arranged in a matrix.

[0023] 2(a), a pixel array 200 has a plurality of unit pixels 201 arranged in a row and column direction. Each unit pixel 201 has two photodiodes (PD) 203a, 203b as photoelectric conversion means under a single microlens 202. With this configuration, the PDs 203a, 203b have a pupil-split configuration, and separate images of the same subject with a phase difference are incident on the two PDs 203a, 203b. These two separate images of the same subject with a phase difference are referred to as image A and image B, and PD 203a constitutes a photoelectric conversion unit for image A, and PD 203b constitutes a photoelectric conversion unit for image B.

[0024] FIG. 2B is a diagram illustrating a detailed circuit configuration of the unit pixel 201. As shown in FIG.

[0025] In FIG. 2(b), PD 203a and PD 203b constitute a unit pixel 201 under the same microlens 202 described above. A transfer switch 204a for an image A is controlled by a control signal φtxa, and a transfer switch 204b for an image B is controlled by a control signal φtxb. By setting the control signals φtxa and φtxb to High (hereinafter, High will be referred to as H), the charge accumulated in the photoelectric conversion section can be transferred to a floating diffusion section (FD) 205. The ON / OFF of these transfer switches can be controlled independently, so that the signals for the images A and B can be transferred independently.

[0026] The reset switch 206 is a switch for initializing (resetting) the FD 205, and is controlled by a control signal φres. The pixel amplifier transistor 207 is connected to a constant current source 212 (described later) via a select switch 208 and a column output line 211 (described later). When a control signal φsel to the select switch 208 becomes H, the pixel amplifier transistor 207 is connected to the constant current source 212 (described later) to form a pixel amplifier (source follower circuit). Since the FD 205 is connected to this pixel amplifier, the charge transferred from the PD 203a and PD 203b to the FD 205 is converted by this pixel amplifier into a voltage value according to the amount of charge, and is output to the column output line 211 as a pixel signal.

[0027] In the above description, the pixel signals corresponding to the charges transferred from the PDs 203a and 203b to the FD 205 are read out, but a reset signal is read out before the charges are transferred from the PDs. By reading out the reset signal prior to the charge transfer and then subtracting the reset signal from the pixel signal read out after the charge transfer, it is possible to remove reset noise (kTC noise) from the pixel signal. This type of operation is called correlated double sampling and is widely known as a method for improving image quality, and the image sensor of this embodiment is also capable of such an operation.

[0028] FIG. 2C is a diagram showing a detailed circuit configuration of the image sensor 107.

[0029] In the pixel array 200, (m+1) unit pixels 201 are arranged in the horizontal direction and (n+1) unit pixels 201 in the vertical direction. A timing generator (TG) 210 supplies control signals required for readout to each circuit block according to settings made by the CPU 110 and a synchronization signal periodically input by the SSG 111. A vertical scanning circuit 209 controls the pixels to transfer pixel signals to column output lines 211 by supplying control signals to the pixels. In addition, it is possible to select specific pixels and switch between driving selected pixels and non-selected pixels. In this embodiment, the TG 210 is built into the image sensor 106, but it may be configured to be arranged outside the image sensor 106.

[0030] The pixel signals photoelectrically converted in each unit pixel 201 are output to the column output lines 211 for each row by the control signal supplied from the vertical scanning circuit 209 as described above. The constant current source 212 is combined with the pixel amplifier transistor 207 described above to form a source follower circuit. The readout circuit 213 has a function of amplifying the output from the column output line 211 of each column. The AD conversion circuit (hereinafter, ADC) 214 converts the output of the readout circuit 213 into a digital signal. The image signals converted by the ADC 214 are selected in order by the horizontal scanning circuit 215 and output from the output unit 216 to the outside of the image sensor 107 as a digital signal.

[0031] In the above description, the signals of each pixel in the pixel array are output row by row, but this is not limited to this. By providing multiple column output lines 211 for each pixel column, it is also possible to configure the number of rows read out at one time to be multiple rows. In addition, the unit of pixels read out simultaneously may be each pixel, or a rectangular range consisting of multiple pixels may be read out as one unit.

[0032] Also, a method has been described in which pixel signals are output to the column output line 211 one pixel at a time, and the screen is scanned row by row in sequence to output pixel signals for all pixels, but this need not be the case. For example, it is possible to simultaneously connect two pixels to the column output line 211 and add up pixel signals output from the two pixels on the column output line. Also, there may be pixels whose pixel signal reading is skipped. In this way, the resolution of the image may be changed by adding up pixel signals or skipping reading them.

[0033] Next, a number of operations of the image sensor 107 will be described with reference to the timing chart of FIG.

[0034] The image sensor 107 receives a periodic synchronization signal from the SSG 111 and performs periodic operations based on the input synchronization signal. In the following description, a synchronization signal that specifies a unit period for driving a readout circuit is defined as a basic synchronization signal BD (Basis Driving Signal).

[0035] In this embodiment, the image sensor 107 has four operation modes (operation modes in which multiple readouts are performed): "reset operation", "N readout", "S(A) readout", and "S(A+B) readout". "N readout" refers to reading out a reset signal, "S(A) readout" refers to reading out a pixel signal of PD203a, and "S(A+B) readout" refers to reading out a signal that combines the pixel signals of PD203a and PD203b. The S(B) signal, which is the pixel signal of PD203b, can be obtained by subtracting the S(A) signal from the S(A+B) signal.

[0036] FIG. 3(a) is a timing chart of the reset operation. At time ta300, a basic synchronization signal BD is issued to start the operation. Then, at time ta301, the control signals φtxa and φtxb change from High (hereinafter referred to as H) to Low (hereinafter referred to as L). At this time, the control signal φres remains at H, so PD203a and PD203b, which were connected to the power supply VDD via FD205, are disconnected from the reset level (VDD) at this moment and start accumulating the electric charge generated by the photoelectric conversion. This accumulation start operation occurs simultaneously in multiple pixels (for example, in units of rows), so the load of the power supply VDD fluctuates greatly at this moment. The time from the issuance of the basic synchronization signal BD to this power supply fluctuation is defined as time Δt_evnt. At time ta302, the next basic synchronization signal BD is issued and the reset operation ends. The interval between these basic synchronization signals BD is defined as time T_BD.

[0037] 3(b) is a timing chart of N readout. N readout refers to the reading of a reset signal in CDS (Correlated Double Sampling), where N stands for "noise." At time tb300, a basic synchronization signal BD is issued to start operation. At time tb301, the control signal φres is set to L, and the control signal φsel is set to H. Setting the control signal φres to L determines the reset release level, and setting the control signal φsel to H connects the unit pixel 201 to the column output line 211, and the reset signal is input to the readout circuit 213 and the ADC 214.

[0038] Both of the two operations at time tb301 affect the power supply VDD. That is, by disconnecting the FD 205 under the control of the control signal φres, the number of FDs connected to the power supply VDD changes, causing a power supply fluctuation. Also, under the control of the control signal φsel, a signal is read out to the column output line 211, but since this column output line 211 is also connected to the power supply via the constant current source 212, fluctuations in the potential of this column output line 211 will lead to power supply fluctuations.

[0039] The time from time tb300, the timing of issuing the basic synchronization signal BD, to this power supply fluctuation time tb301 is controlled to be equal to the time Δt_evnt in the reset operation.

[0040] Thereafter, AD conversion starts at time tb302 and ends at time tb303. The period from time tb301 to time tb302 is a settling time for the column output line 211. The next basic synchronization signal BD is issued at time tb304, and the operation ends.

[0041] FIG. 3(c) is a timing chart of S(A) readout. S(A) readout is the reading out of pixel signals corresponding to the charge accumulated in PD203a of the pupil-divided photoelectric conversion unit. Since N readout is performed immediately before this operation, it starts with the control signal φres being L and the control signal φsel being H. At time tc300, a basic synchronization signal BD is issued to start the operation. At time tc301, the control signal φtxa is set to H, and at time tc302, the control signal φtxa is set to L. This operation transfers the charge accumulated in PD203a to FD205.

[0042] At time tc302, when the transfer of the charge from PD 203a to FD 205 is completed, the column output line 211 changes to a voltage according to the amount of charge in FD 205. This change in voltage in the column output line 211 also causes the power supply voltage VDD to change. Therefore, the time from time tc300 when the basic synchronization signal BD is issued to time tc302 when the charge transfer from PD 203a is completed is controlled to be equal to the time Δt_evnt.

[0043] Thereafter, AD conversion starts at time tc303 and ends at time tc304. The period from time tc302 to time tc303 is a settling time for the column output line 211. At time tb305, the next basic synchronization signal BD is issued and the operation ends.

[0044] FIG. 3(d) is a timing chart of S(A+B) readout. S(A+B) readout is the reading of pixel signals according to the charges accumulated in both PDs (PD203a, PD203b) of the pupil-split photoelectric conversion unit. Just before this operation, N readout or S(A) readout is performed, so the operation starts with the control signal φres at L and the control signal φsel at H. At time td300, a basic synchronization signal BD is issued to start operation. At time td301, the control signals φtxa and φtxb are set to H, and at time td302, the control signals φtxa and φtxb are set to L. This operation transfers the charges accumulated in PD203a and PD203b to FD205.

[0045] At time td302, when the transfer of charges from PD203a and PD203b to FD205 is completed, the column output line 211 changes to a voltage corresponding to the amount of charge in FD205. This change in voltage in the column output line 211 also causes the power supply voltage VDD to change. Therefore, the time from time td300 when the basic synchronization signal BD is issued to time td302 when the charge transfer from PD203a to PD203b is completed is controlled to be equal to the time Δt_evnt.

[0046] Thereafter, AD conversion starts at time td303 and ends at time td304. The period from time td302 to time td303 is the settling time of the column output line 211. At time td305, the control signals φres, φtxa, and φtxb are set to H. This operation causes the charge transferred to FD205 to return to the reset state again, and further PD203a and PD203b are also reset via FD205 and return to their initial states.

[0047] At time td306, the control signal φsel is set to L. This operation releases the selection state of the unit pixel 201. At time td307, the next basic synchronization signal BD is issued, and the operation ends.

[0048] In this embodiment, the control signals φtxa and φtxb are changed to H together with the control signal φres when the S(A+B) readout is completed, and the photodiode is reset outside the accumulation time, but this is not limited to this. That is, the control signals φtxa and φtxb do not have to be H at time td305. In this case, since the control signals φtxa and φtxb are L before the reset operation starts, it is necessary to change the control signals φtxa and φtxb to H once somewhere between time ta300 and time ta301 to reset the photodiode. After that, the operation after time ta301 is as described above.

[0049] Next, two readout methods of the unit pixels 201 included in the image sensor 107 and a method of controlling the accumulation time will be described with reference to Fig. 4. The two executable readout methods are non-pupil-split operation and pupil-split operation. For ease of understanding, only the operation of the nth row and the (n+1)th row will be described, but the rows before and after these will also be read out in the same manner as the nth row and the (n+1)th row described below. The entire image read out here is composed of readout by only one of the non-pupil-split operation or pupil-split operation.

[0050] FIG. 4A is a timing chart showing a readout method and an accumulation time control method in a non-pupil division operation.

[0051] At time ta400, a basic synchronization signal BD is issued, and the reset operation of the nth row is started. At time ta401, the reset operation of the nth row is completed. At this timing, the reset operation of the (n+1)th row is not performed. In the non-pupil division operation, when reading out one row, N readout and S(A+B) readout must be performed to perform CDS. Each of these readout operations takes one cycle of the basic synchronization signal BD. In other words, one horizontal scan is performed in an operation of two cycles of the basic synchronization signal BD to read out one row's worth of signals. Therefore, the reset scan for this readout scan must also be performed in the same horizontal scan period for a certain row.

[0052] When the next basic synchronization signal BD is issued at time ta402, two cycles of the basic synchronization signal BD are generated from time ta400 to time ta402, so the reset operation of the next (n+1)th row begins, and the reset operation of the (n+1)th row ends at time ta403.

[0053] Then, after a certain period of time has passed, a basic synchronization signal BD is issued at time ta404, and N readout of the nth row begins. At time ta405, a basic synchronization signal BD is issued, N readout ends, and S(A+B) readout begins. The time from time ta400 to time ta405 corresponds to the accumulation time for the nth row. At time ta406, a basic synchronization signal BD is issued, S(A+B) readout of the nth row ends, and N readout of the (n+1)th row begins.

[0054] The same operation as described above continues for the (n+1)th row, and readout of the (n+1)th row is completed at time ta408. The accumulation time for the (n+1)th row is from time ta402 to time ta407, but as described above, the period of two cycles of the basic synchronization signal BD, which is the cycle of the readout scan (e.g., from time ta404 to time ta406), is matched with the cycle of the reset scan (e.g., from time ta400 to time ta402), so the accumulation time for the nth row and the accumulation time for the (n+1)th row are controlled to be equal.

[0055] FIG. 4B is a timing chart showing a method of reading out signals by pupil division operation and a method of controlling the accumulation time.

[0056] At time tb400, a basic synchronization signal BD is issued, and the reset operation of the nth row is started. At time tb401, the reset operation of the nth row is completed. As in FIG. 4(a), the reset operation of the (n+1)th row is not performed at this timing. In the pupil division operation, when reading out one row, N readout and S(A+B) readout must be performed to perform CDS, and S(A) readout must be performed for the pupil division operation. Each of these readout operations takes one cycle of the basic synchronization signal BD. In other words, one horizontal scan is performed in an operation of three cycles of the basic synchronization signal BD, and one row's worth of signals is read out. Therefore, the reset scan for this readout scan must also be performed in the same horizontal scan period for a certain row.

[0057] At time tb402, the next basic synchronization signal BD is issued, but at this point, only two cycles of the basic synchronization signal BD have passed since time ta400, so the reset operation does not proceed to the next row. When the next basic synchronization signal BD is issued at time tb403, the time from time tb400 to time tb403 now corresponds to three cycles of the basic synchronization signal BD. As a result, the reset operation of the next (n+1)th row begins. The reset operation of the (n+1)th row ends at time tb404, and at the following time tb405, the time from time tb403 corresponds to three cycles of the basic synchronization signal BD, and the reset operation of the next row begins.

[0058] After that, after a certain period of time has elapsed, a basic synchronization signal BD is issued at time tb406, starting N readout of the nth row. At time tb407, a basic synchronization signal BD is issued, ending N readout and starting S(A) readout. At time tb408, a basic synchronization signal BD is issued, ending S(A) readout and starting S(A+B) readout. The time from time tb400 to time tb408 corresponds to the accumulation time of the nth row.

[0059] At time tb409, the basic synchronization signal BD is issued, the S(A+B) readout of the nth row ends, and N readout of the (n+1)th row begins. The same operation as described above continues for the (n+1)th row, and readout of the (n+1)th row is completed at time tb411. The accumulation time for the (n+1)th row is from time tb403 to time tb410, but as described above, the period of three cycles of the basic synchronization signal BD (e.g., from time tb406 to time tb409), which is the cycle of the readout scan, is matched with the cycle of the reset scan (e.g., from time tb400 to time tb403), so the accumulation time for the nth row and the accumulation time for the (n+1)th row are controlled to be equal.

[0060] As described above, according to the timing chart of Figure 4, by combining the four operating modes of "reset operation," "N readout," "S(A) readout," and "S(A+B) readout" described in Figure 3, it is possible to realize both non-pupil-divided operation and pupil-divided operation.

[0061] In addition, in this embodiment, the timing (Δt_evnt) at which the power supply voltage of the pixel changes significantly is the same for each operation, as described in Fig. 3. By controlling in this way, even if any of the operations overlap, the configuration is such that they are unlikely to affect each other.

[0062] For example, in the timing chart of S(A+B) readout described in FIG. 3(d), after Δt_evnt has elapsed, the transfer of charges from both PD 203a and PD 203b is completed, and the power supply voltage changes. After that, there is a waiting time for the voltage of the column output line 211 to settle. If Δt_evnt is the same, there is no problem even if a reset operation of another row is performed during this operation. For example, as shown in FIG. 3(a), the power supply voltage change timing Δt_evnt of the reset operation is the same as the power supply voltage change timing Δt_evnt of the S(A+B) readout, so it can be seen that it does not affect the settling of the column output line 211.

[0063] In addition, in Fig. 3, Δt_evnt is assumed to be completely the same in each operation, but the present invention is not limited to this. It can be freely set within a range that does not affect each other's operations.

[0064] FIG. 5 is a timing chart showing a method of switching between non-pupil-divided operation readout and pupil-divided operation readout.

[0065] Figure 5(a) is a timing chart showing a method of switching between non-pupil-split operation and pupil-split operation when acquiring images over multiple frames. In the figure, VD indicates a vertical synchronization signal (Vertical Driving Signal), and the period between successive vertical synchronization signals is set to an integer multiple of the basic synchronization signal BD. SHT_X indicates the reset scan for non-pupil-split operation, and RD_X indicates the readout scan for non-pupil-split operation. SHT_Y indicates the reset scan for pupil-split operation, and RD_Y indicates the readout scan for pupil-split operation. The horizontal axis represents time, and the inclined scanning line indicates that the timing of the reset operation and readout operation is different at the top and bottom of the screen because it takes time to scan from the top to the bottom of the screen using the rolling shutter method.

[0066] When VD is issued at time ta500, a read scan of a non-pupil-divided operation starts. Then, at time ta501, a reset scan of a non-pupil-divided operation for the next readout starts. At this point, the read scan mode and the reset scan mode match.

[0067] When VD is issued at time ta502, a readout scan of a non-pupil-divided operation corresponding to the reset scan at time ta501 starts. The accumulation time is the period from time ta501 to time ta502.

[0068] From time ta503, before the readout scan of the non-pupil-divided operation that started at time ta502 is completed, a reset scan for the pupil-divided operation is started. At this time, the readout scan is a non-pupil-divided operation, and the reset scan is a pupil-divided operation, and the readout scan and reset scan of different operation modes are performed simultaneously. Next, when VD is issued at time ta504, the readout scan of the pupil-divided operation is started.

[0069] From time ta505, ​​before the readout scan of the pupil-divided operation that started at time ta504 is completed, a reset scan for a non-pupil-divided operation is started.

[0070] Fig. 5(b) is a timing chart showing the operation when the readout scan and the reset scan are in different modes. Here, the readout scan is for the non-pupil-divided operation, and the reset scan is for the pupil-divided operation. Expressed in the timing chart of Fig. 5(a), it is the period after time ta503 and before the end of the non-pupil-divided operation that started at time ta502.

[0071] When a basic synchronization signal BD is issued at time tb500, a reset operation of the mth row is started. At the same time, an N readout operation of the nth row is started. When a basic synchronization signal BD is issued at time tb501, an S(A+B) readout of the nth row is started. At the following time tb502, the readout scanning proceeds to the next row and N readout of the (n+1)th row is started.

[0072] On the other hand, the reset scan corresponds to the readout of the pupil division operation in which one horizontal scanning period is composed of three cycles of the basic synchronization signal BD. Therefore, at time Tb502, which is the timing when two cycles of the basic synchronization signal BD have passed from time tb500, the reset scan of the next row does not proceed.

[0073] At time tb503, S(A+B) readout of the (n+1)th row begins. Since the basic synchronization signal BD has three cycles from time tb500 to time tb503, reset scanning proceeds to the next row and reset scanning of the (m+1)th row begins.

[0074] In this timing chart, the reset operation on the mth row starts at time tb500, and at the same time the N read operation on the nth row is performed. As explained in Figure 4, the power supply voltage change timing Δt_evnt of the reset operation and the N read operation are the same, so the reset operation does not affect the N read operation. Also, the reset operation on the (m+1)th row starts at time tb503, and at the same time the S(A+B) read operation on the (n+1)th row is performed. Again, the reset operation does not affect the S(A+B) read operation.

[0075] As described above, according to this embodiment, even if reset scanning and readout scanning, which perform scanning at different cycles, are performed in parallel at the same timing on different rows, control can be performed so as not to affect image quality. This makes it possible to easily switch modes while selecting a horizontal scanning period more suitable for each of a plurality of modes.

[0076] Second embodiment In the first embodiment, switching between different modes was described, but by dividing one horizontal scanning period into multiple periods (composing one horizontal scanning period by multiple cycles of a basic synchronization signal), it is possible to provide flexibility in readout even between the same modes.

[0077] 6 is a diagram showing a circuit configuration of the image sensor 107 in the second embodiment. The same components as those in the circuit diagram of FIG. 2(c) are given the same reference numerals. Compared to the diagram of FIG. 2(c), a plurality of column output lines are provided. These plurality of column output lines are referred to as a first column output line 600 and a second column output line 601.

[0078] The first column output line 600 is connected to pixels in odd-numbered rows, and the second column output line 601 is connected to pixels in even-numbered rows. In this case, if the pixels in odd-numbered rows and the pixels in even-numbered rows are read out simultaneously, the readout speed can be improved, but it is also possible to read out the pixels completely independently in terms of timing. The readout scan of the pixels connected to the first column output line 600 is called the first readout scan, and the readout scan of the pixels connected to the second vertical line 601 is called the second readout scan.

[0079] In this embodiment, the PD included in the unit pixel 201 may be pupil-divided, but for ease of understanding, the PD is described as not being pupil-divided. Also, reading of pixel signals in this case is simply referred to as "S readout."

[0080] 7A is a timing chart for reading out using the first readout scan and the second readout scan. RD_1 represents the first readout scan, and RD_2 represents the second readout scan. Although the notation of the reset scan is omitted, as explained in the first embodiment, the reset scan and the readout scan can operate without affecting each other, regardless of the phase relationship.

[0081] When the vertical synchronization signal VD is issued at time ta700, the first readout scan starts.

[0082] Subsequently, at time ta701, the second readout scan is started. This second readout scan may be started at any timing, with the basic synchronization signal BD as a period. For example, the start timing of the second readout scan may be controlled by programming the number of basic synchronization signals BD issued from the issuance of VD until the start of the second readout scan in the image sensor 107. Also, the second readout scan may be started from the next basic synchronization signal BD after receiving an input signal from outside.

[0083] The second readout scan is completed by time ta702, and the next second readout scan starts at time ta702.

[0084] At time ta703, the first readout scan is started, but the second readout scan is still running at this point. The phase relationship between the first readout scan and the second readout scan at time ta701 and the phase relationship between the first readout scan and the second readout scan at time ta703 may be the same, but for ease of understanding, the following description will be given assuming that they are different phase relationships.

[0085] FIG. 7B is a timing chart illustrating the phase relationship between the readout timing of the first readout scan and the second readout scan.

[0086] When the basic synchronization signal BD is issued at time tb700, the first readout scan is performed on the nth row, and the second readout scan is performed on the mth row, and both scans start Nth readout at exactly time tb700. At this time, the first readout scan and the second readout scan can be said to be in phase. In a phase-matched relationship, the same operation is performed on different rows, so the power supply fluctuation timing is exactly the same for both, and there is no impact on image quality.

[0087] Next, at time tb701, a basic synchronization signal BD is issued and N readout of the nth row is performed by a first readout scan, and at time tb702, the next basic synchronization signal BD is issued and N readout of the mth row is performed by a second readout scan.

[0088] For both the first readout scan and the second readout scan, one horizontal scan period is two cycles of the basic synchronization signal BD, so in this case they can be said to be out of phase. In a phase-out relationship, different operations are performed on different rows (N readout and S readout in this case). However, as explained in the timing chart of Figure 3, the power supply voltage change timing Δt_evnt is designed to be the same for all operations, so even if such operations are performed, they do not affect each other's image quality.

[0089] As described above, according to this embodiment, in a configuration in which multiple readout scans can be started at independent timings, it is possible to control the readout scan start timing in units finer than one horizontal scanning period while controlling it in a way that does not affect the image.

[0090] (Third embodiment) The ADC 214 may have a variety of configurations, and the embodiment of the present invention may vary depending on the configuration.

[0091] Fig. 8 is a timing chart relating to a number of operations of the image sensor 107 in the third embodiment. The same timings as those explained in Fig. 3 of the first embodiment are given the same reference symbols. In this embodiment, as in the first embodiment, the image sensor 107 operates in four types of operation modes: "reset operation", "N readout", "S(A) readout", and "S(A+B) readout".

[0092] FIG. 8(a) is a timing chart showing the reset operation in the third embodiment, but since it is the same as the timing chart in FIG. 3(a), the description will be omitted.

[0093] 8B is a timing chart showing the operation of N readout in the third embodiment. Here, the operation period of the ADC214 is the period from time tb302 to time tb800. This is shorter than the operation period of the ADC214 for N readout in the first embodiment, from time tb302 to time tb303. This is for the following reason. That is, since N readout contains only dark current and kTC noise components, it is not necessary to perform AD conversion in the same range as the signal components. Therefore, accuracy can be guaranteed even if the time required for AD conversion is shorter than that for S(A+B) readout.

[0094] FIG. 8(c) is a timing chart showing the operation of S(A) readout in the third embodiment. Here, the operation period of the ADC214 is the period from time tc303 to time tc800. This is shorter than the operation period of the ADC214 for S(A) readout in the first embodiment, which is from time tc303 to time tc304. This is for the following reason. That is, since the S(A) readout includes only the charge component of the PD203a, which is one side of the pupil division of the unit pixel, it is not necessary to perform AD conversion in the same range as when all signals under the unit pixel are AD converted. Therefore, accuracy can be guaranteed even if the time required for AD conversion is shorter than that required for S(A+B) readout.

[0095] FIG. 8(d) is a timing chart showing the operation of reading S(A+B) in the third embodiment, but since it is the same as the timing chart in FIG. 3(d), the description will be omitted.

[0096] As described above, the ADC 214 can be configured to perform AD conversion in an appropriate range depending on the signal. In this case, when each operation is viewed individually, the interval of the basic synchronization signal BD can be shortened by the amount of the AD conversion that is shortened. However, in order to perform the operations described in the first and second embodiments, the period of the basic synchronization signal BD is adjusted to match that required for the AD conversion shown in FIG. 8(d), which takes the longest time in each operation mode.

[0097] When operated in this way, there is an excess of time for the shortened AD conversion in N readout and S(A) readout. During this excess time, the ADC214 can save power (reduce power consumption) by turning off the power supply for part of the circuit. Other blocks in the image sensor can also save power in the same way.

[0098] It is also possible to configure the circuit so that the time required for AD conversion is not included in the cycle by providing a sample-and-hold circuit before the ADC 214. Figure 9 shows a circuit diagram of a pixel circuit with a sample-and-hold circuit. The same reference symbols are used for the same components as in Figure 2.

[0099] 9, a control signal φSH is applied to the gate terminal of a sample and hold switch 900. By setting the control signal φSH to H level, the column output line 211 and the sample and hold capacitance 901 are connected, making it possible to sample and hold the output of the column output line 211. Thereafter, by setting the control signal φSH to L level, the sampled and held signal is held even if the potential of the column output line 211 fluctuates.

[0100] The comparator 902 compares the signal held in the sample and hold capacitor 901 with the ramp signal generated by the ramp signal generating circuit 903. The output of the comparator 902 is input to the counting circuit 904, and the counting of the counting circuit 904 is stopped at the timing when the output of the comparator 902 is inverted. In this manner, the signal of the sample and hold capacitor 901 is AD converted. The AD conversion operation of the ADC 214 is performed by the comparator 902, the ramp signal generating circuit 903, and the counting circuit 904 operating as described above. Such an ADC 214 is also called a single-slope type AD conversion circuit.

[0101] In this embodiment, a single-slope AD conversion circuit is shown, but the present invention is not limited to this. In addition, the AD conversion method is known to be a ΔΣ method or a successive approximation method, and any of them may be used. In addition, a sample hold capacitor 901 is prepared as a sample hold means, and sample hold is performed by voltage, but this is not necessarily the case, and any means that can hold a pixel signal may be used.

[0102] 9 into multiple power domains, the independence of the sample-and-hold capacitance can be improved. The circuits around the pixels are power domain A 905, and the circuits around the sample-and-hold circuit and AD conversion unit are power domain B 906, and each is supplied with a different power source. This makes it possible to achieve a configuration in which the AD conversion is not affected by power supply fluctuations around the unit pixels 201 and column output lines 211.

[0103] Next, a number of operations of the image sensor 107 in this embodiment will be described with reference to the timing chart in Fig. 10. In this embodiment, as in the first embodiment, the image sensor 107 operates in four operation modes: "reset operation", "N readout", "S(A) readout", and "S(A+B) readout".

[0104] Of these, the "reset operation" shown in Fig. 10(a) is not affected by the operation of the sample-and-hold capacitor, and the control signal φSH is always at level L. At this time, the only difference from the timing chart in Fig. 3(a) is that the period T_BD of the basic synchronization signal BD becomes shorter, so the explanation of the timing chart will be omitted.

[0105] 10(b) is a timing chart of N readout in this embodiment. At time tb1000, a basic synchronization signal BD is issued to start operation. At time tb1001, the control signal φres is set to L, the control signal φsel is set to H, and the control signal φSH is set to H. By setting the control signal φres to L, the reset release level is determined, and by setting the control signal φsel to H, the pixel circuit is connected to the column output line 211. In addition, by setting the control signal φSH to H, the output of the column output line 211 is output to the sample and hold capacitance 901.

[0106] At time tb1002, it is assumed that the output of the column output line 211 has sufficiently charged the sample and hold capacitance 901. At this time, the control signal φSH is set to L, and the sample and hold capacitance 901 is disconnected from the column output line 211. At the same time, the control signal φsel is also set to L, and the pixel and the column output line 211 are also disconnected. By disconnecting the sample and hold circuit from the pixel circuit in this way, even if there is a fluctuation in the column output line 211 while the sampled and held signal is being AD converted, the result of the AD conversion is not affected.

[0107] At time tb1002, AD conversion of the N signal held in the sample and hold capacitor 901 starts, and ends at time tb1003. At time tb1004, the next basic synchronization signal BD is issued, and the operation ends.

[0108] 10(c) is a timing chart of S(A) readout in this embodiment. At time tc1000, a basic synchronization signal BD is issued to start operation. At time tc1001, the control signal φtxa is set to H, and at time tc1002, the control signal φtxa is set to L. This operation transfers the charge accumulated in PD203a to FD205. At this time tc1002, the control signals φsel and φSH are also set to H. As a result, the charge in PD203a is transferred to FD205, the column output line 211 changes to a voltage according to the amount of charge, and the signal is held in the sample and hold capacitance 901.

[0109] When the signal holding is completed at time tc1003, the control signals φsel and φSH are set to L, disconnecting the sample and hold capacitor 901 from the column output line 211. At the same time, AD conversion of the signal held in the sample and hold capacitor 901 is started.

[0110] At time tc1004, the basic synchronization signal BD is issued, but the AD conversion operation is not completed. However, the AD conversion operation is performed on the signal held in the sample and hold capacitance 901, and the signal held in the sample and hold capacitance 901 is disconnected from the pixel circuit. Therefore, the unit pixel 201 can start the next operation. The AD conversion started at time tc1003 is completed at time tc1005, which is after the basic synchronization signal BD is issued.

[0111] FIG. 10(d) is a timing chart of S(A+B) readout. At time td1000, a basic synchronization signal BD is issued to start operation. At time td1001, the control signals φtxa and φtxb are set to H, and at time td1002, the control signals φtxa and φtxb are set to L. This operation transfers the charges accumulated in PD203a and PD203b to FD205. At this timing, the control signals φsel and φSH are also set to H. At this time td1002, when the transfer of the charges in PD203a and PD203b to FD205 is completed, the column output line 211 changes to a voltage corresponding to the amount of charge. At the same time, the sample and hold capacitance 901 starts to hold a signal corresponding to the voltage of the column output line 211.

[0112] At time td1003, the control signals φsel and φSH are set to L, disconnecting the sample and hold capacitance 901 from the column output line 211. At the same time, AD conversion of the signal held in the sample and hold capacitance 901 is started.

[0113] At time td1004, the control signals φres, φtxa, and φtxb are set to H, and the FD 205, PD 203a, and PD 203b are set to a reset state.

[0114] At time td1005, a basic synchronization signal BD is issued, and the pixel-related circuits start the following operations. AD conversion ends at time td1006.

[0115] As described above, by using a sample-and-hold circuit, even when the time required for AD conversion differs depending on the type of signal, it is possible to control the operation timing of each circuit so as to commonize and reduce wasted time for each operation.

[0116] In this case, the period T_BD of the basic synchronization signal BD is controlled to be longer than the longer of the time required for the pixel circuit operation and the sample-and-hold circuit to settle and the time required for the AD conversion, which takes the longest time. This is because, even if it does not take long for the circuit operation and the sample-and-hold circuit to settle, if the basic synchronization signal BD is issued at a period shorter than the AD conversion time, the next AD conversion of a pixel may start before the completion of the AD conversion, and the signal cannot be read out correctly. Conversely, even if it takes longer for the circuit operation and the sample-and-hold circuit to settle than the time required for the AD conversion, which takes the longest time, if the period T_BD of the basic synchronization signal BD is set to exactly the AD conversion period, the pixel signal may not be read out correctly due to, for example, a lack of settling time.

[0117] As described above, according to the present embodiment, when AD conversion of a plurality of types of signals takes different times, it is possible to operate with reduced power consumption. In addition, it is possible to suppress an increase in scanning time caused by differences in AD conversion times.

[0118] (Fourth embodiment) The present invention can be applied to various readout methods and pixel structures. In general, when reading out a signal from a pixel N times (N is a positive integer), one horizontal scanning period can be configured by issuing a basic synchronization signal BD N times. In addition, it is not necessary to read out the entire screen using one type of readout mode.

[0119] 11(a) is a diagram showing an example in which a screen is constructed by S(A) readout and S(A+B) readout. Since the nth row is a readout of a non-pupil-divided operation, one horizontal scanning period is two cycles of the basic synchronization signal BD, and since the (n+1)th row is a readout of a pupil-divided operation, one horizontal scanning period is three cycles of the basic synchronization signal BD. In this way, one image may be constructed by two readout methods.

[0120] 11(b) is a diagram showing an example of a multi-sampling operation in which one pixel signal is read out multiple times to perform noise reduction processing. In this way, when performing an operation in which N readout is performed once and S(A+B) readout is performed four times, one horizontal scanning period is set to five cycles of the basic synchronization signal BD. In addition, in the S(A+B) readout, PD203a, PD203b, and FD205 are not reset except in the last cycle. Using the S(A+B) signal read out multiple times in this way, noise can be reduced by performing averaging processing in, for example, the DSP 108.

[0121] The noise reduction method is not limited to this. Two signals multiplied by different gains may be read out and processed to reduce noise. Any other method is possible as long as it is a method of acquiring signals multiple times from the same pixel and reducing noise. In addition, although the noise reduction calculation is performed by the DSP 108 in this embodiment, this is not limited to this. For example, a configuration in which a calculation circuit for noise reduction is built into the image sensor 107 may be used.

[0122] 12(a) is a diagram showing an example in which four photodiodes PD1203a, PD1203b, PD1203c, and PD1203d are arranged under a single microlens 202 of a unit pixel 201. When the unit pixel 201 is pupil-divided into four in this way, five signal readouts, including N readout, are required to obtain all pupil-divided signals. Therefore, in such a case, one horizontal scanning period is composed of five cycles of the basic synchronization signal BD.

[0123] 12(b) is a timing chart showing a readout method when the unit pixel 201 is pupil-divided into four. The four divided PDs are designated as A, B, C, and D, and the signal types are shown in parentheses for S() readout. This timing chart shows that a period of five cycles of the basic synchronization signal BD is required for each of the signals PD1203a, PD1203b, PD1203c, and PD1203d, and five readouts of N readout.

[0124] In this embodiment, the four divided signals are read out independently by S(A), S(B), S(C), and S(D) readout, but the present invention is not limited to this. For example, the pixel signals may be read out by S(A), S(A+B), S(A+B+C), and S(A+B+C+D) readout, and the signals of each PD may be separated by arithmetic processing.

[0125] Also, just because the pupil is divided into four does not necessarily mean that it needs to be divided into four and read out; a signal that combines the pupils may be read out. For example, if the PD signals are combined and read out, such as N readout, S(A+B) readout, or S(A+B+C+D) readout, this is essentially equivalent to reading out a signal that divides the pupil in two. In this case, although the phase difference detection capability is inferior to when the pupil is divided into four and read out, one horizontal scanning period can be composed of three cycles of the basic synchronization signal BD, so the readout time can be shortened.

[0126] As described above, according to this embodiment, in image sensors of various configurations, the length of one horizontal scanning period can be changed in units of an integer multiple of a predetermined period depending on the number of times signals are read out from a pixel, thereby realizing an appropriate readout method for each.

[0127] The disclosure of this specification includes the following imaging apparatus, a control method thereof, a program, and a storage medium.

[0128] (Item 1) A pixel array in which a plurality of pixels are arranged in a matrix; a readout means capable of executing a first mode operation for reading out a signal from the pixel a first number of times in one horizontal scanning period, and a second mode operation for reading out a signal from the pixel a second number of times in one horizontal scanning period; a control means for setting the one horizontal scanning period to a first integer multiple of a cycle of a predetermined basic synchronization signal in the first mode, and for setting the one horizontal scanning period to a second integer multiple of the cycle of the basic synchronization signal in the second mode; An imaging device comprising:

[0129] (Item 2) 2. The imaging device according to item 1, wherein the pixel has one microlens and a plurality of photoelectric conversion units.

[0130] (Item 3) 3. The imaging device according to item 2, wherein in the first mode, the readout means reads out from the pixel a signal obtained by adding together a reset signal and signals from the plurality of photoelectric conversion units.

[0131] (Item 4) The imaging device described in item 3, characterized in that in the first mode, the readout means reads out the reset signal in one cycle of the basic synchronization signal, and reads out a signal obtained by adding up the signals of the multiple photoelectric conversion units in another cycle of the basic synchronization signal.

[0132] (Item 5) 5. The imaging device according to item 3 or 4, wherein the control means adjusts the reset cycle of the pixels to the cycle of one horizontal scanning period in the first mode.

[0133] (Item 6) 3. The imaging device according to item 2, wherein in the second mode, the readout means reads out a reset signal from the pixel and also reads out signals of the plurality of photoelectric conversion units in a separable manner.

[0134] (Item 7) The imaging device described in item 6, characterized in that in the second mode, the readout means reads out the reset signal in one cycle of the basic synchronization signal, and reads out signals from the multiple photoelectric conversion units every other cycle of the basic synchronization signal.

[0135] (Item 8) The imaging device described in item 7, characterized in that in the second mode, the readout means reads out the reset signal in one cycle of the basic synchronization signal, reads out some of the signals of the multiple photoelectric conversion units in another cycle of the basic synchronization signal, and reads out a signal obtained by adding up the signals of the multiple photoelectric conversion units in yet another cycle of the basic synchronization signal.

[0136] (Item 9) Any one of items 6 to 8, characterized in that the control means adjusts the reset period of the pixel to the period of one horizontal scanning period in the second mode. The imaging device according to claim 1 .

[0137] (Item 10) The imaging device described in any one of items 1 to 9, further comprising an AD conversion means for AD converting the signal, wherein the control means sets a period of the basic synchronization signal to a time longer than a time required for the AD conversion means to perform AD conversion.

[0138] (Item 11) 11. The imaging device according to item 10, wherein the control means reduces the power of the AD conversion means during a time period corresponding to a difference between a period of the basic synchronization signal and a time period during which the AD conversion means performs AD conversion.

[0139] (Item 12) 12. The imaging device according to item 10 or 11, characterized in that the AD conversion means performs AD conversion on a signal of a holding means that holds a signal of the pixel, and the control means sets a period of the basic synchronization signal to a time longer than a time for the holding means to hold the signal and settle.

[0140] (Item 13) The imaging device described in item 1, characterized in that the control means controls the readout means to read out signals of pixels in some rows of the pixel array by operation in the first mode, and to read out signals of pixels in the remaining rows of the pixel array by operation in the second mode.

[0141] (Item 14) 14. The imaging device according to any one of items 1 to 13, wherein the control means matches the first integer with the first number of times and matches the second integer with the second number of times.

[0142] (Item 15) The imaging device described in item 1, characterized in that the control means sets the one horizontal scanning period to an integer multiple of the period of the basic synchronization signal even when the control means causes the readout means to perform either one of the first mode operation and the second mode operation.

[0143] (Item 16) Item 16. The imaging device described in item 15, characterized in that the pixel has a plurality of output lines, and the control means controls the readout means to perform either the operation of the first mode or the operation of the second mode in one row and another row in the pixel array in an overlapping manner.

[0144] (Item 17) A method for controlling an imaging device having a pixel array in which a plurality of pixels are arranged in a matrix, comprising the steps of: a readout step capable of executing a first mode operation for reading out a signal from the pixel a first number of times in one horizontal scanning period, and a second mode operation for reading out a signal from the pixel a second number of times in one horizontal scanning period; a control step of setting the one horizontal scanning period to a first integer multiple of a period of a predetermined basic synchronization signal in the first mode, and setting the one horizontal scanning period to a second integer multiple of the period of the basic synchronization signal in the second mode; 13. A method for controlling an imaging apparatus comprising:

[0145] (Item 18) Item 18. A program for causing a computer to execute each step of the control method described in Item 17.

[0146] (Item 19) A computer-readable storage medium storing a program for causing a computer to execute each step of the control method described in item 17.

[0147] (Other embodiments) The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0148] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0149] 110: CPU, 200: pixel array, 201: unit pixel, 202: microlens, 203a, 203b: photodiodes, 209: vertical scanning circuit, 210: timing generator

Claims

1. A pixel array in which a plurality of pixels are arranged in a matrix; a readout means capable of executing a first mode operation for reading out a signal from the pixel a first number of times in one horizontal scanning period, and a second mode operation for reading out a signal from the pixel a second number of times in one horizontal scanning period; a control means for setting the one horizontal scanning period to a first integer multiple of a period of a predetermined fundamental synchronization signal in the first mode, and for setting the one horizontal scanning period to a second integer multiple of the period of the fundamental synchronization signal in the second mode; An imaging device comprising:

2. The imaging device according to claim 1 , wherein the pixel includes one microlens and a plurality of photoelectric conversion units.

3. 3. The imaging device according to claim 2, wherein in the first mode, the readout means reads out from the pixel a signal obtained by adding together a reset signal and signals from the plurality of photoelectric conversion units.

4. 4. The imaging device according to claim 3, wherein, in the first mode, the readout means reads out the reset signal during one period of the basic synchronization signal, and reads out a signal obtained by adding up the signals of the multiple photoelectric conversion units during another period of the basic synchronization signal.

5. 4. The imaging device according to claim 3, wherein said control means matches a reset cycle of said pixels to a cycle of one horizontal scanning period in said first mode.

6. 3. The imaging device according to claim 2, wherein in the second mode, the readout means reads out a reset signal from the pixel and also reads out signals from the plurality of photoelectric conversion units in a separable manner.

7. The imaging device according to claim 6, characterized in that, in the second mode, the readout means reads out the reset signal during one period of the basic synchronization signal, and reads out the signals of the multiple photoelectric conversion units every other period of the basic synchronization signal.

8. The imaging device described in claim 7, characterized in that in the second mode, the readout means reads out the reset signal during one period of the basic synchronization signal, reads out some of the signals of the multiple photoelectric conversion units during another period of the basic synchronization signal, and reads out a signal obtained by adding up the signals of the multiple photoelectric conversion units during yet another period of the basic synchronization signal.

9. 7. The imaging device according to claim 6, wherein said control means matches a reset cycle of said pixels to a cycle of one horizontal scanning period in said second mode.

10. 2. The imaging apparatus according to claim 1, further comprising an AD conversion unit for performing AD conversion of the signal, wherein the control unit sets a period of the basic synchronization signal to a time longer than a time required for AD conversion by the AD conversion unit.

11. 11. The image pickup apparatus according to claim 10, wherein the control means reduces the power of the AD conversion means during a time period corresponding to a difference between a period of the basic synchronizing signal and a time period during which the AD conversion means performs AD conversion.

12. 11. The imaging device according to claim 10, wherein the AD conversion means performs AD conversion on a signal from a holding means that holds a signal from the pixel, and the control means sets a period of the basic synchronization signal to a time longer than a time it takes for the holding means to hold the signal and settle.

13. 2. The imaging device according to claim 1, wherein the control means controls the readout means to read out signals of pixels in some rows of the pixel array in the first mode of operation, and to read out signals of pixels in the remaining rows of the pixel array in the second mode of operation.

14. 2. The image pickup apparatus according to claim 1, wherein the control means causes the first integer to coincide with the first number of times, and causes the second integer to coincide with the second number of times.

15. 2. The imaging device according to claim 1, wherein the control means sets the one horizontal scanning period to an integer multiple of the period of the basic synchronization signal even when the control means causes the readout means to perform either one of the first mode operation and the second mode operation.

16. 16. The imaging device according to claim 15, wherein the pixel has a plurality of output lines, and the control means controls the readout means so that one of the operation in the first mode and the operation in the second mode is performed in an overlapping manner in one row and another row in the pixel array.

17. A method for controlling an imaging device having a pixel array in which a plurality of pixels are arranged in a matrix, comprising the steps of: a readout step capable of executing a first mode operation of reading out a signal from the pixel a first number of times in one horizontal scanning period, and a second mode operation of reading out a signal from the pixel a second number of times in one horizontal scanning period; a control step of setting the one horizontal scanning period to a first integer multiple of a period of a predetermined fundamental synchronization signal in the first mode, and setting the one horizontal scanning period to a second integer multiple of the period of the fundamental synchronization signal in the second mode; 13. A method for controlling an imaging apparatus comprising:

18. A program for causing a computer to execute each step of the control method according to claim 17.

19. A computer-readable storage medium storing a program for causing a computer to execute each step of the control method according to claim 17.

Images