Method and apparatus for integrated selective monolayer doping

Abstract

To provide a method and apparatus for forming a doped material layer in a semiconductor device using an integrated selective monolayer doping (SMLD) process.SOLUTION: In a semiconductor structure 300, an SMLD layer 302 is deposited on a substrate 202 using a single layer doping (SMLD) process, the dopant aggregates are annealed to diffuse the dopant aggregates into the substrate, and the SMLD process co-forms the dopant aggregates onto the substrate surface. The SMLD process is performed in a single CVD chamber. The SMLD process may be iterated in order to further modify the diffusion parameters at which the dopant molecules 304 diffuse into the substrate. The SMLD process is compatible with p-type and n-type dopant species.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001]

[0001] Embodiments of the present principles relate generally to semiconductor processing. [Background technology]

[0002]

[0002] The addition of small amounts of foreign atoms to the regular crystal lattice of silicon or germanium causes changes in the electrical properties of the material. The impurities (or dopants) added into the crystal lattice can be controlled to produce semiconductor materials of various electrical properties (e.g., n-type or p-type). Metal-Oxide-Semiconductors (MOS) utilize structures containing n-type and p-type doped materials to regulate the flow of electricity. The inventors of the present invention have realized that conventional doping processes are time-consuming and increase manufacturing costs. Conventional doping processes are performed on the surface of a substrate, and undoped areas of the substrate must be covered with a mask to limit the doped area on the substrate surface. As the size of semiconductor structures shrinks, the masking resolution required to control the doped area increases, reducing yields and requiring more specialized equipment.

[0003] SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, the present inventors have provided an improved method and apparatus for doping semiconductor structures. Summary of the Invention

[0004]

[0004] Provided herein is a method and apparatus for a integrated selective single layer doping (SMLD) process for semiconductor structures.

[0005]

[0005] In some embodiments, a method for forming a doped semiconductor feature includes depositing a dopant concentration on a material layer using a selective monolayer doping (SMLD) process.

[0006]

[0006] In some embodiments, a method includes exposing a doped semiconductor feature to a gas mixture containing a dopant to selectively deposit dopant aggregates on the material layer; varying a duration of exposure to the gas mixture or a dopant concentration in the gas mixture to control a density of the dopant aggregates on the material layer; conforming the dopant aggregates to a surface of the material layer using an SMLD process, the method being performed in a single semiconductor processing chamber; conforming the dopant aggregates; annealing the dopant aggregates to diffuse them into the material layer; The method may further include repeating the method to increase dopant agglomerations in the material layer, varying the temperature of the annealing to vary the depth to which the dopant agglomerates penetrate into the material layer, varying the duration for depositing the dopant agglomerates to increase the amount of active dopant in the dopant agglomerates, depositing dopant agglomerates comprising a p-type dopant species comprising boron or gallium, depositing dopant agglomerates comprising an n-type dopant species comprising arsenic or phosphorous, pre-cleaning the surface of the material layer prior to depositing the dopant agglomerates, and / or integrating the SMLD process with the formation of source / drains of semiconductor structures.

[0007]

[0007] In some embodiments, a method for forming doped semiconductor features on a substrate having a first material with non-dielectric properties and a second material with dielectric properties includes immersing the substrate in a gas containing dopant aggregates, which selectively forms a monolayer of dopant on a first surface of the first material but not on a second surface of the second material, and annealing the substrate to diffuse the dopant into the first material.

[0008]

[0008] In some embodiments, the method may further include varying the gas immersion duration, gas immersion pressure, gas immersion flow rate, or gas immersion dopant concentration to control dopant diffusion parameters, repeating the method while changing the annealing temperature in at least one cycle to vary the depth to which the dopant agglomerates penetrate into the first material, and / or repeating the method while changing the gas immersion duration, gas immersion pressure, gas immersion flow rate, or gas immersion dopant concentration in at least one cycle to vary the amount of dopant on the first surface of the first material.

[0009]

[0009] In some embodiments, a method for forming doped semiconductor features on a substrate having a first material having non-dielectric properties and a second material having dielectric properties may include immersing the substrate in a gas containing dopant aggregates, which selectively forms a monolayer of dopant on a first surface of the first material but not on a second surface of the second material, annealing the substrate to diffuse the dopant into the first material, and repeating the method while varying the gas immersion duration, gas immersion pressure, gas immersion flow rate, or gas immersion dopant concentration in at least one cycle to vary the amount of dopant on the first surface of the first material, and repeating the method while varying the annealing temperature in at least one cycle to vary the depth to which the dopant penetrates into the first material.

[0010]

[0010] Other and further embodiments are disclosed below.

[0011]

[0011] The embodiments of the present principles, briefly summarized above and described in detail below, may be understood by reference to exemplary embodiments of the present principles as illustrated in the accompanying drawings. However, since the present principles are susceptible to other equally effective embodiments, the accompanying drawings illustrate only typical embodiments of the present principles and therefore should not be considered as limiting in scope. [Brief description of the drawings]

[0012] [Figure 1] According to some embodiments of the present principles, there is provided a method for performing selective monolayer doping of a semiconductor structure. [Diagram 2]

[0013] 1 is a cross-sectional view of a semiconductor construction, in accordance with some embodiments of the present principles; [Diagram 3]

[0014] 1 is a cross-sectional view of a semiconductor structure after deposition of selective monolayer doping, in accordance with some embodiments of the present principles; [Figure 4]

[0015] 2 is a cross-sectional view of a semiconductor structure after dopants have diffused into a non-dielectric layer, in accordance with some of the embodiments of the present principles; [Diagram 5]

[0016] 1 is a graph of active concentration in a selectively monolayer doped non-dielectric material, in accordance with some embodiments of the present principles; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0017] To facilitate understanding, the same reference numbers have been used, where possible, to designate identical elements that are common to several figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0014]

[0018] The method and apparatus provide for selective monolayer doping (SMLD) of semiconductor materials. In the SMLD process, dopants are implanted into non-dielectric materials of semiconductor structures, advantageously without modifying the dielectric areas found on the substrate. The SMLD process is conformal, allowing for implantation of dopants laterally and vertically into semiconductor devices of any shape geometry. By repeating the SMLD process until the desired doping state is achieved, very high concentrations of dopant concentration can be achieved. The SMLD process can also be advantageously performed in a single semiconductor processing device, such as a chemical vapor deposition chamber. The SMLD process does not change the shape or damage the crystal lattice of the doped semiconductor structure, allowing for continued reduction in the size of future semiconductor structures.

[0015]

[0019] FIG. 1 is a method 100 for performing selective monolayer doping of a semiconductor structure according to some embodiments. In the description of the method 100, reference is made to semiconductor structures 200, 300, 400 in FIG. 2, FIG. 3, and FIG. 4, respectively. FIG. 2 is a cross-sectional view of a semiconductor structure 200 according to some embodiments. The semiconductor structure 200 is formed on a substrate 202 and represents an exemplary structure in which the method 100 may be performed. The method 100 is not limited to any particular structural geometry. In the semiconductor structure 200, a dielectric feature 204 is formed on a protruding portion of the substrate 202, and a non-dielectric layer 206 is deposited on the substrate 202 up to a bottom surface of the dielectric feature 204. The dielectric feature 204 may include, but is not limited to, a gate structure for a pMOS device, etc. The non-dielectric layer 206 may be deposited on the substrate 202 to form a source / drain extension (SDE) region of the pMOS device. In some embodiments, the substrate 202 can be a silicon material or a silicon germanium material.

[0016]

[0020] In some embodiments, the non-dielectric layer 206 may be a p-type doped region, for example forming the source and drain extensions of a fin field effect transistor (finFET), and may include one or more p-type dopants. The p-type doped extension region may include one or more p-type dopants that act as a diffusion barrier to the p-type dopants in the heavily p-type doped source / drain regions (not shown). Because the p-type doped extension region is disposed between the channel region 210 and the heavily p-type doped region, the p-type dopants (such as boron) in the heavily p-type doped region cannot diffuse into the channel region 210. In pMOS devices (such as finFETs), the diffusion of p-type dopants may be problematic due to the continuing shrinking of size. In some embodiments, the p-type dopants in the heavily p-type doped region may include gallium. In such an embodiment, the p-type dopants included in the p-type doped extension regions may include boron, which may act as a significant diffusion barrier to gallium diffusion or simply as a spatial (geometry) offset.

[0017]

[0021] At block 102 of the method 100, an optional pre-cleaning or surface pretreatment process may be performed on the surface of the substrate 202. The surface pretreatment process may be performed to remove native oxide on the surface 208. The surface pretreatment process may include a dry etching process, a wet etching process, or a combination of both. The dry etching process may be a conventional plasma etch or a remote plasma assisted dry etching process (e.g., SICONI, available from Applied Materials, Inc., Santa Clara, Calif.). (登録商標) Etching process). (登録商標) In the etching process, the surface 208 is 2 , N.F. 3 , and / or NH 3 For example, in some embodiments, the surface 208 is exposed to plasma species (e.g., plasma excited hydrogen and fluorine species). 2 , N.F.3 , and N.H. 3 Simultaneous exposure to plasma of SICONI can be performed. (登録商標) The etching process is SICONI (登録商標) This may be carried out in a pre-cleaning chamber, (登録商標) The pre-clean chamber is compatible with a wide variety of multi-processing platforms, including the Centura 3000 series available from Applied Materials. TM , Dual ACP, Producer TM The wet etching process may be integrated with one of the following platforms (including the GT, GT, and Endura platforms). The wet etching process may include a hydrofluoric (HF) acid final process (i.e., a so-called "HF last" process) in which an HF etch of surface 208 is performed, which leaves surface 208 hydrogen terminated.

[0018]

[0022] In block 104 of the method 100, an SMLD layer 302 is deposited on the substrate 202. Due to its selective nature, the SMLD layer 302 forms on the non-dielectric layer 206 and not on the dielectric features 204, as shown in FIG. 3. In some embodiments, the selective nature of the SMLD layer allows a monolayer of dopant to form on the silicon and / or silicon germanium surface. In some embodiments, the deposition duration of the SMLD layer can be varied to vary the concentration of dopant species deposited on the non-dielectric layer 206. The deposition of the SMLD layer 302 is conformal in nature, allowing the SMLD layer 302 to be deposited vertically and laterally without being limited by the geometry of features on the substrate 202. The conformal ability of the SMLD layer is advantageous over other methods (such as ion implantation) that are limited by the angle of the ion beam and the size of the structures on the substrate. Additionally, the SMLD layer diffuses the dopant into the non-dielectric layer (without damaging or impairing the underlying crystal lattice structure). The method 100 allows for the production of very high concentration dopant agglomerates (e.g., electrically active boron or gallium dopant concentrations of 2e20 atoms / cm) for p-type semiconductor devices. 3This very high concentration of agglomeration can be achieved without damage, even in materials underlying other features on the substrate, due to the lateral diffusion capabilities afforded by the conformal nature of the SMLD layer 302.

[0019]

[0023] In some embodiments, the SMLD layer 302 is obtained by immersing the substrate in a gas (such as, but not limited to, diborane) to provide a selective monolayer of the p-type dopant boron on the non-dielectric surfaces of the substrate 202. The diborane gas does not interact with the dielectric surface and provides a selective process for depositing a monolayer of dopant on the non-dielectric material. In some embodiments, other gases and gas combinations / mixtures may be used to deposit different p-type or n-type dopants on the non-dielectric surfaces of the substrate 202. This gas extends to selectively provide a monolayer of dopant on the non-dielectric surface regardless of the orientation of the surface. This gas also allows the monolayer of dopant to conform to the surface. In some embodiments, the gas immersion duration and / or gas dopant concentration may be varied to produce different concentrations and / or penetration depths of dopant in the non-dielectric material. In some embodiments, the gas pressure and gas flow rate may be varied to produce different dopant concentrations and / or dopant penetration depths in the non-dielectric material.

[0020]

[0024] The substrate 202 is then annealed in block 106, which causes the dopant molecules 304 of the SMLD layer 302 to diffuse into the non-dielectric layer 206, as indicated by arrows 306 in FIG. 3. In some embodiments, the temperature and duration of the annealing may be adjusted to vary the depth to which the dopant is diffused into the material and the dopant concentration. In FIG. 4, the dopant molecules 304 are diffused into the non-dielectric layer 206. In structures such as pMOS devices, the p-type dopant species may include, but are not limited to, boron and gallium. In some embodiments, the method 100 may be used for nMOS devices having n-type doping species (such as arsenic and phosphorus). In some embodiments, the annealing process may include the use of laser-based annealing, for example, by a dynamic scanning anneal (DSA) process. In some embodiments, the annealing process may be the same annealing process used to activate the source / drain. By adding a gas soak process to form the SMLD layer 302 prior to the existing annealing process, the SMLD process can be integrated with the existing source / drain formation process. The integration of the SMLD process provides a very cost-effective and easy means to increase the dopant concentration in the source / drain extensions.

[0021]

[0025] Method 100 provides very high concentration dopant concentration 506 as shown in graph 500, while improving the diffusion falloff gradient 502 (compared to standard implantation process 504) to ensure dopant diffusion under features (such as gates), for example, in the formation of source / drain extensions. Method 100 works well with gate-all-around (GAA) and finFET semiconductor devices. Method 100 also has the advantage of using a single chamber (such as a CVD chamber). In some embodiments, deposition and annealing of the SMLD layer can be a cyclic process in which annealing parameters can be varied over one or more cycles to control dopant depth and / or concentration.

[0022]

[0026] While the forgoing is directed to embodiments of the present principles, other and further embodiments of the present principles may be devised without departing from the basic scope thereof.

Claims

1. 1. A method for forming a doped semiconductor feature, comprising: depositing the dopant aggregates on the material layer using a selective monolayer doping (SMLD) process comprising exposing the doped semiconductor feature to a gas mixture containing a dopant, the gas mixture selectively depositing the dopant aggregates on the material layer; method.

2. 10. The method of claim 1, further comprising varying a duration of exposure to the gas mixture or a dopant concentration in the gas mixture to control a density of the dopant agglomerates on the material layer.

3. The method of claim 1 , further comprising conformalizing the dopant aggregates to a surface of the material layer using the SMLD process.

4. The method of claim 1 , further comprising annealing the dopant agglomerates to diffuse the dopant agglomerates into the material layer.

5. The method of claim 4 , further comprising repeating the method to increase the dopant aggregation within the material layer.

6. The method of claim 4 , further comprising varying a temperature of annealing to vary the depth to which the dopant agglomerates penetrate into the material layer.

7. The method of claim 6 , further comprising varying a period of time for depositing the dopant agglomerates to increase an amount of active dopant in the dopant agglomerates.

8. The method of claim 1 further comprising depositing a dopant aggregate comprising a p-type dopant species or an n-type dopant species.

9. 9. The method of claim 8, wherein the p-type dopant species comprises boron or gallium and the n-type dopant species comprises arsenic or phosphorous.

10. The method of claim 1 , further comprising integrating the SMLD process with source / drain formation of a semiconductor structure.

11. 1. A method for forming doped semiconductor features on a substrate having a first material having non-dielectric properties and a second material having dielectric properties, comprising: immersing the substrate in a gas containing dopant aggregates, the gas selectively forming a monolayer of dopant on a first surface of the first material but not on a second surface of the second material; and annealing the substrate to diffuse the dopant into the first material. method.

12. 12. The method of claim 11, further comprising varying a gas immersion duration, a gas immersion pressure, a gas immersion flow rate, or a gas immersion dopant concentration to control the dopant diffusion parameters.

13. 12. The method of claim 11, further comprising repeating the method while varying the annealing temperature in at least one cycle to vary the depth to which the dopant penetrates into the first material.

14. 12. The method of claim 11, further comprising repeating the method while varying a gas immersion duration, a gas immersion pressure, a gas immersion flow rate, or a gas immersion dopant concentration in at least one cycle to vary an amount of dopant on the first surface of the first material.

15. 1. A method for forming doped semiconductor features on a substrate having a first material having non-dielectric properties and a second material having dielectric properties, comprising: immersing the substrate in a gas containing dopant aggregates, the gas selectively forming a monolayer of dopant on a first surface of the first material but not on a second surface of the second material; annealing the substrate to diffuse the dopant into the first material; repeating the method while varying a gas immersion duration, a gas immersion pressure, a gas immersion flow rate, or a gas immersion dopant concentration in at least one cycle to vary the amount of dopant on the first surface of the first material, and repeating the method while varying an annealing temperature in at least one cycle to vary the depth to which the dopant penetrates into the first material. method.

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