Reconstituted substrate structure and method for manufacturing heterogeneous packaging integration

Abstract

To provide a thin form factor reconstituted substrate for advanced 3D packaging applications and a method for forming the same.SOLUTION: A method 100 for forming a reconstituted substrate comprises: a step 110 for structuring a substrate to be used as a frame; a step 120 for forming an intermediate die assembly with one or more embedded die and an insulating layer; a step 130 for forming one or more interconnections in and / or through the intermediate die assembly to form a functionally reconstituted substrate; and a step 140a for having one or more redistribution layers formed thereon, or step 140b for individualizing into individual packages or system-in-packages, or step 140c for forming a stacked 3D structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to the field of semiconductor device manufacturing, and more particularly to structures and methods for packaging semiconductor devices. [Background technology]

[0002]

[0002] The ever-increasing demand for miniaturized semiconductor devices has continuously increased circuit density and reduced device size. As a result of the continued scaling of these devices, integrated circuits have evolved into complex 3D devices that can contain millions of transistors, capacitors, and resistors on a single chip. 3D integration can significantly reduce the footprint of a device and allows for shorter and faster connections between the subcomponents of the device, thus increasing processing power and its speed. These capabilities make 3D integration a desirable technology for the semiconductor device industry to keep up with Moore's Law.

[0003]

[0003] Currently, the 3D device technology landscape includes several general classes of 3D integration processes that vary in the level at which the device is divided into different pieces. Such 3D integration processes include Stacked Integrated Circuit ("SIC") technology, System-in-Package ("SiP") technology, and System-on-Chip ("SOC") technology. SIC devices are formed by stacking individual semiconductor dies on top of each other. Currently, such SIC devices are achieved by die-to-interposer stacking or die-to-wafer stacking techniques. On the other hand, SiP devices are formed by stacking packages on top of each other or by integrating several semiconductor dies or devices into a single package. Current techniques for manufacturing SiP devices include package-to-package reflow and fan-out wafer-level packaging. Finally, SOC achieves higher density by stacking several different functional divisions of the circuit non-uniformly. Traditionally, these functional circuit divisions are stacked through wafer-to-wafer bonding techniques.

[0004]

[0004] Despite the promise of 3D device technology, current approaches to 3D integration face many challenges. One of the major drawbacks associated with current 3D integration technologies, particularly SiP manufacturing processes, is suboptimal thermal management. As a result of the thermal properties of molding compound materials utilized during conventional packaging manufacturing processes, a coefficient of thermal expansion ("CTE") mismatch can occur between the molding compound and any integrated semiconductor device components (e.g., semiconductor die). The presence of a CTE mismatch can cause undesired rearrangement of device components and even warpage of the wafer and / or the integrated package as a whole, thus inducing a mismatch between device contacts and via interconnects in any subsequently formed redistribution layers.

[0005]

[0005] Therefore, there is a need in the art for improved methods of forming reconfigurable substrates for packaging schemes. Summary of the Invention

[0006] The present disclosure relates generally to device packaging processes, and more particularly to methods for forming reconfigurable substrates for advanced 3D packaging applications.

[0007]

[0007] In one embodiment, a method of forming a 3D integrated semiconductor device includes positioning a first semiconductor die in at least one cavity formed in a first substrate; disposing a first fluid material over a first surface and a second surface of the first substrate, where the first fluid material fills a void formed between a surface of the semiconductor die and a surface of the at least one cavity in the first substrate, the first fluid material being further disposed on a surface of at least one via formed through the first substrate; forming a first conductive layer in at least one via through the first substrate, where the first fluid material is disposed between the first conductive layer and a surface of the at least one via through the first substrate; and disposing a second fluid material over the surface of the first fluid material, where the second fluid material is further disposed on the first fluid material. positioning a second substrate over the second flowable material, the second substrate having at least one cavity and at least one via formed therein; positioning a second semiconductor die within the at least one cavity formed in the second substrate; disposing a third flowable material over an exposed surface of the second substrate, the third flowable material filling a void formed between a surface of the second semiconductor die and a surface of the at least one cavity in the second substrate, the third flowable material disposing the third flowable material to integrate with the second flowable material; and forming a second conductive layer through the second substrate and within the at least one via, the third flowable material forming a second conductive layer disposed through the second substrate between the conductive layer and a surface of the at least one via. Includes.

[0008]

[0008] In order that the above features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate exemplary embodiments, and therefore should not be considered as limiting the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates a flow diagram of a process for forming a reconfigured substrate according to embodiments described herein. [Diagram 2] 1 shows a flow diagram of a substrate structuring process during formation of a reconstructed substrate according to embodiments described herein. [Figure 3-1] 1A-B show schematic cross-sectional views of a substrate at various stages of the substrate structuring process shown in FIG. [Figure 3-2] 5C-5D show schematic cross-sectional views of a substrate at various stages of the substrate structuring process shown in FIG. 2. [Figure 4A] 3A-3E show schematic top views of a substrate structured in the process shown in FIG. 2 and FIGS. 3A-3E according to embodiments described herein. [Figure 4B] 3A-3E show schematic top views of a substrate structured in the process shown in FIG. 2 and FIGS. 3A-3E according to embodiments described herein. [Diagram 5] 1 illustrates a flow diagram of a process for forming an intermediate die assembly having through-assembly vias and contact holes according to embodiments described herein. [Figure 6-1] 6A-C show schematic cross-sectional views of the intermediate die assembly at various stages of the process shown in FIG. [Figure 6-2] 6A-6D show schematic cross-sectional views of the intermediate die assembly at various stages of the process shown in FIG. [Figure 6-3] GH show schematic cross-sectional views of the intermediate die assembly at various stages of the process shown in FIG. [Figure 6-4] 1K-1K show schematic cross-sectional views of the intermediate die assembly at various stages of the process shown in FIG. [Figure 7] 1 illustrates a flow diagram of a process for forming an intermediate die assembly having through-assembly vias and contact holes according to embodiments described herein. [Figure 8-1] 8A-C show schematic cross-sectional views of the intermediate die assembly at various stages of the process shown in FIG. [Figure 8-2] 8A, 8B, 8C, 8D, 8E, and 8F show schematic cross-sectional views of the intermediate die assembly at various stages of the process shown in FIG. [Figure 8-3] 8A-8G show schematic cross-sectional views of the intermediate die assembly at various stages of the process shown in FIG. [Figure 9] 1 illustrates a flow diagram of a process for forming interconnects in a middle die assembly according to embodiments described herein. [Figure 10-1] 1A-C illustrate schematic cross-sectional views of the intermediate die assembly at various stages of the interconnect formation process shown in FIG. [Figure 10-2] 10A-D show schematic cross-sectional views of the intermediate die assembly at various stages of the interconnect formation process shown in FIG. [Figure 10-3] GH illustrate schematic cross-sectional views of the intermediate die assembly at various stages of the interconnect formation process shown in FIG. [Figure 10-4] 1J illustrates generally cross-sectional views of the intermediate die assembly at various stages of the interconnect formation process shown in FIG. [Figure 10-5] 10K illustrates generally cross-sectional views of the intermediate die assembly at various stages of the interconnect formation process illustrated in FIG. [Figure 11] 1 illustrates a flow diagram of a process for forming a redistribution layer on a reconfiguration substrate and subsequent singulation according to embodiments described herein. [Figure 12-1] 10A-C show schematic cross-sectional views of a reconstituted substrate at various stages of forming a redistribution layer and subsequent singulation, as shown in FIG. [Figure 12-2] DE shows schematic cross-sectional views of a reconstituted substrate at various stages of forming a redistribution layer and subsequent singulation, as shown in FIG. [Figure 12-3] FG show schematic cross-sectional views of a reconstituted substrate at various stages of forming a redistribution layer and subsequent singulation as shown in FIG. [Figure 12-4] HI shows schematic cross-sectional views of a reconstituted substrate at various stages of forming a redistribution layer and subsequent singulation, as shown in FIG. [Figure 12-5] JK illustrates, in schematic form, cross-sectional views of a reconstituted substrate at various stages of forming a redistribution layer and subsequent singulation, as shown in FIG. [Figure 12-6] 1L shows schematic cross-sectional views of a reconstituted substrate at various stages of forming a redistribution layer and subsequent singulation as shown in FIG. [Figure 12-7] 1M show schematic cross-sectional views of a reconfigured substrate at various stages of forming a redistribution layer and subsequent singulation as shown in FIG. [Figure 12-8] 1N show schematic cross-sectional views of a reconstituted substrate at various stages of forming a redistribution layer and subsequent singulation as shown in FIG. [Figure 13] FIG. 1 illustrates a process flow diagram for forming a layered 3D structure that integrates reconfigured substrates by build-up stacking, according to embodiments described herein. [Figure 14A] 14A-14C show schematic cross-sectional views of the layered 3D structure shown in FIG. 13 at certain stages of build-up stacking. [Figure 14B] 14A-14C are schematic cross-sectional views of the layered 3D structure shown in FIG. 13 at different stages of build-up stacking. [Figure 14C] 14A-14C are schematic cross-sectional views of the layered 3D structure shown in FIG. 13 at yet another stage of build-up stacking. [Figure 14D] 14A-14C are schematic cross-sectional views of the layered 3D structure shown in FIG. 13 at yet another stage of build-up stacking. [Figure 15A]14A-14C are schematic diagrams illustrating cross-sectional views of structures incorporating dynamic random access memory (DRAM) stacks formed by the process illustrated in FIG. 13 according to embodiments described herein. [Figure 15B] 14A-14C are schematic cross-sectional views of a structure incorporating a DRAM stack formed by the process illustrated in FIG. 13 according to embodiments described herein. [Figure 15C] 14A-14C are schematic cross-sectional views of a structure incorporating a DRAM stack formed by the process illustrated in FIG. 13 according to embodiments described herein. [Figure 16] 1A-1D illustrate schematic diagrams of a layered 3D structure integrating a reconfigurable substrate according to embodiments described herein. [Figure 17A] 1A-1D illustrate schematic diagrams of a layered 3D structure integrating a reconfigurable substrate according to embodiments described herein. [Figure 17B] 1A-1D illustrate schematic diagrams of a layered 3D structure integrating a reconfigurable substrate according to embodiments described herein. [Figure 18] 1A-1C illustrate schematic cross-sectional views of dynamic random access memory (DRAM) stacks formed by processes described herein, according to certain embodiments. [Figure 19] FIG. 1 illustrates a process flow diagram for forming a layered 3D structure that integrates reconfigured substrates by build-up stacking, according to embodiments described herein. [Figure 20A] 19A-19C show schematic cross-sectional views of a layered 3D structure at certain stages of build-up stacking. [Figure 20B] 19A-19C show schematic cross-sectional views of a layered 3D structure at different stages of build-up stacking. [Figure 20C] 19A-C are schematic cross-sectional views of the layered 3D structure at yet another stage of build-up stacking, respectively. [Figure 20D] 19A-C are schematic cross-sectional views of the layered 3D structure at yet another stage of build-up stacking, respectively. [Figure 20E]19A-C are schematic cross-sectional views of the layered 3D structure at yet another stage of build-up stacking, respectively. [Figure 20F] 19A-C are schematic cross-sectional views of the layered 3D structure at yet another stage of build-up stacking, respectively. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0029] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements common to the figures. It is envisioned that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0011]

[0030] The present disclosure relates to a thin form factor reconfigured substrate and a method for forming the same. The reconfigured substrate described herein can be utilized to fabricate homogeneous or heterogeneous high density 3D integrated devices. In one embodiment, a silicon substrate is structured by laser ablation to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types can be placed in the cavities and then embedded in the substrate when forming an insulating layer thereon. One or more conductive interconnects can be formed in the vias and have contacts redistributed to desired surfaces of the reconfigured substrate. The reconfigured substrate can then be integrated into stacked 3D devices such as 3D DRAM stacks.

[0012]

[0031] 1 shows a flow diagram of an exemplary method 100 for forming a reconfigurable substrate and / or subsequent package, which may be homogeneous or heterogeneous. Method 100 has multiple steps 110, 120, 130, and 140a-140c. Each step is described in more detail with reference to FIGS. 2-14D. The method may include one or more additional steps performed before any of the defined steps, between two of the defined steps, or after all of the defined steps (unless the context precludes the possibility).

[0013]

[0032] In general, the method 100 includes structuring a substrate to be used as a frame in step 110, which will be described in more detail with reference to Figures 2, 3A-3E, and 4A-4B. In step 120, an intermediate die assembly is formed having one or more embedded dies and an insulating layer, which will be described in more detail with reference to Figures 5 and 6A-6K, and Figures 7 and 8A-8G. In step 130, which will be described in more detail with reference to Figures 9 and 10A-10K, one or more interconnects are formed in and / or through the intermediate die assembly to form a functional reconfigurable substrate. In step 140, the reconfigurable substrate then has one or more redistribution layers formed thereon (140a), which may be singulated into individual packages or systems in packages ("SiPs") (140b), and / or may be utilized to form stacked 3D structures (140c). The formation of the redistribution layers is described with reference to Figures 11 and 12A-12N. Stacking is explained with reference to Figures 13 and 14A-20F.

[0014]

[0033] Figure 2 shows a flow diagram of an exemplary method 200 for structuring a substrate to be utilized as a reconfigurable substrate frame. Figures 3A-3E show schematic cross-sectional views of a substrate 302 at various stages of the substrate structuring process 200 depicted in Figure 2. Figures 2 and 3A-3E are therefore described together herein for clarity.

[0015]

[0034] The method 200 begins at step 210 and corresponding FIG. 3A where a substrate 302 is exposed to a first defect removal process. The substrate 302 may be a III-V compound semiconductor material, silicon (e.g., having a resistivity between about 1 ohm-com and about 10 ohm-com or a conductivity of about 100 W / mK), crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, silicon germanium, doped or undoped silicon, undoped high resistivity silicon (e.g., float zone silicon with lower dissolved oxygen content and resistivity between about 5000 ohm-cm and about 10000 ohm-cm), doped or undoped polysilicon, silicon nitride, silicon carbide (e.g., with a conductivity of about 500 W / mK), quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In one embodiment, the substrate 302 is a single crystal p-type or n-type silicon substrate. In one embodiment, the substrate 302 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, the substrate 302 is a p-type or n-type silicon solar substrate. The substrate 302 may further have a polygonal or circular shape. For example, substrate 302 may comprise a substantially square silicon substrate having a lateral dimension between about 120 mm and about 180 mm, e.g., about 150 mm, or between about 156 mm and about 166 mm, with or without chamfered edges. In another example, substrate 302 may comprise a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm (e.g., about 200 mm or about 300 mm).

[0016]

[0035] Unless otherwise specified, the embodiments and examples described herein are performed on a substrate having a thickness between about 50 μm and about 1500 μm (such as between about 90 μm and about 780 μm). For example, the substrate 302 has a thickness between about 100 μm and about 300 μm (such as between about 110 μm and about 200 μm). In another example, the substrate 302 has a thickness between about 60 μm and about 160 μm (such as between about 80 μm and about 120 μm).

[0017]

[0036] Prior to step 210, the substrate 302 may be sliced ​​and separated from the bulk material by wire sawing, scribing and breaking, mechanical abrasive sawing, or laser cutting. Slicing typically introduces mechanical defects or deformations into the substrate surface, such as scratches, microcracks, chipping, and other mechanical defects. Thus, the substrate 302 is exposed to a first defect removal process in step 210 to smooth and planarize its surface and remove any mechanical defects in preparation for subsequent structuring and packaging steps. In some embodiments, the substrate 302 may be further thinned by adjusting the process parameters of the first defect removal process. For example, the thickness of the substrate 302 may be reduced as the exposure to the first defect removal process is increased (added).

[0018]

[0037] In some embodiments, the first defect removal process in step 210 includes exposing the substrate 302 to a substrate polishing process and / or an etching process, followed by a rinsing and drying process. For example, the substrate 302 may be exposed to a chemical mechanical polishing (CMP) process in step 210. In some embodiments, the etching process is a wet etching process that includes a buffered etching process that is selective to the removal of desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etching process is a wet etching process that utilizes an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the wet etching process. In one embodiment, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching. During the etching process, the etching solution may be heated to a temperature between about 30° C. and about 100° C., for example, between about 40° C. and about 90° C., to accelerate the etching process. The etchant is heated, for example, to a temperature of about 70° C. during the etching process. In yet another embodiment, the etching process in step 210 is a dry etching process. One example of a dry etching process includes a plasma-based dry etching process.

[0019]

[0038] The thickness of the substrate 302 may be adjusted by controlling the exposure time of the substrate 302 to the polishing process and / or the etchant (e.g., etchant) used during the etching process. For example, the final thickness of the substrate 302 may decrease as exposure to the polishing process and / or etchant increases. Alternatively, the substrate 302 may have a greater final thickness with decreased exposure to the polishing process and / or etchant.

[0020]

[0039] In steps 220 and 230, the now planarized and substantially defect-free substrate 302 has one or more features patterned and smoothed therein, such as vias 303 and cavities 305. (Two cavities 305 and eight vias 303 are depicted in cross section of the underside of substrate 302 in FIG. 3B for clarity.) The vias 303 are utilized to form direct contact electrical interconnects through substrate 302, and the cavities 305 are utilized to receive and encapsulate (i.e., embed) one or more semiconductor dies or devices therein.

[0021]

[0040] In embodiments where the substrate 302 has a relatively thin thickness, such as less than 200 μm thick, the substrate 302 may be coupled to a carrier plate (not shown) prior to patterning. For example, if the substrate 302 has a thickness of less than about 100 μm (such as a thickness of about 50 μm), the substrate 302 is placed on a carrier plate for mechanical support and stabilization during the substrate structuring process in steps 220 and 230, thus preventing the substrate 302 from breaking. The carrier plate is formed from any suitable chemically and thermally stable rigid material, including but not limited to glass, ceramic, metal, and the like, and has a thickness between about 1 mm and about 10 mm. In some embodiments, the carrier plate has a textured surface to hold the substrate 302 in place during structuring. In other embodiments, the carrier plate has a polished or smooth surface.

[0022]

[0041] The substrate 302 may be coupled to the carrier plate via an adhesive, such as wax, glue, or any suitable temporary bonding material that may be applied to the carrier plate by mechanical rolling, pressing, lamination, spin coating, or doctor blading. In some embodiments, the substrate 302 is coupled to the carrier plate via a water-soluble or solvent-soluble adhesive. In other embodiments, the adhesive is a heat-release or UV-release adhesive. For example, the substrate 302 may be released from the carrier plate by exposure to a bake process at a temperature between about 50° C. and about 300° C., such as a temperature between about 100° C. and about 200° C. (e.g., a temperature between about 125° C. and about 175° C.).

[0023]

[0042] In one embodiment, a desired pattern is formed in a substrate 302, such as a solar substrate or even a semiconductor wafer, by laser ablation. The laser ablation system utilized to laser drill features in the substrate 302 may include any suitable type of laser source. In some examples, the laser source is an infrared (IR) laser. In some examples, the laser source is a picosecond UV laser. In other examples, the laser source is a femtosecond UV laser. In yet other examples, the laser source is a femtosecond green laser. The laser source generates a continuous or pulsed laser beam for patterning the substrate. For example, the laser source may generate a pulsed laser beam having a frequency between 5 kHz and 500 kHz, such as between 10 kHz and about 200 kHz. In one example, the laser source is configured to deliver a pulsed laser beam with an output power between about 10 watts and about 100 watts, at a wavelength between about 200 nm and about 1200 nm, and with a pulse duration between about 10 ns and about 5000 ns. The laser source is configured to form any desired patterns and features in the substrate 302, including the cavities 305 and vias 303 described above and shown in FIG. 3B.

[0024]

[0043] Similar to the process of separating substrate 302 from bulk material, laser patterning of substrate 302 can result in undesirable mechanical defects, such as chipping and cracking, on the surface of substrate 302. Therefore, after forming the desired features in substrate 302 by direct laser patterning, substrate 302 is subjected to a second defect removal and cleaning process at step 230 that is substantially similar to the first defect removal process described above. Figures 3B and 3C show structured substrate 302 before and after performing the second damage removal and cleaning process at step 230, resulting in a smoothed substrate 302 with cavities 305 and vias 303 formed therein.

[0025]

[0044] During the second damage removal process, the substrate 302 is etched, rinsed, and dried. The etching process proceeds for a predetermined duration to smooth the surface of the substrate 302, particularly the surface that will be exposed to laser patterning. In another aspect, the etching process is utilized to remove any undesired debris remaining from the laser ablation process. The etching process may be isotropic or anisotropic. In some embodiments, the etching process is a wet etching process utilizing any suitable wet etchant or combination of wet etchants in an aqueous solution. For example, the substrate 302 may be immersed in an aqueous HF etching solution or an aqueous KOH etching solution. In some embodiments, the etching solution is heated to further accelerate the etching process. For example, the etching solution may be heated to a temperature between about 40° C. and about 80° C., such as between about 50° C. and about 70° C. (e.g., about 60° C.) during etching of the substrate 302. In yet another embodiment, the etching process in step 230 is a dry etching process. One example of a dry etching process includes a plasma-based dry etching process.

[0026]

[0045] FIG. 3C illustrates a longitudinal cross-section of the substrate 302 after completion of steps 210-230. The substrate 302 is shown with two cavities 305 formed therethrough, each cavity 305 surrounded on either side by two vias 303. Additionally, the two cavities 305 are shown to have different lateral dimensions D1 and D2, thus allowing for placement of different types of semiconductor devices and / or dies within each cavity during subsequent packaging steps. Thus, the cavities 305 may be shaped and sized to accommodate any desired devices and / or dies in any desired arrangement for 2D heterogeneous packaging integration. Although only two cavities and eight vias are shown in FIGS. 3B-3E, any number and arrangement of cavities and vias may be formed within the substrate during performance of the method 200. Top views of additional exemplary arrangements are described below with reference to FIGS. 4A and 4B.

[0027]

[0046] In step 240, the substrate 302, after removing mechanical defects, is exposed to an optional oxidation or metallization process to grow an oxide layer 314 or a metal clad layer 315 on the desired surfaces. For example, the oxide layer 314 or the metal clad layer 315 may be formed on all surfaces of the substrate 302 (e.g., including the sidewalls of the cavity 305 and the via 303) such that the layer 314 or 315 surrounds the substrate 302.

[0028]

[0047] As shown in FIG. 3D, the oxide layer 314 acts as a passivation layer on the substrate 302 and provides a protective outer barrier against corrosion and other forms of damage. In one embodiment, the substrate 302 is exposed to a thermal oxidation process to grow the oxide layer 314 thereon. The thermal oxidation process is performed at a temperature between about 800° C. and about 1200° C. (such as between about 850° C. and about 1150° C.). For example, the thermal oxidation process is performed at a temperature between about 900° C. and about 1100° C. (such as between about 950° C. and about 1050° C.). In one embodiment, the thermal oxidation process is a wet oxidation process utilizing water vapor as an oxidizing agent. In one embodiment, the thermal oxidation process is a dry process utilizing molecular oxygen as an oxidizing agent. It is contemplated that the substrate 302 may be exposed to any suitable oxidation process in step 240 to form the oxide layer 314 thereon. In some embodiments, the oxide layer 314 is a silicon dioxide film. The oxide layer 314 formed in step 240 typically has a thickness between about 100 nm and about 3 μm (such as between about 200 nm and about 2.5 μm). For example, the oxide layer 314 has a thickness between about 300 nm and about 2 μm (such as about 1.5 μm).

[0029]

[0048] In embodiments where the metal clad layer 315 is formed on the substrate 302 (depicted in FIG. 3E), the metal clad layer 315 acts as a reference layer (e.g., a ground layer or a voltage supply layer). The metal clad layer 315 is disposed on the substrate 302 to protect the subsequently integrated semiconductor devices and connections from electromagnetic interference and to protect the semiconductor signals from the semiconductor material (Si) used to form the substrate 302. In one embodiment, the metal clad layer 315 includes a conductive metal layer including nickel, aluminum, gold, cobalt, silver, palladium, tin, and the like. In one embodiment, the metal clad layer 315 includes a metal layer including an alloy or pure metal including nickel, aluminum, gold, cobalt, silver, palladium, tin, and the like. The metal clad layer 315 generally has a thickness between about 50 nm and about 10 μm (e.g., between about 100 nm and about 5 μm).

[0030]

[0049] Metal cladding layer 315 may be formed by any suitable deposition process, including an electroless deposition process, an electroplating process, a chemical vapor deposition process, an evaporative deposition process, and / or an atomic layer deposition process. In one embodiment, at least a portion of metal cladding layer 315 comprises a deposited nickel (Ni) layer formed by direct displacement or displacement plating on a surface of substrate 302 (e.g., an n-Si substrate or a p-Si substrate). For example, substrate 302 may be formed of a 0.5 M NiSO 4 and N.H. 4 The silicon substrate 302 is exposed to a nickel displacement plating bath having a composition containing OH at a temperature between about 60° C. and about 95° C. and at a pH of about 11 for between about 2 and about 4 minutes. Exposure of the silicon substrate 302 to a nickel ion-loaded aqueous electrolyte in the absence of a reducing agent causes a local oxidation / reduction reaction at the surface of the substrate 302, thus resulting in plating of metallic nickel thereon. Nickel displacement plating thus allows for the selective formation of a thin, pure nickel layer on the silicon material of the substrate 302 using a stable solution. Furthermore, the process is self-limiting, and thus the reaction stops once all surfaces of the substrate 302 are plated (e.g., there is no remaining silicon on which nickel can form). In certain embodiments, the nickel metal clad layer 315 may be utilized as a seed layer for plating additional metal layers, such as nickel or copper plating by electroless and / or electrolytic plating methods. In further embodiments, the substrate 302 is exposed to an SC-1 pre-clean solution and an HF oxide etchant prior to the nickel displacement plating bath to promote adhesion of the nickel metal clad layer 315.

[0031]

[0050] FIG. 4A shows a schematic top view of an exemplary pattern that may be formed on the substrate 302, thus utilizing the substrate 302 as a frame during heterogeneous 2D and 3D packaging integration according to one embodiment. The substrate 302 may be structured during steps 210-240 as described above with reference to FIGS. 2 and 3A-3E. As shown, the substrate 302 is structured to include nine identical quadrilateral regions 412 (separated by scribe lines 410) that may be packaged and singulated into nine individual 2D heterogeneous packages or SiPs. Although nine identical regions 412 are shown in FIG. 4A, it is contemplated that any desired number of regions and arrangements of features may be structured within the substrate 302 using the processes described above. In one example, the regions 412 are not identical and include different features and / or arrangements of features formed therein.

[0032]

[0051] Each region 412 includes five quadrilateral cavities 305a-305e, each of which is surrounded along its major side by two rows 403a, 403b of vias 303. As shown, the cavities 305a-305c are structured to have substantially similar morphologies, and therefore each may accommodate the placement (e.g., integration) of the same type of semiconductor device or die. However, the cavities 305d and 305e have substantially different morphologies from each other in addition to the morphology of the cavities 305a-305c, and therefore may accommodate the placement of two additional types of semiconductor devices or dies. Thus, the structured substrate 302 may be utilized to form a reconfigurable substrate for singulating heterogeneous 2D packages or SiPs in which three types of semiconductor devices or dies are integrated. Although shown as having three types of quadrilateral cavities 305, each region 412 may have more or less than three types of cavities 305 having shapes other than quadrilateral. For example, each region 412 may have one type of cavity 305 formed therein, thus allowing for the formation of homogenous 2D packages.

[0033]

[0052] In one embodiment, the cavities 305 and vias 303 have a depth equal to the thickness of the substrate 302, thus forming holes (e.g., through the thickness of the substrate 302) on the opposing surface of the substrate 302. For example, the cavities 305 and vias 303 formed in the substrate 302 may have a depth of between about 50 μm and about 1 mm, such as between about 100 μm and about 200 μm (e.g., between about 110 μm and about 190 μm), depending on the thickness of the substrate 302. In other embodiments, the cavities 305 and / or vias 303 may have a depth equal to or less than the thickness of the substrate 302. Thus, holes are formed in only one surface (e.g., a side) of the substrate 302.

[0034]

[0053] In one embodiment, each cavity 305 has a lateral dimension in a range between about 0.5 mm and about 50 mm (such as between about 3 mm and about 12 mm (e.g., between about 8 mm and about 11 mm)) depending on the size and number of semiconductor devices or dies to be embedded during package or reconstitution substrate fabrication. A semiconductor die generally includes multiple integrated electronic circuits formed on and / or within a substrate material, such as a piece of semiconductor material. In one embodiment, the cavity 305 is sized to have a lateral dimension substantially similar to a lateral dimension of the semiconductor device or die to be embedded (e.g., integrated) therein. For example, each cavity 305 is formed to have a lateral dimension that exceeds a lateral dimension of the semiconductor device or die (i.e., in the X- or Y-direction of FIG. 4A) by less than about 150 μm (such as less than about 120 μm (e.g., less than 100 μm)). The reduced variation in size of the cavity 305 and the semiconductor device or die embedded therein reduces the amount of subsequent gap fill material required.

[0035]

[0054] Although each cavity 305 is shown surrounded by two rows 403a, 403b of vias 303 along its major sides, each region 412 may have a different arrangement of the vias 303. For example, the cavity 305 may be surrounded by more or less than two rows 403 of vias 303. The vias 303 in each row 403 are staggered and not aligned with the vias 303 in adjacent rows 403. In some embodiments, the vias 303 are formed as a single isolated via through the substrate 302.

[0036]

[0055] Generally, the vias 303 are generally cylindrical in shape. However, other configurations of the vias 303 are also contemplated. For example, the vias 303 may have a tapered or conical configuration. The diameter at its first end (e.g., at one surface of the substrate 302) is larger than the diameter at its second end. The formation of a tapered or conical configuration may be achieved by moving the laser beam of the laser source utilized during structuring in a helical (e.g., circular, swirling) motion relative to the central axis of each of the vias 303. The laser beam may also be angled using a motion system to form tapered vias 303. The same method may also be utilized to form cylindrical vias 303 with a uniform diameter.

[0037]

[0056] In one embodiment, each via 303 has a diameter in the range of between about 20 μm and about 200 μm (e.g., between about 50 μm and about 150 μm, e.g., between about 60 μm and about 130 μm, e.g., between about 80 μm and 110 μm). The minimum center-to-center pitch of the vias 303 is between about 70 μm and about 200 μm (e.g., between about 85 μm and about 160 μm, e.g., between about 100 μm and 140 μm). Although the embodiment is described with reference to FIG. 4A, the substrate structuring process described above with reference to steps 210-240 and FIGS. 2 and 3A-3E may be utilized to form patterned features in the substrate 302 having any desired depth, lateral dimension, and morphology.

[0038]

[0057] 4B shows a schematic top view of region 412 having another exemplary pattern that may be formed in substrate 302. In certain embodiments, during packaging, it may be desirable to place two or more semiconductor dies of the same or different types in a single cavity 305, each semiconductor die having the same or different dimensions and / or shapes. Thus, in some examples, cavity 305 may have an irregular or asymmetric shape to accommodate semiconductor dies having different dimensions and / or shapes. As shown in FIG. 4B, region 412 includes four square and symmetric cavities 305a-d and a single asymmetric cavity 305f. Cavity 305f is shaped to accommodate two semiconductor dies 326a and 326b (shown in dashed lines) having different dimensions. Although only one asymmetric cavity 305f is shown in FIG. 4B for accommodating two semiconductor dies 326a and 326b, it is contemplated that each region 412 may include more or less than one asymmetric cavity 305 for accommodating any desired number of parallel dies having any suitable size and shape.

[0039]

[0058] After structuring, the substrate 302 may be utilized as a frame for forming a reconstituted substrate in a subsequent packaging process. Figures 5 and 7 show flow diagrams of representative methods 500 and 700, respectively, for fabricating an intermediate die assembly 602 around a substrate 302 prior to a completed (e.g., final) reconstituted substrate formation. Figures 6A-6K show schematic cross-sectional views of the substrate 302 at different stages of the method 500 shown in Figure 5 and are described herein in conjunction with Figure 5 for clarity. Similarly, Figures 8A-8G show schematic cross-sectional views of the substrate 302 at different stages of the method 700 shown in Figure 7 and are described herein in conjunction with Figure 7.

[0040]

[0059] Generally, the method 500 begins at step 502 and FIG. 6A where a first side 675 (e.g., first major surface 606) of a substrate 302 having desired features formed therein is disposed on a first insulating film 616a. In one embodiment, the first insulating film 616a includes one or more layers 618a formed from a flowable and polymer-based dielectric material, such as an insulating build-up material. In the embodiment shown in FIG. 6A, the first insulating film 616a includes a flowable layer 618a formed from an epoxy resin. For example, the flowable layer 618a may be formed from a substantially spherical silica (SiO 2 The ceramic filler may be formed of a ceramic filler-containing epoxy resin, such as an epoxy resin filled with (e.g., containing) ceramic filler particles. As used herein, the term "spherical" refers to any circular, elliptical, or spheroidal shape. For example, in some embodiments, the ceramic filler may have an oval, elliptical, or other similar circular shape. However, other shapes are contemplated. Other examples of ceramic fillers that may be utilized to form the flow layer 618a and other layers of the insulating film 616a include aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), Sr 2 Ce 2 Ti 5 O 16 Ceramic, zirconium silicate (ZrSiO 4 ), wollastonite (CaSiO 3 ), beryllium oxide (BeO), cerium dioxide (CeO 2 ), Boron nitride (BN), Calcium copper titanium oxide (CaCu 3 Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO 2 ), zinc oxide (ZnO).

[0041]

[0060] In some examples, the ceramic filler utilized to form the flowing layer 618a has particles ranging in size between about 40 nm and about 1.5 μm (between about 80 nm and about 1 μm). For example, the ceramic filler utilized to form the flowing layer 618a has particles ranging in size between about 200 nm and about 800 nm (such as between about 300 nm and about 600 nm). In some embodiments, the ceramic filler includes particles having a size that is less than about 25% of the width or diameter of a feature (e.g., a via, a cavity, or a through-assembly via) formed in the substrate (such as less than about 15% of the width or diameter of the desired feature).

[0042]

[0061] The flowable layer 618a typically has a thickness of less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the flowable layer 618a has a thickness of between about 10 μm and about 25 μm. In one embodiment, the insulating film 616a may further include one or more protective layers. For example, the insulating film 616a includes a polyethylene terephthalate (PET) protective layer 622a. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 616a. In some embodiments, the entire insulating film 616a has a thickness of less than about 120 μm (such as a thickness of less than about 90 μm).

[0043]

[0062] The substrate 302 is coupled to the insulating film 616a on its first side 675, in particular to the flowable layer 618a of the insulating film 616a, and may optionally be further mounted on a carrier 624 for mechanical support during subsequent processing operations. The carrier 624 is formed from any suitable mechanically and thermally stable material. The carrier 624 is formed, for example, from polytetrafluoroethylene (PTFE). In another example, the carrier 624 is formed from PET.

[0044]

[0063] In step 504, and as depicted in FIG. 6B, one or more semiconductor dies 626 are placed in the cavity 305 formed in the substrate 302, such that the semiconductor dies 626 are now bonded by an insulating film 616a on one side (two semiconductor dies 626 are depicted in FIG. 6B). In one embodiment, the semiconductor die 626 is a multi-purpose die with integrated circuits formed on its active surface 628. In one embodiment, the semiconductor die 626 is the same type of semiconductor device or die. In another embodiment, the semiconductor die 626 is a different type of semiconductor device or die. The semiconductor die 626 is placed in the cavity 305 (e.g., cavities 350a-305e in FIG. 4) and disposed on a surface of the insulating film 616a exposed through the cavity 305. In one embodiment, the semiconductor die 626 is placed on an optional adhesive layer (not shown) disposed or formed on the insulating film 616a.

[0045]

[0064] After placing the die 626 in the cavity 305, a first protective film 660 is placed over a second side 677 (e.g., surface 608) of the substrate 302 in step 506 and FIG. 6C. The protective film 660 is coupled to the second side 677 of the substrate 302 and the opposite side of the first insulating film 616a so as to contact and cover the active surface 628 of the die 626 placed in the cavity 305. In one embodiment, the protective film 660 is formed of a material similar to the protective layer 622a. The protective film 660 is formed of PET, such as, for example, biaxial PET. However, the protective film 660 can be formed of any suitable protective material. In some embodiments, the protective film 660 has a thickness between about 50 μm and about 150 μm.

[0046]

[0065] Here, the substrate 302, attached to the insulating film 616a on a first side 675 and the protective film 660 on a second side 677, and further having the die 626 disposed therein, is exposed to a first lamination process in step 508. During the lamination process, the substrate 302 is exposed to high temperatures, causing the flowing layer 618a of the insulating film 616a to soften and flow into open voids or volumes between the insulating film 616a and the protective film 660 (e.g., into the voids 650 in the vias 303 and gaps 651 between the inner walls of the cavity 305 and the die 626). Thus, the semiconductor die 626 becomes at least partially embedded within the material of the insulating film 616a and the substrate 302, as depicted in FIG. 6D.

[0047]

[0066] In one embodiment, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period of between about 5 seconds and about 1.5 minutes (between about 30 seconds and about 1 minute). In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 50 psig while a temperature between about 80° C. and about 140° C. is applied to the substrate 302 and the insulating film 616a for a period of between about 5 seconds and about 1.5 minutes. For example, the lamination process is performed at a pressure between about 5 psig and about 40 psig and at a temperature between about 100° C. and about 120° C. for a period of between about 10 seconds and about 1 minute. The lamination process is performed, for example, at a temperature of about 110° C. for about 20 seconds.

[0048]

[0067] In step 510, the protective film 660 is removed and the substrate 302, now having the laminated insulating material of the flow layer 618a at least partially surrounding the substrate 302 and one or more dies 626, is coupled to a second protective film 662. As depicted in FIG. 6E, the second protective film 662 is coupled to a first side 675 of the substrate 302 such that the second protective film 662 is disposed against (e.g., adjacent to) the protective layer 622a of the insulating film 616a. In some embodiments, the substrate 302 now coupled to the protective film 662 may be optionally mounted on a carrier 624 for additional mechanical support on the first side 675. In some embodiments, the protective film 662 is mounted on the carrier 624 and laminated therewith with the insulating film 616a prior to coupling the protective film 662 to the substrate 302. Generally, the protective film 662 is substantially similar in composition to the protective film 660. For example, the overcoat 662 may be formed from PET, such as biaxial PET. However, the overcoat 662 may be formed from any suitable protective material. In some embodiments, the overcoat 662 has a thickness between about 50 μm and about 150 μm.

[0049]

[0068] Upon coupling the substrate 302 to the second protective film 662, a second insulating film 616b substantially similar to the first insulating film 616a is deposited on the second side 677 of the substrate 302 in step 512 and FIG. 6F, thus replacing the protective film 660. In one embodiment, the second insulating film 616b is disposed on the second side 677 of the substrate 302 such that the flowing layer 618b of the second insulating film 616b contacts and covers the active surface 628 of the die 626 in the cavity 305. In one embodiment, the deposition of the second insulating film 616b on the substrate 302 may form one or more voids 650 and gaps 651 between the insulating film 616b and the already deposited insulating material of the flowing layer 618a that partially surrounds the one or more dies 626. The second insulating film 616b may include one or more layers formed of a polymer-based dielectric material. 6F, the second insulating film 616b includes a flowable layer 618b similar to the flowable layer 618a described above. The second insulating film 616b may further include a protective layer 622b formed of a material similar to the protective layer 622a, such as PET.

[0050]

[0069] In step 514, as shown in FIG. 6G, a third protective film 664 is placed over the second insulating film 616b. Generally, the protective film 664 is substantially similar in composition to the protective films 660, 662. The protective film 664 is formed of PET, such as, for example, biaxial PET. However, the protective film 664 may be formed of any suitable protective material. In some embodiments, the protective film 664 has a thickness between about 50 μm and about 150 μm.

[0051]

[0070] The substrate 302, now attached to the insulating film 616b and protective layer 664 on the second side 677 and the protective film 662 and optional carrier 624 on the first side 675, is exposed to a second lamination process in step 516 and FIG. 6H. Similar to the lamination process in step 508, the substrate 302 is exposed to high temperature, causing the flowing layer 618b of the insulating film 616b to soften and flow into the voids 650 and gaps 651 between the insulating film 616b and the already deposited insulating material of the flowing layer 618a, thereby integrating itself with the insulating material of the flowing layer 618a. Thus, the cavity 305 and the via 303 are filled (e.g., packed, sealed) with insulating material, and the semiconductor die 626 previously placed in the cavity 305 becomes completely embedded in the insulating material of the flowing layers 618a, 618b.

[0052]

[0071] In one embodiment, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10 psig and about 150 psig while a temperature between about 80° C. and about 140° C. is applied to the substrate 302 and the insulating film 616b for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 20 psig and about 100 psig and a temperature between about 100° C. and about 120° C. for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for about 5 minutes.

[0053]

[0072] After stacking, the substrate 302 is disengaged from the carrier 624 and the protective films 662, 664 are removed in step 518 to obtain the stacked intermediate die assembly 602. As shown in FIG. 6I, the intermediate die assembly 602 includes a substrate 302 with one or more cavities 305 and / or vias 303 formed therein and filled with an insulating dielectric material of flowable layers 618a, 618b, in addition to a die 626 embedded within the cavity 305. The insulating dielectric material of flowable layers 618a, 618b contains the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302, such as major surfaces 606, 608, and covers all sides of the embedded semiconductor die 626. In some examples, the protective layers 622a, 622b are also removed from the intermediate die assembly 602 in step 518. Generally, the protective layers 622a and 622b, the carrier 624, and the protective membranes 662 and 664 are removed from the intermediate die assembly 602 by any suitable mechanical process (eg, by peeling therefrom).

[0054]

[0073] Upon removal of the protective layers 622a, 622b and the protective membranes 662, 664, the intermediate die assembly 602 is exposed to a curing process to fully cure (i.e., harden through chemical reaction and cross-linking) the insulating dielectric material of the flowable layers 618a, 618b, thereby forming a cured insulating layer 619. The insulating layer 619 substantially surrounds the substrate 302 and the semiconductor die 626 embedded therein. For example, the insulating layer 619 contacts or encapsulates at least sides 675, 677 (including surfaces 606, 608) of the substrate 302 and at least six sides or surfaces of each semiconductor die 626, which have a rectangular prism shape as illustrated in FIG. 6I.

[0055]

[0074] In one embodiment, the curing process is carried out at an elevated temperature to fully cure the insulating layer 619. For example, the curing process is carried out at a temperature between about 140° C. and about 220° C. for a period of between about 15 minutes and about 45 minutes (e.g., at a temperature between about 160° C. and about 200° C. for a period of between about 25 minutes and about 35 minutes). The curing process is carried out, for example, at a temperature of about 180° C. for about 30 minutes. In a further embodiment, the curing process in step 518 is carried out at or near ambient (e.g., atmospheric) pressure conditions.

[0056]

[0075] After curing, one or more through-assembly vias 603 are drilled through the intermediate die assembly 602 at step 520 to form channels through the entire thickness of the intermediate die assembly 602 for subsequent interconnect formation. In some embodiments, the intermediate die assembly 602 may be mounted on a carrier, such as carrier 624, for mechanical support during formation of the through-assembly vias 603 and subsequent contact holes 632. The through-assembly vias 603 are formed in the substrate 302 and are drilled through vias 303 that are subsequently filled with an insulating layer 619. Thus, the through-assembly vias 603 may be circumferentially surrounded by the insulating layer 619 filled within the vias 303. By lining the walls of the vias 303 with a polymer-based dielectric material (e.g., ceramic-filled epoxy resin material) of the insulating layer 619, the capacitive coupling between the conductive silicon-based substrate 302 and the interconnects 1044 (described with reference to FIG. 9 and FIG. 10E-10K), and thus between adjacently positioned vias 303 and / or redistribution connections 1244 (described with reference to FIG. 11 and FIG. 12H-12N), is significantly reduced in the completed 2D reconfigured substrate 1000, as compared to other conventional interconnect structures utilizing conventional via insulating liners or films. Furthermore, the flowability of the epoxy resin material allows for more consistent and reliable encapsulation and insulation, thus improving electrical performance by minimizing leakage current in the completed reconfigured substrate 1000.

[0057]

[0076] In one embodiment, the through assembly via 603 has a diameter of less than about 100 μm (such as less than about 75 μm). For example, the through assembly via 603 has a diameter of less than about 60 μm (such as less than about 50 μm). In one embodiment, the through assembly via 603 has a diameter between about 25 μm and about 50 μm (such as a diameter between about 35 μm and about 40 μm). In one embodiment, the through assembly via 603 is formed using any suitable mechanical process. For example, the through assembly via 603 is formed using a mechanical drilling process. In one embodiment, the through assembly via 603 is formed through the intermediate die assembly 602 by laser ablation. For example, the through assembly via 603 is formed using an ultraviolet laser. In one embodiment, the laser source utilized for laser ablation has a frequency between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a pulse duration between about 10 ns and about 100 ns with a pulse energy between about 50 microjoules (μJ) and about 500 μJ. Utilizing an epoxy resin material having small ceramic filler particles in the insulating layer 619 facilitates more precise and accurate laser patterning of small diameter vias, such as via 603, as the small ceramic filler particles therein exhibit reduced laser light reflection, scattering, diffraction and transmission of laser light away from the region where the via is to be formed during the laser ablation process.

[0058]

[0077] In step 522 and FIG. 6K, one or more contact holes 632 are drilled through the insulating layer 619 to expose one or more contacts 630 formed on the active surface 628 of each embedded semiconductor die 626. The contact holes 632 are drilled through the insulating layer 619 by laser ablation, exposing all of the external surfaces of the semiconductor die 626 while remaining covered and surrounded by the insulating layer 619 and the contacts 630. Thus, by forming the contact holes 632, the contacts 630 are exposed. In one embodiment, the laser source may generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and a pulse energy between about 10 μJ and about 300 μJ. In one embodiment, the contact holes 632 are formed by CO 2 The contact holes 632 are drilled using a white, green, or UV laser. In one embodiment, the contact holes 632 have a diameter between about 5 μm and about 60 μm (such as a diameter between about 20 μm and about 50 μm).

[0059]

[0078] After the formation of the contact holes 632, the intermediate die assembly 602 is exposed to a desmear process in step 522 to remove any undesired residue and / or debris caused by laser ablation during the formation of the through-assembly vias 603 and the contact holes 632. Thus, the desmear process cleans the through-assembly vias 603 and the contact holes 632 and fully exposes the contacts 630 on the active surface 628 of the embedded semiconductor die 626 for subsequent metallization. In one embodiment, the desmear process is a wet desmear process. Any suitable aqueous etchant, solvent, and / or combination thereof may be utilized for the wet desmear process. In one example, potassium permanganate (KMnO 4) solution may be utilized as an etchant. Depending on the thickness of the residue, exposure of the intermediate die assembly 602 to the wet desmear process in step 522 may be varied. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process may include O 2 :CF 4 The plasma desmear process may be a plasma desmear process using a gas mixture, such as O2 at a ratio of about 10:1 (e.g., 100:10 sccm) for a period between about 60 seconds and about 120 seconds, with an applied power of about 700 W. 2 :CF 4 In a further embodiment, the desmear process is a combination of a wet process and a dry process.

[0060]

[0079] Following the desmear process at step 522, the intermediate die assembly 602 is ready for the formation of interconnect paths therein, as described below with reference to Figures 9 and 10A-10K.

[0061]

[0080] As mentioned above, Figures 5 and 6A-6K illustrate an exemplary method 500 for forming an intermediate die assembly 602. Figures 7 and 8A-8G illustrate an alternative method 700 that is substantially similar to method 500, but has fewer steps. Method 700 generally includes seven steps 710-770. However, steps 710, 720, 760, and 770 of method 700 are substantially similar to steps 502, 504, 520, and 522, respectively, of method 500. Thus, only steps 730, 740, and 750, shown in Figures 8C, 8D, and 8E, respectively, are described herein for clarity.

[0062]

[0081] Thus, after placing one or more semiconductor dies 626 on the surface of the insulating film 616a exposed through the cavity 305, the second insulating film 616b is positioned above the second side 677 (e.g., major surface 608) of the substrate 302 prior to lamination in step 730 and FIG. 8C. In some embodiments, the second insulating film 616b is disposed on the second side 677 of the substrate 302 such that a flowable layer 618b of the second insulating film 616b contacts and covers the active surface 628 of the semiconductor die 626 within the cavity 305. In some embodiments, the second carrier 825 is affixed to the protective layer 622b of the second insulating film 616b for additional mechanical support during subsequent processing operations. As depicted in FIG. 8C, one or more voids 650 are formed between the insulating films 616a and 616b through the vias 303 and the gaps 651 between the semiconductor die 626 and the interior walls of the cavity 305.

[0063]

[0082] In step 740 and FIG. 8D, the substrate 302, now affixed to the insulating films 616a and 616b and with the die 626 disposed therein, is exposed to a single lamination process. During the single lamination process, the substrate 302 is exposed to an elevated temperature, causing the flowing layers 618a and 618b of both insulating films 616a, 616b to soften and flow into the open voids 650 or gaps 651 between the insulating films 616a, 616b. Thus, the semiconductor die 626 becomes embedded within the material of the insulating films 616a, 616b and the vias 303 that it fills.

[0064]

[0083] Similar to the lamination process described with reference to Figures 5 and 6A-6K, the lamination process in step 740 can be a vacuum lamination process that can be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and for a period of between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 150 psig while a temperature between about 80°C and about 140°C is applied to the substrate 302 and the insulating film 616a, 616b layers for a period of between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 psig and about 100 psig and a temperature between about 100°C and about 120°C for a period of between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for about 5 minutes.

[0065]

[0084] In step 750, one or more protective layers of insulating films 616a and 616b are removed from the substrate 302, resulting in a stacked intermediate die assembly 602. As shown in FIG. 8E, the intermediate die assembly 602 includes a substrate 302 having one or more cavities 305 and / or vias 303 formed therein and filled with an insulating dielectric material of flowable layers 618a, 618b, and an embedded die 626 within the cavity 305. The insulating material encases the substrate 302 such that the insulating material covers at least two surfaces or sides, e.g., major surfaces 606, 608, of the substrate 302. In one example, the protective layers 622a, 622b are removed from the intermediate die assembly 602 such that the intermediate die assembly 602 is disengaged from the carrier 624, 825. Generally, the protective layers 622a, 622b and carriers 624, 825 are removed by any suitable mechanical process (eg, peeled therefrom, etc.).

[0066]

[0085] Upon removal of protective layers 622a, 622b, intermediate die assembly 602 is exposed to a curing process to fully harden the insulating dielectric material of flowable layers 618a, 618b. Curing of the insulating material results in the formation of cured insulating layer 619. As depicted in Figure 8E and similar to step 518 corresponding to Figure 7I, insulating layer 619 substantially surrounds substrate 302 and semiconductor die 626 embedded therein.

[0067]

[0086] In one embodiment, the curing process is carried out at an elevated temperature to fully cure the intermediate die assembly 602. For example, the curing process may be carried out at a temperature between about 140° C. and about 220° C. for a period of between about 15 minutes and about 45 minutes (e.g., at a temperature between about 160° C. and about 200° C. for a period of between about 25 minutes and about 35 minutes). The curing process may be carried out, for example, at a temperature of about 180° C. for about 30 minutes. In a further embodiment, the curing process in step 750 is carried out at or near ambient (e.g., atmospheric) pressure conditions.

[0068]

[0087] After curing at step 750, method 700 is substantially similar to steps 520 and 522 of method 500. For example, intermediate die assembly 602 has one or more through-assembly vias 603 and one or more contact holes 632 drilled through insulating layer 619. Intermediate die assembly 602 is then exposed to a desmear process after which intermediate die assembly 602 is ready to have interconnect paths formed therein, as described below.

[0069]

[0088] Figure 9 illustrates a flow diagram of an exemplary method 900 of forming electrical interconnects through an intermediate die assembly 602. Figures 10A-10K illustrate schematic cross-sectional views of the intermediate die assembly 602 at different stages in the process of the method 900 illustrated in Figure 9. Thus, Figure 9 and Figures 10A-10K are described collectively herein for clarity.

[0070]

[0089] In one embodiment, the electrical interconnects formed through the intermediate die assembly 602 are formed of copper. Thus, the method 900 may optionally begin with step 910 and FIG. 10A, where the intermediate die assembly 602 with the through-assembly vias 603 and contact holes 632 formed therein has an adhesion layer 1040 and / or seed layer 1042 formed thereon. An enlarged partial view of the adhesion layer 1040 and seed layer 1042 formed on the intermediate die assembly 602 is shown in FIG. 10H for reference. The adhesion layer 1040 may be formed on desired surfaces of the insulating layer 619, such as the major surfaces 1005, 1007 of the intermediate die assembly 602, as well as on the active surfaces 628 in the contact holes 632 on each semiconductor die 626 and the inner walls of the through-assembly vias 603, to promote adhesion and help prevent diffusion of the subsequently formed seed layer 1042 and copper interconnects 1044. Thus, in one embodiment, adhesive layer 1040 acts as an adhesive layer, and in another embodiment, adhesive layer 1040 acts as a barrier layer, however, in both embodiments, adhesive layer 1040 will be described below as an "adhesive layer."

[0071]

[0090] In one embodiment, the optional adhesion layer 1040 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, the adhesion layer 1040 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the adhesion layer 1040 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesion layer 1040 is formed by any suitable deposition process, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and the like.

[0072]

[0091] An optional seed layer 1042 may be formed on the adhesion layer 1040 or directly on the insulating layer 619 (e.g., without forming an adhesion layer 1040). The seed layer 1042 is formed from a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. When the seed layer 1042 and the subsequently plated interconnect 1044 are formed from the same conductive material, the seed layer 1042 and the interconnect 1044 may have different grain sizes. For example, the seed layer 1042, when electrolessly deposited and when composed of copper, typically has a grain size between 20 nm and 100 nm. The electrodeposited copper interconnect 1044 typically has a grain size larger than about 100 nm-5 um. When the seed layer 1042 is deposited by sputtering (PVD), the grain size is also smaller than the electroplated copper interconnect 1044 formed thereon. In the case of PVD (sputtering), the grain size in the seed layer 1042 is also about 20 nm to 100 nm.

[0073]

[0092] In one embodiment, the seed layer 1042 has a thickness between about 50 nm and about 500 nm (such as between about 100 nm and about 300 nm). For example, the seed layer 1042 has a thickness between about 150 nm and about 250 nm (such as about 200 nm). In one embodiment, the seed layer 1042 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1040, the seed layer 1042 is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In one embodiment, a molybdenum adhesion layer 1040 is formed on the intermediate die assembly in combination with a seed layer 1042 formed of copper. The Mo-Cu adhesion and seed layer combination allows for improved adhesion with the surface of the insulating layer 619 and reduces undercutting of the conductive interconnect lines during the subsequent seed layer etching process in step 970.

[0074]

[0093] In steps 920 and 930, corresponding to Figures 10B and 10C, respectively, a spin-on / spray-on or dry resist film 1050, such as photoresist, is applied to both major surfaces 1005, 1007 of the intermediate die assembly 602 and then patterned. In one embodiment, the resist film 1050 is patterned via selective exposure to UV radiation. In one embodiment, an adhesion promoter (not shown) is applied to the intermediate die assembly 602 prior to the formation of the resist film 1050. The adhesion promoter improves the adhesion of the resist film 1050 to the intermediate die assembly 602 by creating an interfacial bonding layer for the resist film 1050 and by removing any moisture from the surface of the intermediate die assembly 602. In some embodiments, the adhesion promoter is formed from bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0075]

[0094] In step 940 and FIG. 10D, the intermediate die assembly 602 is exposed to a resist film developing process, an ashing process, and a descum process. In a particular embodiment, the descum process is an oxygen plasma treatment to remove any remaining organic resist residue. As shown in FIG. 10D, developing the resist film 1050 exposes the through assembly vias 603 and the contact holes 632 where the adhesion layer 1040 and the seed layer 1042 are formed thereon. In one embodiment, the film developing process is a wet process, such as a wet process that includes exposing the resist to a solvent. In one embodiment, the film developing process is a wet etching process that utilizes an aqueous etching process. In another embodiment, the film developing process is a wet etching process that utilizes a buffered etching process that is selective to the desired material. Any suitable wet solvent or combination of wet etchants may be used for the resist film developing process.

[0076]

[0095] In steps 950 and 960, corresponding to FIGS. 10E and 10F, respectively, interconnects 1044 are formed on the exposed surface of the intermediate die assembly 602, such as through the exposed through-assembly vias 603 and contact holes 632, and then the resist film 1050 is removed. The interconnects 1044 are formed by any suitable method, including electroplating and electroless plating. In one embodiment, the resist film 1050 is removed by a wet process. As depicted in FIGS. 10E and 10F, the formed interconnects 1044 completely fill or cover the inner walls of the through-assembly vias 603 and contact holes 632, and protrude from the surfaces 1005, 1007 of the intermediate die assembly 602 upon removal of the resist film 1050. For example, the interconnects 1044 may line the inner walls of the through-assembly vias 603 and have a hollow core. In one embodiment, the interconnects 1044 are formed of copper. In other embodiments, the interconnects 1044 may be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, and the like.

[0077]

[0096] In some embodiments, the interconnects 1044 include lateral trace (e.g., lines or pads) regions for electrically connecting the interconnects 1044 with other electrical contacts or devices, such as the redistribution connections 1244 described below. The lateral trace regions can include a portion of the conductive layer formed in step 950, and will typically extend across a portion of the major surfaces 1007 or 1005.

[0078]

[0097] In step 970 and FIG. 10G, the intermediate die assembly 602 with the interconnects 1044 formed therein is exposed to an adhesion and / or seed layer etch process to remove the adhesion layer 1040 and the seed layer 1042, thereby resulting in the formation of the completed reconstituted substrate 1000. In one embodiment, the seed layer etch is a wet etch process that includes rinsing and drying the intermediate die assembly 602. In one embodiment, the seed layer etch process is a buffer etch process that is selective to a desired material, such as copper, tungsten, aluminum, silver, or gold. In another embodiment, the etch process is an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etch process.

[0079]

[0098] 10I and 10J show further exemplary arrangements of a reconfigurable substrate 1000 according to certain embodiments. The packaging scheme shown in FIGURES 10I and 10J is particularly beneficial for memory die stacking because it reduces the amount of steps required to stack a desired number of memory dies (e.g., stacking eight memory dies to form a "byte" now requires stacking only four packages or reconfigurable substrates).

[0080]

[0099] As shown, the reconfigured substrate 1000 includes two semiconductor dies 626 stacked back-to-back in a die stack 1026 within each cavity 305, with the backsides of the semiconductor dies 626 coupled to one another by an adhesive layer 1048. Thus, the active sides 628 of the stacked semiconductor dies 626 face opposite sides of the reconfigured substrate 1000 and have interconnects 1044 extending in opposite directions therefrom. In certain embodiments, the stacked semiconductor dies 626 are of the same type and / or have substantially the same lateral dimensions, as shown in FIG. 10I. In certain other embodiments, the stacked semiconductor dies 626 are of different types and / or have different lateral dimensions, as shown in FIG. 10J. In such embodiments, a dummy die 627 may be placed along the semiconductor die 626 having a smaller lateral dimension to ensure substantially similar overall dimensions of each layer of the die stack 1026. The adhesive layer 1048 utilized to attach the backside of the semiconductor die 626 can be any suitable type of adhesive, such as a laminating adhesive material, a die attach film, an adhesive, or the like.

[0081]

[0100] To form the arrangement shown in Figures 10I and 10J, the semiconductor dies 626 can be attached to each other before placing the die stack 1026 in the cavity 305 of the substrate 302. An exemplary process flow for forming the die stack 1026 is shown in Figure 10K. As shown, the backsides of two die substrates 1002 (e.g., DRAM substrates) are aligned and bonded to each other using an adhesive layer 1048. In an embodiment, the die substrates 1002 can be thinned before or after bonding, depending on the desired thickness of the die stack 1026. The die substrates 1002 are then singulated into individual die stacks 1026, which can be placed in the cavity 305 of the substrate 302 and encapsulated in an insulating layer 619, as described with reference to methods 500 and 700. Thereafter, interconnect and / or redistribution layers may be formed according to any of the processes described herein (e.g., methods 900 and 1200), substantially similar to the example in which a single semiconductor die 626 or an array of semiconductor dies 626 are embedded within the cavity 305 of the substrate 302.

[0082]

[0101] Following the bonding and / or seed layer etching process in step 970, the reconfigured substrate 1000 may be singulated into one or more electrically functional packages or SiPs (e.g., each singulated package or SiP includes a single region 412 of the substrate 302, here including the insulating layer 619 and interconnects 1044 formed thereon, and the semiconductor die 626 embedded therein). Each package or SiP may then be integrated with other semiconductor devices and packages in a variety of 2.5D and 3D configurations and architectures. For example, the packages or SiPs may be vertically stacked with additional packages or SiPs and / or other semiconductor devices and systems to form homogeneous or heterogeneous 3D stacked systems. Alternatively, the reconfigured substrate 1000 may be integrated with additional semiconductor devices and systems prior to being singulated. Such 3D integration of the 2D reconfigured substrate 1000 is further described below with reference to FIG. 13 and FIGS. 14A-14D.

[0083]

[0102] In yet another embodiment, upon etching of the adhesion layer and / or seed layer, the reconfigured substrate 1000 may have one or more redistribution layers 1258, 1260 (shown in FIGS. 12K-12N) formed thereon, as needed, to allow rerouting and / or extension of the contacts of the interconnects 1044 to desired locations on the surface of the reconfigured substrate 1000. FIG. 11 illustrates a flow diagram of an exemplary method 1100 of forming a redistribution layer 1258 on the reconfigured substrate 1000. FIGS. 12A-12N illustrate schematic cross-sectional views of the reconfigured substrate 1000 at different stages of the method 1100 shown in FIG. 11. Accordingly, FIGS. 11 and 12A-12N are collectively described herein for clarity.

[0084]

[0103] Method 1100 is substantially similar to methods 500, 700, and 900 described above. Generally, method 1100 begins with step 1102 and FIG. 12A, where insulating film 1216 is placed on reconfigured substrate 1000, which already has insulating layer 619 formed thereon, and then laminated. Insulating film 1216 is substantially similar to insulating film 616 and may include one or more flowable layers 1218 formed from a polymer-based dielectric material and one or more protective layers 1222 formed from PET.

[0085]

[0104] In one embodiment, the flowable layer 1218 includes an epoxy resin material. In one embodiment, the flowable layer 1218 includes a ceramic filler-containing epoxy resin material. In another embodiment, the flowable layer 1218 includes a photosensitive polyimide material. The material properties of the photosensitive polyimide enable the formation of smaller (e.g., narrower) vias through the resulting interconnect redistribution layer formed from the insulating film 1216. However, any suitable combination of the flowable layer 1218 and insulating material is contemplated for the insulating film 1216. For example, the insulating film 1216 can include one or more flowable layers 1218 including a non-photosensitive polyimide material, a polybenzoxazole (PBO) material, a silicon dioxide material, and / or a silicon nitride material.

[0086]

[0105] In some examples, the material of the flowing layer 1218 is different from the flowing layer 618 of the insulating film 616. For example, the flowing layer 618 can include a ceramic filler-containing epoxy resin material and the flowing layer 1218 can include a photosensitive polyimide material. In another example, the flowing layer 1218 includes a different inorganic dielectric material than the flowing layer 618. For example, the flowing layer 618 can include a ceramic filler-containing epoxy resin material and the flowing layer 1218 can include a silicon dioxide material.

[0087]

[0106] The insulating film 1216 has a total thickness of less than about 120 μm (such as between about 40 μm and about 100 μm). For example, the insulating film 1216 including the flowable layer 1218 and the protective layer 1222 has a total thickness of between about 50 μm and about 90 μm. In one embodiment, the flowable layer 1218 has a thickness of less than about 60 μm (such as between about 5 μm and about 50 μm (e.g., about 20 μm)). The insulating film 1216 is disposed on a surface (such as the major surface 1007) of the reconfigured substrate 1000 having exposed interconnects 1044 that are coupled to contacts 630 on the active surface 628 of the semiconductor die 626 and / or are coupled to metallized through-assembly vias 603.

[0088]

[0107] After deposition of insulating film 1216, reconfigured substrate 1000 is exposed to a lamination process substantially similar to that described with reference to steps 508, 516, and 740. Reconfigured substrate 1000 is exposed to high temperatures to soften flowable layer 1218, which then bonds to insulating layer 619 already formed on reconfigured substrate 1000. Thus, in one embodiment, flowable layer 1218 merges with insulating layer 619 and forms an extension thereof. The merger of flowable layer 1218 and insulating layer 619 results in an extended and merged insulating layer 619 that covers previously exposed interconnects 1044. Thus, the combined flowable layer 1218 and insulating layer 619 will be collectively described herein as insulating layer 619. However, in other embodiments, lamination and subsequent curing of flowable layer 1218 forms a second insulating layer (not shown) on insulating layer 619. In some examples, the second insulating layer is formed of a different material layer than insulating layer 619.

[0089]

[0108] In one embodiment, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between 10 psig and about 100 psig while a temperature between about 80° C. and about 140° C. is applied to the substrate 302 and the insulating film 1216 for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 30 psig and about 80 psig and a temperature between about 100° C. and about 120° C. for a period between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for about 5 minutes. In a further example, the lamination process is performed at a pressure between about 30 psig and about 70 psig (such as about 50 psig).

[0090]

[0109] In step 1104 and FIG. 12B, protective layer 1222 is removed from reconstituted substrate 1000 by a mechanical process. After removing protective layer 1322 and carrier 1324, reconstituted substrate 1000 is exposed to a curing process to fully cure newly extended insulating layer 619. In one embodiment, the curing process is substantially similar to the curing process described with reference to steps 518 and 750. For example, the curing process may be performed at a temperature between about 140° C. and about 220° C. for a period of between about 15 minutes and about 45 minutes (e.g., at a temperature between about 160° C. and about 200° C. for a period of between about 25 minutes and about 35 minutes). The curing process may be carried out, for example, at a temperature of about 180° C. for about 30 minutes. In a further embodiment, the curing process in step 1104 is carried out at or near ambient pressure conditions.

[0091]

[0110] The reconfigured substrate 1000 is then selectively patterned by laser ablation in step 1106 and FIG. 12C. The laser ablation in step 1106 forms redistribution vias 1203 through the newly expanded insulating layer 619, exposing the desired interconnects 1044 for redistribution of their contacts. In one embodiment, the redistribution vias 1203 have a diameter between about 5 μm and about 60 μm, such as a diameter between about 10 μm and about 50 μm (e.g., between about 20 μm and about 45 μm). In one embodiment, the laser ablation process in step 1106 is performed using CO 2 The laser ablation process in step 1106 is performed using a UV laser. In one embodiment, the laser ablation process in step 1106 is performed using a green laser. For example, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam with a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and a pulse energy between about 10 μJ and about 300 μJ.

[0092]

[0111] Once the reconstituted substrate 1000 has been patterned, the reconstituted substrate 1000 is subjected to a desmear process substantially similar to the desmear processes in steps 522 and 770. During the desmear process in step 1106, unwanted residue and debris formed by laser ablation during the formation of the redistribution vias 1203 are removed from the redistribution vias 1203 to clear (e.g., clean) their surfaces for subsequent metallization. In one embodiment, the desmear process is a wet process. Any suitable aqueous etchant, solvent, and / or combination thereof may be utilized for the wet desmear process. In one example, KMnO 4 The solution may be utilized as an etchant. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process may be a dry desmear process. 2 / CF 4It can be a plasma desmear process using a mixed gas. In a further embodiment, the desmear process is a combination of a wet process and a dry process.

[0093]

[0112] In step 1108 and FIG. 12D, optional adhesion layer 1240 and / or seed layer 1242 are formed on insulating layer 619. In one embodiment, adhesion layer 1240 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In one embodiment, adhesion layer 1240 has a thickness between about 10 nm and about 300 nm (such as between about 50 nm and about 150 nm). For example, adhesion layer 1240 has a thickness between about 75 nm and about 125 nm (such as about 100 nm). Adhesion layer 1240 may be formed by any suitable deposition process, including, but not limited to, CVD, PVD, PECVD, ALD, and the like.

[0094]

[0113] The optional seed layer 1242 is formed from a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, the seed layer 1242 has a thickness between about 50 nm and about 500 nm (such as between about 100 nm and about 300 nm). For example, the seed layer 1242 has a thickness between about 150 nm and about 250 nm (such as about 200 nm). In one embodiment, the seed layer 1242 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1240, the seed layer 1242 may be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In one embodiment, a molybdenum adhesion layer 1240 and a copper seed layer 1242 are formed on reconfigured substrate 1000 to reduce undercutting of the conductive interconnect lines during a subsequent seed layer etching process in step 1120 .

[0095]

[0114] In steps 1110, 1112, and 1114, corresponding to Figures 12E, 12F, and 12G, respectively, a spin-on / spray-on or dry resist film 1250, such as photoresist, is applied over the adhesive and / or seed surface of the reconfigured substrate 1000, and then patterned and developed. In one embodiment, an adhesion promoter (not shown) is applied to the reconfigured substrate 1000 before placing the resist film 1250. Exposure and development of the resist film 1250 results in exposure of the insulating layer 619, the adhesion layer 1240, or the copper seed layer 1242 to form the openings of the redistribution vias 1203 and the redistribution connections 1244 thereon. Thus, patterning of the resist film 1250 can be performed by selectively exposing parts of the resist film 1250 to UV radiation and then developing the resist film 1250 by a wet process, such as a wet etching process. In one embodiment, the resist film development process is a wet etching process that utilizes a buffered etching process that is selective to the desired material. In another embodiment, the resist film development process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used in the resist film development process.

[0096]

[0115] In steps 1116 and 1118, corresponding to Figures 12H and 12I, respectively, redistribution connections 1244 are formed on the exposed surface of the reconfigured substrate 1000, such as through the exposed redistribution vias 1203, and then the resist film 1250 is removed. The redistribution connections 1244 are formed by any suitable method, including electroplating and electroless deposition. In one embodiment, the resist film 1250 is removed by a wet process. As shown in Figures 12H and 12I, the redistribution connections 1244 fill the redistribution vias 1203 and protrude from the surface of the reconfigured substrate 1000 upon removal of the resist film 1250. In one embodiment, the redistribution connections 1244 are formed of copper. In other embodiments, the redistribution connections 1244 may be formed of any suitable conductive material, including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, and the like.

[0097]

[0116] As described with reference to interconnects 1044, redistribution connections 1244 may also include lateral trace regions for electrically connecting redistribution connections 1244 with other electrical contacts or devices. The lateral trace regions may include portions of the conductive layer formed in step 1116 and will typically extend across a portion of a major surface of reconfigured substrate 1000.

[0098]

[0117] In step 1120 and FIG. 12J, the reconfigured substrate 1000 with the redistribution connections 1244 formed thereon is exposed to a bonding and / or seed layer etching process substantially similar to step 970. In one embodiment, the bonding and / or seed layer etching is a wet etching process that includes rinsing and drying the reconfigured substrate 1000. In one embodiment, the bonding and / or seed layer etching process is a wet etching process that utilizes a buffered etching process that is selective to the desired material of the seed layer 1242. In another embodiment, the etching process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etching process.

[0099]

[0118] In step 1122, one or more functional 2D packages 1200 may be singulated from the 2D reconfiguration substrate 1000, as shown in FIG. 12K. (Although described as a package, the package 1200 may also refer to a SiP and other functional package devices.) However, in some embodiments, additional redistribution layers may be formed on the reconfiguration substrate 1000 prior to singulation of the package 1200 by utilizing the sequences and processes described above. For example, as shown in FIG. 12L, one or more additional redistribution layers 1260 may be formed on a side or surface of the reconfiguration substrate 1000 opposite the first redistribution layer 1258, such as the major surface 1007. Alternatively, one or more additional redistribution layers 1260 may be formed on the same side or surface of the first redistribution layer 1258, such as the major surface 1007. The package 1200 may then be singulated from the reconfiguration substrate 1000 after all desired redistribution layers have been formed. Each package 1200 is then integrated with other semiconductor devices and packages, which may be heterogeneous or homogeneous, in a desired 2.5D and 3D configuration and architecture. For example, the package 1200 may be vertically stacked with other semiconductor devices and systems to form a heterogeneous 3D stack system. However, in yet another embodiment, the reconfigured substrate 1000 with one or more redistribution layers 1258, 1260 formed thereon is 3D integrated with additional semiconductor devices and systems, which may be heterogeneous or homogeneous, prior to singulation into individual 3D packages or SiPs.

[0100]

[0119] 12L-12N further illustrate package 1200, where reconfigured substrate 1000 includes oxide layer 314 or metal cladding layer 315. As shown in FIG. 12L, oxide layer 314 is formed on all surfaces of substrate 302, including sidewalls of cavity 305 and vias 303, where semiconductor die 626 or interconnects 1044 are disposed therein and surrounded by insulating layer 619. The flowable dielectric material of insulating layer 619 surrounds oxide layer 314, such that at least insulating layer 619 and oxide layer 314 separate the surface of substrate 302 from any semiconductor die 626 and / or interconnects 1044 and prevent contact therebetween.

[0101]

[0120] Similarly, in Figure 12M, metal cladding layer 315 is formed on all surfaces of substrate 302. However, unlike oxide layer 314, metal cladding layer 315 is coupled to at least one cladding connection 1290 that forms at least one connection point on at least one side of package 1200, or is coupled to cladding connection 1290 that forms at least one connection point on both sides 677 and 675 as shown in Figures 12N-12M. Cladding connection 1290 is connected to a common ground used by one or more semiconductor dies disposed with package 1200. Alternatively, cladding connection 1290 is connected to a reference voltage, such as a power supply voltage. As shown, the clad connections 1290 are formed in the insulating layer 619 and connect the metal clad layer 315 to connection ends of the clad connections 1290 located on or at a surface of the package 1200, such as major faces 1007 and 1005, so that the metal clad layer 315 can be connected to an external common ground or reference voltage (shown in FIG. 12N as an exemplary connection to ground). The clad connections 1290 are formed of any suitable conductive material, including but not limited to nickel, copper, aluminum, gold, cobalt, silver, palladium, tin, and the like. The clad connections 1290 are deposited or plated through clad vias 633 formed in step 522 and substantially similar to the contact holes 632. Thus, the clad vias 633 may be laser drilled through the insulating layer 619 directly above or below the substrate 302 on which the metal clad layer 315 is formed. Further, similar to interconnect 1044, clad connect 1290 completely fills or lines the inner periphery of clad via 633, thus having a hollow core. In some embodiments, clad via 633 has a diameter of about 5 μm.

[0102]

[0121] To further clarify the grounding function of the metal cladding layer 315 and the cladding connection 1290, FIG. 12N shows the package 1200 of FIG. 12M in a schematic manner, stacked simultaneously with two electronic systems 1295, 1296 and coupled to an exemplary ground 1299 (however, 3D integration of the reconfigurable substrate 1000 and / or package 1200 is described in more detail with reference to FIGS. 13A-20F below). Although shown as being connected to ground 1299, the metal cladding layer 315 may alternatively be connected to a reference voltage, for example, as described above. Each electronic system 1295, 1296 includes a 2D or 3D circuit including traces, interconnect wiring, and typically one or more electrical devices. In some embodiments, the electronic systems 1295, 1296 include one or more electrical devices forming part of an electrical system, such as a SIP, SIC, or SOC, which may each include one or more semiconductor devices 1297, 1298. As shown, semiconductor device 1297 is electrically connected to interconnect 1044 adjacent major surface 1007 of package 1200, and semiconductor device 1298 is electrically coupled to interconnect 1044 adjacent major surface 1005. Device connections 1297A, 1298A (which may include interconnects and redistribution connections) of semiconductor devices 1297, 1298, respectively, may be coupled to interconnect 1044 or redistribution connections 1244 via any suitable structure and method, including solder bumps or balls 1246.

[0103]

[0122] At the same time, the metal cladding layer 315 may be electrically coupled to an external ground 1299 via the cladding connection 1290 and any other suitable coupling means. For example, the cladding connection 1290 may be indirectly coupled to the external ground 1299 via the solder bumps 1246 on the other side of the package 1200. In some implementations, the cladding connection 1290 may first be routed through a separate electronic system, such as electronic system 1295, before coupling to the external ground 1299. The use of a ground path between the metal cladding layer 315 and the external ground 1299 reduces or eliminates interference between the interconnects 1044 and / or the redistribution connections 1244, preventing shorting of the coupled integrated circuits, which may damage the semiconductor die 626, the package 1200, and any systems or devices integrated therewith.

[0104]

[0123] FIG. 13 shows a flow diagram of an exemplary method 1300 for forming an exemplary laminated 3D structure 1400 having two vertically stacked reconfigured substrates. FIG. 14A-14D show schematic cross-sectional views of the laminated 3D structure 1400 at different stages of the method 1300 shown in FIG. 13. Therefore, FIG. 13 and FIG. 14A-14D are collectively described herein for clarity. Furthermore, the method shown in FIG. 13 and FIG. 14A-14D and described below includes a build-up technique for forming the laminated 3D structure 1400. Therefore, such a method may be referred to as "build-up stacking".

[0105]

[0124] 14A, where a first insulating film 1416 is deposited on a desired surface of a reconfigured substrate 1000a for integration with another device, such as another reconfigured substrate, and then laminated. Reconfigured substrate 1000a may include all of the features described above with reference to reconfigured substrate 1000, including a structural frame formed from substrate 302a having cavity 305a and vias 303a patterned therein.

[0106]

[0125] As shown in FIG. 14A, the insulating film 1416 is disposed on the major surface 1007 having a single redistribution layer 1258a formed thereon. In general, the insulating film 1416 is disposed on a surface of the reconfigured substrate 1000a having exposed interconnects, such as redistribution connections 1244a, conductively coupled to the contacts 630a and / or interconnects 1044a on the active surface 628a of the semiconductor die 626a. Although shown as having a single redistribution layer 1258a, the reconfigured substrate 1000a may have more or less than one redistribution layer formed on any desired surface thereof. Additionally, the method 1300 may be utilized for 3D integration of structures other than the reconfigured substrate 1000a, such as the intermediate die assembly 602. Additionally, prior to deposition and stacking of the insulating film 1416, the reconfigured substrate 1000a may be secured on a carrier, such as the carrier 624, for mechanical support during any of the steps of the method 1300.

[0107]

[0126] The insulating film 1416 is substantially similar to the insulating films 616 and 1216 and may include one or more flowable layers 1418 formed of a polymer-based dielectric material and one or more protective layers 1422 formed of, for example, PET. In one embodiment, the flowable layer 1418 includes an epoxy resin material, such as a ceramic-filled epoxy resin material. In another embodiment, the flowable layer 1418 includes a polyimide material, such as a photosensitive or non-photosensitive polyimide material. In yet other embodiments, the flowable layer 1418 includes a PBO material, a silicon dioxide material, and / or a silicon nitride material.

[0108]

[0127] In some examples, the material of flowing layer 1418 is different from the material of flowing layer 618 and / or flowing layer 1218. In other examples, flowing layer 1418 includes the same material as flowing layer 618 and / or flowing layer 1218.

[0109]

[0128] The insulating film 1416 has a total thickness of less than about 80 μm (such as between about 10 μm and about 60 μm). For example, the insulating film 1416 including the flowable layer 1418 and the protective layer 1422 has a total thickness of less than about 120 μm (such as between about 20 μm and about 40 μm). The flowable layer 1418 itself can have a thickness of between about 5 and about 50 μm (such as between about 10 and about 25 μm).

[0110]

[0129] Once the insulating film 1416 is deposited, the reconfigured substrate 1000a is subjected to a lamination process substantially similar to that described above with reference to steps 508, 516, 740, and 1102. The reconfigured substrate 1000a is subjected to an elevated temperature to soften the flowable layer 1418 of the insulating film 1416, which then bonds (e.g., with the redistribution layer 1258a) to the major surface 1007 of the reconfigured substrate 1000a. The flowable layer 1418 thus merges with the insulating layer 619 of the reconfigured substrate 1000a to form a base layer 1410 for any devices and / or structures laminated directly thereon. The base layer 1410 covers any exposed interconnects on the surface to which it is bonded, such as the redistribution connections 1244a on the major surface 1007, and provides a substantially planar structure upon which further devices may be formed.

[0111]

[0130] In one embodiment, the lamination process in step 1302 is a vacuum lamination process that may be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period of between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between 10 psig and about 100 psig while a temperature between about 80° C. and about 140° C. is applied to the substrate 302 and the insulating film 1216 for a period of between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 30 psig and about 80 psig and a temperature between about 100° C. and about 120° C. for a period of between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for about 5 minutes. In a further example, the lamination process is performed at a pressure between about 30 psig and about 70 psig (such as about 50 psig).

[0112]

[0131] After lamination, the protective layer 1422 is mechanically removed from the base layer 1410, and the reconfigurable substrate 1000a is ready for another device to be laminated (eg, vertically integrated) thereon.

[0113]

[0132] 13 and 14A-14D, reconfigured substrate 1000a is laminated with a second reconfigured substrate 1000b by build-up stacking, with the second reconfigured substrate 1000b being built directly above reconfigured substrate 1000a in a manner substantially similar to the steps described above with reference to methods 500 and 900. Thus, for clarity, only steps 1304 and 1306 will be described in further detail, as the remaining steps of method 1300 have been described above with reference to methods 500 and 900.

[0114]

[0133] In step 1304, the second structured substrate 302b is placed on the base layer 1410 formed on the reconfigured substrate 1000a. The second structured substrate 302b may include any desired features patterned therein, including vias 303b for forming interconnects and cavities 305b for placing semiconductor dies. In some embodiments, the substrate 302b further includes an oxide layer 314, such as a silicon oxide film, formed on the desired surface thereof for insulation. During placement, the substrate 302b is aligned with the reconfigured substrate 1000a such that the vias 303b formed in the substrate 302b are aligned with the contacts of the redistribution connections 1244a or the interconnects 1044a. In some embodiments, the substrate 302b may be placed above the base layer 1410 such that the vias 303b are positioned directly above the interconnects 1044a and / or the redistribution connections 1244a.

[0115]

[0134] In step 1306, one or more semiconductor dies 626b are placed in a cavity 305b formed in the substrate 302b. As described above, the cavity 305b can have any desired lateral dimensions and geometry, thus allowing for placement of different types of semiconductor devices and / or dies in any desired arrangement for heterogeneous 3D integration. Thus, the one or more semiconductor dies 626 placed in the cavity 305b can be of the same type or different types from each other and / or embedded in the reconfigured substrate 1000a. Furthermore, the semiconductor dies 626 in each of the reconfigured substrates 1000a and 1000b can be of the same type or different types and can have different shapes, dimensions, and / or arrangements. In general, even if the semiconductor die 626 in each reconfigured substrate 1000a or 1000b are of different types and / or have different shapes, sizes, and / or configurations, the lateral dimensions of the reconfigured substrates 1000a, 1000b (e.g., substrates 302a, 302b) are still substantially identical to enable build-up stacking. However, it is contemplated that reconfigured substrates of different lateral dimensions may be stacked together by the build-up stacking methods described herein.

[0116]

[0135] After placing die 626b in cavity 305b (i.e., FIG. 14C), steps 512-522 of method 500 and steps 910-970 of method 900 are performed on substrate 302b in step 1308 to form complete reconstituted substrate 1000b over reconstituted substrate 1000a, thereby forming 3D stacked structure 1400. For example, an insulating layer is formed around substrate 302b by depositing, laminating, and curing an insulating film substantially similar to films 616 and 1416 over substrate 302b. The flowing layer of insulating film may flow into vias 303b and cavity 305b and, upon lamination, merge with base layer 1410 and insulating layer 619, thereby forming an extension of insulating layer 619. Thus, insulating layer 619 may be described as extending to substantially surround both substrate 302a and substrate 302b to form a singulated and integrated 3D device structure.

[0117]

[0136] Upon forming the insulating layer around the substrate 302b, the substrate 302b has one or more interconnects 1044b formed therein. Similar to the process described above, one or more through-assembly vias are laser drilled through the vias 303b where they are filled with the extended insulating layer 619. By drilling the through-assembly vias in the substrate 302b, the contacts (e.g., top surface) of the redistribution connections 1244a and the interconnects 1044a of the underlying reconfiguration substrate 1000a are exposed, allowing the interconnects 1044b to be formed in direct contact with the redistribution connections 1244a and the interconnects 1044a. Thus, after exposing the underlying conductive features by laser drilling, interconnect 1044b may be formed (e.g., by growing or plating a conductive material) directly over and in contact with redistribution connection 1244a and interconnect 1044a, eliminating the need to utilize intermediate electrical coupling structures between reconfigured substrates 1000a and 1000b, such as solder bumps or contact pads.

[0118]

[0137] The interconnects 1044b formed through the reconfigured substrate 1000b are formed by any suitable method, including electroplating and electroless deposition. In some embodiments, the interconnects 1044b completely fill the through-assembly vias and contact holes in which they are formed or cover only the inner perimeter walls thereof. For example, the interconnects 1044b may line the inner perimeter walls of their corresponding through-assembly vias and have hollow cores. In some embodiments, the interconnects 1044b are formed of copper. In other embodiments, the interconnects 1044b may be formed of any suitable conductive material, including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, and the like. Furthermore, the interconnects 1044b may be formed of the same or different conductive material as the interconnects 1044a and / or redistribution connections 1244a of the reconfigured substrate 1000b. In some embodiments, the material of the interconnects 1044b has a different grain size than the material of the interconnects 1044a and / or redistribution connections 1244a.

[0119]

[0138] In some embodiments, after the interconnect formation, one or more redistribution layers 1258b with redistribution connections 1244b can be formed on the reconfigured substrate 1000b. Thus, the formation of the reconfigured substrate 1000b results in a fully functional stacked 3D structure 1400, shown in FIG. 14D, vertically integrating the reconfigured substrates 1000a, 1000b. Thus, after the formation of the stacked 3D structure 1400, one or more additional devices can be stacked on the 3D structure 1400 by build-up stacking or other stacking methods, or the 3D structure 1400 can be singulated into individual 3D packages or SiPs.

[0120]

[0139] The above-described devices and methods provide many advantages over conventional stacking configurations and may be utilized in any suitable advanced 2.5D or 3D integration applications. In one exemplary embodiment shown in FIG. 15A, the method 1300 is utilized to efficiently form 3D stacked DRAM structures 1500a-c in a heterogeneous batch, with each stacked DRAM structure 1500a-c having a different grade of memory die 1526a-c embedded therein. Thus, during the formation of the reconfigured substrate 1000, the memory die 1526a-c of each grade is sorted and placed in the same designated cavity formed in the substrate frame (e.g., substrate 302) of each reconfigured substrate 1000. Upon forming the stack of reconfigured substrates 1000, the individual stacked DRAM structures 1500a-c may then be singulated from the stacked reconfigured substrates 1000 to form individual stacks. Thus, method 1300 may be utilized to achieve batch memory stacking, with each memory stack comprising only one type of memory die for performance matching. Although not shown in FIG. 15A, in some embodiments, a singulated stack may include two or more silicon dies within its cavity 305.

[0121]

[0140] In another exemplary embodiment, the stacked DRAM structures 1500a-c are integrated into a high bandwidth memory (HBM) module with a large parallel interconnect density between the memory dies and the central processing unit (CPU) core or logic die. Traditionally, an HBM module includes a flip-chip DRAM die stack interconnected to the logic die by a silicon interposer and solder bumps. Thus, the bandwidth between the DRAM die stack and the logic die is limited by the size of the solder bumps and the pitch between them, which is generally greater than about 20 μm. However, by utilizing stacked memory dies such as the stacked DRAM structures 1500a-c described above and embedding them together with the logic die into the cavity 305 of the larger reconfigurable substrate 1000, as shown in FIG. 15b and FIG. 15c, the pitch between the memory die interconnects of the HBM module can be smaller.

[0122]

[0141] As shown in FIG. 15b, the HBM structure 1550 may include any of the stacked DRAM structures 1500a-c embedded within the cavity 305 of the reconfigured substrate 1000. Alternatively, FIG. 15c illustrates an HBM structure 1560 having an exemplary HBM flip chip stack 1570 instead of the DRAM structures 1500a-c. The HBM flip chip stack 1570 generally includes a stack of DRAM memory dies 1572 communicatively coupled to a controller die 1574, all interconnected by solder bumps 1576. To account for the thickness of the memory die stack, the substrate 302 of the reconfigured substrate 1000 has a thickness of less than about 900 μm, such as less than about 800 μm (e.g., less than about 775 μm). The center-to-center pitch PI of the interconnects 1044 through the reconfigured substrate 1000 is between 150 μm and about 250 μm, such as about 200 μm.

[0123]

[0142] The DRAM structures 1500a-c or HBM flip chip stack 1570 are embedded in the cavity 305 alongside the active logic die 1528 and are interconnected by the interconnects 1044 and the redistribution connections 1244. Using the methods described above, such as methods 900 and 1100, a pitch PM of less than about 20 μm is possible between the interconnects 1044 coupled to the contacts 1530 of the memory stack and between the interconnects 1044 coupled to the active logic die 1528. Thus, the density of the interconnects 1044 coupling the DRAM structures 1500a-c or HBM flip chip stack 1570 to the active logic die 1528 is increased, improving the performance of the HBM structures 1550 and 1560.

[0124]

[0143] Another exemplary embodiment of a stacked structure utilizing the above-described devices and methods is depicted in FIG. 16, where four packages 1200 are homogenously integrated by wafer-wafer polymer-copper hybrid bonding to form a stacked structure 1600. As shown, each package 1200 includes a memory die 1526 embedded within the substrate 302 and encapsulated by an insulating layer 619 (e.g., with a portion of each side in contact with the insulating layer 619). One or more interconnects 1044 are formed through the entire thickness of each package 1200 and are directly bonded to one or more adjacent packages 1200. Although a memory die 1526 is illustrated, any type of semiconductor device or die, such as semiconductor die 626, may be utilized.

[0125]

[0144] Wafer-to-wafer bonding of packages 1200 may be accomplished by planarizing the major surfaces 1005, 1007 of adjacent reconfigured substrates 1000 (before singulation) or packages 1200 (after singulation) and placing the major surfaces 1005, 1007 against each other while applying physical pressure, high temperature, or an electric field to the packages. Upon bonding, one or more interconnects 1044 and / or redistribution connections 1244 of each reconfigured substrate 1000 or package 1200 directly contact one or more interconnects or redistribution connections of an adjacent reconfigured substrate 1000 or package 1200, thus forming a conductive path that may span the thickness or height of the entire DRAM structure 1600. One or more solder bumps 1246 may then be plated or deposited over the interconnects 1044 and / or redistribution connections 1244 for further integration with other systems and / or devices.

[0126]

[0145] Wafer-to-wafer bonding of the packages 1200 allows stacking of semiconductor dies 626 of different sizes without utilizing solder bumps, as both the semiconductor dies 626 and the substrate 302 are made of silicon, providing a CTE-matched stack. Close stacking of the individual packages 1200 further provides a rigid structure that reduces or eliminates warping and / or sagging thereof. In the absence of solder bumps, the copper interconnects 1044 of the individual packages 1200 are also directly coupled to each other, thus reducing or eliminating reliability issues associated with metal-to-metal reactions caused by solder bumps.

[0127]

[0146] 17A-17B show additional exemplary stack structures 1700a and 1700b similar to stack structure 1600. However, unlike stack structure 1600, one or more interconnects 1044 directly contact one or more solder bumps 1246 disposed between major surfaces 1005 and 1007 of adjacent (i.e., stacked above or below) packages 1200. For example, as depicted in stack structure 1700a, four or more solder bumps 1246 are disposed between adjacent packages 1200 to bridge (e.g., bond, couple) the interconnects 1044 of each package 1200 with the interconnects 1044 of the adjacent package 1200. Utilizing solder bumps 1246 allows for stacking of semiconductor dies, packages, and / or reconfigurable substrates having the same or different lateral dimensions. FIG. 17A shows a package 1200 and four stacked memory dies 1526 having substantially the same lateral dimensions, while FIG. 17B shows two stacked packages 1200 with memory dies 1526 having different dimensions.

[0128]

[0147] The use of solder bumps 1246 to bridge interconnects 1044 of adjacent packages 1200 further creates spaces (e.g., distances) between the insulating layers 619. In one embodiment, these spaces are filled with an encapsulant material 1748 to enhance the reliability of the solder bumps 1246. The encapsulant material 1748 can be any suitable type of encapsulant or underfill. In one example, the encapsulant material 1748 includes pre-assembly underfill materials such as no-flow underfill (NUF) materials, non-conductive paste (NCP) materials, and non-conductive film (NCF) materials. In one example, the encapsulant material 1748 includes post-assembly underfill materials such as capillary underfill (CUF) materials and molded underfill (MUF) materials. In one embodiment, the encapsulant material 1748 includes SiO 2 , AlN, Al 2 O 3 , SiC, Si 3 N 4 , Sr 2 Ce 2 Ti 5 O 16 , ZrSiO 4 , CaSiO 3 , BeO, CeO 2 , BN, CaCu 3 Ti 4 O 12 , MgO, TiO 2 , ZnO, etc. In some embodiments, the encapsulant material 1748 has a thickness that corresponds to the diameter of the solder bumps 1246.

[0129]

[0148] In one embodiment, the solder bumps 1246 are formed of a compound between one or more metals, such as tin (Sn) and lead (Pb), silver (Ag), Cu, or any other suitable combination of these metals. For example, the solder bumps 1246 are formed of a solder alloy, such as Sn-Pb, Sn-Ag, Sn-Cu, or any other suitable material or combination thereof. In one embodiment, the solder bumps 1246 include C4 (controlled collapse chip connection) bumps. In one embodiment, the solder bumps 1246 include C2 (chip connection such as Cu pillar with solder cap) bumps. The use of C2 solder bumps allows for smaller contact pad pitch and improved thermal and / or electrical properties for the stack structure 1700. In some embodiments, the solder bumps 1246 have a diameter between about 10 μm and about 150 μm (such as a diameter between about 50 μm and about 100 μm). Solder bumps 1246 may also be formed by any suitable wafer bumping process, including, but not limited to, electrochemical deposition (ECD) and electroplating.

[0130]

[0149] FIG. 18 illustrates a schematic of an efficient method of forming individual stacked memory (e.g., DRAM) structures 1800a-c utilizing solder bumps 1246 instead of a build-up stacking method, similar to stacked structure 1700a. As illustrated, the desired memory die 1526 are embedded within reconfigured substrate 1000 and stacked utilizing solder bumps 1246 to provide coupling between the interconnects and / or redistribution connections of each reconfigured substrate 1000. In the exemplary embodiment illustrated in FIG. 18, the memory die 1526 within each reconfigured substrate 1000 are arranged within a die stack 1026, as previously described with reference to FIGS. 10I-10K and method 900. It is also contemplated that the memory die 1526 may be arranged individually or in a side-by-side configuration with additional memory die 1526 within each cavity of reconfigured substrate 1000. After a desired number of reconfigurable substrates 1000 have been stacked with solder bumps 1246, individual stacked DRAM structures 1800a-c are singulated therefrom, thus enabling batch memory stacking with solder bumps 1246.

[0131]

[0150] The above stacked structures and methods generally include embedded semiconductor dies and devices having substantially the same vertical orientation, with their active surfaces facing the same direction or side of the stacked structure. However, it is further contemplated that semiconductor dies and other devices may be embedded within the above structures having different (e.g., opposite) orientations. FIG. 19 illustrates a flow diagram of a representative method 1900 of forming an exemplary stacked 3D structure 2000 in which embedded semiconductor dies or other devices have different vertical orientations between different layers (e.g., levels). FIG. 20A-20F generally illustrates cross-sectional views of stacked 3D structure 2000 at different stages of method 1900. Thus, FIG. 19 and FIG. 20A-20F are described herein together for clarity. Similar to method 1300, the method illustrated with reference to FIG. 19 and FIG. 20A-20F may also be described as "build-up stacking".

[0132]

[0151] Generally, method 1900 begins at step 1902 and FIG. 20A where a base layer 2010 is formed on a desired surface of reconfigured substrate 1000a to be integrated with another layer of the device. Reconfigured substrate 1000a is formed from silicon substrate 302a and may include all of the features described above, including a structural frame having cavities 305a and vias 303a patterned therein. Base layer 2010 is substantially similar to base layer 1410 and may be formed of the same materials and by the same methods as described above with reference to FIGS. 13 and 14A-14D.

[0133]

[0152] As shown in FIG. 20A, a base layer 2010 is formed on major surface 1007 having a single redistribution layer 1258a thereon. Although shown as having a single redistribution layer 1258a, reconfigured substrate 1000a may have more or less than one redistribution layer formed on any desired surface thereof. Generally, base layer 2010 is formed on a surface of reconfigured substrate 1000a that corresponds to the side facing (e.g., oriented toward) active surface 628a of semiconductor die 626a. In this example, active surface 628a is oriented toward side surface 677 of substrate 302a.

[0134]

[0153] In step 1904 and FIG. 20B, the structured substrate 302b is aligned and placed on the base layer 2010 formed on the reconfigured substrate 1000a. Generally, the structured substrate 302b has substantially the same dimensions as the substrate 302a of the reconfigured substrate 1000a. As described with reference to the method 1300, the second structured substrate 302b may include any desired features patterned therein, including vias 303b and cavities 305b. In some embodiments, the substrate 302b further includes an oxide layer 314 or a metal clad layer 315. During placement, the substrate 302b is aligned with the reconfigured substrate 1000a such that the vias 303b formed in the substrate 302b are aligned with the contacts of the redistribution connections 1244a or the interconnects 1044a.

[0135]

[0154] In step 1906, one or more singulated packages 1200, each having one or more semiconductor dies 626b, are placed in the cavity 305b and then stacked. As shown in FIG. 20C, the singulated packages 1200 are placed in the cavity 305b with the active surfaces 628b of the semiconductor dies 626b facing the base layer 2010 and thus oriented opposite to the orientation of the active surfaces 628a. As previously mentioned, the cavity 305b may have any desired lateral dimensions and geometry to allow for placement of packages 1200 having different types of semiconductor devices and / or dies therein. Thus, the semiconductor dies 626b may be of the same type or different types as each other and / or the semiconductor dies 626a embedded in the reconstituted substrate 1000a. It is further contemplated that in certain embodiments, intermediate die assembly 602 may be placed within cavity 305b in place of, or in addition to, singulated package 1200.

[0136]

[0155] Once the package 1200 is laminated within the substrate 302b, an insulating layer 2019 is formed over the package 1200 and substrate 302b in step 1908 and FIG. 20D. The insulating layer 2019 is substantially similar to the insulating layer 619 and may be formed of the same materials and by the same methods as described above. Thus, forming the insulating layer 2019 over the substrate 302b results in the package 1200 being embedded within the substrate 302b, as well as filling any unoccupied cavities 305b and vias 303b of the substrate 302b with an insulating dielectric material.

[0137]

[0156] In steps 1910-1912 and Figures 20E-20F, one or more interconnects 1044c are formed through the dielectric filled vias 303b to connect with the interconnects 1044a or redistribution connections 1244a of the reconfigured substrate 1000a. In addition, new redistribution connections 1244c may be formed in the insulating layer 2019 to reroute the interconnects 1044b of the package 1200. Prior to metallization, one or more through-assembly vias 603 and / or redistribution vias 1203 are laser drilled through the dielectric material of the insulating layer 2019, the package 1200, and / or the base layer 2010, similar to the process described above. Drilling the through-assembly vias 603 and / or redistribution vias 1203 exposes the contacts (e.g., top surfaces) of the interconnects 1044a, redistribution connections 1244a, and / or interconnects 1044b, allowing the interconnects 1044b and / or redistribution connections 1244c to be formed in direct contact. Thus, after exposing the underlying conductive features by laser drilling, the interconnects 1044c are formed (e.g., by growing or plating a conductive material as described in the above embodiment) directly above and in contact with the redistribution connections 1244a and interconnects 1044a, thereby eliminating the need to utilize intermediate electrical coupling structures between the reconfiguration substrate 1000a and the package 1200 integrated above, such as solder bumps or contact pads. Once step 1912 is completed, one or more additional redistribution layers may be formed and / or stacked devices may be formed above the desired surface of the stacked structure 2000.

[0138]

[0157] The stacked structures 1400, 1500a-d, 1600, 1700a-b, 1800a-c, and 1900 offer several advantages over conventional stacked structures. Such advantages include thin form factors and high die-to-package volume ratios, which allow for greater I / O scaling to meet the ever-increasing bandwidth and power efficiency demands of artificial intelligence (AI) and high performance computing (HPC). The utilization of a structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability of three-dimensional integrated circuit (3D IC) architectures. Additionally, the fabrication methods for assembly through-vias and via-in-via structures described herein provide high performance and flexibility for 3D integration at relatively low manufacturing costs compared to conventional TSV technology.

[0139]

[0158] In summary, the embodiments described herein advantageously provide improved methods of reconstituted substrate formation and wafer-to-wafer stacking for the fabrication of highly integrated semiconductor devices. By utilizing the above-described methods, high aspect ratio features are formed on glass and / or silicon substrates, thus enabling the economical formation of thinner and narrower reconstituted substrates for 2D and 3D integration. The thin and small form factor reconstituted substrates and reconstituted substrate stacks described herein provide the advantages of not only high I / O density and improved bandwidth and power, but also more economical manufacturing with double-sided metallization and high production yields by eliminating single die flip-chip attachment, wire bonding, and overmolding steps that are prone to feature damage in the mass production of integrated semiconductor devices.

[0140]

[0159] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which is determined by the following claims.

Claims

1. 1. A method for forming a 3D integrated semiconductor device, comprising: Positioning a first semiconductor die within at least one cavity formed in a first substrate; disposing a first flowable material over a first surface and a second surface of the first substrate, the first flowable material filling voids formed between a surface of the semiconductor die and a surface of at least one cavity in the first substrate, the first flowable material being further disposed on a surface of at least one via formed through the first substrate; forming a first conductive layer in the at least one via through the first substrate, the first flowable material being disposed between the first conductive layer and a surface of the at least one via through the first substrate; disposing a second flowable material over a surface of the first flowable material, the second flowable material merging with the first flowable material; positioning a second substrate over the second flowable material, the second substrate having at least one cavity and at least one via formed therein; Positioning a second semiconductor die within the at least one cavity formed in the second substrate; disposing a third flowable material over the exposed surface of the second substrate, the third flowable material filling voids formed between a surface of the second semiconductor die and a surface of the at least one cavity in the second substrate, the third flowable material integrating with the second flowable material; forming a second conductive layer through the second substrate and in the at least one via, the third flowable material being disposed through the second substrate and between the conductive layer and the surface of the at least one via; A method comprising:

2. The method of claim 1 , wherein the first substrate is a silicon-containing substrate having a thickness between about 60 μm and about 160 μm.

3. The method of claim 1 , wherein the at least one cavity in the first substrate has a lateral dimension between about 3 mm and about 50 mm.

4. The method of claim 3 , wherein the lateral dimension of the at least one cavity is less than about 150 μm greater than a lateral dimension of the semiconductor die.

5. The method of claim 1 , wherein the at least one via in the first substrate has a diameter between about 50 μm and about 200 μm.

6. forming an oxide layer over the first substrate; The method of claim 1 further comprising:

7. The method of claim 1 , wherein the first flowable material has a thickness between about 5 μm and about 50 μm.

8. The method of claim 1 , wherein the first flowable material comprises ceramic particles ranging in size between about 200 nm and about 800 nm.

9. forming the first conductive layer in the at least one via; depositing an adhesion layer and a seed layer on the surface of the at least one via, the adhesion layer and the seed layer being disposed between the first conductive layer and the first flowable material. The method of claim 1 further comprising:

10. The method of claim 9 , wherein the adhesion layer comprises molybdenum and the seed layer comprises copper.

11. 1. A method for forming a 3D integrated semiconductor device, comprising: Positioning a substrate over a surface of a first semiconductor device, the substrate having at least one cavity and at least one via formed therein; Positioning a semiconductor die within the at least one cavity formed in the substrate; disposing a flowable material over the exposed surface of the substrate and a surface of the at least one via, the flowable material filling a void formed between a surface of the semiconductor die and a surface of the at least one cavity in the substrate and integrating the substrate with the first semiconductor device; forming an opening through the flowable material disposed in the at least one via, the flowable material being disposed between a surface defining the formed opening and a surface of the at least one via; depositing a conductive layer over the surface of the formed opening; A method comprising:

12. The method of claim 11 , wherein the at least one cavity and the at least one via are patterned in the substrate via laser ablation.

13. The method of claim 12 , wherein the opening is formed by laser ablation.

14. The method of claim 13 , wherein the opening has a diameter of less than about 50 μm.

15. forming an oxide layer over said substrate; The method of claim 11 further comprising:

16. The method of claim 11 , wherein the flowable material comprises ceramic particles ranging in size between about 200 nm and about 800 nm.

17. depositing the conductive layer over the surface of the formed opening; depositing an adhesion layer and a seed layer over the surface of the formed opening, the adhesion layer and the seed layer being disposed between the conductive layer and the flowable material; The method of claim 11 further comprising:

18. The method of claim 17 , wherein the adhesion layer comprises molybdenum and the seed layer comprises copper.

19. forming a redistribution layer over the flowable material, the redistribution layer having one or more conductive interconnects for rerouting contacts of the conductive layer to desired locations on an exposed surface of the redistribution layer; The method of claim 11 further comprising:

20. 1. A method for forming a 3D integrated semiconductor device, comprising: positioning a substrate over a first semiconductor device, the substrate having at least one cavity and at least one via formed therein, the at least one via being aligned with a first conductive layer of the first semiconductor device; Positioning a semiconductor die within the at least one cavity formed in the substrate; disposing a flowable material over a first surface of the substrate and a surface of the at least one via, the flowable material filling a void formed between a surface of the semiconductor die and a surface of the at least one cavity in the substrate and integrating the substrate with the first semiconductor device, the flowable material comprising an epoxy resin material including ceramic particles ranging in size between about 200 nm and about 800 nm; forming an opening through the flowable material disposed within the at least one via, the flowable material being disposed between a surface defining the formed opening and a surface of the at least one via, the opening having a diameter smaller than a diameter of the at least one via; depositing a conductive layer over the surface of the formed opening; A method comprising:

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