Radio receiving device

Abstract

To provide a radio receiving device capable of correcting a residual frequency error and a phase error while suppressing a constellation deadlock.SOLUTION: A first APC 88 of a radio communication device compares a first correction value obtained from a pilot signal in a threshold comparison unit 883 with a second correction value obtained from a data signal by a second APC, and selects a correction value to be used for correcting a residual frequency error and a phase error of a received signal.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a radio receiving device that corrects residual frequency error and phase error that occur in a received signal. [Background technology]

[0002] In digital communication, one method for improving the efficiency of frequency band utilization and increasing the speed of data communication is to multi-value digital modulation and demodulation using a modulation method that uses phase information to identify data, such as quadrature amplitude modulation (QAM) and phase shift keying (PSK). In a wireless communication system using such a modulation method, a frequency error occurs in a local signal used for frequency shifting between a transmitter and a receiver, and a local frequency error and a phase error are added to a received signal. The local frequency error is corrected by AFC (Automatic Frequency Control), but a residual frequency error often occurs due to an estimation error at that time. Therefore, in the technology described in Patent Document 1, the residual frequency error and phase error are corrected by APC (Automatic Phase Control).

[0003] A satellite communications system using the DVB-S2 standard, known as the transmission path standard for satellite broadcasting, assumes communications under low CNR (Career-to-Noise Ratio) conditions and employs a first APC that uses a known signal contained in the pilot signal of the communications data to correct residual frequency error and phase error, and a second APC that uses the pilot signal and data portion to correct residual frequency error and phase error. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5730861 Summary of the Invention [Problem to be solved by the invention]

[0005] However, under low CNR conditions, the estimation error in the first APC becomes large, which causes a problem of degradation of the equivalent CNR.On the other hand, when only the second APC is used under low CNR conditions, a problem of deadlock (a phenomenon in which signal points converge at an incorrect phase) occurs in the multi-level modulation constellation.

[0006] SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, an object of the present invention is to provide a radio receiving apparatus capable of correcting the residual frequency error and phase error while suppressing the constellation deadlock. [Means for solving the problem]

[0007] In order to solve the above problem, the invention described in claim 1 is a wireless receiving device comprising: a receiving means for receiving a data frame in which a known pilot signal is inserted at predetermined intervals into a phase-modulated data signal, and outputting a received signal; a first phase control means for correcting a residual frequency error and a phase error occurring in the demodulated received signal using a first correction value obtained from the pilot signal; and a second phase control means for correcting the residual frequency error and the phase error using a second correction value obtained from the data signal after the correction process by the first phase control means, wherein the first phase control means compares the first correction value with the second correction value obtained in the immediately preceding correction process, and corrects the residual frequency error and the phase error using the first correction value or the second correction value depending on the comparison result.

[0008] The invention described in claim 2 is characterized in that, in the wireless receiving device described in claim 1, the first phase control means compares an absolute value of a value obtained by subtracting the first correction value from the second correction value with half the phase interval of a signal point of the demodulated received signal, and uses the first correction value if the absolute value of the value obtained by subtracting the first correction value from the second correction value is greater than half the phase interval of the signal point, and uses the second correction value if the absolute value of the value obtained by subtracting the first correction value from the second correction value is equal to or smaller than half the phase interval of the signal point. Effect of the Invention

[0009] According to the invention described in claim 1, since the first phase control means uses the first correction value or the second correction value, it is possible to suppress the deterioration of the equivalent CNR under low CNR conditions and to improve the resistance to abrupt phase fluctuations. Moreover, since only the second phase control means is not used, it is possible to suppress the occurrence of a deadlock state of the constellation. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram showing a schematic configuration of a wireless communication system according to an embodiment of the present invention; [Diagram 2] 2 is a functional block diagram showing a schematic configuration of a transmission unit of the wireless communication device shown in FIG. [Diagram 3] 2 is a functional block diagram showing a schematic configuration of a receiving section of the wireless communication device shown in FIG. [Figure 4] 3 is a diagram showing a frame structure of a data frame transmitted from a transmitting unit shown in FIG. 2. [Diagram 5] FIG. 2 is a diagram showing a constellation of signal points of a received signal. [Figure 6] FIG. 4 is a functional block diagram showing a schematic configuration of a first APC shown in FIG. [Figure 7] FIG. 4 is a functional block diagram showing a schematic configuration of a second APC shown in FIG. [Figure 8]FIG. 11 is a schematic diagram showing a state in which a first correction value and a second correction value are selectively used in a first APC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention will be described below based on the embodiments shown in the drawings. Note that, in the following, only the characteristic configuration of the present invention will be described, and a description of the same mechanism as the conventional one for performing wireless communication will be omitted.

[0012] 1 is a diagram showing a schematic configuration of a wireless communication system 1 using a wireless communication device (wireless receiving device) 2 according to an embodiment of the present invention. A wireless communication device 2 and an antenna 3 are arranged in each of wireless communication transmitting and receiving stations constituting the wireless communication system 1. The wireless communication devices 2 are connected to each other by a wireless line 4 via the antenna 3. Note that a communication satellite or the like may be used as a relay station in the wireless line 4.

[0013] First, in this embodiment, a schematic configuration of a wireless communication device 2 corresponding to a wireless receiving device according to the present invention will be described.

[0014] The wireless communication device 2 includes an interface unit 5, a transmitter 6, a splitter 7, and a receiver 8 (see the lower part of FIG. 1).

[0015] Here, the wireless communication device 2 is a device that is equipped with a transmission mechanism and a reception mechanism and transmits and receives data. In the following description, the wireless communication device 2 when performing processing related to transmission using the transmission mechanism is referred to as the "transmitting side," and the wireless communication device 2 when performing processing related to reception using the reception mechanism is referred to as the "receiving side."

[0016] The interface unit 5 mainly includes a data circuit-terminating device 51 (including devices called data communication devices and data circuit devices). The interface unit 5 receives transmission data to be transmitted, and outputs the transmission data to the transmission unit 6 via the data circuit-terminating device 51.

[0017] The transmitter 6 receives the transmission data output from the interface 5, generates a data frame by combining a data signal obtained by mapping the transmission data with a pilot signal including information such as the length of the data signal and the modulation method, and further superimposes a carrier signal of a predetermined frequency on the data frame to perform digital modulation. Note that the modulation method used in the wireless communication system 1 is not limited to a specific method, but for example, 16APSK (Amplitude and phase-shift keying) is used.

[0018] The transmitter 6 converts the digitally modulated data frame into an analog signal, converts the frequency of the signal into a high-frequency signal higher than a predetermined frequency, and outputs the signal as a transmission signal after amplifying it with a power amplifier. The transmission signal is guided from the transmitter 6 to the antenna 3 via the splitter 7, and is transmitted as a radio wave from the antenna 3 to the antenna 3 of the other wireless communication device 2 (in other words, the receiving side in this communication) via the wireless line 4.

[0019] In addition, when a transmission signal is transmitted as radio waves from the antenna 3 of the other wireless communication device 2 (in other words, the transmitting side in this communication) to the antenna 3 of the wireless communication device 2 (in other words, the receiving side in this communication) via the wireless line 4, the antenna 3 converts the received radio waves into an electrical signal (received signal) and outputs it.

[0020] The received signal output from the antenna 3 is guided to the receiving unit 8 via the branching filter 7. The receiving unit 8 receives the received signal, passes it through a channel filter that passes only signals in a predetermined frequency band, and converts it into a signal with a frequency lower than the high frequency. The receiving unit 8 further converts the frequency-converted received signal into a digital signal and outputs it.

[0021] The receiver 8 performs quadrature detection processing (demodulation) on the digital received signal to generate an in-phase component (Ich) baseband signal and a quadrature component (Qch) baseband signal, the phases of which are orthogonal to each other. In the following explanation, the in-phase component and the quadrature component will not be particularly distinguished from each other and will be explained as being common to both, except when it is necessary to focus on the in-phase component and the quadrature component separately, and in the drawings, the in-phase component signal and the quadrature component signal are represented by a single signal line.

[0022] The receiving unit 8 performs frequency offset correction, clock error correction, phase correction, etc. on the received data frame. Then, the receiving unit 8 separates the pilot signal from the data frame that has been subjected to various corrections, performs demapping processing on the data signal to generate transmission data, and outputs it to the interface unit 5.

[0023] 2 is a functional block diagram showing a schematic configuration of the transmission unit 6. The transmission unit 6 includes a FIFO memory 61, a mapping unit 62, a pilot signal generation unit 63, a combining unit 64, a transmission ROF 65, a quadrature modulation unit 66, a DAC (Digital Analog Converter) 67, a mixer 68, a local oscillator 69, and a power amplifier 610.

[0024] The FIFO memory 61 is a memory that temporarily stores the transmission data output from the interface unit 5 and outputs it to the mapping unit 62, and transfers the transmission data to the mapping unit 62 on a so-called first-in first-out basis.

[0025] The mapping unit 62 performs mapping processing on the binary data string of the transmission data so as to obtain a predetermined signal point arrangement, generates a data signal consisting of a symbol string, and outputs the generated signal to the combining unit 64. The pilot signal generating unit 63 generates a pilot signal including a known signal such as an alternating signal used to correct a clock error, the length of the data signal, the modulation method, and the like, and outputs the generated signal to the combining unit 64.

[0026] The combining unit 64 inserts and combines pilot signals (first pilot, second pilot, etc.) input from the pilot signal generating unit 63 into the data signals input from the mapping unit 62 at predetermined intervals to generate a data frame DF (see FIG. 4 ) and outputs it to the transmitting ROF 65. The transmitting ROF 65 has a roll-off filter function and performs band limiting processing on the data frame DF input from the combining unit 64 and outputs it to the orthogonal modulation unit 66.

[0027] The quadrature modulation unit 66 superimposes a carrier signal of a predetermined frequency on the data frame DF input from the transmission ROF 65, digitally modulates it, and outputs it to the DAC 67. Note that the modulation method used in the quadrature modulation unit 66 is not limited to a specific method, but for example, quadrature amplitude modulation is used.

[0028] The DAC 67 converts the data frame DF input from the quadrature modulation unit 66 into an analog transmission signal and outputs it to the mixer 68. The local oscillator 69 generates a local oscillation signal having a predetermined fixed frequency and outputs the generated local oscillation signal to the mixer 68. The mixer 68 mixes the local oscillation signal with the transmission signal input from the DAC 67 to convert it into a signal with a higher frequency than the predetermined frequency.

[0029] The power amplifier 610 amplifies the transmission signal frequency-converted by the mixer 68 and outputs it to the antenna 3. The antenna 3 transmits the transmission signal amplified by the power amplifier 610 as a radio wave to the antenna 3 of the other wireless communication device 2 (in other words, the receiving side in this communication). Although not shown, a splitter 7 is connected between the power amplifier 610 and the antenna 3.

[0030] 3 is a functional block diagram showing a schematic configuration of the receiving unit 8. The receiving unit 8 includes a channel filter 81, a mixer 82, a local oscillator 83, an ADC (Analog Digital Converter) 84, a quadrature detection unit 85, an AFC (Automatic frequency control) 86, a receiving ROF 87, a symbol recovery unit 810, a first APC (Automatic Phase Control) 88, a pilot demodulation unit 811, a second APC 89, a separation unit 812, a demapping unit 813, a frame detection unit 814, and a timing control unit 815.

[0031] The antenna 3 converts the received radio waves into an electric signal (received signal) and outputs it to the channel filter 81. The splitter 7 is connected between the antenna 3 and the channel filter 81. The channel filter 81 passes a predetermined frequency band of the received signal input from the antenna 3 and outputs it to the mixer 82. The local oscillator 83 generates a local oscillation signal having a predetermined fixed frequency and outputs the generated local oscillation signal to the mixer 82. The mixer 82 mixes the local oscillation signal with the received signal input from the channel filter 81 to convert it into a signal with a frequency lower than the predetermined frequency, and outputs it to the ADC 84.

[0032] The ADC 84 converts the received signal input from the mixer 82 into a digital signal. The quadrature detection unit 85 performs quadrature detection processing on the received signal to generate an in-phase component (Ich) baseband signal and a quadrature component (Qch) baseband signal whose phases are orthogonal to each other.

[0033] 5(A) is a diagram showing a constellation on an IQ plane (a coordinate plane with Ich on the horizontal axis and Qch on the vertical axis) of the 16APSK baseband signal generated by the quadrature detection unit 85. The 16APSK baseband signal has 16 signal points (symbols) arranged on double circular rings centered on the intersection of Ich and Qch, and the interval between the signal points on the outer ring is the phase interval between the signal points.

[0034] The AFC 86 performs frequency offset correction on the data frame DF of the baseband signal input from the quadrature detection unit 85 and outputs the result to the reception ROF 87. The reception ROF 87 has a roll-off filter function and performs band limiting processing on the baseband signal input from the AFC 86 and outputs the result to the symbol recovery unit 810. The symbol recovery unit 810 corrects clock errors using an alternating signal included in the data frame DF of the baseband signal input from the reception ROF 87 and outputs the result to a first APC (first phase control means) 88.

[0035] The baseband signal input from the symbol recovery unit 810 to the first APC 88 contains a phase error and a residual frequency error that occurs when frequency offset correction is performed by the AFC 86. The first APC 88 corrects the residual frequency error and phase error in the data frame DF of the baseband signal input from the symbol recovery unit 810 by using a first correction value based on a known signal of the pilot signal, and outputs the corrected result to the pilot demodulation unit 811.

[0036] The pilot demodulation unit 811 extracts information relating to the length, modulation method, etc. of the data signal from the pilot signal, and outputs this information together with the data frame DF to a second APC (second phase control means) 89. The second APC 89 generates a second correction value based on the information relating to the length, modulation method, etc. of the data signal input from the pilot demodulation unit 811, and corrects the residual frequency error and phase error of the data frame DF of the baseband signal using this second correction value. The second APC 89 outputs the corrected baseband signal to the separation unit 812.

[0037] The separator 812 separates the data signal from the data frame DF and outputs the data signal to the demapping unit 813. The demapping unit 813 performs demapping processing (decoding processing) on ​​the signal (each of the in-phase component and the quadrature component) consisting of the symbol sequence data input from the separator 812, converts the symbol sequence data into transmission data of a binary data sequence, and outputs the transmission data to the interface unit 5.

[0038] The frame detection unit 814 detects a data frame DF from the baseband signal input from the symbol recovery unit 810, and when the data frame DF is detected, outputs a detection flag to the timing control unit 815. The timing control unit 815, to which the detection flag is input, outputs an enable signal to each module for causing the module to process the data frame DF.

[0039] In the conventional receiver 8, under low CNR conditions, there is a problem that the estimation error in the first APC 88 becomes large, and the equivalent CNR deteriorates. On the other hand, when only the second APC 89 is used under low CNR conditions, there is a problem that a deadlock (a phenomenon in which a signal point converges at an incorrect phase) occurs in the multi-level modulation constellation. Figure 5(B) shows a deadlock state in which the signal point on the inner ring rotates around the intersection of Ich and Qch and converges at a position close to the outer signal point.

[0040] In this embodiment, in order to suppress such a constellation deadlock, the first APC 88 compares the first correction value with the second correction value obtained in the immediately preceding correction process, and corrects the residual frequency error and phase error using the first correction value or the second correction value depending on the comparison result.

[0041] 6 is a functional block diagram showing a schematic configuration of a first APC 88 according to this embodiment. The first APC 88 includes a phase error calculation unit 881, an unwrapping unit 882, a threshold comparison unit 883, a frequency fluctuation estimation unit 884, an averaging unit 885, a frequency correction unit 886, a phase / IQ conversion unit 887, and a phase correction unit 888.

[0042] The phase error calculation unit 881 calculates a phase error of the data frame DF input from the symbol recovery unit 810, and outputs a phase error signal to an unwrapping unit 882. The unwrapping unit 882 reconstructs the phase of the phase error signal input from the phase error calculation unit 881, and outputs the reconstructed phase data to a threshold comparison unit 883.

[0043] The threshold comparator 883 calculates a first correction value based on the phase data input from the phase error calculator 881 and the known signal of the pilot signal of the data frame DF. The threshold comparator 883 also receives a second correction value calculated by the second APC 89 in the immediately preceding correction process. The threshold comparator 883 compares the second correction value input from the second APC 89 with the first correction value, and determines the correction value to be used for correction.

[0044] Specifically, the threshold comparison unit 883 compares the first correction value and the second correction value based on the following equations (1) and (2) to determine the correction value to be used for correction, and outputs the determined correction value to the frequency correction unit 886. |Second correction value - First correction value|>Phase interval of signal points / 2 = First correction value (1) |Second correction value-First correction value| ≦ Phase interval of signal points / 2 = Second correction value (2)

[0045] The first correction value generated by the first APC 88 is generated based on a known signal, and therefore can correct a phase error of 0 to 360 degrees. On the other hand, the second correction value generated by the second APC 89 is generated based on a data signal after demapping (also called hard decision), and therefore can correct a phase error within a range where no hard decision error occurs, that is, within a range of 1 / 2 the phase interval of the signal points, as shown in Fig. 5(A).

[0046] The frequency fluctuation estimation unit 884 estimates a local frequency fluctuation value based on the phase-reconstructed data frame DF input from the phase error calculation unit 881, and outputs the estimated value to an averaging unit 885. The averaging unit 885 averages the estimated values ​​of the local frequency fluctuation value input from the frequency fluctuation estimation unit 884, and outputs the averaged value to a frequency correction unit 886.

[0047] The frequency correction unit 886 corrects the frequency of the correction value determined by the threshold comparison unit 883 based on the correction value determined by the threshold comparison unit 883 and the average value of the estimated values ​​of the local frequency fluctuation values ​​input from the averaging unit 885, and outputs the result to the phase / IQ conversion unit 887.

[0048] The phase / IQ conversion unit 887 converts the phase of the correction value input from the frequency correction unit 886 into Ich and Qch signals and outputs them to the phase correction unit 888. The phase correction unit 888 multiplies the Ich and Qch signals of the correction value input from the symbol recovery unit 810 by the data frame DF to correct the phase error.

[0049] 7 is a functional block diagram showing a schematic configuration of a second APC 89 according to this embodiment. The second APC 89 includes a phase correction unit 891, a corrected signal output unit 892, a demapping unit 893, a phase error calculation unit 894, a loop filter 895, a second correction value output unit 896, and a phase / IQ conversion unit 897.

[0050] The phase correction unit 891 corrects the phase error of the data frame DF by multiplying the data frame DF input from the pilot demodulation unit 811 by the Ich and Qch signals of the second correction value input from the phase / IQ conversion unit 897. The corrected data frame DF is output from the corrected signal output unit 892 to the separation unit 812, and is also output to the demapping unit 893 and the phase error calculation unit 894.

[0051] The demapping unit 893 performs demapping processing (decoding processing) on ​​the data frame DF input from the phase correction unit 891, converts the symbol string data into transmission data of a binary data string, and outputs it to the phase error calculation unit 894. The phase error calculation unit 894 calculates a phase error based on the data frame DF input from the phase correction unit 891 and the transmission data input from the demapping unit 893, and outputs a phase error signal to the loop filter 895.

[0052] The loop filter 895 generates a second correction value by removing a predetermined frequency component from the phase error signal input from the phase error calculation unit 894 in accordance with a predetermined loop bandwidth. The second correction value output unit 896 outputs the generated second correction value to the first APC 88 and also to a phase / IQ conversion unit 897. The phase / IQ conversion unit 897 converts the phase of the second correction value input from the loop filter 895 into Ich and Qch signals and outputs them to the phase correction unit 891.

[0053] 8 is a schematic diagram showing a state in which a first correction value generated by a threshold comparator 883 of the first APC 88 and a second correction value generated by a second APC 89 are compared and selected by the first APC 88. In this way, according to the wireless communication device 2 of the present embodiment, the residual frequency error and phase error can be corrected by effectively using the first correction value and the second correction value.

[0054] As described above, according to the wireless communication device 2 of the present embodiment, since the first correction value or the second correction value is used in the first APC 88, it is possible to suppress the deterioration of the equivalent CNR under low CNR conditions and to improve the resistance to abrupt phase fluctuations. Moreover, since only the second APC 89 is not used, it is possible to suppress the occurrence of a deadlock state of the constellation.

[0055] Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above embodiment, and even if there are design changes and the like within the scope of the gist of the present invention, they are included in the present invention. [Explanation of symbols]

[0056] 1. Wireless communication systems 2. Wireless communication devices 3 Antenna (receiving part) 5. Transmitter 8 Receiving section 88 First APC (first phase control means) 89 Second APC (second phase control means) DF Data Frame

Claims

1. a receiving means for receiving a data frame in which a known pilot signal is inserted at predetermined intervals into a phase-modulated data signal, and outputting a received signal; a first phase control means for correcting a residual frequency error and a phase error occurring in the demodulated received signal by using a first correction value obtained from the pilot signal; a second phase control means for correcting the residual frequency error and the phase error by using a second correction value obtained from the data signal after the correction process by the first phase control means; the first phase control means compares the first correction value with the second correction value obtained in a previous correction process, and corrects the residual frequency error and the phase error using the first correction value or the second correction value depending on a comparison result. A radio receiving device comprising:

2. The first phase control means comparing an absolute value of a value obtained by subtracting the first correction value from the second correction value with a value that is half the phase interval between signal points of the demodulated received signal; When an absolute value of a value obtained by subtracting the first correction value from the second correction value is greater than half the value of the phase interval of the signal point, the first correction value is used; When an absolute value of a value obtained by subtracting the first correction value from the second correction value is equal to or smaller than half the phase interval of the signal point, the second correction value is used.

2. The wireless receiving device according to claim 1,

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