Display device

Abstract

To provide a novel display device capable of suppressing deterioration in display quality due to an increase in resistance of a wiring line for supplying an input signal to a scanning signal line driving circuit.SOLUTION: A GOA type liquid crystal display device 100 includes a plurality of pixels arrayed in a matrix, a plurality of gate bus lines, a plurality of source bus lines, a gate driving circuit 120, a source driving circuit 140, and input signal lines 150 for supplying an input signal to the gate driving circuit 120. The gate driving circuit 120 has a shift register circuit SR, wherein each stage of the shift register circuit SR has an input terminal connected to the input signal line 150 via a branch line 152 and an output terminal connected to the gate bus line, and when a portion between adjacent branch lines is defined as a unit portion UR, the input signal lines have at least one first unit portion UR1 each having a resistance value smaller than that of the unit portion adjacent to a downstream side in an input direction.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] The present invention relates to an active matrix display device, and more particularly to a display device in which a scanning signal line driving circuit for supplying scanning signals for selecting pixel rows is integrally provided on an active matrix substrate of a display panel. The present invention relates to, for example, a liquid crystal display device in which a gate driving circuit is integrally provided on an active matrix substrate of a liquid crystal display panel (so-called gate-on-array (GOA) type). [Background technology]

[0002] As liquid crystal display devices become larger and / or have higher resolution, the degradation of display quality caused by the increase in wiring resistance in the gate drive circuit of GOA type liquid crystal display devices has become a problem. For example, the voltage level of the gate signal and / or the waveform of the gate-on pulse change due to the wiring resistance, which is visually recognized as uneven brightness of the display.

[0003] Therefore, for example, the liquid crystal display device described in Patent Document 1 is provided with a drive circuit capable of uniforming the waveform of a drive signal. This drive circuit includes a plurality of shift registers each having an input terminal, an output terminal, and a switching element connected between the input terminal and the output terminal, the input terminals of each shift register are connected to a plurality of branch points on an input signal line provided on a display panel, the output terminals of each shift register are connected to a plurality of output signal lines provided on the display panel, and a predetermined drive signal is output from the output terminal based on a predetermined signal input via the input terminal of each shift register, and all or a portion of the plurality of shift registers have different resistance values ​​between the input terminal and the output terminal when the switching element is in an on state depending on the position of the branch point to which the input terminal is connected. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 055769 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a novel display device capable of suppressing a decrease in display quality caused by an increase in resistance of wiring that supplies an input signal to a scanning signal line driving circuit. [Means for solving the problem]

[0006] According to an embodiment of the present invention, there are provided solutions as described in the following items.

[0007] [Item 1] a plurality of pixels arranged in a matrix having a plurality of pixel rows and a plurality of pixel columns; a plurality of scanning signal lines, each of which is associated with one of the plurality of pixel rows; a plurality of display signal lines, each of which is associated with one of the plurality of pixel columns; a scanning signal line driving circuit that supplies scanning signals including a selection pulse for selecting one of the pixel rows to the plurality of scanning signal lines; a display signal line driver circuit for supplying display signals to the plurality of display signal lines; a plurality of input signal lines for supplying input signals to the scanning signal line driving circuit; having the scanning signal line driving circuit has a shift register circuit, The shift register circuit has a plurality of stages, Each of the plurality of stages has an input terminal connected to any one of the plurality of input signal lines via a branch line, and an output terminal connected to any one of the plurality of scanning signal lines, the scanning signal line driving circuit is configured to sequentially apply the selection pulse to the plurality of scanning signal lines along a scanning direction in response to the input signal; the scanning signal line driving circuit and the plurality of input signal lines are formed on the same substrate as the plurality of scanning signal lines; A display device, wherein at least one input signal line of the plurality of input signal lines has a plurality of unit parts, where the space between adjacent branch lines is considered to be a unit part, and the plurality of unit parts have at least one first unit part having a smaller resistance value than an adjacent unit part downstream in an input direction of the input signal.

[0008] [Item 2] The at least one first unit portion includes a plurality of first unit portions, and a first unit portion having a smaller resistance value is located upstream in the input direction, 2. The display device according to item 1, wherein each of the plurality of first unit portions has a portion with a wider line width than an adjacent unit portion downstream.

[0009] [Item 3] A display device as described in item 1 or 2, wherein the at least one first unit portion includes a plurality of first unit portions, and the plurality of unit portions have a plurality of second unit portions having the same resistance value as an adjacent unit portion downstream in the input direction.

[0010] [Item 4] 4. The display device according to any one of items 1 to 3, wherein the at least one first unit portion includes a plurality of first unit portions, each of the plurality of unit portions having a constant line width.

[0011] [Item 5] A display device described in any of items 1 to 4, wherein the at least one first unit portion includes a plurality of first unit portions, and the at least one input signal line has more first unit portions upstream than downstream.

[0012] [Item 6] A display device described in any one of items 1 to 5, wherein the at least one first unit portion includes a plurality of first unit portions, and the line widths of the plurality of first unit portions are narrower toward the downstream in the input direction.

[0013] [Item 7] Each of the plurality of pixels includes a display medium layer, a pair of electrodes arranged to face each other with the display medium layer interposed therebetween, and a TFT having a drain electrode connected to one of the pair of electrodes; the plurality of scanning signal lines are a plurality of gate bus lines, and the plurality of display signal lines are a plurality of source bus lines, a gate electrode of the TFT is connected to a gate bus line associated with a pixel row including a pixel having the TFT, and a source electrode of the TFT is connected to a source bus line associated with a pixel column including a pixel having the TFT, the scanning signal line driving circuit is a gate driving circuit, and the scanning signal is a gate scanning signal including a gate-on pulse for turning on the TFT as the selection pulse, 7. The display device according to any one of items 1 to 6, wherein the display signal line driving circuit is a source driving circuit, and the display signals are source signals.

[0014] [Item 8] 8. The display device according to item 7, wherein the display medium layer is a liquid crystal layer. Effect of the Invention

[0015] According to an embodiment of the present invention, for example, a novel display device is provided that can suppress the degradation of display quality caused by an increase in resistance of wiring that supplies an input signal to a scanning signal line driving circuit. According to an embodiment of the present invention, for example, with a simpler configuration than the liquid crystal display device of Patent Document 1, it is possible to suppress the degradation of display quality caused by an increase in resistance of wiring that supplies an input signal to a gate driving circuit. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a schematic plan view of a liquid crystal display device 100 according to an embodiment of the present invention. [Diagram 2] 2 is a schematic diagram showing a circuit configuration for outputting a gate scanning signal GS. FIG. [Diagram 3]1 is a schematic diagram showing the connection relationship between one input signal line 150 and each stage of a shift register circuit SR. [Figure 4A] 1 is a schematic diagram showing the connection relationship between one input signal line 150 and each stage of a shift register circuit SR in a liquid crystal display device 100. FIG. [Figure 4B] 1 is a schematic diagram showing the connection relationship between three input signal lines 150 and each stage of a shift register circuit SR. [Figure 4C] 1 is a schematic diagram showing the connection relationship between three input signal lines 150 and each stage of a shift register circuit SR. [Figure 5A] FIG. 11 is a schematic diagram showing a pulse waveform of a gate-on pulse GOP in a conventional liquid crystal display device. [Figure 5B] 1 is a schematic diagram showing the pulse waveform of a gate-on pulse GOP in the liquid crystal display device 100. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] A display device according to an embodiment of the present invention includes a plurality of pixels arranged in a matrix having a plurality of pixel rows and a plurality of pixel columns, a plurality of scanning signal lines each associated with one of the plurality of pixel rows, a plurality of display signal lines each associated with one of the plurality of pixel columns, a scanning signal line drive circuit that supplies a scanning signal including a selection pulse for selecting one of the plurality of pixel rows to the plurality of scanning signal lines, a display signal line drive circuit that supplies a display signal to the plurality of display signal lines, and a plurality of input signal lines that supply an input signal to the scanning signal line drive circuit, the scanning signal line drive circuit having a shift register circuit, the shift register circuit having a plurality of stages, Each of the input signal lines has an input terminal connected to one of the plurality of input signal lines via a branch line and an output terminal connected to one of the plurality of scanning signal lines, the scanning signal line driving circuit is configured to sequentially apply selection pulses to the plurality of scanning signal lines along a scanning direction in response to an input signal, the scanning signal line driving circuit and the plurality of input signal lines are formed on the same substrate as the plurality of scanning signal lines, and at least one input signal line of the plurality of input signal lines has a plurality of unit parts, assuming that a space between adjacent branch lines is a unit part, and the plurality of unit parts have at least one first unit part having a smaller resistance value than an adjacent unit part downstream in the input direction of the input signal. Typically, the at least one first unit part includes a plurality of first unit parts, and is arranged such that a first unit part having a smaller resistance value is located further upstream in the input direction.

[0018] In the following, an active matrix display device in which each pixel has a TFT is exemplified. In the active matrix display device of the embodiment, each of the pixels has a display medium layer, a pair of electrodes arranged to face each other through the display medium layer, and a TFT with a drain electrode connected to one of the pair of electrodes, the multiple scanning signal lines are multiple gate bus lines, the multiple display signal lines are multiple source bus lines, the gate electrode of the TFT is connected to the gate bus line associated with the pixel row including the pixel having the TFT, the source electrode of the TFT is connected to the source bus line associated with the pixel column including the pixel having the TFT, the scanning signal line driving circuit is a gate driving circuit, the scanning signal is a gate scanning signal including a gate-on pulse as a selection pulse for turning on the TFT, the display signal line driving circuit is a source driving circuit, and the display signal is a source signal.

[0019] Hereinafter, an active matrix type liquid crystal display device in which a display medium layer is a liquid crystal layer will be described with reference to the drawings. Note that the liquid crystal display device according to the embodiment of the present invention is not limited to the following examples.

[0020] FIG. 1 shows a schematic plan view of a liquid crystal display device 100 according to an embodiment of the present invention.

[0021] The liquid crystal display device 100 has a plurality of pixels P arranged in a matrix having a plurality of pixel rows (m rows) and a plurality of pixel columns (n ​​columns). The liquid crystal display device 100 is an active matrix type liquid crystal display device, and each pixel P has a thin film transistor (TFT) and a liquid crystal capacitance Clc. The pixel P may further have an auxiliary capacitance Cs (not shown) electrically connected in parallel with the liquid crystal capacitance Clc. For simplicity, a description of the auxiliary capacitance Cs is omitted here. The liquid crystal capacitance Clc is composed of, for example, a pixel electrode (not shown) formed on the active matrix substrate 110, and a common electrode (also called a counter electrode, not shown) arranged to face the pixel electrode via a liquid crystal layer (not shown). The common electrode is formed, for example, on a counter substrate 112 arranged to face the active matrix substrate 110.

[0022] The area in which the pixels P are formed is called the active area AA or the display area. The pixel in the kth row and lth column of the pixels arranged in m rows and n columns may be expressed as P(k, l). k, l, m, and n are positive integers that satisfy the relationships 1≦k≦m and 1≦l≦n. For example, in a so-called full high-definition liquid crystal display device, m=1080, n=1920×3 (when a color display pixel is composed of an R pixel, a G pixel, and a B pixel, the "pixel" referred to here is sometimes called a "dot," and a "color display pixel" composed of three "dots" is sometimes called a "pixel.") Each of the pixels has a liquid crystal capacitance including a pixel electrode, and a TFT with a drain electrode connected to the pixel electrode.

[0023] The liquid crystal display device 100 further includes a plurality of gate bus lines GB (m lines), each associated with one of a plurality of pixel rows, and a plurality of source bus lines SB (n lines), each associated with one of a plurality of pixel columns. A gate electrode of the TFT of each pixel is connected to the gate bus line GB associated with the pixel row in which the pixel is included, and a source electrode of the TFT is connected to the source bus line SB associated with the pixel column in which the pixel is included.

[0024] The liquid crystal display device 100 further includes a gate drive circuit 120 that supplies gate scanning signals including gate-on pulses GOP that turn on the TFTs to the multiple gate bus lines GB, a source drive circuit 140 that supplies source signals to the multiple source bus lines SB, and multiple input signal lines 150 (see FIG. 2) that supply input signals to the gate drive circuit 120. The input signal lines that supply input signals to the source drive circuit 140 are omitted here.

[0025] The liquid crystal display device 100 is a GOA type, and the gate driving circuit 120 is formed on an active matrix substrate 110, similar to the pixel electrodes, the TFTs, the plurality of source bus lines SB, and the plurality of gate bus lines GB. As is well known, the active matrix substrate 110 is formed, for example, on a glass substrate by forming a conductive layer (metal layer), a semiconductor layer, and an insulating layer by a known method. The source driving circuit 140 may be mounted on the active matrix substrate 110 as, for example, a source driving IC, or a flexible substrate carrying a source driving IC may be connected to the active matrix substrate 110.

[0026] The gate drive circuit 120 and the source drive circuit 140 are controlled by a control circuit (not shown). The control circuit has a display control circuit and a power supply circuit, which are constituted by a timing controller. The display control circuit supplies necessary control signals to the gate drive circuit 120 and the source drive circuit 140, respectively, and the power supply circuit supplies necessary power supply voltages to the gate drive circuit 120 and the source drive circuit 140, respectively. The gate drive circuit 120 supplies gate scanning signals so that gate-on pulses GOP for turning on the TFTs are sequentially applied to the gate bus lines GB along the scanning direction, and the source drive circuit 140 supplies source signals to the source bus lines SB so that the gradation voltage to be displayed at the pixel is applied to the pixel electrode connected to the TFT turned on by the gate-on pulse. The configuration and operation of the control circuit are well known, so a detailed description will be omitted. The embodiment of the present invention is characterized by a plurality of input signal lines 150 for supplying input signals from the control circuit to the gate drive circuit 120, and other configurations can be appropriately applied to known configurations.

[0027] Next, reference will be made to Fig. 2. Fig. 2 is a schematic diagram showing the configuration of a circuit that outputs a gate scan signal GS.

[0028] The GOA type gate driving circuit 120 is composed of a shift register circuit SR, and the shift register circuit SR has a plurality of stages (sometimes called unit circuits or shift circuits).

[0029] A plurality of input signals are supplied to the gate drive circuit 120 from a control circuit (not shown) via a plurality of input signal lines 150. Here, the input signals are clock signals CLK1, 2, 3, 4 and a reference voltage signal Vss, and the respective input signal lines may be referred to as clock signal lines CLK1, 2, 3, 4 and reference voltage signal line Vss. A clock signal CLK, a reference voltage signal Vss, a Set signal, and a Reset signal are input to each stage of the shift register circuit SR. For the Set signal and the Reset signal, signals generated in other stages are used. A gate scanning signal GS is output from each stage of the shift register circuit SR to a gate bus line GB corresponding to each pixel row. In FIG. 2, the gate signal corresponding to the k-th pixel row is represented as GS(k), and the k-th stage of the shift register circuit SR is represented as SR(k).

[0030] The gate driving circuit 120 is configured to sequentially apply gate-on pulses GOP to the gate bus lines GB along the scanning direction in response to an input signal. The scanning direction is typically a direction from the first pixel row located at the top of the active area AA to the pixel row located at the bottom, as shown in FIG. 2. The side of the input signal line 150 closer to a control circuit (e.g., a timing controller, not shown) is expressed as upstream, and the farther side is expressed as downstream. The input signal flows from upstream to downstream in the input signal line 150. The direction in which the input signal flows through the input signal line 150 is referred to as the input direction of the input signal. Here, a case is illustrated in which the input direction of the input signal coincides with the scanning direction, but the embodiment of the present invention is not limited to this, and also includes a case in which the input direction of the input signal does not coincide with the scanning direction. For example, when an input signal is input from both the upper and lower ends of the active area AA toward the center, the upper end and lower end of the active area AA are upstream (upstream-most, upstream end), and the center of the active area AA is downstream (downstream-most, downstream end).

[0031] Next, reference is made to Fig. 3. Fig. 3 is a schematic diagram showing the connection relationship between one input signal line 150 and each stage of the shift register circuit SR. Here, the connection relationship between the clock signal line CLK1 shown in Fig. 2 and each stage of the shift register circuit SR is shown.

[0032] Each of the multiple stages of the shift register circuit SR has an input terminal (IN) connected to one of the multiple input signal lines 150 via a branch line 152, and an output terminal (Gout) connected to one of the multiple gate bus lines GB. If the space between adjacent branch lines 152 of the input signal line 150 is defined as a unit part UR, the input signal line 150 has multiple unit parts UR.

[0033] A plurality of input signal lines in a conventional GOA type liquid crystal display device are formed of a conductive layer with a constant line width from the upstream to the downstream, and the resistance value per unit length is constant, and each unit part UR has a constant resistance value. Therefore, the input signal is affected by the resistance according to the length of the input signal line before reaching the downstream of the input signal line, and is attenuated and / or delayed. The more upstream the input signal line, the more the input signal path to the many stages of the shift register, so the more upstream the input signal line, the larger the current value. The higher the current value, the larger the voltage drop and Joule heat, so the more upstream the input signal line, the greater the attenuation and / or delay of the input signal. In addition, the heat generated by Joule heat is also large upstream, so the degree of non-uniformity in the temperature distribution of the liquid crystal display device is also large upstream the input signal line. For example, the gate-on pulse output from the gate drive circuit has a pulse waveform that is significantly different between the upstream side and the downstream side, as shown in FIG. 5A. The difference in the pulse waveform of the gate-on pulse affects the display, and for example, when a certain intermediate tone is displayed over the entire display area, the upper side is brighter and the lower side is less bright, resulting in uneven brightness. In addition, because the degree of change in the pulse waveform is greater on the upstream side than on the downstream side, the degree of brightness unevenness is greater (steeper) on the upper side and less noticeable (gentler) on the lower side. In addition, because the characteristics of TFTs are affected by temperature, degradation of display quality caused by uneven temperature distribution is also more likely to become apparent on the upper side of the display area.

[0034] In the liquid crystal display device 100 according to the embodiment of the present invention, the resistance of the input wiring is reduced on the upstream side, thereby suppressing changes in the pulse waveform of the gate-on pulse and / or unevenness in the temperature distribution of the liquid crystal display device, and suppressing deterioration of display quality caused by increased wiring resistance.

[0035] Next, FIG. 4A is a schematic diagram showing the connection relationship between one input signal line 150 and each stage of the shift register circuit SR in the liquid crystal display device 100 according to the embodiment of the present invention, and shows the connection relationship between the clock signal line CLK1 shown in FIG. 2 and each stage of the shift register circuit SR, similar to FIG. 3. The multiple unit parts UR of the input signal line 150 have multiple first unit parts UR1 with a smaller resistance value than the unit part UR adjacent downstream in the input direction, and the first unit part UR1 with a smaller resistance value is located upstream in the input direction. As shown in FIG. 4A, the first unit part UR1 may be provided on the upstream side, and multiple second unit parts UR2 with the same resistance value as the unit part adjacent downstream may be provided on the downstream side.

[0036] Among the multiple unit parts UR, the unit part UR located upstream in the input direction is the first unit part UR1, which has a smaller resistance value as it is located upstream. That is, the resistance value of the first unit part UR1(1) located most upstream is smaller than the resistance value of the first unit part UR1(2) located downstream, and the resistance value of the first unit part UR1(2) is smaller than the resistance value of the first unit part UR(3) located downstream. This relationship may be maintained up to the unit part UR located most downstream. In this case, it is preferable that the difference in resistance value between the unit part UR1 adjacent downstream is larger as it is located upstream. The second unit part UR2(268) in FIG. 4A has the same resistance value as the second unit part UR2(269).

[0037] The difference in resistance value can be adjusted, for example, by changing the line width of the conductive layer forming the input signal line 150, as shown in FIG. 4B. Each of the multiple first unit parts UR1 may have a portion with a line width wider than that of the unit part UR adjacent downstream. For example, it may have a portion with a line width wider than the maximum line width of the unit part adjacent downstream, and may not have a portion with a line width narrower than the maximum line width of the unit part adjacent downstream. In this case, the line width of the input signal line 150 may be gradually narrowed continuously from the most upstream side to the most downstream side. Alternatively, the resistance value may be adjusted by changing the length of the unit part UR. Of course, both the line width and the length may be adjusted.

[0038] 4C, the line width of each unit part UR may be constant and gradually narrowed. By making the line width of each unit part UR constant, the accuracy of the patterning of the conductive layer can be improved more than by gradually narrowing the line width continuously. Also, it is easy to inspect the conductive layer for patterning defects.

[0039] By changing the resistance value of the input signal line 150 in this way, for example, the difference in pulse waveform between the upstream side and the downstream side of the gate-on pulse output from the gate drive circuit is suppressed as shown in Fig. 5B. As can be seen by comparing with Fig. 5A, the change in the waveform is particularly suppressed on the upstream side, and the change in the pulse waveform between adjacent pixel rows (for example, the interval between adjacent waveforms in Fig. 5B) can be made uniform across the entire panel. That is, in the liquid crystal display device 100 according to the embodiment of the present invention, the deterioration of display quality caused by an increase in the resistance value of the input signal line 150 is suppressed.

[0040] In the above description, the clock signal line CLK1 is exemplified as the input signal line 150, but it is preferable that the same is applied to all the clock signal lines CLK1 to 4. Also, instead of the clock signal lines CLK1 to 4, the invention may be applied to the reference voltage signal line Vss, or to the clock signal lines CLK1 to 4 and the reference voltage signal line Vss. Also, the arrangement of the input signal lines 150 is not limited to the example shown in FIG. 2.

[0041] In an active matrix type liquid crystal display device, the timing at which the gate-on pulse GOP is applied and the timing at which the source signal is supplied must match. If the gate-on pulse GOP is delayed, a shift occurs between the timing at which the source signal is supplied. If this timing shift differs depending on the pixel row, it is visually recognized as a deterioration in display quality. As a method for preventing this, a method of intentionally slightly shifting the timing of the gate-on pulse GOP and the timing at which the source signal is supplied is known. However, as described above, if the delay difference between adjacent pixel rows of the gate-on pulse GOP is larger on the upstream side than on the downstream side in the input direction and differs greatly depending on the pixel row, it is difficult to make the shift between the timing of the gate-on pulse GOP and the timing at which the source signal is supplied constant regardless of the pixel row because it requires complex timing adjustment, and the deterioration of the display quality cannot be effectively suppressed. In the liquid crystal display device 100 according to the embodiment of the present invention, the variation in delay of the gate-on pulse GOP can be suppressed and the delay difference between adjacent pixel rows can be made uniform across the entire panel, eliminating the need for complex timing adjustments, and effectively suppressing excessive deviations between the timing at which the gate-on pulse GOP and the source signal are supplied.

[0042] In the above, a GOA type liquid crystal display device is exemplified, but the present invention is not limited to this, and the active matrix type display device according to the embodiment of the present invention may be another display device such as an electrophoretic type display device having an electrophoretic display layer as a display medium layer. Also, the method of selecting pixel rows is not limited to the TFT type, and may be a method using other switching elements. [Industrial Applicability]

[0043] A display device according to an embodiment of the present invention can improve the display quality of a large-sized or high-definition display device. [Explanation of symbols]

[0044] 100: Active matrix liquid crystal display device 110: Active matrix substrate 112: Opposing substrate 120: Gate drive circuit 140: Source driver circuit 150: Input signal line 152: Branch line AA : Active Area Clc: Liquid crystal capacity Cs: Auxiliary capacity GB: Gate bus line GS: Gate scan signal P: Pixel SB: Source bus line SR: Shift register circuit UR: Unit part UR1: First unit part UR2: Second unit part

Claims

1. a plurality of pixels arranged in a matrix having a plurality of pixel rows and a plurality of pixel columns; a plurality of scanning signal lines, each of which is associated with one of the plurality of pixel rows; a plurality of display signal lines, each of which is associated with one of the plurality of pixel columns; a scanning signal line driving circuit that supplies scanning signals including a selection pulse for selecting one of the pixel rows to the plurality of scanning signal lines; a display signal line driver circuit for supplying display signals to the plurality of display signal lines; a plurality of input signal lines for supplying input signals to the scanning signal line driving circuit; having the scanning signal line driving circuit has a shift register circuit, The shift register circuit has a plurality of stages, Each of the plurality of stages has an input terminal connected to any one of the plurality of input signal lines via a branch line, and an output terminal connected to any one of the plurality of scanning signal lines, the scanning signal line driving circuit is configured to sequentially apply the selection pulse to the plurality of scanning signal lines along a scanning direction in response to the input signal; the scanning signal line driving circuit and the plurality of input signal lines are formed on the same substrate as the plurality of scanning signal lines; A display device, wherein at least one input signal line of the plurality of input signal lines has a plurality of unit parts, where the space between adjacent branch lines is considered to be a unit part, and the plurality of unit parts have at least one first unit part having a smaller resistance value than an adjacent unit part downstream in an input direction of the input signal.

2. The at least one first unit portion includes a plurality of first unit portions, and a first unit portion having a smaller resistance value is located upstream in the input direction, The display device according to claim 1 , wherein each of the plurality of first units has a portion having a line width wider than that of an adjacent unit located downstream.

3. The display device according to claim 1 , wherein the at least one first unit portion includes a plurality of first unit portions, and the plurality of unit portions have a plurality of second unit portions having an equal resistance value to an adjacent unit portion downstream in the input direction.

4. The display device according to claim 1 , wherein the at least one first unit portion includes a plurality of first unit portions, each of the plurality of unit portions having a constant line width.

5. The display device according to claim 1 , wherein the at least one first unit portion includes a plurality of first unit portions, and the at least one input signal line has more first unit portions upstream than downstream.

6. The display device according to claim 1 , wherein the at least one first unit portion includes a plurality of first unit portions, and line widths of the plurality of first unit portions narrow toward a downstream side in the input direction.

7. Each of the plurality of pixels includes a display medium layer, a pair of electrodes arranged to face each other with the display medium layer interposed therebetween, and a TFT having a drain electrode connected to one of the pair of electrodes; the plurality of scanning signal lines are a plurality of gate bus lines, and the plurality of display signal lines are a plurality of source bus lines, a gate electrode of the TFT is connected to a gate bus line associated with a pixel row including a pixel having the TFT, and a source electrode of the TFT is connected to a source bus line associated with a pixel column including a pixel having the TFT; the scanning signal line driving circuit is a gate driving circuit, and the scanning signal is a gate scanning signal including a gate-on pulse for turning on the TFT as the selection pulse, 2. The display device according to claim 1, wherein the display signal line driving circuit is a source driving circuit, and the display signals are source signals.

8. The display device according to claim 7 , wherein the display medium layer is a liquid crystal layer.

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