Wiring board

Abstract

To provide a wiring board having wiring with excellent signal transmission quality.SOLUTION: A wiring board 100 in an embodiment includes a first insulating layer 21, and a first conductive layer 11 formed on the first insulating layer 21. The first conductive layer 11 has wiring EW including a first layer 10b in contact with the first insulating layer 21 and a second layer 10c being an electrolytic plating layer formed on the first layer 10b. In a cross section along a thickness direction of the wiring EW, the second layer 10c has a plurality of crystal particles exposed to a surface of the wiring EW, and a ratio of the number of crystal particles expressing the same crystal orientation in the cross section inside the plurality of crystal particles to the number of crystal particles exposed to the surface is 25% or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board in which a conductor circuit is formed on an insulating layer. The insulating layer side of the conductor circuit is made of an electroless plating film, and the opposite side is made of an electrolytic plating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-214828 Summary of the Invention [Problem to be solved by the invention]

[0004] In the printed wiring board disclosed in Patent Document 1, it is believed that localized undulations may be formed on the surface of the conductor circuit, which may result in degradation of the signal transmission quality in the printed wiring board. [Means for solving the problem]

[0005] The wiring board of the present invention includes a first insulating layer and a first conductor layer formed on the first insulating layer, the first conductor layer having wiring including a first layer in contact with the first insulating layer and a second layer which is an electrolytic plating layer formed on the first layer, the second layer having a plurality of crystal grains exposed on a surface of the wiring in a cross section along a thickness direction of the wiring, and a ratio of the number of crystal grains among the plurality of crystal grains showing the same crystal orientation in the cross section to the number of the plurality of crystal grains is 25% or less.

[0006] According to the embodiment of the present invention, it is possible to provide a high-quality wiring board in which the occurrence of local undulations (for example, local recesses) on the surface of the wiring is suppressed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. [Diagram 2] An enlarged view of part II in Figure 1. [Figure 3A] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of [Figure 3B] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of [Figure 3C] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of [Figure 3D] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of [Figure 3E] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A wiring board according to an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a cross-sectional view showing a wiring board 100, which is an example of a wiring board according to an embodiment. The wiring board 100 is merely an example of a wiring board according to the present embodiment. The layered structure of the wiring board according to the embodiment and the number of conductor layers and insulating layers are not limited to the layered structure of the wiring board 100 shown in Fig. 1 and the number of conductor layers and insulating layers included in the wiring board 100.

[0009] 1, wiring board 100 includes a core substrate 3 and insulating layers and conductor layers alternately laminated on each of two main surfaces (first surface 3a and second surface 3b) opposing each other in the thickness direction of core substrate 3. Core substrate 3 includes insulating layer 32 and conductor layers 31 formed on both surfaces of insulating layer 32.

[0010] In the description of the embodiment, the side of the wiring board 100 farther from the insulating layer 32 in the thickness direction is also referred to as the "upper side" or "upper", or simply "upper", and the side closer to the insulating layer 32 is also referred to as the "lower side" or "lower", or simply "lower". Furthermore, in each conductor layer and each insulating layer, the surface facing the side opposite the insulating layer 32 is also referred to as the "upper surface", and the surface facing the insulating layer 32 is also referred to as the "lower surface".

[0011] The wiring board 100 includes an insulating layer 21 (first insulating layer), a first conductor layer 11, an insulating layer 22 (second insulating layer), and a second conductor layer 12 on a first surface 3a of a core substrate 3. The insulating layer 21 covers the first surface 3a of the core substrate 3. The first conductor layer 11 is formed on a surface 21a of the insulating layer 21, and the insulating layer 22 is formed on the insulating layer 21 and the first conductor layer 11. The second conductor layer 12 is formed on the insulating layer 22.

[0012] The wiring board 100 further includes two insulating layers 23 and two conductor layers 13 that are alternately laminated on the second surface 3b of the core board 3. The wiring board 100 further includes a connection conductor 33 and a connection conductor 4 that penetrate each insulating layer and connect adjacent conductor layers via each insulating layer. The connection conductor 33 is a so-called through-hole conductor included in the insulating layer 32 of the core board 3. The connection conductor 4 is a so-called via conductor formed in each of the insulating layers 21 to 23 that are built up in sequence. For example, the connection conductor 4 formed in the insulating layer 22 connects the first conductor layer 11 and the second conductor layer 12.

[0013] A solder resist 6 is formed on the insulating layer 22 and the second conductor layer 12. A solder resist 6 is also formed on the outermost layer on the second surface 3b side of the core substrate 3. The solder resist 6 has an opening 6a that exposes a part of the second conductor layer 12 or the conductor layer 13. The solder resist 6 is formed of, for example, a photosensitive epoxy resin or a polyimide resin.

[0014] The insulating layers 21 to 23 and the insulating layer 32 are formed of any insulating resin. Examples of the insulating resin include epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. In the example of FIG. 1, the insulating layer 32 includes a core material (reinforcing material) 32a formed of glass fiber, aramid fiber, or the like. Although not shown in FIG. 1, each insulating layer other than the insulating layer 32 may also include a core material made of glass fiber or the like. Each insulating layer may further include an inorganic filler (not shown) made of fine particles of silica (SiO2), alumina, mullite, or the like.

[0015] The first and second conductor layers 11, 12, conductor layer 13, and conductor layer 31, as well as the connecting conductor 4 and connecting conductor 33, are formed using any metal such as copper or nickel. In the example of Fig. 1, the conductor layer 31 includes a metal foil 31a, a metal film 31b, a plating film 31c, a metal film 31d, and a plating film 31e. The connecting conductor 33 is formed integrally with the conductor layer 31, and is composed of the metal film 31b and the plating film 31c. The inside of the connecting conductor 33 is filled with a resin body 33i including an epoxy resin or the like.

[0016] On the other hand, the first and second conductor layers 11, 12, and conductor layer 13, as well as the connecting conductor 4, are each composed of a metal film 10b and a plating film 10c. Each connecting conductor 4 is integrally formed with the conductor layer connected thereto on the upper side. The plating films 31c, 10c are, for example, electrolytic plating films. In the wiring board of the embodiment, in particular, the plating film 10c constituting the first conductor layer 11 is composed of an electrolytic plating film (for example, an electrolytic copper plating film). The metal film 31b and the metal film 10b are, for example, electroless plating films or sputtering films, and function as power supply layers when the plating films 31c and the plating films 10c are formed by electrolytic plating, respectively.

[0017] Each of the conductor layers 11, 12, 13, and 31 constituting the wiring board 100 includes a predetermined conductor pattern. The first conductor layer 11 includes a wiring EW. The wiring EW extends in a direction perpendicular to the paper surface in the drawing, that is, in FIG. 1, a cross section perpendicular to the extending direction of the wiring EW is shown. The wiring EW is a conductor pattern that functions as a conductive path used for transmitting any electric signal or supplying electric power. In the illustrated example, the wiring EW is covered with the insulating layer 22 on the surface other than the surface facing the insulating layer 21. The wiring EW may, for example, connect a predetermined source and destination of an electric signal alone or in cooperation with another conductor pattern, or may connect a predetermined power supply source and power supply destination.

[0018] The wiring EW may be a transmission path for a high-frequency signal, for example, exceeding several GHz. For example, the wiring EW may be formed so that the minimum wiring width is 5 μm or less, and the minimum distance between adjacent wirings (minimum wiring spacing) is 7 μm or less. The wiring height of the wiring EW (the minimum distance from the upper surface of the first insulating layer 21 to the upper surface of the first conductor layer 11) may be, for example, 12 μm or less.

[0019] FIG. 2 shows an enlarged view of an area II including the wiring EW in FIG. 1. The wiring EW includes a first layer (metal film 10b) and a second layer (electrolytic plating layer 10c). The electrolytic plating layer 10c constituting the first conductor layer 11 is constituted as an aggregate of a plurality of crystal grains of a material (e.g., copper) forming the electrolytic plating layer 10c. FIG. 2 illustrates the crystal grain structure constituting the electrolytic plating layer 10c. Specifically, a plurality of crystal grains exposed in a cross section perpendicular to the extension direction of the wiring EW (i.e., the cross section shown in FIG. 2) are illustrated. The boundaries (grain boundaries) of the plurality of crystal grains are indicated by dashed lines. In the description of this specification, the cross section perpendicular to the extension direction of the wiring EW shown in FIG. 2 is also referred to as a "cross section perpendicular to the wiring."

[0020] As shown in the figure, for example, the first conductor layer 11 may have a coating film CL formed on the surface opposite to the insulating layer 21. That is, the surface of the wiring EW on the side of the second insulating layer 22 may be covered with a coating film. The coating film CL is an organic coating formed of a material that can bond with both an organic material such as a resin constituting the insulating layer 22 and an inorganic material such as a metal constituting the first conductor layer 11, and can improve the adhesion between the first conductor layer 11 and the insulating layer 22. An example of the material for the coating film CL is a silane coupling agent containing an azole silane compound such as a triazole compound. Note that the material for the coating film CL is not limited to a silane coupling agent as long as it can increase the adhesion strength between the conductor layer and the insulating layer compared to the case where the insulating layer is directly formed on the conductor layer.

[0021] Each of the multiple crystal grains constituting the electrolytic plating layer 10c, which is the second layer of the wiring EW, may have any shape and size. As shown in the figure, among the multiple crystal grains constituting the second layer (electrolytic plating layer 10c) of each wiring EW, any number of crystal grains are exposed on the surface of the wiring EW (the upper surface and side surface of the wiring EW). In the example of FIG. 2, of the two wirings EW shown, the wiring EW shown on the left has 20 crystal grains exposed in the cross section, of which 11 crystal grains are exposed on the surface of the wiring EW. The wiring EW shown on the right has 22 crystal grains exposed in the cross section, of which 13 crystal grains are exposed on the surface of the wiring EW.

[0022] Each of the crystal grains constituting the electrolytic plated layer 10c has a crystal structure (crystal lattice) according to the material constituting the electrolytic plated layer 10c. For example, when the material constituting the electrolytic plated layer 10c is composed of copper or nickel, each of the crystal grains may have a face-centered cubic lattice structure. Each of the multiple crystal grains constituting the electrolytic plated layer 10c may be arranged in the electrolytic plated layer 10c with any crystal orientation in the crystal lattice facing any direction. That is, each of the multiple crystal grains constituting the electrolytic plated layer 10c may be arranged with any crystal orientation facing perpendicular to the wiring orthogonal cross section.

[0023] More specifically, each of the multiple crystal grains in the electrolytic plating layer 10c of the wiring EW is arranged with an arbitrary crystal orientation on an arbitrary cross section along the thickness direction of the wiring EW, and is accordingly exposed on the surface (side and top surface) of the wiring EW with an arbitrary crystal orientation. When a relatively large number of the multiple crystal grains are arranged with the same crystal orientation on the cross section, it may result in a relatively large number of crystal grains being exposed with the same crystal orientation on the surface of the wiring EW. When a relatively large number of the multiple crystal grains are exposed with the same crystal orientation on the surface of the wiring EW, defects such as local undulations (e.g., dents) may be easily formed on the surface of the wiring EW.

[0024] That is, when the deviation of the crystal orientation toward the cross section of the wiring EW is large among the multiple crystal grains constituting the electrolytic plating layer 10c of the wiring EW, the deviation of the crystal orientation toward the surface of the wiring EW may also be large. Therefore, when the deviation of the crystal orientation toward the cross section of the wiring EW is large, the possibility that crystal grains having the same crystal orientation toward the surface are locally distributed unevenly on the surface of the wiring EW may increase.

[0025] The processability of a crystal having a lattice structure may differ depending on its crystal orientation. For example, the resistance to etching using a chemical solution may differ depending on the crystal orientation. That is, even if a material has the same lattice structure, the etching rate may differ depending on the crystal orientation. Therefore, the presence of a portion on the surface of the wiring EW where crystal grains having the same crystal orientation are unevenly distributed may cause undulations such as localized depressions in the processing of the surface of the wiring EW in the manufacturing process of the wiring board. The undulations such as localized depressions on the surface of the wiring EW may cause an increase in impedance in the wiring EW. The signal transmission quality of the wiring board may be impaired. Therefore, it is preferable that the deviation of the crystal orientation of the crystal grains constituting the electrolytic plating layer 10c of the wiring EW toward the surface (side and top surface) of the wiring EW is relatively small.

[0026] The degree of bias in the crystal orientation of the multiple crystal grains constituting the electrolytic plating layer 10c of the wiring EW toward the surface of the wiring EW can be evaluated by the degree of bias in the crystal orientation of the multiple crystal grains constituting the electrolytic plating layer 10c of the wiring EW toward the cross section of the wiring EW. That is, when the bias in the crystal orientation toward the cross section of the wiring EW is large, the bias in the crystal orientation toward the surface of the wiring EW is also large, and when the bias in the crystal orientation toward the cross section of the wiring EW is small, the bias in the crystal orientation toward the surface of the wiring EW is also small. Specifically, the degree of bias in the crystal orientation toward the surface of the wiring EW can be evaluated by the ratio of the number of crystal grains that have the same crystal orientation toward the cross section among the multiple crystal grains that are exposed in the cross section and exposed on the surface of the wiring EW to the number of multiple crystal grains that are exposed in the cross section along the thickness direction of the wiring EW and exposed on the surface of the wiring EW. In this specification, the ratio of the number of crystal grains exposed in a cross section along the thickness direction of the wiring EW and exposed on the surface of the wiring EW, among the number of crystal grains exposed in the cross section and exposed on the surface of the wiring EW, that have the same crystal orientation facing the cross section, is also referred to as the "same crystal orientation rate." For example, the degree of bias in the crystal orientation facing the surface of the wiring EW can be evaluated by the same crystal orientation rate in any wiring orthogonal cross section that is approximately perpendicular to the extension direction of the wiring EW.

[0027] In the wiring board of the present embodiment, the ratio of the number of crystal grains that have the same crystal orientation facing the cross section among the plurality of crystal grains that are exposed on the cross section along the thickness direction of the wiring EW and on the surface of the wiring EW (same crystal orientation rate) to the number of crystal grains that are exposed on the cross section and on the surface of the wiring EW is 25% or less. Since the crystal grains that make up the electrolytic plating layer 10c in the wiring EW have such a configuration in terms of crystal orientation, the wiring EW can be formed with relatively few defects such as localized recesses on its surface. A wiring board having wiring with relatively good signal transmission quality can be provided. In the description of this specification, "same crystal orientation" or "same crystal orientation" means a crystal orientation that can be evaluated as being the same in a crystal orientation analysis using electron backscatter diffraction (EBSD) method.

[0028] As described above, there may be cases where the minimum value of the wiring width of the wiring EW is 5 μm or less and the wiring height of the wiring EW is 7 μm or less. In this way, when the wiring EW has a relatively small wiring width and wiring height, it may be particularly beneficial for the same crystal orientation rate to be 25% or less.

[0029] In addition, since the deviation in the crystal orientation of the crystal grains constituting the electrolytic plating layer 10c is relatively small, the roughness of the wiring EW surface may be suppressed to be relatively small. Specifically, the surface roughness of the surface of the first conductor layer 11 (particularly, the wiring EW) facing the second insulating layer 22 may be suppressed to be relatively small. The root-mean-square roughness Rq of the surface of the wiring EW facing the second insulating layer 22 may be, for example, 0.15 μm or less. In general, in a wiring pattern having a surface with high surface roughness, the transmission characteristics may be deteriorated in the transmission of high-frequency signals due to an increase in substantial impedance caused by the skin effect. In contrast, since the surface of the wiring EW may have a relatively low surface roughness, it is considered that problems such as deterioration of high-frequency transmission characteristics caused by high surface roughness are unlikely to occur.

[0030] The wiring EW included in the first conductor layer 11 may be a wiring for transmitting a high-frequency signal. Therefore, it is preferable that the first insulating layer 21 in contact with the wiring pattern 1b has excellent high-frequency characteristics. When the insulating layer in contact with the wiring has a relatively high dielectric constant and dielectric loss tangent, the dielectric loss (transmission loss) of the high-frequency signal transmitted by the wiring is relatively large. From the viewpoint of realizing good signal transmission quality of the signal carried by the wiring EW, it is preferable that the relative dielectric constant and dielectric loss tangent of the first insulating layer 21 have relatively low numerical values. Therefore, it is preferable that the insulating layer 21 in contact with the wiring EW is made of a material having a relatively small dielectric constant and dielectric loss tangent. From the same viewpoint, it is preferable that the second insulating layer 22 is also made of a material having a relatively small dielectric constant and dielectric loss tangent. For example, the material forming the first insulating layer 21 and the second insulating layer 22 is made of a material having a dielectric loss tangent of 0.005 or less at a frequency of 5.8 GHz and a relative dielectric constant of 3.5 or less.

[0031] Next, a method for manufacturing a wiring board according to an embodiment will be described with reference to Figures 3A to 3E using the wiring board 100 of Figure 1 as an example. First, as shown in Figure 3A, a starting substrate (e.g., a double-sided copper-clad laminate) is prepared, which includes an insulating layer 32 and metal foils 31a laminated on both surfaces of the insulating layer 32. Through holes 33a are formed in the starting substrate at positions where connecting conductors 33 (see Figure 3B) are to be formed, for example, by drilling or irradiation with a carbon dioxide laser beam.

[0032] Next, as shown in FIG. 3B, the conductor layer 31 and the connection conductor 33 of the core substrate 3 are formed. A metal film 31b is formed in the through hole 33a and on the metal foil 31a by electroless plating or sputtering. Then, a plating film 31c is formed by electrolytic plating using the metal film 31b as a power supply layer. As a result, the conductor layer 31 having a three-layer structure and the connection conductor 33 having a two-layer structure are formed. The inside of the connection conductor 33 is filled with a resin body 103i by, for example, injecting an epoxy resin. After the filled resin body 103i is solidified, a metal film 31d and a plating film 31e are further formed on the upper surface of the resin body 103i and the electrolytic plating film layer. As a result, the conductor layer 31 having a five-layer structure of the metal foil 31a, the metal film 31b, the plating film 31c, the metal film 31d, and the plating film 31e are formed on both sides of the insulating layer 32. Then, the conductor layer 31 is patterned by a subtractive method to obtain a core substrate 3 having a predetermined conductor pattern.

[0033] 3C, an insulating layer 21 is formed on the first surface 3a of the core substrate 3, and a conductor layer 11 is formed on the insulating layer 21. First, the insulating layer 21 covering the first surface 3a of the core substrate 3 is formed by thermocompression bonding a film-like insulating resin or the like. For example, an insulating resin having a dielectric loss tangent of 0.005 or less at a frequency of 5.8 GHz and a relative dielectric constant of 3.5 or less may be used to form the insulating layer 21. Next, a through hole penetrating the insulating layer 21 is formed at the location of the insulating layer 21 where the via conductor 4 is to be formed, for example, by irradiating the insulating layer 21 with a carbon dioxide laser beam.

[0034] Next, a metal film 10b is formed in the through holes of the insulating layer 21 and on the upper surface of the insulating layer 21 by electroless plating, sputtering, or the like. After the metal film 10b is formed, an electrolytic plating layer 10c is formed using the metal film 10b as a power supply layer. The electrolytic plating layer 10c can be formed by a so-called pattern plating method or the like using a plating resist having predetermined openings in the areas where the conductor patterns are formed and at the positions of the through holes.

[0035] In forming the conductor layer 11, a plating resist having an opening at a position corresponding to the wiring EW may be used as the conductor pattern. After forming the electrolytic plating layer 10c, the plating resist is removed, and the exposed portion of the metal film 10b that is not covered by the electrolytic plating layer 10c is removed by etching. As a result, the via conductor 4 is formed by the conductor layer 11 on the insulating layer 21, and the metal film 10b and the electrolytic plating layer 10c in the through hole.

[0036] In forming the electrolytic plating layer 10c constituting the conductor layer 11, the deviation in the crystal orientation of the multiple crystal grains constituting the electrolytic plating layer 10c of the wiring EW included in the conductor layer 11 can be controlled to be relatively small by the electrolytic plating conditions (plating solution concentration, plating temperature, current density, etc.). Specifically, in the electrolytic plating layer 10c of the wiring EW, the ratio of the number of crystal grains that have the same crystal orientation facing the cross section among the multiple crystal grains exposed on the cross section and on the surface of the wiring EW to the number of multiple crystal grains exposed on the cross section along the thickness direction of the wiring EW and exposed on the surface of the wiring EW (same crystal orientation rate) is 25% or less.

[0037] As described above, the electrolytic plating layer 10c of the wiring EW is formed so that the rate of uniform crystal orientation is 25% or less. Therefore, the degree of deviation of the crystal orientation toward the surface of the wiring EW is relatively small, and therefore, there are relatively few areas where crystal grains having the same crystal orientation toward the surface of the wiring EW are locally unevenly distributed. The occurrence of undulations such as localized depressions due to etching on the surface of the wiring EW can be suppressed.

[0038] Also, a coating film (organic coating) may be formed on the surface of the conductor layer 11 by, for example, immersing the conductor layer 11 and the insulating layer 21 in a liquid containing a material capable of bonding with both organic and inorganic materials, such as a silane coupling agent, or by spraying such a liquid. At the same time as the formation of the insulating layer 21 and the conductor layer 11, the insulating layer 23 and the conductor layer 13 may also be formed on the second surface 3b side of the core substrate 3 by a method similar to that of the insulating layer 21 and the conductor layer 11.

[0039] Next, as shown in FIG. 3D, a method similar to the above-mentioned method for forming insulating layer 21 and conductor layer 11 is repeated to form insulating layer 22 and conductor layer 12 on the first surface 3a side of core substrate 3, and further form insulating layer 23 and conductor layer 13 on the second surface 3b side of core substrate 3.

[0040] Next, as shown in FIG. 3E, solder resist 6 is formed on the outermost side of the first surface 3a side and the second surface 3b side of the core substrate 3. Solder resist 6 is formed on the outermost conductor layer 12 on the first surface 3a side of the core substrate 3 and on the insulating layer 22 exposed from the pattern of the conductor layer 12. Solder resist 6 is formed on the outermost conductor layer 13 on the second surface 3b side of the core substrate 3 and on the insulating layer 23 exposed from the pattern of the conductor layer 13. For example, a photosensitive epoxy resin film is formed by spray coating, curtain coating, or film attachment, etc., to form the solder resist 6, and an opening 6a can be formed by exposure and development. The wiring substrate 100 is completed.

[0041] The wiring board of the embodiment is not limited to those having the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. In the wiring board of the embodiment, the ratio of the number of crystal grains that are exposed in the cross section along the thickness direction of the wiring and exposed on the surface of the wiring to the number of crystal grains that are exposed in the cross section and exposed on the surface of the wiring and have the same crystal orientation facing the cross section (same crystal orientation rate) is 25% or less in the electrolytic plating layer of the wiring, and the form is not limited to those having a core substrate. In addition, for example, the number of insulating layers and conductor layers formed on both sides of the core substrate is not limited to the example shown in the drawing, and any number of insulating layers and conductor layers may be formed. [Explanation of symbols]

[0042] 100 Wiring board 10b 1st layer 10c 2nd layer 11 Conductive layer (first conductive layer) 12 Conductive layer (second conductive layer) 21 Insulating layer (first insulating layer) 22 Insulating layer (second insulating layer) 33 Connecting conductor (through hole conductor) 3 Core Board 4 Connecting conductor (via conductor) 6a aperture EW Wiring CL coating film

Claims

1. A wiring board including a first insulating layer and a first conductor layer formed on the first insulating layer, the first conductor layer has wiring including a first layer in contact with the first insulating layer and a second layer which is an electrolytic plating layer formed on the first layer; the second layer has a plurality of crystal grains exposed on a surface of the wiring in a cross section along a thickness direction of the wiring, The ratio of the number of crystal grains among the plurality of crystal grains that exhibit the same crystal orientation in the cross section to the total number of the plurality of crystal grains is 25% or less.

2. 2. The wiring board according to claim 1, wherein each of the plurality of crystal grains has a face-centered cubic lattice structure.

3. 2. The wiring board according to claim 1, wherein the root mean square roughness Rq of the surface of the wiring is 0.15 [mu]m or less.

4. 2. The wiring board according to claim 1, wherein a surface of the wiring is covered with an organic coating layer.

5. 2. The wiring board according to claim 1, wherein the minimum width of the wiring is 5 μm or less, and the wiring height is 7 μm or less.

6. 2. The wiring board according to claim 1, wherein the first insulating layer has a dielectric loss tangent of 0.005 or less at 5.8 GHz and a relative dielectric constant of 3.5 or less.

Images