Memory system and memory device

Abstract

To provide a memory system with high performance and high reliability.SOLUTION: A memory system of an embodiment includes a memory and a memory controller. The memory includes a memory cell and a control circuit that writes the n-bit of first data into the memory cell by first write operation and writes the m-bit of second data including the first data into the memory cell by second write operation. The memory controller instructs the memory to execute the first write operation, selects whether a first method for preparing the first data included in the second data used for the second write operation in the memory or a second method for preparing it outside the memory based on an index regarding reliability of the first data in the memory cell, and instructs to execute the second write operation for the second data including the first data prepared in the selected method.SELECTED DRAWING: Figure 16

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to memory systems and memory devices. [Background technology]

[0002] As a memory system, a solid state drive (SSD) including a memory controller and a memory device is known. The memory device is, for example, a non-volatile memory. The non-volatile memory is, for example, a NAND flash memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 11,437,104 [Patent Document 2] US Patent Application Publication No. 2020 / 0004446 [Patent Document 3] U.S. Pat. No. 11,429,538 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a high performance and high reliability memory system. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a nonvolatile memory and a memory controller electrically connected to the nonvolatile memory. The nonvolatile memory includes a memory cell configured to store data nonvolatilely, and a control circuit configured to write n (n is a real number equal to or greater than 1) bits of first data to the memory cell by a first write operation, and write m (m is a real number greater than n) bits of second data including the first data to the memory cell by a second write operation. The memory controller is configured to instruct the nonvolatile memory to perform the first write operation, select whether the first data included in the second data used in the second write operation is to be prepared using a first method for preparing the first data in the nonvolatile memory or a second method for preparing the first data outside the nonvolatile memory based on an index regarding the reliability of the first data written to the memory cell, prepare the first data included in the second data using either the selected first method or the selected second method, and instruct the nonvolatile memory to perform a second write operation on the second data including the first data prepared using the selected method. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to a first embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of the configuration of a nonvolatile memory according to a first embodiment. [Diagram 3] 1 is a circuit diagram of a memory cell array of a nonvolatile memory according to a first embodiment. [Figure 4] FIG. 4 is a diagram showing an example of the relationship between the threshold voltage and data of a memory cell according to the first embodiment. [Diagram 5] 2 is a block diagram showing an example of the configuration of a write management circuit in the memory system of the first embodiment; [Figure 6] FIG. 4 is a diagram showing an example of the configuration of a management table in the memory system of the first embodiment. [Figure 7] 5 is a diagram showing an example of a first write operation in the memory system of the first embodiment; [Figure 8] 6 is a diagram showing an example of a second write operation in the memory system of the first embodiment; [Figure 9] 5 is a diagram showing an example of a write operation in the memory system according to the first embodiment; [Figure 10] FIG. 4 is a sequence diagram showing an example of a write operation in the memory system of the first embodiment. [Figure 11] FIG. 11 is a sequence diagram showing another example of a write operation in the memory system of the first embodiment. [Figure 12] FIG. 11 is a sequence diagram showing yet another example of a write operation in the memory system of the first embodiment. [Figure 13] FIG. 4 is a sequence diagram showing an example of a command sequence of a first write operation in the memory system of the first embodiment. [Figure 14] FIG. 4 is a sequence diagram showing an example of a command sequence of a second write operation in the memory system of the first embodiment. [Figure 15A] FIG. 11 is a sequence diagram showing another example of the command sequence of the second write operation in the memory system of the first embodiment. [Figure 15B] FIG. 11 is a sequence diagram showing yet another example of the command sequence of the second write operation in the memory system of the first embodiment. [Figure 16] 6 is a flowchart showing an example of a write operation in the memory system of the first embodiment. [Figure 17] 6 is a flowchart showing an example of a first write operation in the memory system of the first embodiment. [Figure 18] 5 is a diagram showing an example of a first write operation in the memory system of the first embodiment; [Figure 19] 10 is a flowchart showing an example of a second write operation in the memory system of the first embodiment. [Figure 20] 6 is a diagram showing an example of a second write operation in the memory system of the first embodiment; [Figure 21]FIG. 2 is a block diagram showing a configuration example of a first modification of the memory system according to the first embodiment. [Figure 22] FIG. 13 is a diagram showing a configuration example of a second modified example of the memory system of the first embodiment. [Diagram 23] FIG. 11 is a block diagram showing a configuration example of a third modified example of the memory system according to the first embodiment. [Figure 24] FIG. 11 is a block diagram showing an example of the configuration of a memory system according to a second embodiment. [Diagram 25] 10 is a flowchart showing an example of a write operation in the memory system of the second embodiment. [Figure 26] 13 is a diagram showing an example of a write operation in the memory system according to the second embodiment; [Figure 27] FIG. 13 is a block diagram showing a configuration example of a first modified example of a memory system according to the second embodiment. [Figure 28] FIG. 11 is a diagram showing an example of a write operation in the memory system according to the modified example of the second embodiment. [Figure 29] FIG. 13 is a block diagram showing a configuration example of a second modified example of a memory system according to the second embodiment. [Diagram 30] 13 is a flowchart showing an example of a write operation in the memory system according to the second modification of the second embodiment. [Diagram 31] FIG. 13 is a block diagram showing an example of the configuration of a memory system according to a third embodiment. [Diagram 32] 13 is a flowchart showing an example of a write operation in the memory system of the third embodiment. [Diagram 33] 13 is a flowchart showing an example of a write operation in a modified example of the memory system of the third embodiment. [Diagram 34] FIG. 13 is a block diagram showing an example of the configuration of a memory system according to a fourth embodiment. [Diagram 35] FIG. 13 is a diagram showing an example of a write operation in the memory system according to the fourth embodiment. [Diagram 36] FIG. 13 is a block diagram showing an example of the configuration of a memory system according to a fifth embodiment. [Figure 37]13 is a flowchart showing an example of a write operation in the memory system according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A memory system according to an embodiment will be described with reference to Figures 1 to 37. In the following description, elements having the same function and configuration are given the same reference numerals. In addition, in each of the following embodiments, a number / letter may be used at the end of the reference numeral of a component (e.g., a circuit, wiring, various voltages and signals, etc.) for differentiation. When the components do not need to be distinguished from each other, a description (reference numeral) with the number / letter at the end omitted is used.

[0008] (Embodiment) (1) First embodiment A memory system according to a first embodiment will be described with reference to FIGS.

[0009] (a) Configuration example (a-1) Information processing system As shown in FIG. 1, an information processing system 9 includes a memory system 1 and a host 2.

[0010] The memory system 1 is a device for storing data. The memory system 1 may be, for example, a solid state drive (SSD), a universal flash storage (UFS) device, a universal serial bus (USB) memory, a multi-media card (MMC), or an SD TM The memory system 1 is a card. The memory system 1 can be connected to a host 2 via a host bus HBS. The memory system 1 performs processing based on a request (a command or a host command) received from the host 2 or a spontaneous processing request generated within the memory system 1.

[0011] The host 2 is a computing device that controls the memory system 1. The host 2 is, for example, a personal computer, a server system, a mobile device, an in-vehicle device, or a digital camera.

[0012] (a-1-1) Internal structure of memory system The memory system 1 includes a memory controller 10 and a memory device 30. The memory device 30 is, for example, a nonvolatile memory. The memory device 30 is, for example, a nonvolatile semiconductor memory such as a NAND flash memory. Hereinafter, the memory device 30 will be referred to as the nonvolatile memory 30 or the NAND memory 30.

[0013] The memory controller 10 is a device that controls the NAND memory 30. The memory controller 10 is connected to the host 2 via a host bus HBS. The memory controller 10 receives requests from the host 2 via the host bus HBS. The type of the host bus HBS depends on the application applied to the memory system 1. When the memory system 1 is an SSD, the host bus HBS may be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TM (Peripheral Component Interconnect Express) standard. If the memory system 1 is a UFS device, the host bus HBS complies with the M-PHY standard. If the memory system 1 is a USB memory, the host bus HBS complies with the USB standard. If the memory system 1 is an MMC, the host bus HBS complies with the eMMC (Embedded Multi Media Card) standard. If the memory system 1 is an SD TM If it is a card, the host bus HBS is TM Comply with standards.

[0014] The memory controller 10 controls the NAND memory 30 via the NAND bus NBS based on a request received from the host 2 or an autonomous processing request generated inside the memory system 1. The NAND bus NBS complies with, for example, the Toggle NAND Flash Interface standard or the Open NAND Flash Interface standard.

[0015] The NAND memory 30 is a device that stores data. The NAND memory 30 includes a plurality of memory cells. Each of the plurality of memory cells stores data in a non-volatile manner according to a threshold voltage of the memory cell. The NAND memory 30 stores data received from the memory controller 10 in a non-volatile manner in the plurality of memory cells. The NAND memory 30 outputs data read from the plurality of memory cells to the memory controller 10.

[0016] (a-1-2) Memory controller An example of the internal configuration of the memory controller 10 will be described.

[0017] As shown in FIG. 1, the memory controller 10 includes a host interface (I / F) circuit 11, a processor 12, a buffer memory 13, an error checking and correcting (ECC) circuit 14, a read only memory (ROM) 15, a random access memory (RAM) 16, a NAND interface (I / F) circuit 17, and a write management circuit 18. The host interface circuit 11, the processor 12, the buffer memory 13, the ECC circuit 14, the ROM 15, the NAND interface circuit 17, and the write management circuit 18 may be configured as, for example, a system-on-a-chip (SoC) 100. In the example shown in FIG. 1, the RAM 16 is implemented outside the SoC 100, but the RAM 16 may also be implemented inside the SoC 100. The memory controller 10 may be configured by multiple chips. The functions of each part of the memory controller 10 may be realized by a dedicated hardware circuit, a processor that executes a program (firmware), or a combination of these.

[0018] The host interface circuit 11 is a circuit that manages communication between the memory controller 10 and the host 2. The host interface circuit 11 is connected to the host 2 via a host bus HBS.

[0019] The processor 12 is a control circuit of the memory controller 10. The processor 12 is, for example, a CPU (central processing unit). The processor 12 controls the operation of the entire memory controller 10 by executing a program (firmware) stored in the ROM 15. For example, when the processor 12 receives a write request from the host 2, it controls a write operation based on the received write request. The same applies to a read operation and an erase operation.

[0020] The buffer memory 13 is a memory that temporarily stores data. The buffer memory 13 is, for example, a static random access memory (SRAM). The buffer memory 13 temporarily stores write data, read data, and the like. The write data is data that is written to the NAND memory 30. The read data is data that is read from the NAND memory 30.

[0021] The ECC circuit 14 is a circuit that performs ECC (error checking and correcting) processing for correcting data errors. The ECC circuit 14 generates an error correction code based on the write data during a data write operation. The ECC circuit 14 generates a syndrome based on the error correction code in a predetermined unit during a data read operation, and detects errors. The ECC circuit 14 corrects the detected errors.

[0022] The ROM 15 is a non-volatile memory. For example, the ROM 15 is an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). The ROM 15 stores programs such as firmware.

[0023] The RAM 16 is a volatile memory. The RAM 16 is, for example, an SRAM or a DRAM (Dynamic random access memory). The RAM 16 is used as a working area for the processor 12. The RAM 16 stores firmware for managing the NAND memory 30 and various types of management information. The RAM 16 holds, for example, various tables TBL1.

[0024] The NAND interface circuit 17 is a circuit that manages communication between the memory controller 10 and the NAND memory 30. The NAND interface circuit 17 is connected to the NAND memory 30 via a NAND bus NBS. For example, the NAND interface circuit 17 controls the transfer of data, commands, addresses, and the like between the memory controller 10 and the NAND memory 30.

[0025] The write management circuit 18 performs various management of the write operation to be executed by the NAND memory 30 based on the state of the data in the NAND memory 30 .

[0026] (a-1-3) NAND flash memory The configuration of the NAND memory 30 will be described with reference to FIG.

[0027] 2 is a block diagram showing an example of a configuration of the NAND memory 30. The NAND memory 30 includes a memory cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy control circuit 34, a register 35, a sequencer 36, a driver module 37, a row decoder module 38, a sense amplifier module 39, and a data latch 40.

[0028] The memory cell array 31 includes one or more blocks BLK0, BLK1, . . . , BLKk-1, where k is an integer equal to or greater than 1. The block BLK is, for example, a set of memory cells from which data is erased collectively. For example, the block BLK is used as a unit of a data erase operation. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 31. Each memory cell is associated with, for example, one bit line and one word line. The memory cell array 31 will be described in detail later.

[0029] The input / output circuit 32 is a circuit that transmits and receives signals and information to and from the memory controller 10. The input / output circuit 32 transmits and receives input / output signals DQ (for example, 8-bit signals DQ0 to DQ7) and a data strobe signal DQS to and from the memory controller 10. The signal DQ is the substance of data transmitted and received between the NAND memory 30 and the memory controller 10. The signal DQ is, for example, a command CMD, an address ADD, status information STS, and data DAT. The signal DQS is a signal (clock signal) for controlling the timing of transmission and reception of the signal DQ. For example, when writing data, the signal DQS is transmitted from the memory controller 10 to the NAND memory 30 together with the signal DQ including the write data. The NAND memory 30 receives the signal DQ including the write data in synchronization with the signal DQS. When reading data, the signal DQS is transmitted from the NAND memory 30 to the memory controller 10 together with the signal DQ including the read data. The memory controller 10 receives a signal DQ including read data in synchronization with the signal DQS. The input / output circuit 32 may receive the signal DQS from the memory controller 10 via the logic control circuit 33.

[0030] The input / output circuit 32 transmits the command CMD in the signal DQ to the command register 35A. The input / output circuit 32 transmits the address ADD in the signal DQ to the address register 35B. The input / output circuit 32 receives the status information STS from the status register 35C. The input / output circuit 32 transmits and receives the data DAT in the signal DQ to and from the data latch 40.

[0031] The logic control circuit 33 is a circuit that controls the input / output circuit 32 and the sequencer 36 based on the control signal. The logic control circuit 33 receives a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REN from the memory controller 10. The signal CEn is a signal for enabling the NAND memory 30. The signal CLE is a signal indicating that the signal DQ received by the NAND memory 30 is a command CMD. The signal ALE is a signal indicating that the signal DQ received by the NAND memory 30 is an address ADD. The signal WEn is a signal that instructs the NAND memory 30 to input the signal DQ. The signal REn is a signal that instructs the NAND memory 30 to output the signal DQ. The NAND memory 30 generates a signal DQS based on the signal REN. The NAND memory 30 outputs a signal DQ to the memory controller 10 based on the generated signal DQS.

[0032] The ready / busy control circuit 34 is a circuit that notifies the memory controller 10 of the operating status of the sequencer 36. The ready / busy control circuit 34 transmits a ready / busy signal RBn to the memory controller 10 based on the operating status of the sequencer 36. The signal RBn is a signal that indicates whether the NAND memory 30 is in a ready state or a busy state. The signal level of the signal RBn is, for example, a “High” level (an “H” level) when the NAND memory 30 is in a ready state. The ready state is a state in which the NAND memory 30 can accept a command from the memory controller 10. The signal level of the signal RBn is, for example, a “Low” level (an “L” level) when the NAND memory 30 is in a busy state. The busy state is a state in which the NAND memory 30 cannot accept a command from the memory controller 10.

[0033] The register 35 is a circuit for temporarily storing information, and includes a command register 35A, an address register 35B, and a status register 35C.

[0034] The command register 35A is a circuit that stores a command CMD. The command CMD includes, for example, an instruction for causing the sequencer 36 to execute a read operation, a write operation, or an erase operation.

[0035] The address register 35B is a circuit that stores an address ADD. The address ADD includes, for example, a row address and a column address CAd. The row address includes a block address BAd and a page address (word line address) PAd. The block address BAd, the page address PAd, and the column address CAd are used to select, for example, a block BLK, a word line, and a bit line, respectively.

[0036] The status register 35C is a circuit that temporarily stores status information STS during, for example, a read operation, a write operation, or an erase operation. The status information STS is used to notify the memory controller 10 whether the operation has ended normally.

[0037] The sequencer 36 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 36 controls the operation of the entire NAND memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, the driver module 37, the row decoder module 38, and the sense amplifier module 39 based on the command CMD stored in the command register 35A. For example, the sequencer 36 executes a read operation, a write operation, and an erase operation.

[0038] The driver module 37 is a circuit that generates voltages used in read, write, and erase operations. The driver module 37 applies the generated voltage to a signal line corresponding to a selected word line based on a page address PAd stored in the address register 35B.

[0039] The row decoder module 38 is a circuit that selects one block BLK in the memory cell array 31 based on a block address BAd stored in the address register 35B. The row decoder module 38 transfers a voltage applied to a signal line corresponding to a selected word line to the selected word line in the selected block BLK.

[0040] In a write operation, the sense amplifier module 39 receives write data DAT from the input / output circuit 32 via the data latch 40. The sense amplifier module 39 applies a voltage based on the received write data DAT to the bit line. In a read operation, the sense amplifier module 39 determines the data stored in the memory cell based on the presence or absence of current generation in the bit line or the voltage of the bit line. The sense amplifier module 39 transfers the determination result as read data DAT to the input / output circuit 32 via the data latch 40.

[0041] The data latch (data cache) 40 includes a plurality of latch circuits (not shown). Each latch circuit temporarily stores write data or read data. For example, in a write operation, the data latch 40 temporarily holds write data received from the input / output circuit 32 and transmits the write data to the sense amplifier module 39. In a read operation, the data latch 40 temporarily holds read data received from the sense amplifier module 39 and transmits the read data to the input / output circuit 32.

[0042] <Example of memory cell array configuration> The circuit configuration of the memory cell array 31 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram of the memory cell array 31. Fig. 3 shows the circuit configuration of a block BLK0 included in the memory cell array 31 as an example of the circuit configuration of the memory cell array 31. The other blocks BLK have the same configuration as that shown in Fig. 3.

[0043] The block BLK0 includes, for example, five string units SU0, SU1, SU2, SU3, and SU4. Each string unit SU is a set of multiple NAND strings NS that are selected collectively in, for example, a write operation or a read operation. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0, BL1, . . . , BLm-1, respectively. m is an integer equal to or greater than 1. The NAND string NS is a set of multiple memory cells connected in series. Each NAND string NS includes, for example, memory cells MC0, MC1, MC2, MC3, . . . , MCn-2, MCn-1, select transistor ST1, and select transistor ST2. n is an integer equal to or greater than 1. The memory cells (also called memory cell transistors) MC are field-effect transistors including a control gate and a charge storage layer. The select transistors ST1 and ST2 are switching elements. Each of the select transistors ST1 and ST2 is used to select a string unit SU during various operations.

[0044] In each NAND string NS, the memory cells MC0,...,MCn-1 are connected in series. The drain of the select transistor ST1 is connected to the associated bit line BL. The source of the select transistor ST1 is connected to one end of the memory cells MC0,...,MCn-1 connected in series. The drain of the select transistor ST2 is connected to the other end of the memory cells MC0,...,MCn-1 connected in series. The source of the select transistor ST2 is connected to a source line SL.

[0045] In the same block BLK, the control gates of memory cells MC0, MC1, MC2, MC3, . . . , MCn-2, MCn-1 are connected to word lines WL0, WL1, WL2, WL3, . . . , WLn-2, ​​WLn-1, respectively, in common among the multiple NAND strings. The gates of select transistors ST1 in string units SU0, SU1, SU2, SU3, SU4 are connected to select gate lines SGD0, SGD1, SGD2, SGD3, SGD4, respectively, in common among the multiple NAND strings. The gates of select transistors ST2 included in the same block BLK are connected to select gate line SGS in common among the multiple NAND strings.

[0046] In the circuit configuration of the memory cell array 31 described above, the bit lines BL are shared by, for example, the NAND strings NS to which the same column address CAd is assigned in each string unit SU, and the source lines SL are shared by, for example, a plurality of blocks BLK.

[0047] A set of multiple memory cells MC connected to a common word line WL in one string unit SU is called, for example, a cell unit CU. A block BLK includes multiple cell units CU. Data stored in a cell unit CU including multiple memory cells MC each storing one bit of data according to a threshold voltage corresponds to one page of data. A cell unit CU can store two or more pages of data based on the number of bits of data stored in the memory cells MC. In this embodiment, one memory cell MC can store four bits of data. That is, the memory cell MC in this embodiment is a QLC (quad level cell) that stores four bits of data. In this case, the data stored in the cell unit CU corresponds to four pages of data.

[0048] The number of bits of data that the memory cell MC can store may be any real number. For example, the memory cell MC may be a multi-level cell (MLC) that stores 2 bits of data, a triple-level cell (TLC) that stores 3 bits of data, or a penta-level cell (PLC) that stores 5 bits of data.

[0049] Furthermore, the circuit configuration of the memory cell array 31 is not limited to the above configuration. For example, the number of string units SU included in each block BLK, and the number of memory cells MC and select transistors ST1 and ST2 included in each NAND string NS may be any number.

[0050] <Memory cell threshold voltage distribution> The possible threshold voltage distribution of memory cells MC will be described with reference to Fig. 4. Fig. 4 is a diagram showing an example of the relationship between the threshold voltage distribution of memory cells MC and the data stored in the memory cells MC. The horizontal axis of Fig. 4 indicates the threshold voltage of the memory cells MC. The vertical axis of Fig. 4 indicates the number of memory cells MC.

[0051] 4, when a memory cell MC stores 4-bit data, the distribution of its threshold voltages is divided into 16. These 16 threshold distributions are denoted as "St0" state, "St1" state, ..., "St14" state, and "St15" state in order from the lowest threshold voltage.

[0052] Moreover, voltages V1, . . . , V15 are voltages (hereinafter referred to as "verify voltages") used for verifying the "St1" state, . . . , "St15" state during a write operation, respectively. Voltage VREAD is a voltage applied to unselected word lines WL during a read operation. When voltage VREAD is applied to the gate of memory cell MC, memory cell MC turns on regardless of the data stored therein. The relationship between these voltage values ​​is as follows: V1 <V2<V3<V4<V5<V6<V7<V8<V9<V10<V11<V12<V13<V14<V15<VREADである。

[0053] The "St0" state corresponds to the erased state of the memory cell MC. The "St1", ..., "St15" states correspond to states in which charge is injected into the charge storage layer of the memory cell MC and data is written. The threshold voltage of the memory cell MC included in the "St0" state is less than voltage V1. The threshold voltages of the memory cells MC included in the "St1" to "St14" states are equal to or greater than voltage V1 to voltage V14 and less than voltage V2 to voltage V15, respectively. The threshold voltage of the memory cell MC included in the "St15" state is equal to or greater than voltage V15 and less than voltage VREAD.

[0054] The setting value of the verify voltage and the setting value of the read voltage corresponding to each state may be the same or different. In the following, for the sake of simplicity, the case where the verify voltage and the read voltage are the same setting value will be described.

[0055] Hereinafter, the read operations using voltages V1,...,V15 will be referred to as read operations R1,...,R15, respectively. Read operation R1 determines whether the threshold voltage of memory cell MC is less than voltage V1. Read operation R2 determines whether the threshold voltage of memory cell MC is less than voltage V2. Read operation R3 determines whether the threshold voltage of memory cell MC is less than voltage V3. The same applies below.

[0056] As described above, each memory cell MC can have one of 16 threshold voltage distributions and can take 16 different states. By assigning these states to data of "0000",...,"1111" in binary notation, each memory cell MC can store 4 bits of data. Hereinafter, the 4 bits of data are referred to as the Lower bit, Middle bit, Upper bit, and Top bit, from the least significant bit. In addition, a set of Lower bits stored in memory cells MC included in the same cell unit CU is referred to as a Lower page, a set of Middle bits is referred to as a Middle page, a set of Upper bits is referred to as an Upper page, and a set of Top bits is referred to as a Top page.

[0057] In the example of FIG. 4, data is allocated to the "Lower bit / Middle bit / Upper bit / Top bit" of the memory cells MC included in each state as shown below. “St0” state: “1111” data “St1” state: “1110” data “St2” state: “1100” data “St3” state: “1101” data “St4” state: “1001” data “St5” state: “1011” data “St6” state: “0011” data “St7” state: “0010” data “St8” state: “1010” data “St9” state: “1000” data “St10” state: “0000” data “St11” state: “0001” data “St12” state: “0101” data “St13” state: “0111” data “St14” state: “0110” data “St15” state: “0100” data The data assigned to each state is not limited to this.

[0058] When reading data allocated in this way, the Lower bit is determined by read operations R6, R8, and R10. The Middle bit is determined by read operations R4 and R12. The Upper bit is determined by read operations R2, R5, R9, R13, and R15. The Top bit is determined by read operations R1, R3, R7, R11, and R14.

[0059] In the memory system 1 of this embodiment, the four pages of data are written into the NAND memory 30 by a first write operation (hereinafter also referred to as an MLC program) that writes data of the Lower page and the Middle page, and a second write operation (hereinafter also referred to as a Fine program) that writes data of the Lower page and the Middle page, as well as data of the Upper page and the Top page, after the first write operation, as described below.

[0060] During the second write operation, the Lower page data and the Middle page data used in the second write operation are prepared by loading data from inside the NAND memory 30 or from outside the NAND memory 30.

[0061] The data loading method for the Lower / Middle page data includes an internal data load (IDL) and an external data load (EDL).

[0062] The IDL is a method of loading (providing) the Lower / Middle page data used in the second write operation from the memory cell array 31 inside the NAND memory 30.

[0063] The EDL is a method of loading (providing) the Lower / Middle page data used in the second write operation from outside the NAND memory 30 (for example, the RAM 16 of the memory controller 10).

[0064] The memory system 1 of this embodiment determines a data loading method for the Lower page data and Middle page data to be used in the second write operation based on a certain indicator regarding the reliability of the Lower page data and Middle page data written to the NAND memory 30 by the first write operation.

[0065] For example, the reliability of data written to the memory cell array 31 of the NAND memory 30 varies depending on the period during which the data is retained in the memory cell array 31 or the operating conditions of the NAND memory 30 (e.g., temperature and / or period of use).

[0066] (a-1-4) Write management circuit FIG. 5 is a block diagram showing an example of the configuration of the write management circuit 18 of the memory controller 10 in the memory system 1 of the present embodiment.

[0067] As shown in FIG. 5, the write management circuit 18 includes a data load selector 181 and a global clock 182.

[0068] The data load selector 181 selects either the IDL or EDL data load method based on a certain index related to the reliability of the Lower page data and Middle page data written by the first write operation.

[0069] The global clock 182 is a timer. The global clock 182 starts measuring time, for example, from the time when the memory system 1 is powered on for the first time. The global clock 182 may temporarily stop measuring time when power to the memory system 1 is cut off. The time measured up to the time when the power is cut off may be stored in the NAND memory 30. When the supply of power to the memory system 1 in the power-cut state is resumed, the global clock 182 may resume measuring time. The global clock 182 may resume measuring time from the time measured up to the time when the power was cut off.

[0070] In the write management circuit 18, the data load selector 181 records the completion time of the first write operation measured by the global clock 182 in a management table TBL1. The management table TBL1 is stored in, for example, the RAM 16. The management table TBL1 may be stored in a storage area (for example, a register) provided in the write management circuit 18.

[0071] FIG. 6 is a diagram for explaining the management table TBL1 in the memory system 1 of the present embodiment.

[0072] The management table TBL1 is a log table that records corresponding values ​​for each of the items: the number (word line address) of the word line WL targeted for the first write operation, the number of the string unit SU targeted for the first write operation, and the completion time of the first write operation. For example, one management table TBL1 is prepared for one write destination block. This is because multiple write destination blocks may be used in parallel.

[0073] In the following, the management table TBL1 is also called the MLC program log table TBL1.

[0074] The data load selector 181 refers to the MLC program log table TBL1 and selects the data load method for the Lower page data and the Middle page data during the second write operation. The data load selector 181 determines the data load method for the second write operation based on the current time indicated by the global clock 182 (i.e., the time immediately before the execution of the second write operation or the time when the data load method is selected) and the completion time of the first write operation at the corresponding address in the MLC program log table TBL1.

[0075] For example, the data load selector 181 compares the difference value between the current time and the completion time of the first write operation with a threshold value for determining the data load method. If the difference value is greater than the threshold value, the data load selector 181 selects the EDL. As a result, the EDL is used as the data load method for the Lower / Middle page data in the second write operation. If the difference value is equal to or less than the threshold value, the data load selector 181 selects the IDL. As a result, the IDL is used as the data load method for the Lower / Middle page data in the second write operation.

[0076] (b) Operation An operation example of the memory system 1 of the present embodiment will be described with reference to FIGS.

[0077] (b-1) Overview of write operation An overview of the write operation of the NAND memory 30 in the memory system 1 of this embodiment will be described.

[0078] A write operation (write sequence) of the NAND memory 30 includes a program operation and a verify operation (also called program verify). By repeating a combination of the program operation and the verify operation, the threshold voltage of the memory cell MC is raised to a target level.

[0079] The program operation is an operation of increasing the threshold voltage of the memory cell MC by injecting electrons into the charge storage layer of the memory cell MC (or maintaining the threshold voltage by prohibiting the injection). Hereinafter, the operation of increasing the threshold voltage of the memory cell MC is called "0" program. For example, increasing the threshold voltage of the memory cell MC included in the "St0" state so that it is included in the "St1" state is called "0" program. A voltage for "0" program (e.g., voltage VSS) is applied from the sense amplifier module 39 to the bit line BL targeted for "0" programming. On the other hand, an operation of maintaining the threshold voltage of the memory cell MC is called "1" program or write prohibition. A voltage for "1" program (e.g., a positive voltage) is applied from the sense amplifier module 39 to the bit line BL targeted for "1" programming.

[0080] The verify operation is an operation for determining whether or not the threshold voltage of the memory cell MC has reached a target level by reading data from the memory cell MC after the program operation. The memory cell MC whose threshold voltage has reached the target level is set to be write-protected.

[0081] In this embodiment, the above-mentioned write operation is executed in two stages. Specifically, the write operation of 4 pages of data corresponding to a certain cell unit CU is executed in two stages, a first write operation (MLC program) and a second write operation (Fine program).

[0082] (b-1-1) First Write Operation The first write operation (MLC program) of the memory system 1 of this embodiment will be described with reference to FIG.

[0083] FIG. 7 is a diagram showing changes in the threshold voltage distribution of memory cells MC due to the first write operation.

[0084] When the first write operation is performed, the threshold voltage of the memory cells MC increases based on the write data, and four threshold voltage distributions are formed.

[0085] As shown in FIG. 7, the first write operation forms an "M0" state, an "M1" state, an "M2" state, and an "M3" state. In the first write operation, for example, the threshold voltage distribution of the "M0" state is formed by a plurality of memory cells MC into which "11" data is written. Here, the notation "kh" data indicates that the lower bit is "k" data and the middle bit is "h" data. The threshold voltage distribution of the "M1" state is formed by a plurality of memory cells MC into which "10" data is written. The threshold voltage distribution of the "M2" state is formed by a plurality of memory cells MC into which "00" data is written. The threshold voltage distribution of the "M3" state is formed by a plurality of memory cells MC into which "01" data is written.

[0086] The sequencer 36 uses voltages VM1, VM2, and VM3 as verify voltages. Voltage VM1 is a verify voltage used when "10" data is written. Voltage VM1 is equal to or greater than voltage V1 and less than voltage V4. Voltage VM2 is a verify voltage used when "00" data is written. Voltage VM2 is equal to or greater than voltage V4 and less than voltage V6. Voltage VM3 is a verify voltage used when "01" data is written. Voltage VM3 is equal to or greater than voltage V6 and less than voltage V12.

[0087] The threshold voltage of memory cells MC included in the "M0" state is less than voltage V1. The threshold voltage of memory cells MC included in the "M1" state is equal to or greater than voltage VM1 and less than voltage V5. The threshold voltage of memory cells MC included in the "M2" state is equal to or greater than voltage VM2 and less than voltage V7. The threshold voltage of memory cells MC included in the "M3" state is equal to or greater than voltage VM3 and less than voltage V13.

[0088] Hereinafter, the stage where the first write operation is performed is called the MLC stage, and the memory cells MC where the first write operation is performed but the second write operation is not performed are called memory cells MC in the MLC state.

[0089] (b-1-2) Second write operation The second write operation (Fine program) of the memory system 1 of this embodiment will be described with reference to FIG.

[0090] FIG. 8 is a diagram showing changes in the threshold voltage distribution of memory cells MC due to the second write operation.

[0091] When the second write operation is performed, the threshold voltages of the memory cells MC are increased based on the write data, forming 16 threshold voltage distributions.

[0092] 8, in the second write operation, for example, threshold voltage distributions of the "St0" state, the "St1" state, the "St2" state, and the "St3" state are formed from the threshold voltage distribution of the "M0" state. Threshold voltage distributions of the "St4" state, the "St5" state, the "St8" state, and the "St9" state are formed from the threshold voltage distribution of the "M1" state. Threshold voltage distributions of the "St6" state, the "St7" state, the "St10" state, and the "St11" state are formed from the threshold voltage distribution of the "M2" state. Threshold voltage distributions of the "St12" state, the "St13" state, the "St14" state, and the "St15" state are formed from the threshold voltage distribution of the "M3" state.

[0093] For example, when the threshold voltage distribution of the “M0” state is shifted to the threshold voltage distribution of the “St3” state, the data stored in the memory cell MC changes from the data of the “M0” state (“11” data) to the data of the “St3” state (“1101” data).

[0094] For example, when the threshold voltage distribution of the “M1” state is shifted to the threshold voltage distribution of the “St4” state, the data stored in the memory cell MC changes from the data of the “M1” state (“10” data) to the data of the “St4” state (“1001” data).

[0095] For example, when the threshold voltage distribution of the “M2” state is shifted to the threshold voltage distribution of the “St7” state, the data stored in the memory cell MC changes from the data of the “M2” state (“00” data) to the data of the “St7” state (“0010” data).

[0096] For example, when the threshold voltage distribution of the “M3” state is shifted to the threshold voltage distribution of the “St14” state, the data stored in the memory cell MC changes from the data of the “M3” state (“01” data) to the data of the “St14” state (“0110” data).

[0097] In the following, the stage where the second write operation is performed is called the Fine stage.

[0098] (b-1-3) Execution sequence of write operations FIG. 9 shows an example of the selection order of word lines WL and string units SU when data is written to a certain block BLK. A solid-line rectangular frame corresponding to the intersection of each word line WL and each string unit SU indicates one cell unit CU. The upper part of the rectangular frame separated by a dashed line indicates the write operation of the MLC stage. The lower part of the rectangular frame separated by a dashed line indicates the write operation of the Fine stage. The numbers in the upper and lower parts of the rectangular frame indicate the execution order (hereinafter referred to as the "write order") of the MLC program and the Fine program to multiple memory cells MC in each cell unit CU of a certain block BLK.

[0099] As shown in FIG. 9, the sequencer 36 executes a first write operation as the first to fifth operations by selecting the word line WL0 and sequentially selecting the string units SU0, . . . , SU4.

[0100] As a sixth operation, the sequencer 36 selects the string unit SU0 and executes a first write operation by selecting the word line WL1. As a seventh operation, the sequencer 36 selects the string unit SU0 and executes a second write operation by selecting the word line WL0.

[0101] As the 8th to 15th operations, the sequencer 36 selects string units SU1, ..., SU4 in order, and alternately performs a first write operation selecting word line WL1 and a second write operation selecting word line WL0 in the same procedure as the 6th and 7th operations.

[0102] As the 16th to 25th operations, the sequencer 36 selects string units SU0, ..., SU4 in sequence, similar to the 6th to 15th operations, and alternately performs a first write operation selecting word line WL2 and a second write operation selecting word line WL1.

[0103] Similarly, the sequencer 36 sequentially selects the string units SU0, . . . , SU4 as the (26+10p)th to (35+10p)th operations, and alternately executes a first write operation selecting the word line WL(3+p) and a second write operation selecting the word line WL(2+p), where p is an integer equal to or greater than 0.

[0104] In the above-mentioned order, the first write operation and the second write operation are sequentially executed on the cell unit CU designated by the address (hereinafter also referred to as the selection address) to which data is to be written.

[0105] The NAND memory 30 performs a second write operation (MLC program) and a second write operation (Fine program) for a cell unit CU specified by a selected address without performing an erase operation for the block BLK containing the cell unit CU.

[0106] (b-2) Data loading method The data loading method in a write operation will be described with reference to FIGS.

[0107] As described above, in the second write operation (Fine program), the Lower page data and the Middle page data are prepared inside the NAND memory 30 by the IDL, or are prepared outside the NAND memory 30 by the EDL.

[0108] (b-2-1)IDL With reference to FIG. 10, the IDL during fine programming in the memory system 1 of this embodiment will be described.

[0109] FIG. 10 is a sequence diagram for explaining the IDL in the Fine program.

[0110] As shown in FIG. 10, the memory system 1 of the embodiment executes the MLC program (first write operation) before executing the Fine program (second write operation).

[0111] In the MLC program, the SoC 100 of the memory controller 10 loads the lower page data and the middle page data from the RAM 16. The RAM 16 stores the lower page data and the middle page data received from the host 2.

[0112] For the MLC program, the SoC 100 sends the lower page data and middle page data loaded from the RAM 16, together with a command and an address, to the NAND memory 30. As a result, the sense amplifier module 39 of the NAND memory 30 receives the lower page data and middle page data via the data latch 40 (referred to as data in).

[0113] The NAND memory 30 programs the lower page data and middle page data in the sense amplifier module 39 into the cell unit CU specified by the address received from the NAND interface circuit 17. As a result, the memory cell array 31 stores two pages of data, the lower and middle page data.

[0114] As described above, the MLC program in the memory system 1 of this embodiment is completed.

[0115] The memory system 1 of the embodiment executes the Fine program for the cell unit CU specified by the address at which the MLC program is executed.

[0116] The SoC 100 loads the Upper page data and the Top page data from the RAM 16. The RAM 16 stores the Upper page data and the Top page data received from the host 2.

[0117] During Fine programming using the IDL, the SoC 100 sends the Upper page data and Top page data loaded from the RAM 16, together with a command and an address, to the NAND memory 30 without transferring the Lower / Middle page data to the NAND memory 30. As a result, the sense amplifier module 39 receives the Upper page data and Top page data.

[0118] When a Fine program using the IDL is executed, the Lower / Middle page data is loaded from the memory cell array 31 to the sense amplifier module 39 inside the NAND memory 30.

[0119] As a result, the sense amplifier module 39 holds the Upper / Top page data from the SoC 100 and the Lower / Middle page data from the memory cell array 31 .

[0120] The NAND memory 30 programs the Lower page data, Middle page data, Upper page data, and Top page data in the sense amplifier module 39 into the cell unit CU specified by the address received from the NAND interface circuit 17. As a result, the memory cell array 31 stores four pages of data: Lower / Middle / Upper / Top page data.

[0121] As described with reference to FIG. 10, the IDL prepares the lower page data and middle page data to be used in the fine program by reading the lower page data and middle page data from the memory cell array 31 to the sense amplifier module 39 inside the NAND memory 30.

[0122] (b-2-2) EDL The EDL at the time of fine programming in the memory system 1 of this embodiment will be described with reference to FIG. 11 and FIG.

[0123] The EDL used for the Fine program prepares Lower / Middle page data from the RAM 16. The EDL may further include ECC processing for the Lower / Middle page data.

[0124] As shown in FIG. 11, the Lower page data and the Upper page data are programmed in the memory cell array 31 by the MLC program, similarly to the example of FIG.

[0125] When executing the Fine program, the SoC 100 loads the Upper / Top page data provided by the host 2 from the RAM 16 .

[0126] As described above, the EDL prepares the Lower page data and the Middle page data outside the NAND memory 30.

[0127] 11, the RAM 16 holds Lower / Middle page data provided by the host 2. This Lower / Middle page data is the same as the Lower / Middle page data stored in the cell unit CU designated by the selection address where the Fine program is executed. The NAND interface circuit 17 loads the Lower / Middle page data from the RAM 16.

[0128] The SoC 100 sends the Lower / Middle / Upper / Top page data loaded from the RAM 16, together with a command and an address, to the NAND memory 30. As a result, the sense amplifier module 39 receives the Lower / Middle / Upper / Top page data.

[0129] The NAND memory 30 programs the Lower / Middle / Upper / Top page data in the sense amplifier module 39 into the cell unit CU specified by the address received from the NAND interface circuit 17. As a result, the memory cell array 31 stores four pages of Lower / Middle / Upper / Top page data.

[0130] FIG. 12 shows a data loading method of the EDL that is different from the example of FIG.

[0131] As shown in FIG. 12, the Lower page data and the Upper page data are programmed in the memory cell array 31 by the MLC program, similarly to the examples of FIGS.

[0132] 12, when execution of the Fine program is requested, the memory controller 10 (SoC100) reads the lower page data and the middle page data from the cell unit CU specified by the corresponding address of the NAND memory 30. The ECC circuit 14 of the SoC100 performs ECC processing on the lower page data and the middle page data. As a result, the ECC-processed lower page data and the middle page data are generated.

[0133] The SoC 100 sends the ECC-processed Lower / Middle page data to the NAND memory 30. The sense amplifier module 39 receives the ECC-processed Lower / Middle page data. The ECC-processed Lower / Middle page data may be stored in the RAM 16 before being sent to the sense amplifier module 39.

[0134] The SoC 100 loads the Upper / Top page data from the RAM 16. The SoC 100 sends the Upper / Top page data, along with a command and an address, to the NAND memory 30. The sense amplifier module 39 receives the Upper / Top page data.

[0135] The NAND memory 30 programs the Lower / Middle / Upper / Top page data in the sense amplifier module 39 into the cell unit CU specified by the address received from the NAND interface circuit 17. As a result, the memory cell array 31 stores four pages of Lower / Middle / Upper / Top page data.

[0136] A Fine program using the EDL of either Fig. 11 or Fig. 12 can be applied to the memory system 1. For example, when the RAM 16 has a large storage capacity, the memory system 1 is configured to execute the Fine program of the example of Fig. 11. Note that the memory system 1 may be configured to be able to switch the method of the Fine program to be executed between the example of Fig. 11 and the example of Fig. 12 depending on a request from the host 2 or the operating status of the memory system 1.

[0137] As described with reference to FIGS. 11 and 12, in the EDL, the Lower page data and the Middle page data used in the Fine program are prepared outside the NAND memory 30.

[0138] (b-3) Command sequence The command sequence of the memory system 1 of the present embodiment will be described with reference to FIGS. 13 to 15B.

[0139] (b-3-1) Command sequence for the first write operation FIG. 13 is a diagram showing a command sequence of the first write operation (MLC program) in the memory system 1 of the present embodiment.

[0140] As shown in FIG. 13, when the memory controller 10 instructs the NAND memory 30 to execute an MLC program, the memory controller 10 sends a plurality of command sets 500 (500-1, 500-2) to the NAND memory 30 in a stage (MLC stage) for executing the MLC program.

[0141] The memory controller 10 sends a command set 500-1 to the NAND memory 30. The command set 500-1 is a group of signals related to writing Lower page data.

[0142] The command set 500-1 includes commands 501, 502-1, 503, and 507, addresses 504 (504-1 and 504-2) and 505 (505-1, 505-2, 505-3, and 505-4), and write data 506-1.

[0143] The commands 501, 502-1, and 503 include command codes "A1h", "01h", and "80h", respectively. The NAND memory 30 receives the commands 501, 502-1, and 503. The command 501 with the command code "A1h" is a prefix command that is added when instructing a write operation in the MLC stage (or a read operation from a memory cell MC in the MLC state). The command 502-1 with the command code "01h" is a command that instructs the NAND memory 30 to perform an operation corresponding to the data of the first page (Lower page). The command 503 with the command code "80h" is a command that indicates the start of input of the address to be written.

[0144] After transmitting the command 503 with the command code "80h", the memory controller 10 transmits addresses 504 and 505 to the NAND memory 30. The address 504 includes addresses 504-1 and 504-2. The address 505 includes addresses 505-1, 505-2, 505-3, and 505-4. The NAND memory 30 receives the addresses 504 and 505. The addresses 504-1 and 504-2 are column addresses. The addresses 505-1, 505-2, 505-3, and 505-4 are row addresses. The column address 504 is transmitted in two cycles. The row address 505 is transmitted in four cycles. The number of cycles for transmitting each address is appropriately changed depending on the size of the memory cell array 31 (e.g., the number of blocks BLK and the number of word lines WL).

[0145] After transmitting the addresses 504 and 505, the memory controller 10 transmits the lower page data 506-1 as write data to the NAND memory 30. The NAND memory 30 receives the lower page data 506-1.

[0146] After transmitting the lower page data 506-1, the memory controller 10 transmits a command 507 having a command code “1Ah” to the NAND memory 30. The NAND memory 30 receives the command 507. The command 507 having the command code “1Ah” is a command for instructing the transfer of data from the data latch 40 in the NAND memory 30 to the sense amplifier module 39.

[0147] After the NAND memory 30 receives the command 507 with the command code "1Ah", the NAND memory 30 goes into a busy state. Accordingly, the NAND memory 30 changes the signal level of the ready / busy signal RBn from the "H" level to the "L" level.

[0148] During the period in which the ready / busy signal RBn is at the “L” level, the lower page data 506 - 1 is transferred from the data latch 40 to the sense amplifier module 39 .

[0149] After the sense amplifier module 39 holds the lower page data 506-1, the NAND memory 30 enters a ready state. Accordingly, the NAND memory 30 changes the signal level of the ready / busy signal RBn from the "L" level to the "H" level.

[0150] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-2 to the ready state NAND memory 30. The command set 500-2 is a group of signals related to writing Middle page data.

[0151] The command set 500-2 includes commands 502-2, 503, and 508, addresses 504 and 505, and write data 506-2.

[0152] The commands 502-2 and 503 include command codes "02h" and "80h", respectively. The NAND memory 30 receives the commands 502-2 and 503. The command 502-2 with the command code "02h" is a command to instruct the NAND memory 30 to perform an operation corresponding to the data of the second page (Middle page).

[0153] After transmitting the command 503 with the command code "80h", the memory controller 10 sends addresses 504 and 505 to the NAND memory 30. The NAND memory 30 receives the addresses 504 and 505. The values ​​of the addresses 504 and 505 included in the command set 500-2 are the same as the values ​​of the addresses 504 and 505 included in the command set 500-1.

[0154] After transmitting the addresses 504 and 505, the memory controller 10 transmits the Middle page data 506-2 as write data to the NAND memory 30. The NAND memory 30 receives the Middle page data 506-2.

[0155] After transmitting the Middle page data 506-2, the memory controller 10 transmits a command 508 with a command code "10h" to the NAND memory 30. The NAND memory 30 receives the command 508. The command 508 with a command code "10h" is a command to instruct the execution of a program operation.

[0156] The NAND memory 30 executes writing (MLC program) of the Lower / Middle page data in the sense amplifier module 39 based on receiving the command 508 with the command code "10h". The NAND memory 30 enters a busy state during the execution of the MLC program. The NAND memory 30 changes the signal level of the ready / busy signal RBn from the "H" level to the "L" level during the period tPROG during which the MLC program is executed.

[0157] During a period tPROG during which the ready / busy signal RBn is at the "L" level, two pages of data are written to the cell unit CU designated by the address in the memory cell array 31 to which data is to be written.

[0158] Upon completion of the MLC program, the NAND memory 30 enters a ready state, and accordingly, the NAND memory 30 changes the signal level of the ready / busy signal RBn from the "L" level to the "H" level.

[0159] As described above, the memory system 1 of this embodiment can execute the MLC program based on the command sequence of FIG.

[0160] (b-3-2) Command sequence for the second write operation When writing of Upper / Top page data is requested to an address storing Lower / Middle page data, a second write operation (Fine program) is executed to that address based on the command sequence of FIG. 14, or FIG. 15A or FIG. 15B.

[0161] (b-3-2-1) Command sequence for second write operation using IDL FIG. 14 is a diagram showing a command sequence of a Fine program using IDL in the memory system 1 of this embodiment.

[0162] When data is written to an address where the MLC program has been executed by the command sequence of FIG. 14, the memory system 1 of this embodiment executes the Fine program to that address.

[0163] As shown in FIG. 14, when the memory controller 10 instructs the NAND memory 30 to execute a Fine program using IDL, the memory controller 10 sends a plurality of command sets 500 (500-3, 500-4) for executing the Fine program to the NAND memory 30 in the stage for executing the Fine program (Fine stage).

[0164] In this embodiment, to notify the selection of IDL in the Fine program, the memory controller 10 sends a signal 555 to the NAND memory 30. The NAND memory 30 receives the signal 555. The signal 555 is a flag (setting value) or a prefix command indicating that the data loading method used in the Fine program is IDL. The signal 555 is a signal of 1 or more bits.

[0165] After transmitting the signal 555, the memory controller 10 transmits a command set 500-3 to the NAND memory 30. The command set 500-3 is a group of signals related to writing the upper page data.

[0166] The command set 500-3 includes commands 502-3, 503, and 507, addresses 504 (504-1 and 504-2) and (505-1, 505-2, 505-3, and 505-4), and write data 506-3.

[0167] The commands 502-3 and 503 include command codes "03h" and "80h", respectively. The NAND memory 30 receives the commands 502-3 and 503. The command 502-3 with the command code "03h" is a command to instruct the NAND memory 30 to perform an operation corresponding to the data of the third page (Upper page).

[0168] After transmitting the command 503 with the command code "80h", the memory controller 10 sends addresses 504 and 505 to the NAND memory 30. The NAND memory 30 receives the addresses 504 and 505. For example, the values ​​of the addresses 504 and 505 included in the command set 500-3 are the same as the values ​​of the addresses 504 and 505 included in the command sets 500-1 and 500-2 used in the MLC program.

[0169] After transmitting the addresses 504 and 505, the memory controller 10 transmits the Upper page data 506-3 as write data to the NAND memory 30. The NAND memory 30 receives the Upper page data 506-3.

[0170] After transmitting the upper page data 506-3, the memory controller 10 transmits a command 507 with a “command code 1Ah” to the NAND memory 30. The NAND memory 30 receives the command 507.

[0171] After the NAND memory 30 receives the command 507 with the command code "1Ah", the NAND memory 30 goes into a busy state.

[0172] During the period in which the signal level of the ready / busy signal RBn is at the “L” level, the upper page data 506 - 3 is transferred from the data latch 40 in the NAND memory 30 to the sense amplifier module 39 .

[0173] After the sense amplifier module 39 holds the upper page data 506-3, the NAND memory 30 enters a ready state.

[0174] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-4 to the ready state NAND memory 30. The command set 500-4 is a group of signals related to writing the Top page data.

[0175] Command set 500-4 includes commands 502-4, 503, and 508, addresses 504 and 505, and write data 506-4.

[0176] The commands 502-4 and 503 include command codes "04h" and "80h", respectively. The NAND memory 30 receives the commands 502-4 and 503. The command 502-4 with the command code "04h" is a command to instruct the NAND memory 30 to perform an operation corresponding to the data of the fourth page (Top page).

[0177] After transmitting the command 503 with the command code "80h", the memory controller 10 sends addresses 504 and 505 to the NAND memory 30. The NAND memory 30 receives the addresses 504 and 504. The values ​​of the addresses 504 and 505 included in the command set 500-4 are the same as the values ​​of the addresses 504 and 505 included in the command sets 500-1, 500-2, and 500-3.

[0178] After transmitting the addresses 504 and 505, the memory controller 10 transmits the Top page data 506-4 as write data to the NAND memory 30. The NAND memory 30 receives the Top page data 506-4.

[0179] After transmitting the Top page data 506-4, the memory controller 10 transmits a command 508 having a command code “10h” to the NAND memory 30. The NAND memory 30 receives the command 508.

[0180] For example, in the Fine stage using IDL, the Lower / Middle page data is loaded from the memory cell array 31 to the sense amplifier module 39 after the transfer of the command sets 500-3 and 5004 relating to the Upper / Top page data.

[0181] Upon receiving command 508 with command code “10h”, the NAND memory 30 executes writing (fine program) of Lower / Middle / Upper / Top page data in the sense amplifier module 39. Upon receiving command 508 with command code “10h”, the NAND memory 30 enters a busy state.

[0182] During a period tPROG during which the ready / busy signal RBn is at the "L" level, four pages of data are written to the cell unit CU designated by the address of the memory cell array 31 to which data is to be written.

[0183] Upon completion of the Fine program, the NAND memory 30 becomes ready.

[0184] As described above, the Fine program using IDL in the memory system 1 of this embodiment is completed.

[0185] In this way, the memory system 1 of this embodiment can execute a Fine program using IDL based on the command sequence of FIG.

[0186] (b-3-2-2) Command sequence for second write operation using EDL FIG. 15A is a diagram showing a command sequence of a Fine program using an EDL in the memory system 1 of this embodiment.

[0187] When the Lower / Middle page data prepared by the EDL is generated by ECC processing (see FIG. 12), the memory system 1 executes reading of the Lower / Middle page data from the NAND memory 30.

[0188] As shown in FIG. 15A, in the Fine stage using the EDL, the memory controller 10 sends to the NAND memory 30 a set of multiple commands 700 (700-1, 700-2) for reading Lower / Middle page data from the NAND memory 30.

[0189] The memory controller 10 sends a command set 700-1 to the NAND memory 30. The command set 700-1 is a group of signals related to reading lower page data from the memory cell array 31 to the sense amplifier module 39.

[0190] The command set 700-1 includes commands 501, 502-1, 701, and 702, and addresses 504 and 505.

[0191] The commands 501, 502-1, and 701 include command codes “A1h”, “01h”, and “00h”, respectively. The NAND memory 30 receives the commands 501, 502-1, and 701. The command 701 with the command code “00h” is a command indicating the start of input of the address to be read.

[0192] After transmitting the command 701 with the command code “00h”, the memory controller 10 transmits addresses 504 and 505 from which the Lower page data is to be read to the NAND memory 30. The NAND memory 30 receives the addresses 504 and 505.

[0193] After transmitting the addresses 504 and 505, the memory controller 10 transmits a command 702 with a command code "30h" to the NAND memory 30. The NAND memory 30 receives the command 702. The command 702 with the command code "30h" is a command that instructs the NAND memory 30 to output data of the address to be read from the memory cell array 31 to the data latch 40 (sense amplifier module 39).

[0194] After the NAND memory 30 receives the command 702 with the command code “30h”, the NAND memory 30 enters a busy state. The NAND memory 30 reads out the Lower page data from the cell units CU indicated by the addresses 504 and 505 to the sense amplifier module 39 during a period tR.

[0195] The NAND memory 30 becomes ready after the sense amplifier module 39 holds the lower page data.

[0196] After the signal level of the ready / busy signal RBn changes from the “L” level to the “H” level, the memory controller 10 sends a command set 700-2 to the NAND memory 30. The command set 700-2 is a group of signals related to the transfer of data from the NAND memory 30 to the memory controller 10.

[0197] The command set 700-2 includes commands 703 and 704 and addresses 504 and 505.

[0198] The memory controller 10 sends a command 703 with a command code “05h” to the NAND memory 30. The command 703 with a command code “05h” is a command to instruct the NAND memory 30 to output data starting from the specified column address 504 from the data latch 40 to the memory controller 10 (cache read).

[0199] After transmitting the command 703 with the command code "05h", the memory controller 10 transmits the addresses 504 and 505 to the NAND memory 30. The values ​​of the addresses 504 and 505 in the command set 700-2 are the same as the values ​​of the addresses 504 and 505 in the command set 700-1.

[0200] After transmitting the addresses 504 and 505, the memory controller 10 transmits a command 704 with a command code “E0h” to the NAND memory 30. The command 704 with the command code “E0h” is a command that instructs the NAND memory 30 to output data to the memory controller 10.

[0201] The NAND memory 30 sequentially receives the command 703, the addresses 504 and 505, and the command 704. Based on the commands 703 and 704 with command codes "05h" and "E0h", the NAND memory 30 sends the lower page data 705-1 in the sense amplifier module 39 to the memory controller 10 via the data latch 40. The memory controller 10 receives the lower page data 705-1.

[0202] After receiving the read Lower page data 705-1, the memory controller 10 sends a command set 700-3 to the NAND memory 30. The command set 700-3 is a group of signals related to reading Middle page data from the memory cell array 31 to the sense amplifier module 39.

[0203] The command set 700-3 includes commands 501, 502-2, 701, and 702, and addresses 504 and 505.

[0204] Similar to the reading of the Lower page data in response to the command set 700-1, after the sense amplifier module 39 holds the Middle page data in response to the command set 700-3, the NAND memory 30 enters a ready state.

[0205] After the signal level of the ready / busy signal RBn changes to the “H” level, the memory controller 10 sends a command set 700-4 to the NAND memory 30. The command set 700-4 includes commands 703 and 704 and addresses 504 and 505.

[0206] Similar to the reading of the Lower page data in response to the command set 700-2, in response to the command set 700-4, the NAND memory 30 sends the Middle page data 705-2 to the memory controller 10. The memory controller 10 receives the Middle page data 705-2.

[0207] The memory controller 10 performs ECC processing on each of the received Lower page data 705-1 and Middle page data 705-2.

[0208] By performing the ECC processing, ECC-processed lower page data and middle page data are generated.

[0209] After the ECC processing, the memory controller 10 executes writing (Fine program) of the Lower / Middle / Upper / Top page data.

[0210] For example, in this embodiment, to notify the selection of the EDL in the Fine program, the memory controller 10 sends a signal 777 to the NAND memory 30. The NAND memory 30 receives the signal 777. The signal 777 is a flag or a prefix command indicating that the data loading method used in the Fine program is the EDL. The signal 777 is a signal of 1 or more bits.

[0211] As a result, in this embodiment, the memory controller 10 can notify the NAND memory 30 of the execution of the Fine program using the EDL.

[0212] After transmitting the signal 777, the memory controller 10 transmits a command set 500-A related to the lower page data to the NAND memory 30. The command set 500-A includes the same commands, addresses, and write data as the command set 500-1 described with reference to FIG. 13. However, the command set 500-A does not include the command 501 with the command code "A1h". The write data 506-A included in the command set 500-A is the lower page data after ECC processing. The signal 777 may be a signal (command) included in the command set 500-A. The NAND memory 30 receives the command set 500-A.

[0213] Similar to the operation described with reference to FIG. 13, after receiving command 507 with command code “1Ah” included in command set 500-A, the NAND memory 30 stores the ECC-processed lower page data 506-A in the sense amplifier module 39.

[0214] After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-B for the Middle page data to the NAND memory 30. The command set 500-B includes the same commands, addresses, and write data as the command set 500-2 described with reference to FIG. 13. However, the write data 506-B included in the command set 500-B is the Middle page data after ECC processing. The NAND memory 30 receives the command set 500-B.

[0215] Similar to the operation described with reference to FIG. 13, after receiving command 507 with command code “1Ah” included in command set 500-B, the NAND memory 30 stores the post-ECC-processed Middle page data 506-B in the sense amplifier module 39.

[0216] After the signal level of the ready / busy signal RBn changes from the “L” level to the “H” level, the memory controller 10 sends a command set 500-C related to the Upper page data to the NAND memory 30. The command set 500-C includes a command, an address, and write data similar to the command set 500-3 described with reference to FIG.

[0217] Similar to the operation described with reference to FIG. 14, the NAND memory 30 stores the upper page data 506-C in the sense amplifier module 39 after receiving the command 507 with the command code "1Ah" included in the command set 500-C.

[0218] After the signal level of the ready / busy signal RBn changes from the “L” level to the “H” level, the memory controller 10 sends a command set 500-D for the Top page data 506-D to the NAND memory 30. The command set 500-D includes a command, an address, and write data similar to the command set 500-4 described with reference to FIG.

[0219] Similar to the operation described with reference to FIG. 14, the NAND memory 30 writes the Lower / Middle / Upper / Top page data in the sense amplifier module 39 to the memory cell array 31 by the Fine program based on command 508 with command code “10h” included in command set 500-D.

[0220] As described above, the Fine program using the EDL in the memory system 1 of this embodiment is completed.

[0221] Furthermore, when the memory controller 10 transfers Lower page data and Middle page data from the RAM 16 to the NAND memory 30, the memory system 1 of this embodiment executes a Fine program using an EDL based on command sets 500-A, 500-B, 500-C, and 500-D without performing operations based on command sets 700-1, 700-2, 700-3, and 700-4.

[0222] In this way, the memory system 1 of this embodiment can execute a Fine program using an EDL based on the command sequence of FIG. 15A.

[0223] FIG. 15B shows a modified example of the command sequence of the Fine program using the EDL in the memory system 1 of this embodiment.

[0224] As shown in FIG. 15B, the ECC-processed Lower page data 506-A may be sent from the RAM 16 to the NAND memory 30 before reading the Middle page data. After the ECC-processed Lower page data 506-A is sent to the NAND memory 30 by the command set 500-A, the Middle page data 705-2 is sent from the NAND memory 30 to the memory controller 10 by a read operation according to the command sets 700-3 and 700-4. The memory controller 10 performs ECC processing on the Middle page data 705-2. The memory controller 10 sends the ECC-processed Middle page data 506-B to the NAND memory 30 by the command set 500-B. After this, the memory controller 10 sends the Upper page data 506-C and the Top page data 506-D to the NAND memory 30.

[0225] (b-4) Processing flow for write operation The process flow of a write operation in the memory system 1 of this embodiment will be described with reference to FIGS.

[0226] (b-4-1) Basic flow of write operation FIG. 16 is a flowchart for explaining the write operation in the memory system 1 of the present embodiment.

[0227] The memory controller 10 receives a write request from the host 2 (S1). The memory controller 10 determines to write the data requested to be written as Lower page data and Middle page data to the NAND memory 30 in accordance with the write order described with reference to FIG.

[0228] The memory controller 10 sends a command set for executing an MLC program (first write operation) to the NAND memory 30 based on the write request (S2).

[0229] The NAND memory 30 executes the MLC program in response to the command set from the memory controller 10 (S3). As a result, the Lower page data and the Middle page data are written to the memory cell array 31 of the NAND memory 30.

[0230] The memory controller 10 receives a write request from the host 2 (S4). The memory controller 10 determines to write the data requested to be written as Upper page data and Top page data to the NAND memory 30 (the address where the MLC program was executed) according to the write order described with reference to Fig. 9, for example. The memory controller 10 prepares to execute the Fine program (second write operation).

[0231] The memory controller 10 determines (S5) which data loading method to use, IDL or EDL, based on an index related to the reliability of the Lower page data and Middle page data stored in the NAND memory 30 when executing the Fine program. The memory controller 10 selects either the IDL or EDL based on the index (S6).

[0232] For example, in this embodiment, either the IDL or the EDL is selected based on the period from the completion of the MLC program to the start of the Fine program.

[0233] When the memory controller 10 determines that IDL is to be used as the data loading method for the Fine program (YES in S6), the memory controller 10 sends a command set instructing the execution of the Fine program using IDL to the NAND memory 30 (S7A).

[0234] The NAND memory 30 executes a Fine program using IDL based on the command set from the memory controller 10 (S8A).

[0235] When the memory controller 10 determines that the EDL is to be used as the data loading method for the Fine program (NO in S6), the memory controller 10 sends a command set instructing the execution of the Fine program using the EDL to the NAND memory 30 (S7B).

[0236] The NAND memory 30 executes the Fine program using the EDL based on the command set from the memory controller 10 (S8B).

[0237] After the execution of the Fine program in the NAND memory 30, the memory system 1 ends its operation.

[0238] (b-4-2) Specific Example of the First Write Operation As described above, the memory system 1 of this embodiment selects the data loading method when executing the Fine program based on the index of reliability of the Lower / Middle page data at the start of the Fine program.

[0239] Fig. 17 is a flowchart showing an example of operation during MLC programming in the memory system 1 of this embodiment. Fig. 18 is a diagram for explaining an example of operation during MLC programming in the memory system 1 of this embodiment.

[0240] As shown in FIG. 17, the memory system 1 of this embodiment starts managing information related to an index used to select a data loading method when executing an MLC program and a Fine program.

[0241] The memory controller 10 instructs the NAND memory 30 to execute the MLC program (S100). As a result, the MLC program is executed in the NAND memory 30.

[0242] The processor 12 of the memory controller 10 detects the completion of the MLC program in response to, for example, a change in the ready / busy signal RBn from the "L" level to the "H" level. The processor 12 notifies the data load selector 181 of the write management circuit 18 of the completion of the MLC program. For example, as shown in FIG. 18, the processor 12 sends a notification signal ACK1 indicating the completion of the MLC program to the data load selector 181.

[0243] The data load selector 181 receives a notification signal ACK1 notifying completion of the MLC program (S101 in FIG. 17).

[0244] The data load selector 181 receives the MLC program completion time t based on the MLC program completion notification signal ACK1. MLC The current time regarded as the current time is obtained from the global clock 182 of the write management circuit 18 (S102).

[0245] As shown in FIG. 18, the data load selector 181 receives the number of the word line WL to be programmed in the MLC program, the number of the string unit SU to be programmed in the MLC program, and the acquired MLC program completion time t MLCis recorded in a management table (MLC program log table) TBL1 relating to the MLC program in the RAM 16 (S103 in FIG. 17).

[0246] In this way, the memory system 1 of the present embodiment can obtain information (here, the MLC program completion time t MLC ) can be obtained.

[0247] As described above, the processing of each part of the memory controller 10 during MLC programming is completed.

[0248] (b-4-3) Specific example of the second write operation Fig. 19 is a flowchart showing an example of operation during fine programming of the memory system 1 of this embodiment. Fig. 20 is a diagram for explaining an example of operation during fine programming of the memory system 1 of this embodiment.

[0249] As shown in FIG. 19, the memory system 1 of this embodiment starts various processes for selecting a data loading method when the Fine program is executed.

[0250] The memory system 1 determines to execute a Fine program for a certain address (S110).

[0251] When execution of the Fine program is determined in the memory system 1, the processor 12 notifies the data load selector 181 of the execution of the Fine program. For example, as shown in Fig. 20, the processor 12 sends a notification signal ACK2 indicating the execution of the Fine program to the data load selector 181. The data load selector 181 receives the notification signal ACK2.

[0252] The data load selector 181 selects the current time before the start of the Fine program (the time immediately before the start of the Fine program) t cis obtained from the global clock 182 (S111 in FIG. 19).

[0253] The data load selector 181 selects the MLC program completion time t associated with the number of the word line WL targeted for the fine program and the number of the string unit SU. MLC From among multiple entries in the MLC program log table TBL1, the data load selector 181 searches for the MLC program completion time t MLC (S112).

[0254] The data load selector 181 is the current time t c and the obtained MLC program completion time t MLC For example, the data load selector 181 executes a calculation process using the current time t c and MLC program completion time t MLC Subtraction process with (Dx=t c -t MLC As a result, the data load selector 181 acquires the elapsed time Dx from the completion of the MLC program at the corresponding address to the present as the result (difference value) Dx of the calculation process (S113).

[0255] When the difference value (elapsed time) Dx is a relatively large value, the large difference value Dx indicates that a relatively long time has passed since the completion of the MLC program, and when the difference value Dx is a relatively small value, the small difference value Dx indicates that a relatively short time has passed since the completion of the MLC program.

[0256] Generally, in a NAND flash memory, the reliability of data stored in a memory cell decreases with the passage of time.

[0257] The data loading selector 181 compares the elapsed time Dx with a threshold value Dth for selecting a data loading method. For example, the data loading selector 181 determines whether the elapsed time Dx is greater than the threshold value Dth (S114).

[0258] If the elapsed time Dx is greater than the threshold value Dth (YES in S114), the data load selector 181 selects EDL as the data load method for the Lower / Middle page data used in the Fine program (S115).

[0259] If the elapsed time Dx is equal to or less than the threshold value Dth (NO in S114), the data load selector 181 selects IDL as the data load method for the Lower / Middle page data used in the Fine program (S116).

[0260] The processor 12 (or the write management circuit 18) notifies the NAND memory 30 of the selection result of the data load selector 181 by sending a flag or a prefix command such as the above-mentioned signals 555 and 777 (S117). The processor 12 sends to the NAND memory 30 a set of commands corresponding to the selected data load method.

[0261] As a result, the memory controller 10 instructs the NAND memory 30 to execute the Fine program using the selected data load method of IDL or EDL. The NAND memory 30 executes the Fine program using the Lower / Middle page data prepared by the selected data load method.

[0262] As described above, the processing of each part of the memory controller 10 during the Fine program ends.

[0263] In this manner, the memory system 1 of the present embodiment selects either the IDL or the EDL using the elapsed time Dx from the completion of the MLC program as an index of data reliability. This allows the memory system 1 of the present embodiment to achieve high write performance of the memory system and high reliability of data stored in the memory system.

[0264] (c) Modifications A modification of the memory system 1 of the present embodiment will be described with reference to FIGS.

[0265] (c-1) Variation 1 FIG. 21 is a block diagram for explaining a modified example of the memory system 1 of the present embodiment.

[0266] The memory system 1 of the first modification of this embodiment selects the data load method during fine programming, taking into consideration the temperature of the memory system 1.

[0267] Data errors are likely to occur when the temperature of the memory system 1 is high or when there is a large temperature change between the write operation and the read operation of the memory system 1. Therefore, the reliability of data may change depending on the temperature of the memory system 1.

[0268] 21, the NAND memory 30 includes a temperature sensor 43. The MLC program log table TBL1A stores the chip temperature T MLCchip It further includes a field for recording:

[0269] For example, the write management circuit 18 may MLCchip Based on this, the magnitude of the criterion value for the index of data reliability (for example, the threshold value Dth for the elapsed time Dx) is adjusted.

[0270] The data load selector 181 detects the MLC program completion time t MLCIn parallel with the acquisition of the chip temperature T MLCchip is acquired from the temperature sensor 43.

[0271] The data load selector 181 receives the acquired chip temperature T MLCchip The MLC program completion time t MLC At the same time, it is recorded in the corresponding entry of the MLC program log table TBL1A.

[0272] The data load selector 181 (or the processor 12) receives the acquired chip temperature T MLCchip Based on this, the threshold Dth for selecting the data loading method is adjusted.

[0273] An example of the adjustment of the threshold value Dth is as follows.

[0274] The data load selector 181 is MLCchip , two thresholds T H ,T L Compare with the threshold T H is the threshold value for the high temperature side. L is the threshold value for the low temperature side. MLCchip is the threshold T H If the chip temperature T MLCchip is the threshold T L If it is lower, the data load selector 181 reduces the value of the threshold Dth for the elapsed time Dx from the initial setting value. By reducing the threshold Dth in this way, the EDL is selected with a shorter elapsed time Dx.

[0275] Another example of the adjustment of the threshold value Dth is as follows.

[0276] When the fine program is executed, the data load selector 181 selects the chip temperature T x The data load selector 181 acquires the chip temperature T MLCchip and the current chip temperature Tx The temperature difference (here, denoted as D1) is calculated by subtracting the temperature difference D1 from the elapsed time Dx. The data load selector 181 compares the temperature difference D1 with a certain reference value (here, denoted as a threshold value D2). If the temperature difference D1 is greater than the threshold value D2, the data load selector 181 reduces the value of the threshold value Dth for the elapsed time Dx to a value less than the initial setting value. This causes the EDL to be selected at a shorter elapsed time Dx.

[0277] Furthermore, the chip temperature T MLCchip and the current chip temperature T x The temperature difference D1 may have a positive value or a negative value depending on the magnitude relationship with the chip temperature T MLCchip and the current chip temperature T x It may be expressed as the absolute value of the difference between the two.

[0278] In this modification, an example is described in which the method of loading the Lower / Middle page data in the Fine program is selected taking into consideration both the time during which the memory cell MC stores data and the temperature of the memory system 1 (more specifically, the temperature of the NAND memory 30). However, the memory system 1 of this embodiment may select the method of loading the Lower / Middle page data in the Fine program based only on the temperature of the memory system 1. For example, when the temperature of the memory system 1 is higher than the threshold value, the data load selector 181 selects the method of loading the Lower / Middle page data in the Fine program based on the MLC program completion time t MLC For example, when the temperature of the memory system 1 is equal to or lower than the threshold, the data load selector 181 selects the EDL without comparing the elapsed time Dx corresponding to the MLC program completion time t MLC The IDL is selected without comparing the elapsed time Dx corresponding to the IDL with the threshold value Dth.

[0279] In this way, the memory system 1 of the present embodiment can select the more appropriate one of the IDL and the EDL, taking into consideration the effect of the temperature of the NAND memory 30 on the reliability of data.

[0280] (c-2) Variation 2 FIG. 22 is a diagram for explaining the second modification of the memory system 1 of the present embodiment.

[0281] The multiple chips included in the NAND memory 30 have variations in characteristics. The multiple blocks included in the memory cell array 31 have variations in characteristics. The memory cells MC connected to the multiple word lines WL included in each block have variations in characteristics. For this reason, the data error rate varies among the multiple chips, the multiple blocks, and the multiple word lines.

[0282] In the memory system 1 according to the second variant of this embodiment, a threshold value for selecting a data loading method during fine programming is set on a chip-by-chip, block-by-block, or word-line basis, taking into account variations in error rates among multiple chips, multiple blocks, and multiple word lines.

[0283] For example, as shown in (a) of Fig. 22, the threshold Dth may be set for each block BLK. In this case, the threshold Dth_BLK0 is set for the block BLK0, and the threshold Dth_BLKi is set for the block BLKi. i is an integer equal to or greater than 0. The value of the threshold Dth_BLK0 may be the same as or different from the value of the threshold Dth_BLKi.

[0284] 22(b), the threshold Dth may be set for each word line WL. In this case, the threshold Dth_WL0 is set for the word line WL0, and the threshold Dth_WLi is set for the word line WLi.

[0285] 22(c), the threshold Dth may be set for each chip included in the NAND memory 30. In this case, a threshold Dth_Chip0 is set for one chip, and a threshold Dth_Chipi is set for another chip.

[0286] The threshold value Dth for each unit is determined, for example, at the time of designing the memory system 1 or at the time of screening during the manufacture of the NAND memory 30.

[0287] In addition, when the threshold Dth for selecting the data loading method is set on a block or word line basis, the value of the threshold Dth may be set so that the IDL or EDL is always selected for a specific block and a specific word line. For example, when the EDL is always selected for a specific block or a specific word line, the value of the threshold Dth is set to zero. For example, when the IDL is always selected for a specific block or a specific word line, the value of the threshold Dth is set to the maximum value of the numerical range used for the threshold Dth.

[0288] In this way, the memory system 1 of the present embodiment can set an index for selecting either the IDL or the EDL on a chip-by-chip, block-by-block, and word-line-by-word-line basis.

[0289] (c-3) Variation 3 FIG. 23 is a diagram for explaining the third modification of the memory system 1 of the present embodiment.

[0290] As the memory system 1 is used, the blocks BLK (and the memory cells MC) of the NAND memory 30 become worn out.

[0291] The memory system 1 of the third modification dynamically adjusts the threshold Dth for selecting either the IDL or the EDL in accordance with the degree of exhaustion of the block BLK.

[0292] As shown in FIG. 23, in this embodiment, the memory controller 10 includes a program / erase counter (P / E counter) 44 in the write management circuit 18. The memory controller 10 may make the program / erase counter 44 non-volatile in the NAND memory 30 when the power to the memory system 1 is cut off, and may load the program / erase counter 44 into the write management circuit 18 in response to the start of the supply of power to the memory system 1. The program / erase counter 44 may be loaded into the RAM 16. The program / erase counter 44 measures the number of program and erase operations executed in each block BLK. For example, a set of one write operation and one erase operation is measured as one operation cycle.

[0293] The memory controller 10 includes a management table TBL2 relating to the number of program / erase operations in the RAM 16. The management table TBL2 records the number of program and erase operations in each block BLK.

[0294] The rate at which data errors occur in a block BLK varies depending on the number of program / erase operations. For example, the rate at which data errors occur increases as the number of program / erase operations increases.

[0295] For example, in the memory system 1 of this modified example, the memory controller 10 (the processor 12 or the data load selector 181) refers to the program / erase count counter 44 to obtain the program / erase count of each block BLK.

[0296] The memory controller 10 records the acquired program / erase count in the management table TBL2.

[0297] The data load selector 181 (or the processor 12) adjusts the value of the threshold Dth corresponding to each block BLK based on the number of program / erase operations recorded in the management table TBL2.

[0298] For example, if the number of program / erase cycles of the block BLK is relatively large (if the block BLK is highly worn out), the threshold Dth is adjusted to a value smaller than the initial setting value, so that the EDL is more likely to be selected for the block BLK with a high degree of wear.

[0299] In this way, the memory system 1 of this embodiment can select the more appropriate data loading method from the IDL or EDL depending on the degree of exhaustion of the block BLK.

[0300] (d) Summary The memory system 1 of this embodiment selects whether to load the Lower / Middle page data used in the Fine program from within the NAND memory 30 or from outside the NAND memory 30 based on an index related to the reliability of the Lower / Middle page data written to the memory cell array 31 by the MLC program.

[0301] For example, in a NAND flash memory, the threshold voltage of a memory cell MC tends to change over time after data is programmed into the memory cell MC, and therefore the reliability of data written to the memory cell MC may decrease over time.

[0302] If the Lower / Middle page data in the memory cell array 31 contains an error, there is a possibility that the correct four page data will not be written to the cell unit CU specified by the selected address of the memory cell array 31 during fine programming.

[0303] On the other hand, when the memory controller 10 provides Lower / Middle page data to the NAND memory 30 during Fine programming, the time required to complete the Fine programming may be longer due to ECC processing on the Lower / Middle page data and / or the transfer of a command set including the Lower / Middle page data from the memory controller 10 to the NAND memory 30.

[0304] In this embodiment, when the Fine program is executed for a certain address, the time t MLC Based on a comparison between the elapsed time Dx from the start of execution of the Fine program and the threshold Dth, the memory controller 10 evaluates the reliability of the Lower / Middle page data.

[0305] This allows the memory system 1 of this embodiment to select the more appropriate data loading method, IDL or EDL, for data loading (data preparation) of Lower / Middle page data used in the Fine program to be executed.

[0306] As a result, this embodiment can provide a high-performance and highly reliable memory system.

[0307] (2) Second embodiment The memory system of the second embodiment will be described with reference to FIGS.

[0308] (a) Configuration example With reference to FIG. 24, a configuration example of the memory system 1 of the present embodiment will be described.

[0309] FIG. 24 is a block diagram showing an example of the configuration of a memory system 1 of the present embodiment.

[0310] The memory system 1 of this embodiment selects a data loading method during Fine programming based on the workload imposed on the memory system 1.

[0311] As shown in FIG. 24, in the memory controller 10 of the memory system 1 of this embodiment, the write management circuit 18 includes a throughput monitor 183.

[0312] The throughput monitor 183 measures the amount of write data supplied from the host 2 to the memory system 1 within a certain time window (unit time) (hereinafter referred to as host write throughput or simply write throughput). For example, the throughput monitor 183 acquires an average value of the write throughput in the time window based on the measurement result of the amount of write data supplied from the host 2.

[0313] The data load selector 181 of the write management circuit 18 compares the measured write throughput with a preset threshold (TPth). When the Fine program is executed, the data load selector 181 selects either the IDL or the EDL based on the comparison result between the write throughput (TP) and the threshold (TPth).

[0314] (b) Example of operation An operation example of the memory system 1 of the present embodiment will be described with reference to FIGS.

[0315] Fig. 25 is a flowchart for explaining an example of the operation of the memory system 1 of this embodiment. Fig. 26 shows an example of the relationship between the write throughput and time in the memory system 1 of this embodiment. In Fig. 26, the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to the write throughput.

[0316] 25, in the memory controller 10 of the memory system 1 of this embodiment, the throughput monitor 183 of the write management circuit 18 measures the write throughput TP in a certain time window (S200). For example, the throughput monitor 183 acquires the amount of write data supplied from the host 2 in a certain time window. The throughput monitor 183 holds the acquired measurement result in the write management circuit 18.

[0317] The data load selector 181 compares the write throughput TP with a threshold value TPth (S201). Based on the comparison result, the data load selector 181 selects a data load method for a Fine program that can be executed in the next time window after a certain time window.

[0318] 26, in a certain time window TW0, when the write throughput TP is greater than the threshold TPth, it is assumed that the period during which the memory cells MC are in the MLC state is short. Therefore, when the write throughput TP is greater than the threshold TPth, as in the time window TW0, the data load selector 181 selects IDL as the data load method for the Fine program that may be executed in the next time window TW1 (S202 in FIG. 25).

[0319] 26, in a certain time window TW2, when the write throughput TP is equal to or lower than the threshold TPth, it is assumed that the memory cells MC are in the MLC state for a long period of time. Therefore, when the write throughput TP is equal to or lower than the threshold TPth, as in the time window TW2, the data load selector 181 selects the EDL as the data load method for the Fine program that may be executed in the next time window TW3 (S203 in FIG. 25).

[0320] The data load selector 181 notifies the processor 12 of the selection result of the data load method (S204). As a result, when executing the Fine program, the processor 12 instructs the NAND memory 30 to execute the Fine program using the data load method indicated by the selection result.

[0321] The NAND memory 30 executes the Fine program using the selected data loading method, whereby the four pages of data are written to the write target addresses of the memory cell array 31.

[0322] With the above, the memory system 1 of this embodiment ends its operation.

[0323] It should be noted that the range of the time window may be variable rather than fixed. Instead of the amount of write data in the time window, the amount of write data per certain number of commands may be measured as the write throughput.

[0324] Within the same time window in which the write throughput is measured, a data loading method for the Fine program executed during that time window may be selected based on the measurement result of the write throughput.

[0325] (c) Modifications A modification of the memory system 1 of the second embodiment will be described with reference to FIGS.

[0326] (c-1) Variation 1 FIG. 27 is a block diagram showing a configuration example of a memory system 1 according to the first modification.

[0327] The memory system 1 of this embodiment can select the IDL or EDL with greater accuracy by taking into account not only the write throughput from the host 2 to the memory system 1, but also the performance of background processes executed within the memory system 1, such as compaction.

[0328] As shown in FIG. 27, in the memory system 1 of the first modification, the write management circuit 18 includes a WAF monitor 184. The WAF monitor 184 calculates a write amplification factor (WAF) of the memory system 1. The WAF is a value indicating the ratio of the amount of data written to the NAND memory 30 to the amount of data written (amount of data transferred) from the host 2 to the memory system 1. For example, the WAF is obtained from "amount of data written to the NAND memory 30 / amount of data written from the host 2 to the memory system 1". The WAF monitor 184 multiplies the write throughput obtained by the throughput monitor 183 by the WAF. The result of the multiplication (product) indicates the amount of data written to the NAND memory 30 during a certain time window (hereinafter referred to as NAND throughput).

[0329] The data load selector 181 selects a data load method for the Fine program that can be executed in the next time window based on the result of comparing the NAND throughput with the threshold value TPthz.

[0330] Fig. 28 shows a graph of the relationship between NAND throughput and time in the memory system 1 of this embodiment. In Fig. 28, the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to NAND throughput.

[0331] The memory system 1 of the first modified example performs a comparison between the NAND throughput and the threshold value TPthz and a selection of a data loading method to be used in the Fine program based on a process flow substantially the same as the process flow described with reference to FIG.

[0332] As shown in FIG. 28, when the NAND throughput in a certain time window TW0 is greater than the threshold value TPthz, the data load selector 181 selects IDL as the data load method for the Fine program that can be executed in the next time window TW1.

[0333] When the NAND throughput in a certain time window TW2 is equal to or less than the threshold value TPthz, the data load selector 181 selects the EDL as the data load method for the Fine program that can be executed in the next time window TW3.

[0334] As described above, the memory system 1 of the first modification can select a data loading method more suitable for use in the Fine program by further taking into consideration the processing volume of the background processing of the memory system 1.

[0335] (c-2) Variation 2 FIG. 29 is a block diagram showing a configuration example of a memory system 1 according to the second modification.

[0336] The data load method of the Fine program may be selected according to the size of write data requested in a command (request) sent from the host 2 (hereinafter referred to as command size) and the continuity of addresses.

[0337] As shown in FIG. 29, in the memory controller 10 of the memory system 1 of the second modification, the write management circuit 18 includes a command size monitor 185 and an access pattern analyzer 186.

[0338] The command size monitor 185 measures the command size for each of the multiple commands (requests) sent from the host 2. For example, the command size monitor 185 stores the command sizes of the multiple commands sent most recently and obtains the average value of these command sizes. The command size monitor 185 notifies the data load selector 181 whether the obtained average command size is greater than a set threshold value.

[0339] The access pattern analyzer 186, for example, analyzes a pattern of logical addresses associated with the data to be written. The access pattern analyzer 186 detects the continuity of the logical addresses associated with the data to be written based on the analysis result of the logical address pattern. The access pattern analyzer 186 determines that the logical addresses associated with each of the data to be written are continuous when, for example, the range of logical addresses of the write data requested to be written by the first command and the range of logical addresses of the write data requested to be written by the second command are continuous. The access pattern analyzer 186 notifies the data load selector 181 whether the logical addresses associated with each of the data to be written are continuous.

[0340] When the command size is relatively large (e.g., 128 KB) and the access has consecutive logical addresses, the frequency of writing data to logical addresses in that range tends to be relatively high, so the impact of a decrease in the reliability of the data corresponding to that logical address is likely to be small.

[0341] In the memory system 1 of the second variant, when the command size is larger than a set threshold and the logical addresses associated with the data to be written are consecutive, the data load selector 181 selects IDL as the data load method during Fine programming.

[0342] If the command size is equal to or smaller than a set threshold, or if the logical addresses associated with the data to be written are discontinuous, the data load selector 181 selects either the IDL or the EDL based on the elapsed time from the above-mentioned MLC program or the write throughput, etc.

[0343] FIG. 30 is a flowchart showing an operation example of the second modification of the memory system 1 of the present embodiment.

[0344] The memory controller 10 determines to execute the Fine program (S230).

[0345] The command size monitor 185 monitors the command size included in a write request from the host 2. The access pattern analyzer 186 analyzes the pattern (address continuity) of the logical address to be written (S231).

[0346] The data load selector 181 determines whether or not the command size is larger than a certain threshold based on the result of monitoring the command size (S232).

[0347] If the command size is greater than the threshold value (YES in S232), the data load selector 181 determines whether the addresses to be written are consecutive or not based on the analysis result of the access pattern (S233).

[0348] If the command size is large and the addresses to be written are consecutive, the data load selector 181 selects IDL as the data load method to be used for the Fine program (S234).

[0349] If the command size is less than or equal to the threshold (NO in S232) or if the addresses to be written are not consecutive (NO in S233), the data load selector 181 selects either IDL or EDL as the data load method to be used for the Fine program based on the above-mentioned indicator (e.g., the elapsed time since the completion of the MLC program) (S235).

[0350] The data load selector 181 notifies the processor 12 of the selection result of the data load method (S236). As a result, when executing the Fine program, the processor 12 instructs the NAND memory 30 to execute the Fine program using the data load method indicated in the selection result.

[0351] With the above, the memory system 1 of this modified example ends its operation.

[0352] (d) Summary As described above, the memory system 1 of this embodiment can select the data loading method to be used in the Fine program based on the write throughput in the time window.

[0353] Therefore, this embodiment can provide a high-performance and highly reliable memory system.

[0354] (3) Third embodiment A memory system according to a third embodiment will be described with reference to FIGS.

[0355] (a) Configuration example FIG. 31 is a block diagram showing an example of the configuration of a memory system 1 of the present embodiment.

[0356] The memory system 1 of this embodiment controls the selection of the IDL or the EDL depending on whether the write operation is a write operation using write data from the host 2 or a write operation corresponding to background processing. In the following, a write operation requested by the host 2 is called a host write. In the following, a write operation corresponding to background processing is called a background write.

[0357] The host write is an operation mode in which write data transferred from the host 2 is written to the NAND memory 30. The background write is an operation mode in which data prepared inside the memory system 1, such as compaction (garbage collection), wear leveling, or data refresh, is written to the NAND memory 30.

[0358] As shown in FIG. 31, in the memory controller 10 of the memory system 1 of this embodiment, the write management circuit 18 includes a command analyzer 187.

[0359] The command analyzer 187 analyzes whether the command generated by the NAND interface circuit 17 is a command for host writing or a command for background writing based on various information (e.g., attribute information) included in the command generated by the NAND interface circuit 17. The command analyzer 187 sends the command analysis result to the data load selector 181.

[0360] The data load selector 181 selects the data load method to be used for the Fine program based on the analysis result of the command by the command analyzer 187 .

[0361] If the write operation to be performed is a background write, IDL is selected as the data loading method of the Fine program for the write operation to be performed.

[0362] For example, the progress of the background write can be adjusted by the memory system 1. Therefore, the memory controller 10 can control the memory cells MC that are the target of the background write so that the elapsed time Dx from the completion of the MLC program to the present is relatively short.

[0363] In addition, in the IDL, the loading of the Lower / Middle page data is executed inside the NAND memory 30, so the IDL does not occupy the NAND bus NBS as much as the EDL does. Therefore, in the case of a workload with a relatively short idle time (a workload in which the interval between host write requests is equal to or less than a certain threshold), the impact on the host write performance can be reduced by using the IDL for background writing.

[0364] In addition, when background writing is performed by a Fine program using IDL, it is preferable to perform ECC processing on the data written by the background writing. If the error correction fails in the ECC processing, the memory controller 10 can perform background writing again using the Lower / Middle page data stored in the block targeted for the background processing.

[0365] If the write operation to be performed is a host write, then either the IDL or the EDL is selected as the data loading method for the Fine program based on the time elapsed since completion of the MLC program or other indicators mentioned above, such as write throughput.

[0366] (b) Example of operation FIG. 32 is a flowchart showing an operation example of the memory system 1 of the present embodiment.

[0367] 32, in the memory system 1 of this embodiment, when the NAND interface circuit 17 generates a command, the command analyzer 187 analyzes the command (S300). The command analyzer 187 sends the analysis result of the command to the data load selector 181.

[0368] The data load selector 181 determines whether the write operation to be executed is a background write based on the analysis result of the command (S301).

[0369] If the write operation to be executed is background write (YES in S301), the data load selector 181 selects IDL as the data load method for the Fine program (S302).

[0370] If the write operation to be performed is a host write (NO in S301), the data load selector 181 selects either the IDL or the EDL based on one or more of the indicators described above (for example, the elapsed time since the completion of the MLC program) (S303).

[0371] The data load selector 181 notifies the processor 12 of the selection result of the data load method (S304). When executing the Fine program, the processor 12 instructs the NAND memory 30 to execute the Fine program using the data load method indicated in the selection result.

[0372] With the above, the memory system 1 of this embodiment ends its operation.

[0373] (c) Modifications FIG. 33 is a flowchart showing an operation example in a modification of the memory system 1 of the present embodiment.

[0374] In the case of a workload with a relatively long idle time (a workload in which the interval between host write requests is longer than a certain threshold), the time required for data loading during a Fine program is likely to affect the performance of the memory system as seen by the host. Therefore, it is desirable to use IDL for host-write Fine programs in workloads with a relatively long idle time.

[0375] In the case of a workload with a relatively long idle time, background processing is unlikely to be reflected in the performance of the memory system as seen by the host. Therefore, it is desirable to use the EDL for Fine programming of background writes in a workload with a relatively long idle time.

[0376] The configuration of the memory system 1 of this modified example is the same as that of the third embodiment described with reference to FIG.

[0377] As shown in FIG. 33, in this modification, the data load selector 181 determines whether the write operation to be executed is a background write (S300, S301).

[0378] If the write operation to be executed is background write (YES in S301), the data load selector 181 selects the EDL (S302A).

[0379] If the write operation to be executed is not a background write (NO in S301), the data load selector 181 selects, for example, the IDL (S303A).

[0380] The data load selector 181 notifies the processor 12 of the selection result of the data load method (S304). When executing the Fine program, the processor 12 instructs the NAND memory 30 to execute the Fine program using the data load method indicated in the selection result.

[0381] With the above, the memory system 1 of the modified example ends its operation.

[0382] (d) Summary The memory system 1 of this embodiment selects IDL or EDL as the data loading method during Fine programming, based on whether the write operation to be executed is a host write or a background write.

[0383] This allows the memory system 1 of the present embodiment to execute the requested write operation using a data loading method suited to the Fine program, based on the type of write operation to be executed.

[0384] Therefore, the memory system 1 of the present embodiment can provide a high-performance and highly reliable memory system.

[0385] (4) Fourth embodiment A memory system according to a fourth embodiment will be described with reference to FIGS.

[0386] (a) Configuration example FIG. 34 is a block diagram showing an example of the configuration of the memory system 1 of the present embodiment.

[0387] The memory system 1 of this embodiment selects either the IDL or the EDL as the data load method for the Fine program based on hint information from the host 2.

[0388] The host 2 sends a pair of a start flag SF and an end flag EF as hint information to the memory controller 10. The start flag SF is a signal notifying the host 2 that it will transfer a large number of write commands to the memory system 1. The end flag EF is a signal notifying the end of the transfer of the large number of write commands.

[0389] As shown in FIG. 34, in the memory controller 10 of the memory system 1 of the present embodiment, the write management circuit 18 includes a flag post 188.

[0390] The flag post 188 receives the start flag SF and the end flag EF as hint information. Based on the received start flag SF, the flag post 188 sends a notification signal ACK3 to the data load selector 181 so that an IDL is selected in the period from reception of the start flag SF to reception of the end flag EF.

[0391] The data load selector 181 selects the IDL in the period from reception of the start flag SF to reception of the end flag EF, based on the notification signal ACK3 from the flag post 188.

[0392] (b) Example of operation FIG. 35 is a schematic diagram for explaining an operation example of the memory system 1 of the present embodiment.

[0393] 35, at a certain time t10a, the host 2 sends a start flag SF as hint information to the memory system 1. The start flag SF notifies the memory system 1 that a large number of write commands will soon be issued.

[0394] At a certain time t10b, the memory controller 10 receives a start flag SF.

[0395] The flag post 188 analyzes the start flag SF. The flag post 188 sends a notification signal ACK3 to the data load selector 181 based on the analysis result of the start flag SF.

[0396] The data load selector 181 recognizes, based on the notification signal ACK3, that the IDL is to be selected when the Fine program is executed.

[0397] The host 2 sends a large number of write commands WC to the memory system 1 in the period from time t11a to time t12a.

[0398] In the period from time t11b to time t12b, the memory system 1 receives a large number of write commands WC.

[0399] The data load selector 181 continues to select IDL as the data load method for the Fine program to be executed during the period from time t11b to time t12b.

[0400] The host 2 sends an end flag EF as hint information to the memory system 1 at time t13a after sending all the write commands WC.

[0401] At a certain time t13b, the memory controller 10 receives the end flag EF. In the memory controller 10, the flag post 188 receives the end flag EF.

[0402] The flag post 188 analyzes the end flag EF. The flag post 188 stops supplying the acknowledgement signal ACK3 based on the analysis result of the end flag.

[0403] The data load selector 181 recognizes that the write operation corresponding to the large amount of write command WC has ended based on the halt in the supply of the acknowledgement signal ACK3, and thereby stops the continuous selection of the IDL.

[0404] After this, the data load selector 181 selects either the IDL or the EDL based on an indicator for selecting the above-mentioned data load method (e.g., the elapsed time since the completion of the MLC program) until it receives a new notification signal ACK3 from the flag post 188.

[0405] Incidentally, the memory system 1 of this embodiment may select the EDL as the data load method during Fine programming, based on hint information from the host 2.

[0406] (c) Summary As described above, the memory system 1 of this embodiment can select a data loading method suitable for the write operation to be executed from among IDL and EDL, based on the hint information from the host 2.

[0407] Therefore, the memory system 1 of the present embodiment can provide a high-performance and highly reliable memory system.

[0408] (5) Fifth embodiment A memory system according to a fifth embodiment will be described with reference to FIGS.

[0409] (a) Configuration example FIG. 36 is a block diagram showing an example of the configuration of a memory system 1 of the present embodiment.

[0410] The memory system 1 of this embodiment controls the selection of the IDL and EDL during Fine programming depending on the state of power supply interruption and restoration.

[0411] As shown in FIG. 36, in the memory controller 10 of the memory system 1 of this embodiment, the write management circuit 18 includes a power supply monitor 189.

[0412] When a cutoff of the power supply to the memory system 1 is detected, the power supply monitor 189 sends a power cut signal PS to the processor 12.

[0413] In response to the power-off signal PS, the processor 12 generates a management table TBL3 indicating the word lines WL and string units SU to which memory cells MC in the MLC state are connected. Hereinafter, the management table TBL3 indicating the word lines and string units to which memory cells MC in the MLC state are connected is referred to as an MLC state list TBL3.

[0414] The MLC state list TBL3 is temporarily stored in, for example, the RAM 16. For example, the memory controller 10 writes the generated MLC state list TBL3 to the NAND memory 30 or transmits it to the host 2 when the power supply to the memory system 1 is cut off. When the memory system 1 is started up upon recovery of the power supply, the memory controller 10 reads the MLC state list TBL3 from the NAND memory 30 or receives it from the host 2.

[0415] When the memory controller 10 receives a write command from the host 2 after the power supply is restored, the data load selector 181 refers to the MLC status list TBL3.

[0416] For memory cells MC managed in the MLC state list TBL3, the elapsed time Dx from the completion of the MLC program to the present is unknown. Therefore, when the address of the write target corresponding to the write command from the host 2 corresponds to the word line WL number and the string unit SU number in the MLC state list TBL3, the data load selector 181 selects the EDL, which has higher data reliability than the IDL, as the data load method for the Fine program.

[0417] After the power supply is restored, the fine program using EDL is executed on all the cell units CU specified by the addresses corresponding to the multiple word lines WL and multiple string units SU recorded in the MLC status list TBL3, and then the data load selector 181 selects either the IDL or the EDL as the data load method to be used for the fine program based on the above-mentioned indicator (e.g., the elapsed time since the completion of the MLC program).

[0418] Incidentally, there are cases where the processor 12 cannot generate the MLC state list TBL3 due to an illegal power cut such as a power outage. In such a case, a write operation is executed based on the write order described with reference to Fig. 9, starting from the cell unit CU that was in the MLC state at the time of the illegal power cut. This makes it possible to execute the Fine program of the data load method selected by the data load selector 181 for the cell units CU following the cell unit CU that was in the MLC state at the time of the illegal power cut.

[0419] Furthermore, even if a management table (e.g., an MLC status list) regarding the addresses to be written to is not updated each time a power supply interruption is detected, the data loading method used in the Fine program may be selected after the power supply is restored based on the history of write operations before the power supply was interrupted.

[0420] (b) Example of operation FIG. 37 is a flowchart showing an operation example of the memory system 1 of the present embodiment.

[0421] 37, when the power supply monitor 189 detects a power cutoff, the processor 12 generates a management table TBL3 (MLC status list TBL3) in response to a power cutoff signal PS from the power supply monitor 189. The generated MLC status list TBL3 is transferred to the NAND memory 30 or the host 2 (S500).

[0422] When the memory system 1 is started up upon recovery of the power supply, the MLC state list TBL3 is stored in the RAM 16 of the memory system 1.

[0423] After the power supply is restored, when the memory controller 10 receives a write request from the host 2, the data load selector 181 refers to the MLC status list TBL3 (S501).

[0424] The data load selector 181 determines whether or not the address to be written (the number of the word line WL and the number of the string unit SU) exists in the MLC status list TBL3 (S502).

[0425] If the number of the word line WL to be written and the number of the string unit SU are present in the MLC status list TBL3 (YES in S502), the data load selector 181 selects EDL as the data load method for the Fine program to be executed based on the recognition that the write operation to be executed is a Fine program (S503).

[0426] The data load selector 181 updates the MLC state list TBL3 (S504). For example, the data load selector 181 deletes the number of the word line WL and the number of the string unit SU to which the Fine program is executed by the selected EDL from the MLC state list TBL3.

[0427] If the number of the word line WL to be written and the number of the string unit SU are not present in the MLC status list TBL3 (NO in S502), the data load selector 181 selects either the IDL or the EDL based on indicators such as the elapsed time since the completion of the MLC program or the write throughput if the write operation to be executed is a Fine program (S505).

[0428] The data load selector 181 notifies the processor 12 of the selection result of the data load method (S506). As a result, when executing the Fine program, the processor 12 instructs the NAND memory 30 to execute the Fine program using the data load method indicated by the selection result.

[0429] With the above, the memory system 1 of this embodiment ends its operation.

[0430] (c) Summary As described above, the memory system 1 of the present embodiment can provide a high-performance and highly reliable memory system even if the power supply to the memory system 1 is interrupted.

[0431] (6) Other In the memory system of the embodiment, the nonvolatile memory is not limited to a NAND flash memory, and may be another memory device.

[0432] In the memory system of the embodiment, if data is written to the memory cell by multiple write stages (write operations), the data written to the memory cell may be 2-bit data, 3-bit data, 5-bit data, or 6-bit data.

[0433] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0434] 1: Memory system, 2: Host, 10: Memory controller, 30: Non-volatile memory, 11: Host interface circuit, 12: Processor, 13: Buffer memory, 14: ECC circuit, 15: ROM, 16: RAM, 17: NAND interface circuit, 18: Write management circuit, 181: Data load selector, 182: Global clock, 183: Throughput monitor, 184: WAF monitor, 185: Command size monitor, 186: Access pattern analyzer, 187: Command analyzer, 188: Flag post, 189: Power supply monitor, 31: Memory cell array, 33: Logic control circuit, 36: Sequencer, 43: Temperature sensor, 44: Program / erase counter.

Claims

1. a memory cell configured to store data in a non-volatile manner; a control circuit configured to write n-bit (n is a real number equal to or greater than 1) first data to the memory cell by a first write operation, and to write m-bit (m is a real number greater than n) second data including the first data to the memory cell by a second write operation; a non-volatile memory including: electrically connected to the non-volatile memory; instructing the non-volatile memory to perform the first write operation; selecting whether to prepare the first data included in the second data used in the second write operation using a first method of preparing the first data within the non-volatile memory or a second method of preparing the first data outside the non-volatile memory based on an index related to reliability of the first data written to the memory cell; preparing the first data to be included in the second data using the selected one of the first method or the second method; instructing the non-volatile memory to perform the second write operation on the second data, the second data including the first data prepared in the selected manner; a memory controller configured to A memory system comprising:

2. the indicator is an amount of time elapsed since completion of the first write operation to the memory cell; The memory controller includes: selecting the first scheme if the elapsed time is equal to or less than a first threshold; If the elapsed time is greater than the first threshold, selecting the second scheme.

2. The memory system of claim 1.

3. A first memory; A clock for measuring time, The memory controller includes: storing in the first memory a first management table that holds a plurality of addresses and a first time related to the first write operation in each of a plurality of the memory cells designated by the plurality of addresses; selecting the first scheme when a difference value between a second time and the first time related to the second write operation is equal to or less than a second threshold; If the difference value is greater than the second threshold, the second scheme is selected.

2. The memory system of claim 1.

4. Further comprising a temperature sensor for measuring a temperature of the nonvolatile memory; The memory controller adjusts the second threshold based on a measurement result of the temperature sensor.

4. The memory system of claim 3.

5. The memory controller includes: The second threshold value when a first temperature measured by the temperature sensor as the temperature of the non-volatile memory when the first write operation is executed is higher than a third threshold value is set to be smaller than the second threshold value when the first temperature is equal to or lower than the third threshold value; or the second threshold value when the first temperature is lower than a fourth threshold value that is lower than the third threshold value is set to be smaller than the second threshold value when the first temperature is equal to or higher than the fourth threshold value; 5. The memory system of claim 4.

6. The memory controller includes: acquiring a temperature difference between a first temperature measured by the temperature sensor as the temperature of the non-volatile memory when the first write operation is executed and a second temperature measured by the temperature sensor as the temperature of the non-volatile memory when the second write operation is executed; The second threshold value when the temperature difference is greater than a fifth threshold value is set to be smaller than the second threshold value when the temperature difference is equal to or smaller than the fifth threshold value.

5. The memory system of claim 4.

7. The memory controller includes: Managing the number of erase operations for the memory cells; The second threshold value when the number of times is greater than a sixth threshold value is set to be smaller than the second threshold value when the number of times is equal to or smaller than the sixth threshold value.

4. The memory system of claim 3.

8. the indicator is a throughput of data from a host during a first period of time; The memory controller includes: If the throughput is greater than a seventh threshold, select the first scheme in a second period after the first period; When the throughput is equal to or less than the seventh threshold, the second scheme is selected in the second period.

2. The memory system of claim 1.

9. the indicator is a throughput of write data to the non-volatile memory during a first period; The memory controller includes: If the throughput is greater than an eighth threshold, select the first scheme in a second period after the first period; When the throughput is equal to or less than the eighth threshold, the second scheme is selected in the second period.

2. The memory system of claim 1.

10. The memory controller includes: selecting the first method when a size of first write data specified by a first command from a host is larger than a ninth threshold value and a logical address associated with second write data specified by a second command and a logical address associated with the first write data are consecutive; selecting either the first method or the second method based on the index when a size of the first write data is equal to or smaller than the ninth threshold value, or when a logical address associated with the second write data and a logical address associated with the first write data are not consecutive; 2. The memory system of claim 1.

11. The memory controller includes: If the second write operation is a background process for writing data, the first method is selected; selecting either the first method or the second method based on the indicator when the second write operation is a write of data from a host; 2. The memory system of claim 1.

12. The memory controller includes: determining whether an interval between write requests from the host is equal to or less than a tenth threshold; If the interval is equal to or less than the tenth threshold, selecting the first scheme for the second write operation by the background process; selecting either the first method or the second method based on the indicator for the second write operation of the data from the host; 12. The memory system of claim 11.

13. The memory controller includes: selecting the first scheme if the second write operation is a write of data from a host; selecting the second method when the second write operation is a data write operation by a background process; 2. The memory system of claim 1.

14. The memory controller includes: determining whether an interval between write requests from the host is longer than an eleventh threshold; If the interval is greater than the eleventh threshold, selecting the first scheme for the second write operation of the data from the host; selecting the second scheme for the second write operation by the background process; 14. The memory system of claim 13.

15. The memory controller includes: when a first flag indicating transmission of a plurality of commands from a host is received, continuing selection of the first method based on the first flag; canceling the continuation of the selection of the first method when a second flag indicating the end of the transmission of the plurality of commands from the host is received; 2. The memory system of claim 1.

16. The memory controller includes: when the supply of power to the memory system is stopped, an address of the memory cell for which the first write operation has been executed and the second write operation has not been executed is recorded in a third management table; selecting the second method when an address of a memory cell to be subjected to the second write operation is recorded in the third management table after the supply of power to the memory system is resumed; selecting either the first method or the second method based on the index when an address of a memory cell to be subjected to the second write operation is not recorded in the third management table; 2. The memory system of claim 1.

17. the memory controller updates the third management table after executing the second write operation on the target memory cell of the second write operation; 17. The memory system of claim 16.

18. The memory controller includes: recording an address of the memory cell for which the first write operation has been executed and the second write operation has not been executed in a third management table; selecting the second method when the address of the memory cell to be subjected to the second write operation is recorded in the third management table; selecting either the first method or the second method based on the index when an address of a memory cell to be subjected to the second write operation is not recorded in the third management table; 2. The memory system of claim 1.

19. the nonvolatile memory does not execute an erase operation on the memory cell between the first write operation and the second write operation; 2. The memory system of claim 1.

20. A memory device connectable to a controller, comprising: a memory cell configured to store data in a non-volatile manner; a control circuit configured to write n-bit (n is a real number equal to or greater than 1) first data to the memory cell by a first write operation, and to write m-bit (m is a real number greater than n) second data including the first data to the memory cell by a second write operation; Equipped with The control circuit further comprises: and configured to select, based on a command from the controller, whether to execute the second write operation using either a first scheme in which the first data included in the second data used for the second write operation is prepared within the memory device or a second scheme in which the first data is prepared outside the memory device. Memory device.

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