Memory system and information processing system

Abstract

To reduce power consumption.SOLUTION: A memory system includes: a non-volatile memory including a plurality of memory cells; and a memory controller having a first state for writing write data transferred from an external host into the non-volatile memory at a first number of bits per memory cell and a second state for writing at a second number of bits greater than the first number of bits. The memory controller is configured to transmit information relating to a transfer rate of the write data to the host in response to a first request from the host. The information includes first information associated with the first state and second information associated with the second state.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The embodiments relate to a memory system and an information processing system. [Background technology]

[0002] 2. Description of the Related Art There is known an information processing system including a host and a memory system connected to the host. The memory system includes a NAND flash memory as a nonvolatile memory and a memory controller that controls the nonvolatile memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0294654 [Patent Document 2] U.S. Pat. No. 1,127,5620 [Patent Document 3] US Patent Application Publication No. 2021 / 0034536 Summary of the Invention [Problem to be solved by the invention]

[0004] Reduce power consumption. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a non-volatile memory including a plurality of memory cells, and a memory controller having a first state in which write data transferred from an external host to the non-volatile memory with a first number of bits per memory cell and a second state in which write data with a second number of bits greater than the first number of bits. The memory controller is configured to transmit information regarding a transfer rate of the write data to the host in response to a first request from the host. The information includes first information associated with the first state and second information associated with the second state. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of a configuration of an information processing system according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of a connection configuration of a host and a memory controller according to the embodiment. [Diagram 3] 4 is a diagram showing an example of a data structure of transfer rate information stored in the memory system according to the embodiment; [Figure 4] FIG. 1 is a circuit diagram showing an example of the configuration of a nonvolatile memory according to an embodiment. [Diagram 5] 4 is a diagram showing a first example of threshold voltage distributions of a plurality of memory cell transistors according to the embodiment. FIG. [Figure 6] FIG. 13 is a diagram showing a second example of threshold voltage distributions of a plurality of memory cell transistors according to the embodiment. [Figure 7] 11 is a sequence diagram showing an example of a series of processes including a transfer rate change process in the information processing system according to the embodiment. [Figure 8] FIG. 11 is a sequence diagram showing an example of a transfer rate change process in the information processing system according to the embodiment. [Figure 9] 13 is a diagram showing an example of a data structure of transfer rate information stored in a memory system according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference symbols. When multiple components having a common reference symbol are to be distinguished from one another, a subscript is added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol is added to the multiple components, and no subscript is added.

[0008] 1. Embodiment 1.1 Configuration 1.1.1 Information Processing System The configuration of an information processing system according to an embodiment will be described.

[0009] 1 is a block diagram showing an example of a configuration of an information processing system according to an embodiment of the present invention. As shown in FIG. 1, the information processing system 1 includes a host 2 and a memory system 3.

[0010] The host 2 is a data processing device that processes data using the memory system 3. The host 2 is, for example, a mobile SoC (System on a Chip) implemented in a smartphone.

[0011] The memory system 3 is, for example, a storage device such as UFS (Universal Flash Storage). The memory system 3 executes data write, read, and erase processes in response to requests from the host 2. For example, the memory system 3 supports a write booster function compliant with the UFS3.1 and UFS4.0 standards.

[0012] A memory system 3 with the light booster function enabled can improve write performance by writing data faster than a memory system 3 with the light booster function disabled. Hereinafter, the state of the memory system 3 with the light booster function enabled is also referred to as a "high-speed mode." The state of the memory system 3 with the light booster function disabled is also referred to as a "normal mode."

[0013] 1.1.2 Memory System Next, the internal configuration of the memory system 3 will be described with reference to Fig. 1. The memory system 3 includes a memory controller 10 and a non-volatile memory 20.

[0014] The memory controller 10 is configured as an integrated circuit such as a System-on-a-Chip (SoC). The memory controller 10 controls the non-volatile memory 20 based on a request from the host 2.

[0015] Specifically, for example, the memory controller 10 writes write data to the non-volatile memory 20 based on a write request from the host 2. Also, the memory controller 10 reads read data from the non-volatile memory 20 based on a read request from the host 2. Then, the memory controller 10 transmits data based on the read data to the host 2.

[0016] The nonvolatile memory 20 is, for example, a NAND flash memory. The nonvolatile memory 20 includes a plurality of blocks BLK (BLK0 to BLK3). Each block BLK includes a plurality of memory cells. Each memory cell stores data in a nonvolatile manner. The block BLK is, for example, a data erase unit.

[0017] 1.1.3 Memory Controller Next, the internal configuration of the memory controller 10 will be described with continued reference to Fig. 1. The memory controller 10 includes a control circuit 11, a non-volatile memory interface circuit (NVMI / F) 12, a host interface circuit (host I / F) 13, a volatile memory 14, and a buffer memory 15. The functions of the control circuit 11, the non-volatile memory interface circuit 12, the host interface circuit 13, the volatile memory 14, and the buffer memory 15 described below can be realized by dedicated hardware, a processor that executes a program, or a combination of these.

[0018] The control circuit 11 is a circuit that controls the entire memory controller 10. The control circuit 11 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory).

[0019] The nonvolatile memory interface circuit 12 manages communication between the memory controller 10 and the nonvolatile memory 20. The nonvolatile memory interface circuit 12 is connected to the nonvolatile memory 20 via a memory bus MB. The memory bus MB complies with, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, or an open NAND flash interface (ONFI).

[0020] The host interface circuit 13 is responsible for communication with the host 2. The host interface circuit 13 is, for example, an M-PHY TM It is connected to host 2 in accordance with the above.

[0021] The volatile memory 14 is, for example, a static random access memory (SRAM). The data stored in the volatile memory 14 is initialized with the value stored in the non-volatile memory 20 when the memory system 3 is started. The volatile memory 14 stores information about the data transfer rate between the host 2 and the memory system 3, etc. Specifically, for example, the volatile memory 14 stores transfer rate information 16. The volatile memory 14 may be a dynamic random access memory (DRAM). When the volatile memory 14 is configured with a DRAM, the volatile memory 14 is connected to the memory controller 10 via a bus that complies with the DRAM interface standard.

[0022] The transfer rate information 16 stores an optimum transfer rate according to the state of the memory system 3 as capability information. The transfer rate information 16 may be stored in a non-volatile memory 20. The transfer rate information 16 will be described in detail later.

[0023] The buffer memory 15 is, for example, an SRAM. The buffer memory 15 buffers data between the host 2 and the nonvolatile memory 20. Specifically, the buffer memory 15 temporarily stores write data and read data.

[0024] 1.1.4 Host Next, still referring to Fig. 1, the internal configuration of the host 2 will be described. The host 2 includes a control circuit 5 and a device interface circuit (device I / F) 6. The functions of the control circuit 5 and the device interface circuit 6 described below can be realized by dedicated hardware, a processor that executes a program, or a combination of both.

[0025] The control circuit 5 is a circuit that controls the entire host 2. The control circuit 5 includes, for example, a processor such as a CPU, a ROM, and a RAM.

[0026] The device interface circuit 6 is responsible for communication with the memory system 3. The device interface circuit 6 is TM 1. The host interface circuit 13 of the memory controller 10 is connected in accordance with the above.

[0027] 1.1.5 Connection between the host and the memory controller 2 is a block diagram showing an example of a connection configuration between a host and a memory controller according to an embodiment. In FIG. 2, an example of a connection configuration between a device interface circuit 6 of the host 2 and a host interface circuit 13 of the memory controller 10 is shown. The host interface circuit 13 includes a signal processing unit 41, a protocol control unit 42, and a data transmission / reception unit 43. The device interface circuit 6 includes a signal processing unit 51, a protocol control unit 52, and a data transmission / reception unit 53. The device interface circuit 6 is connected to the host interface circuit 13 of the memory controller 10 by communication paths LA1, LA2, LB1, and LB2. The communication paths LA1, LA2, LB1, and LB2 are physical lanes used for transmitting and receiving data.

[0028] First, the configuration of the host interface circuit 13 will be described.

[0029] The signal processing unit 41 is a circuit corresponding to the physical layer. For example, the signal processing unit 41 is a M-PHYTM The signal processing unit 41 includes a receiving unit 41R and a transmitting unit 41T.

[0030] The receiving unit 41R receives a signal from the transmitting unit 51T via the communication paths LA1 and LA2. The receiving unit 41R extracts a packet from the signal received from the transmitting unit 51T, and transfers the packet to the protocol control unit .

[0031] The transmitting unit 41T generates a signal based on the packet received from the protocol control unit 42. The transmitting unit 41T transmits the generated signal to the receiving unit 51R via the communication paths LB1 and LB2.

[0032] The protocol control unit 42 is a circuit corresponding to the data link layer, the network layer, and the transport layer. TM The protocol control unit 42 complies with the standard. The protocol control unit 42 generates a packet based on the data received from the data transmission / reception unit 43 and transfers it to the transmission unit 41T of the signal processing unit 41. The protocol control unit 42 extracts data from the packet received from the reception unit 41R of the signal processing unit 41 and transfers it to the data transmission / reception unit 43. The protocol control unit 42 also controls the number of lanes and frequency used for receiving signals by the reception unit 41R and the number of lanes and frequency used for transmitting signals by the transmission unit 41T.

[0033] The data transmitter / receiver 43 functions as an interface between the host interface circuit 13 and various circuits in the memory controller 10. The data transmitter / receiver 43 transfers data transferred from the protocol control unit 42 to various circuits in the memory controller 10. The data transmitter / receiver 43 transfers data received from various circuits in the memory controller 10 to the protocol control unit 42.

[0034] Next, the configuration of the device interface circuit 6 will be described.

[0035] The signal processing unit 51 is a circuit corresponding to the physical layer. For example, the signal processing unit 51 isTM The signal processing unit 51 includes a receiving unit 51R and a transmitting unit 51T.

[0036] The receiving unit 51R receives a signal from the transmitting unit 41T via the communication paths LB1 and LB2. The receiving unit 51R extracts a packet from the signal received from the transmitting unit 41T and transfers it to the protocol control unit 52.

[0037] The transmitting unit 51T generates a signal based on the packet received from the protocol control unit 52. The transmitting unit 51T transmits the generated signal to the receiving unit 41R via the communication paths LA1 and LA2.

[0038] The protocol control unit 52 is a circuit corresponding to the data link layer, the network layer, and the transport layer. TM The protocol control unit 52 complies with the standard. The protocol control unit 52 generates a packet based on the data received from the data transmission / reception unit 53 and transfers it to the transmission unit 51T of the signal processing unit 51. The protocol control unit 52 extracts data from the packet received from the reception unit 51R of the signal processing unit 51 and transfers it to the data transmission / reception unit 53. The protocol control unit 52 also controls the number of lanes and frequency used for receiving signals by the reception unit 51R and the number of lanes and frequency used for transmitting signals by the transmission unit 51T.

[0039] The data transmitter / receiver 53 functions as an interface between the device interface circuit 6 and various circuits in the host 2. The data transmitter / receiver 53 transfers data transferred from the protocol control unit 52 to various circuits in the host 2. The data transmitter / receiver 53 transfers data received from various circuits in the host 2 to the protocol control unit 52.

[0040] 1.1.6 Transfer rate information FIG. 3 is a diagram showing an example of a data structure of transfer rate information stored in the memory system according to the embodiment.

[0041] 3, the transfer rate information 16 stores a parameter A corresponding to the high-speed mode and a parameter B corresponding to the normal mode as parameters for determining the transfer rate. Each of the parameters A and B includes a frequency and a number of lanes corresponding to a transfer rate (Rx transfer rate) when the memory system 3 receives data from the host 2, and a frequency and a number of lanes corresponding to a transfer rate (Tx transfer rate) when the memory system 3 transmits data to the host 2.

[0042] Specifically, the parameter A includes a frequency f_r1 and a number of lanes n_r1 corresponding to the Rx transfer rate in the high-speed mode, and a frequency f_t1 and a number of lanes n_t1 corresponding to the Tx transfer rate in the high-speed mode, while the parameter B includes a frequency f_r2 and a number of lanes n_r2 corresponding to the Rx transfer rate in the normal mode, and a frequency f_t2 and a number of lanes n_t2 corresponding to the Tx transfer rate in the normal mode.

[0043] The Rx transfer rate and the Tx transfer rate in the same mode are set independently of each other. That is, the frequency f_r1 and the number of lanes n_r1 are set independently of the frequency f_t1 and the number of lanes n_t1, respectively. The frequency f_r2 and the number of lanes n_r2 are set independently of the frequency f_t2 and the number of lanes n_t2, respectively.

[0044] The Tx transfer rate in the high-speed mode and the Tx transfer rate in the normal mode may be the same or different.

[0045] The Rx transfer rate in the high-speed mode is set to be higher than the Rx transfer rate in the normal mode. That is, the Rx transfer rate determined by the frequency f_r1 and the number of lanes n_r1 is higher than the Rx transfer rate determined by the frequency f_r2 and the number of lanes n_r2. Specifically, for example, when the number of lanes n_r1 and n_r2 are equal, the frequency f_r1 is higher than the frequency f_r2. When the frequency f_r1 and f_r2 are equal, the number of lanes n_r1 is 2, and the number of lanes n_r1 is 1. Note that the above combinations of the frequencies f_r1 and f_r2 and the number of lanes n_r1 and n_r2 are merely examples, and may be set to any value within a range in which the Rx transfer rate in the high-speed mode is higher than the Rx transfer rate in the normal mode.

[0046] 1.1.7 Non-volatile memory Next, the configuration of the nonvolatile memory 20 will be described. Fig. 4 is a circuit diagram showing an example of the configuration of the nonvolatile memory according to the embodiment. In Fig. 4, the configuration of block BLK0 is shown as an example. The configurations of the other blocks BLK1 to BLK3 are the same as the configuration of block BLK0. Block BLK0 includes, for example, four string units SU0 to SU3. Note that in Fig. 4, the configurations of string units SU2 and SU3 are shown in a simplified manner.

[0047] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0, BL1, ..., and BLm (m is an integer equal to or greater than 2). The NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2.

[0048] The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select a string unit SU during various processes.

[0049] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. A select transistor ST1 is connected between one end of the series-connected memory cell transistors MT0 to MT7 and the associated bit line BL. The drain of a select transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. A source line SL is connected to the source of the select transistor ST2.

[0050] In the same block BLK, the gates of the select transistors ST1 included in the string units SU0 to SU3 are commonly connected to select gate lines SGD0 to SGD3, respectively. The control gates of the memory cell transistors MT0 to MT7 are commonly connected to word lines WL0 to WL7, respectively. The gates of the select transistors ST2 are commonly connected to a select gate line SGS.

[0051] The bit lines BL0 to BLm are shared by the multiple blocks BLK0 to BLK3. The same bit line BL is connected to the NAND strings NS corresponding to the same column address. The word lines WL0 to WL7 are provided in each of the blocks BLK0 to BLK3. The source line SL is shared by, for example, the multiple blocks BLK0 to BLK3.

[0052] A set of memory cell transistors MT connected to a common word line WL in one string unit SU is called, for example, a cell unit CU, and is used as a data write unit. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data". That is, one page of data is a data area of ​​one-bit data strings having a number of columns corresponding to the number of memory cell transistors MT in the cell unit CU. One page of data is used, for example, as a data read unit. The cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0053] The circuit configuration of the block BLK described above is merely an example and is not limited to this. For example, the number of bit lines BL is not limited to three or more, and may be one or two. The number of blocks BLK included in the nonvolatile memory 20 can be designed to be any number. The number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0054] 1.1.8 Threshold voltage distribution The multiple memory cell transistors MT have different threshold voltage distributions depending on the number of bits of data to be stored. Fig. 5 is a schematic diagram showing a first example of threshold voltage distributions of the multiple memory cell transistors MT according to the embodiment. Fig. 6 is a schematic diagram showing a second example of threshold voltage distributions of the multiple memory cell transistors MT according to the embodiment. The first example corresponds to a case where each of the multiple memory cell transistors MT stores 1-bit data. The second example corresponds to a case where each of the multiple memory cell transistors MT stores 3-bit data.

[0055] First, the first example will be described with reference to FIG.

[0056] When storing one bit of data in multiple memory cell transistors MT, the threshold voltage distribution is divided into two. These two threshold voltage distributions are called the "Er" state and the "A" state, in order from lowest to highest threshold voltage.

[0057] Of the above threshold voltage distributions, the "Er" state corresponds to the erased state of the memory cell transistor MT. The threshold voltage in the "Er" state is less than the voltage VA. The threshold voltage in the "A" state is equal to or greater than the voltage VA and less than the voltage VREAD. The voltage VREAD is the voltage applied to unselected word lines during a read process. When the voltage VREAD is applied to the gate of the memory cell transistor MT, the memory cell transistor MT is turned on regardless of the data stored therein. The relationship between these voltage values ​​is VA <VREADである。

[0058] The above-mentioned two threshold voltage distributions correspond to different one-bit data. That is, the memory cell transistor MT included in the “Er” state stores “1” data. The memory cell transistor MT included in the “A” state stores “0” data.

[0059] Such a threshold voltage distribution formed when one bit of data is stored in a plurality of memory cell transistors MT is realized by a single level cell (SLC) write process.

[0060] Next, a second example will be described with reference to FIG.

[0061] When 3-bit data is stored in multiple memory cell transistors MT, the distribution of the threshold voltages is divided into eight states. These eight threshold voltage distributions are called the "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state, in order from the lowest threshold voltage.

[0062] Of the above threshold voltage distributions, the "S0" state corresponds to the erased state of the memory cell transistor MT. The threshold voltage in the "S0" state is less than voltage VS1. The threshold voltage in the "S1" state is equal to or greater than voltage VS1 and less than voltage VS2. The threshold voltage in the "S2" state is equal to or greater than voltage VS2 and less than voltage VS3. The threshold voltage in the "S3" state is equal to or greater than voltage VS3 and less than voltage VS4. The threshold voltage in the "S4" state is equal to or greater than voltage VS4 and less than voltage VS5. The threshold voltage in the "S5" state is equal to or greater than voltage VS5 and less than voltage VS6. The threshold voltage in the "S6" state is equal to or greater than voltage VS6 and less than voltage VS7. The threshold voltage in the "S7" state is equal to or greater than voltage VS7 and less than voltage VREAD. The relationship between these voltage values ​​is VS1. <VS2<VS3<VS4<VS5<VS6<VS7<VREADである。

[0063] The eight threshold voltage distributions described above correspond to three different bits of data. That is, the memory cell transistor MT included in the "S0" state stores "111" data. The memory cell transistor MT included in the "S1" state stores "110" data. The memory cell transistor MT included in the "S2" state stores "100" data. The memory cell transistor MT included in the "S3" state stores "000" data. The memory cell transistor MT included in the "S4" state stores "010" data. The memory cell transistor MT included in the "S5" state stores "011" data. The memory cell transistor MT included in the "S6" state stores "001" data. The memory cell transistor MT included in the "S7" state stores "101" data.

[0064] Such a threshold voltage distribution formed when storing 3-bit data in a plurality of memory cell transistors MT is realized by a TLC (Triple Level Cell) write process.

[0065] 1.2 Operation Next, the operation of the information processing system according to the embodiment will be described.

[0066] 1.2.1 Write Processing According to the TLC write process, it is possible to store three times as much data as in the SLC write process for the same number of memory cell transistors MT. On the other hand, as shown in Figures 5 and 6, the threshold voltage distribution formed by the SLC write process is simpler than the threshold voltage distribution formed by the TLC write process. Therefore, when writing data of the same size to the non-volatile memory 20, the time required for the SLC write process (tProg(SLC)) is shorter than the time required for the TLC write process (tProg(TLC)).

[0067] Therefore, in the memory system 3 in the high-speed mode, from the viewpoint of write speed, for example, an SLC write process is executed. Also, in the memory system 3 in the normal mode, from the viewpoint of memory capacity, for example, a TLC write process is executed. As a result, when writing the same data, the memory system 3 in the high-speed mode can notify the host 2 of the write completion notification earlier than the memory system 3 in the normal mode.

[0068] Note that data written by the SLC write process in the high-speed mode is read from the non-volatile memory 20 by background processing during a time period when there is no request from the host 2, and then written back to the non-volatile memory 20 by a write process (e.g., TLC write processing) with a higher data integration than the SLC write process. The background processing is processing that is executed voluntarily by the memory controller 10, regardless of a request from the host 2. This prevents the memory capacity of the non-volatile memory 20 from being reduced by the SLC write process in the high-speed mode.

[0069] 1.2.2 A series of processes including transfer rate change processing FIG. 7 is a sequence diagram showing an example of a series of processes including a transfer rate change process in the information processing system according to the embodiment.

[0070] First, the host 2 and the memory system 3 execute a communication establishment process to establish communication via a communication path (S1). This initializes the signal processing units 41 and 51. In this case, the data transfer rate between the host 2 and the memory system 3 is set to an initial value. In other words, a parameter corresponding to the transfer rate is set to an initial parameter INI. The initial parameter INI may be the same as parameter A or B, or may be a parameter different from parameters A and B. Immediately after communication is established with the host 2, the state of the memory system 3 is the normal mode.

[0071] Next, the host 2 and the memory system 3 execute a transfer rate information read process (S2). Specifically, the host 2 issues a transfer rate information read request and transmits it to the memory system 3. In response to the transfer rate information read request, the memory system 3 transmits the transfer rate information 16 to the host 2.

[0072] The host 2 determines a transfer rate according to the state of the memory system 3, based on the transfer rate information 16 received in the process of S2. Specifically, since the state of the memory system 3 is the normal mode, the host 2 selects parameter B corresponding to the normal mode from the transfer rate information 16. Then, the host 2 and the memory system 3 execute a transfer rate change process (S3). As a result, the parameter corresponding to the data transfer rate between the host 2 and the memory system 3 is changed from the initial parameter INI to parameter B.

[0073] The host 2 and the memory system 3 execute the write process and the read process based on the transfer rate changed in the process of S3 (S4).

[0074] Specifically, the host 2 issues a write request and transmits it together with write data to the memory system 3. The write data is transferred from the host 2 to the memory system 3 at a frequency f_r2 corresponding to the Rx transfer rate in the normal mode and at the number of lanes n_r2. In response to the write request, the memory system 3 executes a TLC write process corresponding to the normal mode and writes the data to the non-volatile memory 20.

[0075] Furthermore, the host 2 issues a read request and transmits it to the memory system 3. In response to the read request, the memory system 3 reads data from the non-volatile memory 20. Then, the memory system 3 transmits the read data to the host 2. The read data is transferred from the memory system 3 to the host 2 at a frequency f_t2 and a number of lanes n_t2 corresponding to the Tx transfer rate in the normal mode.

[0076] Next, the host 2 decides to write data at a higher speed. Accordingly, the host 2 and the memory system 3 execute a mode change process (S5). As a result, the state of the memory system 3 changes from the normal mode to the high-speed mode.

[0077] The host 2 determines a transfer rate according to the state of the memory system 3, based on the transfer rate information 16 received in the process of S2. Specifically, because the state of the memory system 3 was changed to high-speed mode in the process of S5, the host 2 selects parameter A corresponding to the high-speed mode from the transfer rate information 16. Then, the host 2 and the memory system 3 execute a transfer rate change process (S6). As a result, the parameter corresponding to the data transfer rate between the host 2 and the memory system 3 is changed from parameter B to parameter A.

[0078] The host 2 and the memory system 3 execute the write process and the read process based on the transfer rate changed in the process of S6 (S7).

[0079] Specifically, the host 2 issues a write request and transmits it together with write data to the memory system 3. The write data is transferred from the host 2 to the memory system 3 at a frequency f_r1 and a number of lanes n_r1 corresponding to the Rx transfer rate in the high-speed mode. In response to the write request, the memory system 3 executes an SLC write process corresponding to the high-speed mode and writes the data to the non-volatile memory 20.

[0080] Furthermore, the host 2 issues a read request and transmits it to the memory system 3. In response to the read request, the memory system 3 reads data from the non-volatile memory 20. Then, the memory system 3 transmits the read data to the host 2. The read data is transferred from the memory system 3 to the host 2 at a frequency f_t1 and a number of lanes n_t1 corresponding to the Tx transfer rate in the high-speed mode.

[0081] When the write and read processes of S7 are completed, the host 2 decides to return the state of the memory system 3 to the normal mode. Accordingly, the host 2 selects parameter B corresponding to the normal mode based on the transfer rate information 16 received in the process of S2. Then, the host 2 and the memory system 3 execute a transfer rate change process (S8). As a result, the parameter corresponding to the data transfer rate between the host 2 and the memory system 3 is changed from parameter A to parameter B.

[0082] Next, the host 2 and the memory system 3 execute a mode change process (S9), which changes the state of the memory system 3 from the high-speed mode to the normal mode.

[0083] Thereafter, the host 2 and the memory system 3 execute the write process and read process based on the transfer rate changed in the process of S9 (S10). The write process and read process of S10 are the same as the write process and read process of S4.

[0084] As described above, the host 2 and the memory system 3 select an appropriate transfer rate depending on the state of the memory system 3, and execute a series of processes.

[0085] 1.2.3 Transfer rate change processing Fig. 8 is a sequence diagram showing an example of a transfer rate change process in the information processing system according to the embodiment. Fig. 8 corresponds to the details of the processes of S3, S6, and S8 in Fig. 7. Fig. 8 shows details of the exchanges between the control circuit 5, protocol control unit 52, and signal processing unit 51 in the host 2, and the control circuit 11, protocol control unit 42, and signal processing unit 41 in the memory controller 10 in the transfer rate change process.

[0086] First, the control circuit 5 of the host 2 issues a request to change the transfer rate and transmits it to the protocol control unit 52 via the data transmission / reception unit 53 (S11). The request to change the transfer rate includes, for example, information on the frequency and number of lanes corresponding to the desired transfer rate.

[0087] When receiving the request to change the transfer rate, the protocol control unit 52 instructs the signal processing unit 51 to inquire of the memory controller 10 whether the transfer rate can be changed (S12). Specifically, for example, the protocol control unit 52 generates an inquiry packet inquiring whether the transfer rate can be changed and transmits it to the signal processing unit 51.

[0088] Upon receiving the inquiry packet generated in the process of S12, the signal processing unit 51 generates an inquiry signal based on the inquiry packet and transmits it to the signal processing unit 41 of the memory controller 10 (S13).

[0089] Upon receiving the inquiry signal generated in the process of S13, the signal processing unit 41 detects an inquiry packet from the inquiry signal and transmits it to the protocol control unit 42 (S14).

[0090] Upon receiving the inquiry packet detected in the process of S14, the protocol control unit 42 checks whether the transfer rate can be changed (S15). Specifically, the protocol control unit 42 checks whether the memory controller 10 supports the frequency and number of lanes that correspond to the transfer rate desired by the host 2.

[0091] The protocol control unit 42 instructs the signal processing unit 41 to respond to the inquiry from the host 2 (S16). Specifically, for example, the protocol control unit 42 generates a response packet including the confirmation result obtained by the process of S15, and transmits the response packet to the signal processing unit 41.

[0092] Upon receiving the response packet generated in the process of S16, the signal processing unit 41 generates a response signal based on the response packet and transmits it to the signal processing unit 51 of the host 2 (S17).

[0093] Upon receiving the response signal generated in the process of S17, the signal processing unit 51 detects a response packet from the response signal and transmits it to the protocol control unit 52 (S18).

[0094] Upon receiving the response packet detected in the process of S18, the protocol control unit 52 checks the response to the inquiry about whether the transfer rate can be changed (S19). Specifically, the protocol control unit 52 determines, based on the response packet, whether the memory controller 10 supports the frequency and number of lanes corresponding to the transfer rate desired by the host 2.

[0095] If the memory controller 10 supports the frequency and number of lanes corresponding to the transfer rate desired by the host 2, the protocol control unit 52 instructs the signal processing unit 51 to stop transferring data to the memory controller 10 at the current transfer rate and to start changing the setting to a new transfer rate (S20). In addition, the protocol control unit 52 generates a transfer stop packet instructing to stop transferring data from the memory controller 10 to the host 2 at the current transfer rate, and transmits it to the signal processing unit 51.

[0096] Upon receiving the transfer stop packet generated in the process of S20, the signal processor 51 generates a transfer stop signal based on the stop packet and transmits it to the signal processor 41 of the memory controller 10 (S21).

[0097] Furthermore, upon receiving the instruction to stop transfer and change the setting generated in the process of S20, the signal processing unit 51 stops the transfer of data to the memory controller 10 and changes the setting of the transfer rate (S22). As a result, the setting of the transfer rate in the signal processing unit 51 is changed.

[0098] Upon receiving the transfer stop signal generated in the process of S21, the signal processing unit 41 detects a transfer stop packet from the transfer stop signal and transmits it to the protocol control unit 42 (S23).

[0099] When the protocol control unit 42 receives the transfer stop packet detected in the process of S23, it instructs the signal processing unit 41 to stop transferring data to the host 2 at the current transfer rate, and to start changing the setting to a new transfer rate (S24). Note that the protocol control unit 42 may set the transfer rate, for which it has confirmed in the process of S15 whether or not it can be changed, as the new transfer rate to which the setting is to be changed.

[0100] When receiving the instruction to stop transfer and change the setting generated in the process of S24, the signal processing unit 41 stops the transfer of data to the host 2 and changes the setting of the transfer rate (S25). As a result, the setting of the transfer rate in the signal processing unit 41 is changed.

[0101] After the process of S25, the signal processing unit 41 notifies the protocol control unit 42 of the completion of changing the transfer rate setting (S26).

[0102] The protocol control unit 42 transfers the notification received from the signal processing unit 41 in the process of S26 to the control circuit 11 (S27).

[0103] Similarly, after the process of S22, the signal processing unit 51 notifies the protocol control unit 52 of the completion of changing the transfer rate setting (S28).

[0104] The protocol control unit 52 transfers the notification received from the signal processing unit 51 in the process of S28 to the control circuit 5 (S29).

[0105] After the processes of S27 and S29, the transfer rate change process ends.

[0106] 1.3 Effects of the embodiment According to the embodiment, the memory controller 10 is configured to transmit transfer rate information 16 including information regarding the transfer rate of write data to the host 2 in response to a transfer rate information read request from the host 2. The transfer rate information 16 includes a frequency f_r1 and a number of lanes n_r1 associated with the high-speed mode of the memory system 3, and a frequency f_r2 and a number of lanes n_r2 associated with the normal mode. This allows the host 2 to distinguish between an optimal transfer rate when the memory system 3 is operated in the high-speed mode and an optimal transfer rate when the memory system 3 is operated in the normal mode.

[0107] In addition, the write performance of the memory system 3 is limited by the time tProg required for the write process. In other words, if the transfer rate is sufficiently higher than the speed of the write process, the transfer rate does not contribute to the write performance. Therefore, an excessively high transfer rate is not preferable because it not only does not contribute to improving the write performance, but also increases power consumption.

[0108] According to the embodiment, the host 2 can change the transfer rate according to the state of the memory system 3. Specifically, when operating the memory system 3 in the normal mode, the host 2 applies a transfer rate lower than the transfer rate applied in the high-speed mode. Therefore, it is possible to reduce power consumption while maintaining the maximum write performance according to the state of the memory system 3.

[0109] 2. Modifications, etc. Various modifications can be applied to the above-described embodiment.

[0110] 2.1 Variations In the above embodiment, the number of lanes and the frequency are stored in the transfer rate information 16 as parameters related to the optimum transfer rate in association with the state of the memory system 3, but this is not limiting. For example, the parameters related to the optimum transfer rate may be stored in association with the number of bits written per memory cell by the write process.

[0111] FIG. 9 is a diagram showing an example of a data structure of transfer rate information stored in a memory system according to a modified example.

[0112] 9, the frequency f_r1 and the number of lanes n_r1 corresponding to the Rx transfer rate in the high-speed mode, and the frequency f_t1 and the number of lanes n_t1 corresponding to the Tx transfer rate in the high-speed mode are the same as the transfer rate information 16 shown in FIG 3 in the embodiment. That is, the frequency f_r1 and the number of lanes n_r1 corresponding to the Rx transfer rate in the high-speed mode, and the frequency f_t1 and the number of lanes n_t1 corresponding to the Tx transfer rate in the high-speed mode are included in the parameter A. The parameter A is associated with the SLC write process.

[0113] In the transfer rate information 16A, the parameters corresponding to the Rx transfer rate in the normal mode are further classified into two types of parameters B and C. The parameters B and C correspond to a TLC write process and a QLC (Quadruple Level Cell) write process, respectively. The QLC write process is a write process for storing 4 bits of data in one memory cell transistor MT. That is, when writing data of the same size to the nonvolatile memory 20, the time required for the QLC write process (tProg(QLC)) is longer than the time required for the TLC write process (tProg(TLC)).

[0114] Parameter B includes a frequency f_r2_1 and a number of lanes n_r2_1 corresponding to the Rx transfer rate in normal mode when a TLC write process is performed. Parameter C includes a frequency f_r2_2 and a number of lanes n_r2_2 corresponding to the Rx transfer rate in normal mode when a QLC write process is performed. Note that the frequency f_t2 and the number of lanes n_t2 corresponding to the Tx transfer rate in normal mode are included in both parameters B and C.

[0115] The Rx transfer rate in the high-speed mode is set to be higher than the Rx transfer rate in the normal mode. That is, the Rx transfer rate determined by the frequency f_r1 and the number of lanes n_r1 is higher than both the Rx transfer rate determined by the frequency f_r2_1 and the number of lanes n_r2_1 and the Rx transfer rate determined by the frequency f_r2_2 and the number of lanes n_r2_2. Also, the Rx transfer rate in the normal mode when the TLC write process is performed is set to be higher than the Rx transfer rate in the normal mode when the QLC write process is performed.

[0116] By transmitting the transfer rate information 16A as described above from the memory system 3 to the host 2, the host 2 can grasp the optimal transfer rate according to the number of bits written per memory cell by the write process. This allows the host 2 to transfer data at different transfer rates when the memory system 3 is caused to execute a TLC write process and when the memory system 3 is caused to execute a QLC write process when the memory system 3 is in the normal mode. Therefore, by selecting a transfer rate according to the length of time required for the write process, it is possible to further suppress an increase in power consumption during data transfer.

[0117] 2.2 Other In the above embodiment, the frequency and the number of lanes are stored as the transfer rate information 16, but the present invention is not limited to this. For example, the transfer rate information 16 may store information indicating a mode that defines the transfer rate. Specifically, for example, when the memory system 3 is UFS, "HS-G5B 2Lane" and "HS-G4B 1Lane" may be stored as parameters A and B of the transfer rate information 16, respectively.

[0118] In the above embodiment, the memory system 3 is described as being UFS, but the present invention is not limited to this. For example, the memory system 3 may be TM In this case, the communication between the device interface circuit 6 and the host interface circuit 13 is performed using a PCIe TM (Peripheral Component Interconnect express).

[0119] In addition, in the above embodiment, it is assumed that two-lane communication paths LA1 and LA2 are provided as a physical communication path for the memory controller 10 to receive data from the host 2, and two-lane communication paths LB1 and LB2 are provided as a physical communication path for the memory controller 10 to transmit data to the host 2, but this is not limited to the above. For example, each of the communication path for the memory controller 10 to receive data from the host 2 and the communication path for the memory controller 10 to transmit data to the host 2 may be provided with three or more lanes.

[0120] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0121] 1. Information processing system 2. Host 3. Memory system 6...Device interface circuit 10…Memory controller 5, 11...Control circuit 12...Non-volatile memory interface circuit 13...Host interface circuit 14...Volatile memory 15...Buffer memory 16,16A...Transfer rate information 20...Non-volatile memory 41, 51 ... signal processing section 41R, 51R…Receiver 41T, 51T…Transmitter 42, 52…Protocol control section 43, 53…Data transmission / reception section

Claims

1. a non-volatile memory including a plurality of memory cells; a memory controller having a first state for writing write data transferred from an external host to the nonvolatile memory in a first bit number per memory cell and a second state for writing write data in a second bit number different from the first bit number; Equipped with the memory controller is configured to transmit, in response to a first request from the host, information regarding a transfer rate of the write data to the host; The information is First information associated with the first state; and second information associated with the second state; and Including, Memory system.

2. Each of the first information and the second information includes at least one of a number of lanes of a bus used for transferring the write data from the host and a frequency.

2. The memory system of claim 1.

3. The first information includes a first number of lanes and a first frequency, The second information includes a second number of lanes and a second frequency; When the first number of lanes is equal to the second number of lanes, the first frequency is higher than the second frequency; When the first frequency and the second frequency are equal, the first number of lanes is greater than the second number of lanes.

3. The memory system of claim 2.

4. The memory controller includes: receiving the write data from the host at a first transfer rate in the first state; In the second state, the write data is received from the host at a second transfer rate different from the first transfer rate. It was configured as follows:

2. The memory system of claim 1.

5. The memory controller includes: In the first state, transmitting data to the host at a third transfer rate independent of the first transfer rate; In the second state, data is transmitted to the host at a fourth transfer rate that is independent of the second transfer rate. It was configured as follows:

5. The memory system of claim 4.

6. the first number of bits is smaller than the second number of bits; The first transfer rate is higher than the second transfer rate.

5. The memory system of claim 4.

7. the first number of bits is smaller than the second number of bits; The memory controller in the first state execute a first write process in response to a write request from the host to write the write data to the non-volatile memory with the first bit number per memory cell; notifying the host of the completion of the write process after the first write process is completed; After the notification, a second write process is executed to read the write data from the nonvolatile memory and write the data to the nonvolatile memory at the second bit number per memory cell. It was configured as follows:

2. The memory system of claim 1.

8. The memory controller in the first state is configured to execute the second write operation independent of a request from the host.

8. The memory system of claim 7.

9. a time period during which the write data is written to the nonvolatile memory by the first write process is shorter than a time period during which the write data is written to the nonvolatile memory by the second write process; 8. The memory system of claim 7.

10. the first number of bits is 1; 8. The memory system of claim 7.

11. the memory controller further has a third state for writing the write data to the non-volatile memory in a third number of bits per memory cell; the information further includes third information associated with the third state; the third number of bits is different from the first number of bits and the second number of bits; 2. The memory system of claim 1.

12. The host, A memory system; Equipped with The memory system includes: a non-volatile memory including a plurality of memory cells; a memory controller having a first state for writing write data transferred from the host to the non-volatile memory in a first number of bits per memory cell and a second state for writing write data in a second number of bits different from the first number of bits; Including, the memory controller is configured to transmit, in response to a first request from the host, information regarding a transfer rate of the write data to the host; The information is First information associated with the first state; and second information associated with the second state; and Including, Information processing system.

13. Each of the first information and the second information includes at least one of a number of lanes of a bus used for transferring the write data from the host and a frequency.

13. The information processing system according to claim 12.

14. The host is When the memory controller is operated in the first state, the write data is transmitted to the memory controller at a first transfer rate based on the first information; When the memory controller is operated in the second state, the write data is transmitted to the memory controller at a second transfer rate different from the first transfer rate based on the second information. It was configured as follows:

13. The information processing system according to claim 12.

15. the first number of bits is smaller than the second number of bits; The first transfer rate is higher than the second transfer rate.

15. An information processing system according to claim 14.

16. the first number of bits is smaller than the second number of bits; The memory controller in the first state execute a first write process in response to a write request from the host to write the write data to the non-volatile memory with the first bit number per memory cell; notifying the host of the completion of the write process after the first write process is completed; After the notification, a second write process is executed to read the write data from the nonvolatile memory and write the data to the nonvolatile memory at the second bit number per memory cell. It was configured as follows:

13. The information processing system according to claim 12.

17. The memory controller in the first state is configured to execute the second write operation independent of a request from the host.

17. An information processing system according to claim 16.

18. a time period during which the write data is written to the nonvolatile memory by the first write process is shorter than a time period during which the write data is written to the nonvolatile memory by the second write process; 17. An information processing system according to claim 16.

19. the first number of bits is 1; 17. An information processing system according to claim 16.

20. The memory system is UFS.

13. The information processing system according to claim 12.

21. The first state is a state in which a light booster function is enabled, The second state is a state in which the light booster function is disabled.

21. The information processing system according to claim 20.

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