Reference voltage source circuit

Abstract

To stably output a reference voltage by decreasing an influence of a base current amplification factor of a PNP bipolar transistor included in a circuit structure.SOLUTION: A reference voltage source circuit for outputting a reference voltage comprises: a compensation current supplying unit for supplying a compensation current to at least one emitter of a first PNP bipolar transistor or a second PNP bipolar transistor, so that a difference in emitter currents of the first PNP bipolar transistor or a PNP bipolar transistor included in the circuit decreases.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a reference voltage source circuit. [Background technology]

[0002] In analog circuits on integrated circuits, reference voltage source circuits are often used as a circuit configuration for generating a reference voltage. For example, Non-Patent Document 1 discloses a circuit configuration for generating a constant voltage lower than the bandgap voltage (≈1.2 V) as this type of reference voltage source circuit. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] H.banba, “A CMOS bandgap reference circuit with sub-1-V operation,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5 pp.670-674, May. 1999. Summary of the Invention [Problem to be solved by the invention]

[0004] Here, a reference voltage source circuit 1' disclosed in Non-Patent Document 1 will be described as a reference technique with reference to Fig. 3 and Fig. 4. Fig. 3 is a circuit diagram showing a reference voltage source circuit 1' according to the reference technique, and Fig. 4 is a circuit diagram showing a reference voltage V output from the reference voltage source circuit 1' in Fig. 3. REFp 4 is a simulation result showing the temperature characteristics of

[0005] The reference voltage source circuit 1' includes a PMOS transistor M p1p , M p2p , M p3p , power supply V DD , operational amplifier A 1p , resistance R 1p , R 2p , R 3p , R4p , PNP bipolar transistor Q p1p , Q p2p The PMOS transistor M p1p , M p2p , M p3p Each source is connected to the power supply V DD and each gate is connected to the operational amplifier A 1p Also, the PMOS transistor M p1p The drain of the operational amplifier A 1p is connected to the positive input terminal of the PMOS transistor M p2p The drain of the operational amplifier A 1p The negative input terminal of the MOSFET is connected to the negative input terminal of the MOSFET.

[0006] Also, the PMOS transistor M p1p Between the drain of and the ground point GND, there is a resistor R 2p A PMOS transistor M p1p Drain and resistor R 2p A first node N 1 is resistor R 1p Through the PNP bipolar transistor Q p1p The emitter of the PMOS transistor M p2p Between the drain of and the ground point GND, there is a resistor R 3p A PMOS transistor M p2p Drain and resistor R 3p A second node N 2 The PNP bipolar transistor Q p2p The emitter terminal of the PNP bipolar transistor Q p1p and PNP bipolar transistor Q p2p The collector and base of each of the PMOS transistors M p3p The drain of the resistor R 4p The PMOS transistor M p3p Drain and resistor R 4p Between REFp An output terminal capable of outputting the signal is provided.

[0007] Next, the operating principle of the reference voltage source circuit having the above configuration will be explained. Generally, the characteristics of a PNP bipolar transistor are as follows: C , normalized emitter area ratio is x, saturation current is I S , the base-emitter voltage is V BE , the elementary charge is q, the Boltzmann constant is k, the absolute temperature is T, and the thermal voltage is V T = k × T ÷ q, base current I B , base current amplification factor β, emitter current I E Then, the following relationship holds: I C =x×I S ×exp(V EB / V T ),I C = βI B ,I C +I B =I E (1)

[0008] In the circuit configuration shown in FIG. p1p Drain current I dMp1p , and a PMOS transistor M p2p Drain current I dMp2p is the operational amplifier A 1p Voltage gain A 1p , operational amplifier A 1p The potential of the positive input terminal of +p , the potential of the negative input terminal of the operational amplifier V -p , PMOS transistor M p1p Voltage-current conversion ratio g mMp1p , PMOS transistor M p2p Voltage-current conversion ratio g mMp2p Using these, they are expressed by the following equations: I dMp1p =g mMp1p A 1p (v +p -v -p ) (2) I dMp2p =g mMp2p A 1p (v +p -v -p ) (3)

[0009] (2) g mMp1p A 1p Divide both sides of equation (3) by g mMp2p A 1p By dividing by , the above equations (2) and (3) are transformed as follows: I dMp1p / g mMp1p A 1p =(v +p -v -p ) (4) I dMp2p / g mMp2p A 1p =(v +p -v -p ) (5) Here, operational amplifier A 1p Voltage gain A 1p If is designed to be sufficiently large, the left sides of equations (4) and (5) can both be considered to be zero, and the following equation is obtained: v +p =v -p (6) Also, according to the circuit diagram in Figure 1, the operational amplifier A 1p The potential of the negative input terminal of -p is a PNP bipolar transistor Q p2p The emitter-base voltage V EBQp2p Therefore, the above equation (6) can be expressed as follows: v +p =v -p =V EBQp2p (7)

[0010] Here, the resistor R 2p and resistor R 3p is equal to the resistance R EBp If the design is such that 2p Current I R2p , and resistor R 3p Current I R3p Using the above equation (7), these are equal to the following equations: I R2p =v +p / R 2p =V EBQp2p / R EBp (8) I R3p =v -p / R 3p =V EBQp2p / R EBp (9)

[0011] Also, the PNP bipolar transistor Q p1p The emitter current I EQp1p , PNP bipolar transistor Q p2p The emitter current I EQp2p is the first node N 1 and the second node N 2 By applying Kirchhoff's law to the above equations (8) and (9), the following equation can be obtained: I EQp1p =I dMp1p -I R2p =I dMp1p -V EBQp2p / R EBp (10) I EQp2p =I dMp2p -I R3p =I dMp2p -V EBQp2p / R EBp (11) In addition, according to the circuit configuration shown in FIG. p1p Gate-source voltage and PMOS transistor M p2p The gate-source voltages of the PMOS transistor M p1p Voltage-current conversion ratio g mMp1p and PMOS transistor M p2p Voltage-current conversion ratio g mMp2p When the PMOS transistor M p1p Drain current I dMp1p and PMOS transistor M p2p Drain current I dMp2p At this time, from the above equations (10) and (11), the PNP bipolar transistor Q p1p The emitter current I EQp1p and PNP bipolar transistor Q p2p The emitter current I EQp2p is equal to the following equation: IEQp1p =I EQp2p (12)

[0012] PNP bipolar transistor Q p1p The emitter-base voltage of V EBQp1p Then, the resistance R 1p The current I R1p can be expressed as follows using the above equation (7): I R1p =(v +p -V EBQp1p ) / R 1p =(V EBQp2p -V EBQp1p ) / R 1p (13)

[0013] Here, the second equation of the above (1) is I C / β=I B If the base current amplification factor β of the PNP bipolar transistor is sufficiently large, then I B = 0. In this case, the third equation of the above (1) can be regarded as I C =I E Therefore, the first equation of the above equation (1) can be rewritten as follows: I E =x×I S ×exp(V EB / V T ) (14) This formula (14) can be further modified as follows: V EB =V T ln(I E / xI S ) (15)

[0014] PNP bipolar transistor Q p1p The normalized emitter area ratio of m p , PNP bipolar transistor Q p2p When the normalized emitter area ratio is designed to be 1, the above formula (13) is expressed as follows using the above formulas (12) and (15). TIFF2025034330000002.tif17170

[0015] From Figure 3, PMOS transistor M p3p The gate-source voltage of the PMOS transistor M p1p Gate-source voltage and PMOS transistor M p2p The gate-source voltages of the PMOS transistor M p1p Voltage-current conversion ratio g mMp1p and PMOS transistor M p2p Voltage-current conversion ratio g mMp2p and PMOS transistor M p3p Voltage-current conversion ratio g mMp3p If all are designed equally, the PMOS transistor M p1p Drain current I dMp1p and PMOS transistor M p2p Drain current I dMp2p and PMOS transistor M p3p Drain current I dMp3p In this case, from the above formulas (8), (9), (12), and (16), the PMOS transistor M p3p Drain current I dMp3p is expressed as follows: TIFF2025034330000003.tif12170

[0016] The PMOS transistor M p3p Drain current I dMp3p is the resistance R 4p Therefore, the reference voltage V REFp is expressed by the following equation. According to Non-Patent Document 1 (TIFF2025034330000004.tif12170), the emitter-base voltage V EB It is known that V has a negative temperature characteristic. Therefore, in the above formula (18), the first term V EB The negative temperature characteristic of the second term, thermal voltage V T The positive temperature characteristic of the reference voltage V REFp can be made insensitive to temperature (see FIG. 4).

[0017] In the circuit configuration according to the above-mentioned reference technique, the base current amplification factor β of the PNP bipolar transistor is sufficiently large, and the collector current and the emitter current are equal (I C =I E However, in recent years, the base current amplification factor β of PNP bipolar transistors available on the market has become significantly smaller, and the prerequisite that the collector current and emitter current are equal may not be met. In this case, the second formula (I C = βI B ) and the third equation of equation (1), C +I B =I E ) to I C =β(β+1)I E From this and the first equation of (1), the above equations (15) and (16) become as follows. TIFF2025034330000005.tif11170TIFF2025034330000006.tif12170From equations (19) and (20), in the reference technology shown in Figure 3, the base current amplification factor β of the PNP bipolar transistor decreases and is affected by the base current amplification factor β. Figure 4 shows the verification results when the base current amplification factor β of the PNP bipolar transistor used in the reference voltage source circuit 1' is changed, and these verification results also show that when the base current amplification factor β changes, the characteristics of the PNP bipolar transistor are affected and the reference voltage V REFp has been shown to be unstable.

[0018] At least one embodiment of the present disclosure has been made in consideration of the above-mentioned circumstances, and aims to provide a reference voltage source circuit that can stably output a reference voltage by reducing the influence of the base current amplification factor of a PNP bipolar transistor included in the circuit configuration. [Means for solving the problem]

[0019] In order to solve the above problems, a reference voltage source circuit according to at least one aspect of the present disclosure comprises: (1) A first PMOS transistor (e.g., the PMOS transistor M in this embodiment) whose sources are connected to a common power supply p6 ), a second PMOS transistor (for example, the PMOS transistor M p7 ) and a third PMOS transistor (for example, the PMOS transistor M p10 )and, a first operational amplifier (e.g., operational amplifier A in this embodiment) having an output terminal to which the gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected, a positive input terminal to which the drain of the first PMOS transistor is connected, and a negative input terminal to which the drain of the second PMOS transistor is connected; 2 )and, A first PNP bipolar transistor (e.g., PNP bipolar transistor Q in this embodiment) has a collector and a base connected to a ground point. p3 ) and a second PNP bipolar transistor (for example, the PNP bipolar transistor Q p4 )and, A first resistor (for example, resistor R 3 )and, A first node (for example, a first node N in this embodiment) is provided between the drain of the first PMOS transistor and the first resistor. 1 )and, A second resistor (for example, resistor R 2 )and, A second node (for example, the second node N in this embodiment) is provided between the drain of the second PMOS transistor and the emitter of the second PNP bipolar transistor. 2 )and, A third resistor (for example, resistor R 4 )and, A fourth resistor (for example, resistor R 5 )and, an output terminal provided between the drain of the third PMOS transistor and the fourth resistor; a compensation current supplying unit for supplying a compensation current to at least one of the emitters of the first PNP bipolar transistor and the second PNP bipolar transistor so that a difference between the emitter currents of the first PNP bipolar transistor and the second PNP bipolar transistor is reduced; Equipped with.

[0020] According to the above aspect (1), a compensation current is supplied from the compensation current supply unit to the emitter of at least one of the first PNP bipolar transistor or the second PNP bipolar transistor, thereby reducing the difference between the emitter currents of the first PNP bipolar transistor and the second PNP bipolar transistor, thereby effectively reducing the influence of the base current amplification factor even when the base current amplification factor of the PNP bipolar transistor is reduced.

[0021] (2) In another embodiment, in the above embodiment (1), The compensation current supply unit supplies the compensation current so that the emitter currents of the first PNP bipolar transistor and the second PNP bipolar transistor become equal to each other.

[0022] According to the above aspect (2), by supplying a compensation current so that the emitter currents of the first PNP bipolar transistor and the second PNP bipolar transistor are equal, the influence of the base current amplification factor can be more effectively reduced even when the base current amplification factor of the PNP bipolar transistor is reduced.

[0023] (3) In another embodiment, in the above embodiment (1) or (2), The compensation current supply unit is configured to supply a first compensation current and a second compensation current as the compensation current to the first PNP bipolar transistor and the second PNP bipolar transistor, respectively.

[0024] According to the above aspect (3), The first compensation current and the second compensation current are respectively supplied as compensation currents to the emitters of the first PNP bipolar transistor and the second PNP bipolar transistor, thereby suitably reducing the difference between the emitter currents of the two.

[0025] (4) In another embodiment, in the above embodiment (3), The compensation current supply unit includes: A fourth PMOS transistor (for example, the PMOS transistor M in this embodiment) whose source is connected to the power supply p1 ) and a fifth PMOS transistor (for example, the PMOS transistor M p2 ), a sixth PMOS transistor (for example, the PMOS transistor M p3 )and, a second operational amplifier (for example, operational amplifier A in this embodiment) having an output terminal to which the gates of the fourth PMOS transistor and the fifth PMOS transistor are connected, a positive input terminal to which the drain of the fourth PMOS transistor is connected, and a negative input terminal to which the drain of the fifth PMOS transistor is connected; 1 )and, A third PNP bipolar transistor (e.g., PNP bipolar transistor Q in this embodiment) has its collector connected to the ground point and its base connected to each other. p1 ) and a fourth PNP bipolar transistor (for example, the PNP bipolar transistor Q p2 )and, A fifth resistor (for example, resistor R 1 )and, A third node (for example, the third node N in this embodiment) is provided between the bases of the third PNP bipolar transistor and the fourth PNP bipolar transistor. 3 )and, A first NMOS transistor (e.g., NMOS transistor M in this embodiment) has a drain connected to the third node and a source connected to the ground node. n1 )and, A second NMOS transistor (e.g., NMOS transistor M in this embodiment) has a gate and a drain connected to the gate of the first NMOS transistor and a source connected to the ground. n2 )and, A third NMOS transistor (e.g., NMOS transistor M in this embodiment) has a source connected to the drain of the second NMOS transistor and a gate connected to the emitter of the fourth PNP bipolar transistor. n3 )and, A sixth PMOS transistor (for example, the PMOS transistor M in this embodiment) whose drain is connected to the drain of the third NMOS transistor p3 )and, A seventh PMOS transistor (for example, the PMOS transistor M in this embodiment) whose drain is connected to the emitter of the third PNP bipolar transistor p4 )and, An eighth PMOS transistor (for example, the PMOS transistor M in this embodiment) whose drain is connected to the emitter of the fourth PNP bipolar transistor p5 )and, A ninth PMOS transistor (for example, the PMOS transistor M in this embodiment) having a drain that is connected to the emitter of the first PNP bipolar transistor to output the first compensation current. p8 )and, A tenth PMOS transistor (for example, the PMOS transistor M in this embodiment) having a drain that is connected to the emitter of the second PNP bipolar transistor to output the second compensation current. p9 )and, Equipped with The sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor and the tenth PMOS transistor each have a source connected to the power supply and a gate connected to the drain of the sixth PMOS transistor.

[0026] According to the above aspect (4), it is possible to realize a compensation current supply unit capable of suitably supplying the first compensation current and the second compensation current for reducing the difference between the emitter currents of the first PNP bipolar transistor and the second PNP bipolar transistor.

[0027] (5) In another embodiment, in any one of the above (1) to (4), The reference voltage output from the output terminal (for example, the reference voltage V REF ) is lower than the bandgap voltage.

[0028] According to the above aspect (5), it is possible to realize a reference voltage source circuit capable of outputting a reference voltage lower than the bandgap voltage from the output terminal. Effect of the Invention

[0029] According to at least one embodiment of the present disclosure, it is possible to provide a reference voltage source circuit capable of stably outputting a reference voltage by reducing the influence of the base current amplification factor of a PNP bipolar transistor included in the circuit configuration. [Brief description of the drawings]

[0030] [Figure 1] 1 is a circuit diagram illustrating a reference voltage source circuit according to an embodiment. [Diagram 2] 2 is a simulation result showing the temperature characteristics of the reference voltage output from the reference voltage source circuit of FIG. 1. [Diagram 3] FIG. 1 is a circuit diagram showing a reference voltage source circuit according to a reference technique. [Figure 4] 4 is a simulation result showing the temperature characteristics of the reference voltage output from the reference voltage source circuit of FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, some embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of components described as the embodiments or shown in the drawings are merely illustrative examples and are not intended to limit the scope of the present disclosure.

[0032] FIG. 1 is a circuit diagram showing a reference voltage source circuit 1 according to an embodiment, and FIG. 2 is a circuit diagram showing a reference voltage V REF The figure shows the results of a simulation that shows the temperature characteristics of the reference voltage source circuit 1. The reference voltage source circuit 1 outputs a reference voltage V REF The circuit is configured to include a reference voltage generating section 10 and a compensation current generating section 20.

[0033] The reference voltage generating unit 10 generates the reference voltage V REF The reference voltage generating unit 10 has a circuit configuration for generating a reference voltage source circuit 1′ according to the reference technique described above with reference to FIG. p6 (The PMOS transistor M in Fig. 3 p1p ), M p7 (The PMOS transistor M in Fig. 3 p2p ), M p10 (The PMOS transistor M in Fig. 3 p3p ) and the operational amplifier A 2 (Operational amplifier A in Figure 3 1p ) and a PNP bipolar transistor Q p3 (The PNP bipolar transistor Q in Figure 3 p1p ), Q p4 (The PNP bipolar transistor Q in Figure 3 p2p ) and resistor R 2 (Resistance R in Figure 3) 1p ), R 3 (Resistance R in Figure 3) 2p ), R 4 (Resistance R in Figure 3) 3p ), R 5 (Resistance R in Figure 3) 4p (corresponding to).

[0034] In the reference voltage generating unit 10, a PMOS transistor M p6 , M p7 , M p10 Each source is connected to the power supply V DD and each gate is connected to the operational amplifier A 2 Also, the PMOS transistor M p6 The drain of the operational amplifier A 2 is connected to the positive input terminal of the PMOS transistor M p7 The drain of the operational amplifier A 2 The negative input terminal of the MOSFET is connected to the negative input terminal of the MOSFET.

[0035] Also, the PMOS transistor M p6 Between the drain of and the ground point GND, there is a resistor R 3 A PMOS transistor M p6 The drain terminal and resistor R 3 A first node N 1 is resistor R 2 Through the PNP bipolar transistor Q p3 The emitter of the PMOS transistor M p7 Between the drain of and the ground point GND, there is a resistor R 4 A PMOS transistor M p7 Drain and resistor R 4 A second node N 2 The PNP bipolar transistor Q p4 The emitter terminal of the PNP bipolar transistor Q p3 , Q p4 The collector and base of each of the PMOS transistors M p10 The drain of the resistor R 5 The PMOS transistor M p10 Drain and resistor R 5 Between REF An output terminal is provided for outputting the signal.

[0036] The compensation current generating unit 20 includes a PNP bipolar transistor Q p3 , or PNP bipolar transistor Q p4 The compensation current is supplied to at least one of the emitters of the PNP bipolar transistor Q p3 , or PNP bipolar transistor Q p4 In this embodiment, the compensation current generating unit 20 is adjusted so that the difference between the emitter currents of the PNP bipolar transistor Q p3 , and a PNP bipolar transistor Q p4 As a result, even if the base current amplification factor β of each PNP bipolar transistor included in the reference voltage source circuit 1 becomes small, the influence of the base current amplification factor β is reduced, and the reference voltage V REF can be output stably.

[0037] The compensation current generating unit 20 includes a PNP bipolar transistor Q p3 , and a PNP bipolar transistor Q p4 In this manner, the PNP bipolar transistor Q p3 and PNP bipolar transistor Q p4 By supplying compensation currents to both emitters, the difference between the emitter currents can be suitably reduced.

[0038] Next, a specific circuit configuration of the compensation current generating unit 20 will be described. The compensation current generating unit 20 includes a PMOS transistor M p1 , M p2 , M p3 , M p4 , M p5 , M p8 , M p9 and operational amplifier A 1 and a PNP bipolar transistor Q p1 , Q p2 and resistor R 1 and

[0039] PMOS transistor M p1 , M p2 , M p3 , M p4 , M p5 , M p8 , M p9 Each source is connected to the power supply V DD Also connected to the PMOS transistor M p1 , M p2 Each gate is an operational amplifier A 1 The output terminal of the PMOS transistor M p1 The drain of the operational amplifier A 1 is connected to the positive input terminal of the PMOS transistor M p2 The drain of the operational amplifier A 1 The negative input terminal of the MOSFET is connected to the negative input terminal of the MOSFET.

[0040] PNP bipolar transistor Q p1 , Q p2 The collectors of the PMOS transistors M are connected to the ground node GND, and the bases of the PMOS transistors M are connected to each other. p1 and the drain of the PNP bipolar transistor Q p1 Between the emitter and the 1 A PNP bipolar transistor Q p1 , Q p2 Between the gates of the third node N 3 will be established.

[0041] NMOS transistor M n1 The drain is the third node N 3 and the source is connected to the ground point GND. n2 The gate and drain of the NMOS transistor M n1 The gate of the NMOS transistor M is connected to the ground node GND. n3 The source is an NMOS transistor M n2 The gate of the PNP bipolar transistor Q p2 is connected to the emitter of the

[0042] PMOS transistor M p3 The drain of the NMOS transistor M n3 The drain of the PMOS transistor M p4 The drain of the bipolar transistor Q p1 The emitter of the PMOS transistor M p5は、 The drain is a PNP bipolar transistor Q p2 The emitter of the PMOS transistor M p8 is a PNP bipolar transistor Q p3 The PMOS transistor M has a drain that is connected to the emitter of the PMOS transistor M to output the first compensation current. p9 is a PNP bipolar transistor Q p4 The drain of the PNP bipolar transistor Q is connected to the emitter of the p3 The emitter of the PMOS transistor M p8 The drain of the PMOS transistor M p8 Drain current I dMp8 is supplied. PNP bipolar transistor Q p4 The emitter of the PMOS transistor M p9 The drain of the PMOS transistor M p9 Drain current I dMp9 is supplied.

[0043] PNP bipolar transistor Q p3 The emitter current I EQp3 , base current I BQp3 , collector current I CQp3 , the emitter current I of the PNP bipolar transistor Qp4 EQp4 , base current I BQp4 , collector current I CQp4 Using this, a PNP bipolar transistor Q p3 , Q p4 For an emitter, the following relationship holds: I EQp3 +I dMp8 =IBQp3 +I CQp3 (twenty one) I EQp4 +I dMp4 =I BQp4 +I CQp4 (twenty two) Here I dMp8 =I BQp3 and I dMp9 =I BQp4 If these are already established, then the above equations (21) and (22) can be transformed as follows: I EQp3 =I CQp3 (twenty three) I EQp4 =I CQp4 (twenty four)

[0044] The above formulas (23) and (24) mean that a state equivalent to when the base current amplification factor β is sufficiently large in the reference technology shown in Fig. 3 is realized, that is, formulas (14) and (15) are realized, not formulas (19) and (20). This means that the effect of the base current amplification factor β is eliminated by the compensation current supplied from the compensation current generating unit 20.

[0045] Here, the PMOS transistor M p1 , M p2 and resistor R 1 and operational amplifier A 1 and a PNP bipolar transistor Q p1 , Q p2 The circuit is configured by each element (PMOS transistor M p6 , M p7 and resistor R 2 and operational amplifier A 2 and a PNP bipolar transistor Q p3 , Q p4 ) are the same as the PMOS transistor M p1 , M p2 , M p6 , M p7 have equal W / L values, and the resistance R 1 , R 2 have equal resistance values, and operational amplifier A 1, A 2 are the same circuit elements, and the PNP bipolar transistor Q p1 , Q p3 have equal normalized emitter area ratios, and the PNP bipolar transistor Q p2 , Q p4 have equal normalized emitter area ratios. This results in a resistor R 1 , R 2 The currents flowing through the

[0046] PNP bipolar transistor Q p1 , Q p2 The bases of the third nodes N 3 Through the NMOS transistor M n1 Therefore, the drain of the NMOS transistor M n1 Drain current I dMn1 , PNP bipolar transistor Q p1 The base current I BQp1 , PNP bipolar transistor Q p2 The base current I BQp2 Using this, the following relation holds: I BQp1 +I BQp2 =I dMn1 (twenty five)

[0047] Here, the NMOS transistor M n1 , M n2 If the W / L value is designed to be 2:1, the NMOS transistor M n2 Drain current I dMn2 is the drain current I dMn1 This half of the current I dMn2 is the NMOS transistor M n3 The current flows from the source to the drain of the PMOS transistor M p3 The drain of the PMOS transistor M p3 , M p4 , M p5 , M p8 , M p9 The gate of the PMOS transistor M p3Since it is connected to the drain of the PMOS transistor M p3 , M p4 , M p5 , M p8 , M p9 By designing the W / L values ​​to be 1:1:1:1:1, the drain currents of these five PMOS transistors are equal. p3 Drain current I dMp3 , PMOS transistor M p4 Drain current I dMp4 , PMOS transistor M p5 Drain current I dMp5 Using this, the following equation is established: I dMp3 =I dMp4 =I dMp5 =I dMp8 =I dMp9 (26)

[0048] Also, the PNP bipolar transistor Q p1 and PNP bipolar transistor Q p2 The current flowing through the PNP bipolar transistor Q p1 The emitter current I EBQp1 , PNP bipolar transistor Q p1 The collector current I CBQp1 , PNP bipolar transistor Q p2 The emitter current I EBQp2 , PNP bipolar transistor Q p2 The collector current I CBQp2 , PMOS transistor M p1 Drain current I dMp1 , PMOS transistor M p2 Drain current I dMp2 Using this, it is expressed by the following formula: I EBQp1 =I dMp1 +I dMp4 =I BQp1 +I CBQp1 (27) I EBQp2 =I dMp2 +I dMp5 =I BQp2 +I CBQp2 (28)

[0049] Here, the relation I used in the case of the reference technology C = βI B and I C =β / (β+1)I E From I B =1 / (β+1)I E The following relationship holds: In addition, since the left side of the above equation (27) is equal to the left side of the above equation (28), the PNP bipolar transistor Q p1 The base current of the PNP bipolar transistor Q p2 The base currents of the two transistors are equal. In other words, the following relationship holds: I BQp1 =I BQp2 (29) Therefore, from the above equations (29) and (25), equation (26) can be rewritten as follows: I dMp3 =I dMp4 =I dMp5 =I dMp8 =I dMp9 =I BQp1 =I BQp2 (30)

[0050] According to the above formula (30), the PMOS transistor M p8 Drain current I dMp8 and PMOS transistor M p9 Drain current I dMp9 are PNP bipolar transistors Q p1 The base current I BQp1 and PNP bipolar transistor Q p2 The base current I BQp2 This means that the PNP bipolar transistor Q p3 and PNP bipolar transistor Q p4 This means that the above equations (23) and (24) can be established, and the effect of the base current amplification factor β can be eliminated.

[0051] In the simulation results shown in FIG. 2, the reference voltage V REFIt is shown that the characteristic variation with respect to the base current amplification factor β is significantly reduced compared to the simulation result of the reference technology shown in FIG. 4 (the variation range is about 1.22V to 1.229V in the reference technology, but is about 1.224V to 1.227V in this embodiment, which is about one third of the variation range). Also, the reference voltage V REF In this way, according to the present embodiment, the influence of the base current amplification factor β of the PNP bipolar transistor included in the circuit configuration is reduced, thereby REF It is possible to realize a reference voltage source circuit 1 capable of stably outputting the above. [Explanation of symbols]

[0052] 1. Reference voltage source circuit 10 Reference voltage generator 20 Compensation current generation section M p1 ~M p9 PMOS Transistor Q p1 ~Q p4 PNP Bipolar Transistor M n1 ~M n3 NMOS Transistor R 1 ~R 5 resistance A 1 ~A 2 Operational Amplifier V DD power supply V REF Reference Voltage

Claims

1. a first PMOS transistor, a second PMOS transistor and a third PMOS transistor, each of whose sources is connected to a common power supply; a first operational amplifier having an output terminal to which the gates of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor are connected, a positive input terminal to which the drain of the first PMOS transistor is connected, and a negative input terminal to which the drain of the second PMOS transistor is connected; a first PNP bipolar transistor and a second PNP bipolar transistor, each having a collector and a base connected to a ground point; a first resistor provided between the drain of the first PMOS transistor and the ground point; a first node provided between the drain of the first PMOS transistor and the first resistor; a second resistor provided between the first node and the emitter of the first PNP bipolar transistor; a second node provided between the drain of the second PMOS transistor and the emitter of the second PNP bipolar transistor; a third resistor provided between the second node and the ground point; a fourth resistor provided between the drain of the third PMOS transistor and the ground point; an output terminal provided between the drain of the third PMOS transistor and the fourth resistor; a compensation current supplying unit for supplying a compensation current to at least one of the emitters of the first PNP bipolar transistor and the second PNP bipolar transistor so that a difference between the emitter currents of the first PNP bipolar transistor and the second PNP bipolar transistor is reduced; A reference voltage source circuit comprising:

2. 2. The reference voltage source circuit according to claim 1, wherein said compensation current supply section supplies said compensation current so that emitter currents of said first PNP bipolar transistor and said second PNP bipolar transistor become equal to each other.

3. 3. The reference voltage source circuit according to claim 1, wherein the compensation current supply unit is configured to supply a first compensation current and a second compensation current as the compensation current to the first PNP bipolar transistor and the second PNP bipolar transistor, respectively.

4. The compensation current supply unit includes: a fourth PMOS transistor (Mp1), a fifth PMOS transistor (Mp2), and a sixth PMOS transistor (Mp3), each of whose sources is connected to the power supply; an output terminal to which the gates of the fourth PMOS transistor and the fifth PMOS transistor are connected, a positive input terminal to which the drain of the fourth PMOS transistor is connected, and a second operational amplifier (A1) having a negative input terminal connected to the drain; a third PNP bipolar transistor (Qp1) and a fourth PNP bipolar transistor (Qp2), each having a collector connected to the ground point and a base connected to each other; a fifth resistor (R1) provided between the drain of the fourth PMOS transistor and the emitter of the third PNP bipolar transistor; a third node provided between the bases of the third PNP bipolar transistor and the fourth PNP bipolar transistor; a first NMOS transistor (Mn1) having a drain connected to the third node and a source connected to the ground; a second NMOS transistor (Mn2) having a gate and a drain connected to the gate of the first NMOS transistor and a source connected to the ground; a third NMOS transistor (Mn3) having a source connected to the drain of the second NMOS transistor and a gate connected to the emitter of the fourth PNP bipolar transistor; a sixth PMOS transistor (Mp3) whose drain is connected to the drain of the third NMOS transistor; a seventh PMOS transistor (Mp4) having a drain connected to the emitter of the third PNP bipolar transistor; an eighth PMOS transistor (Mp5) whose drain is connected to the emitter of the fourth PNP bipolar transistor; a ninth PMOS transistor (Mp8) having a drain connected to the emitter of the first PNP bipolar transistor to output the first compensation current; a tenth PMOS transistor (Mp9) having a drain connected to the emitter of the second PNP bipolar transistor to output the second compensation current; Equipped with 4. The reference voltage source circuit of claim 3, wherein the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor have respective sources connected to the power supply and respective gates connected to the drain of the sixth PMOS transistor.

5. 3. The reference voltage source circuit according to claim 1, wherein the reference voltage output from said output terminal is lower than a bandgap voltage.

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