Bonding process

Abstract

To provide a bonding process that can prevent displacement of a chip at chip on wafer bonding.SOLUTION: In a bonding process, a concave part is formed by installing a chip-shaped layer partially on a substrate including a metal wire, and then a chip including a metal wire is installed in the concave part.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present invention relates to a bonding process. [Background technology]

[0002] Conventionally, hybrid bonding (hereinafter sometimes referred to as "wafer-wafer bonding"), which bonds wafers having metal wiring together, has been used as one of the 3D bonding methods from the viewpoints of low resistance, high heat dissipation, low profile, fine bonding, etc. In the wafer-wafer bonding, high precision can be obtained by using appropriate devices and systems for aligning wafers with large surface areas such as 8 inches and 12 inches, and bump bonding of 5 μm or less (e.g., 1 μm, submicron) is possible.

[0003] On the other hand, there is also an increasing demand for hybrid bonding (hereinafter sometimes referred to as "chip on wafer bonding") that bonds a chip having metal wiring to a wafer. However, in the above-mentioned Chip on Wafer Bonding, because the chip and the wafer to be bonded are different sizes, there is a problem that the bonding between the metal wiring on the chip surface and the metal wiring on the wafer surface (hereinafter sometimes referred to as "bump bonding") is misaligned due to the misalignment of each chip. For this reason, the bump bonding of 5 μm is the limit in conventional Chip on Wafer Bonding.

[0004] Here, as the Chip on Wafer Bonding, for example, a method for manufacturing a semiconductor device including a first semiconductor substrate having an opening formed on one side and a first wiring layer formed on the other side, a second semiconductor substrate configured inside the opening and having a second wiring layer formed on a surface facing the bottom surface of the opening, and wiring electrically connecting the first wiring layer and the second wiring layer is known (see, for example, Patent Document 1).

[0005] However, the method described in Patent Document 1 does not mention a process for preventing misalignment of each chip. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2021-190440 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a bonding process capable of preventing chip misalignment during chip on wafer bonding. [Means for solving the problem]

[0008] The means for solving the above problems are as follows. <1> A bonding process comprising the steps of partially placing a chip-shaped layer on a substrate having metal wiring to form a recess, and then placing a chip having metal wiring in the recess. <2> the chip-shaped layer is a resin layer containing a resin, The resin layer is formed by coating, exposing, and developing. <1> The bonding process described in <3> The reaction is carried out under a reducing atmosphere. <1> or <2> The bonding process described in <4> After placing the chip having the metal wiring in the recess, at least one of pressure and heat is applied. <1> or <2> The bonding process described in Effect of the Invention

[0009] According to one embodiment of the present invention, it is possible to provide a bonding process capable of preventing chip misalignment during chip on wafer bonding. [Brief description of the drawings]

[0010] [Figure 1] 1A-1C are schematic diagrams illustrating an example of wafers in a bonding process of one embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic diagram illustrating an example of a step of placing a chip-like layer in a bonding process according to an embodiment of the present invention. [Diagram 3] FIG. 4 is a schematic diagram showing an example of a step of placing a tip in a bonding process according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Bonding process) The bonding process of one embodiment of the present invention includes a step of partially placing a chip-shaped layer on a substrate having metal wiring to form a recess, and then placing a chip having metal wiring in the recess, and preferably further includes other steps such as pressurization and heating as necessary. In this specification, a circular base material having metal wiring and a substrate is referred to as a "wafer," and a chip-shaped base material having metal wiring and a substrate is referred to as a "chip." The term "wafer" also includes a printed circuit board.

[0012] 1 to 3 are schematic diagrams showing an example of a bonding process according to an embodiment. In the bonding process of one embodiment of the present invention, as shown in FIG. 1, a wafer 10 has a substrate 11A, a SiO2 film 12A, and metal wiring 13A. Then, as shown in FIG. 2, a chip-shaped layer 20 is partially placed on the wafer 10 to form a recess 30. Next, as shown in FIG. 3, a chip 40 having a substrate 11B, a SiO2 film 12B, and metal wiring 13B is placed on the recess 30. By these steps, it is possible to prevent the chips from being displaced while bonding them.

[0013] <Wafer> The wafer preferably has metal wiring and a substrate, and further has a SiO2 film as required.

[0014] -Metal wiring- The metal wiring is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include gold (Au), silver (Ag), nickel (Ni), copper (Cu), titanium (Ti), aluminum (Al), etc. These may be used alone or in combination of two or more.

[0015] The width of the metal wiring is not particularly limited and can be appropriately selected depending on the purpose, but is preferably 100 nm or more and 1,000 nm or less.

[0016] -substrate- The substrate is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include substrates containing silicon (Si), silicon oxide (SiO), silicon carbide (SiC), sapphire (Al2O3), compound semiconductors, etc. In addition, when the substrate is a printed circuit board, examples thereof include substrates having glass epoxy, paper epoxy, paper phenol, plastic film, etc.

[0017] The thickness of the substrate is not particularly limited and can be appropriately selected depending on the purpose, but is preferably from 1 μm to 1,000 μm.

[0018] -Chip-like layer- The chip-shaped layer is not particularly limited and may be appropriately selected depending on the purpose, and examples thereof include a resist film, a metal film, an organic film, etc. Among these, a resist film is preferred from the viewpoint of ensuring the flatness of the substrate and from the viewpoint of easily removing the chip-shaped layer when the film is not required after bonding. By providing the chip-shaped layer, a recess can be formed on the wafer, and by providing the chip so as to fit into the recess, bonding can be performed without causing misalignment of the chip. Note that the chip-shaped layer may or may not be removed after bonding.

[0019] --Resist film-- The resist film is a resin layer containing a resin, and may further contain filler, organic particles, etc., as necessary. When the resist film contains filler, organic particles, etc., the shape of the recesses and the shape retention when pressure is applied are excellent. The resist film may be either positive type or negative type, but the positive type is preferred from the viewpoint of removability after bonding.

[0020] The resin is not particularly limited and can be appropriately selected according to the purpose, for example, a novolac-based, resol-based, PHS-based, acrylic-based, siloxane-based, urethane-based, or amide-based skeleton can be used, and an acetal group, a secondary or tertiary ester group, a sulfonic acid ester group, or an interpolymer bond group can be combined with an acid generator. In addition, a positive resist using naphthoquinone diazide and its derivatives, and a negative resist using a novolac-based, resol-based, PHS-based, acrylic-based, siloxane-based, urethane-based, or amide-based compound combined with a methylol compound, an acrylic compound, a methacryl compound, an acrylamide compound, a methacrylamide compound, a styrene compound, a vinyl compound, or the like, an acid generator, or a radical generator can be used.

[0021] The method for forming the recesses by applying the resist film is not particularly limited and can be appropriately selected depending on the purpose. Examples of the method include a method in which a composition containing the resin is applied, and then exposure and development are performed to apply a resist film to form the recesses, and a method in which a film resist is applied.

[0022] The exposure method is not particularly limited and can be appropriately selected depending on the purpose. Examples of the exposure method include a method of applying energy by light from a light source such as a stepper, proxy exposure, and direct imaging exposure. The light source can be anything from an electron beam to UV light, visible light, or infrared light.

[0023] The development method is not particularly limited and can be appropriately selected depending on the purpose. For example, development methods using an organic base, an inorganic base, an organic solvent, water, an aqueous solution, etc. can be mentioned.

[0024] --Metal Film-- The metal film is not particularly limited and can be appropriately selected depending on the purpose. Examples of the metal film include metals such as titanium (Ti), nickel (Ni), silver (Ag), copper (Cu), and tungsten (W). The method for providing the metal film and forming the recesses is not particularly limited and can be appropriately selected depending on the purpose. For example, there is a method in which the recesses are formed by performing etching after plating, vapor deposition or sputtering.

[0025] --Organic film-- The organic film can be made of the same material as the resist film described above, and the recesses can be formed by the same method.

[0026] The thickness of the chip-shaped layer is not particularly limited and can be appropriately selected depending on the purpose as long as it does not cause the chip to be misaligned as described below, but is preferably 0.5 μm or more and 200 μm or less, more preferably 1 μm or more and 150 μm or less, and particularly preferably 5 μm or more and 100 μm or less.

[0027] <Tip> The chip preferably has metal wiring and a substrate, and further has a SiO2 film as required.

[0028] The metal wiring, substrate, and SiO2 film in the chip may be the same as those in the wafer described above.

[0029] The chip is placed so as to fit into a recess formed by placing the chip-shaped layer, thereby making it possible to perform bonding without causing misalignment of the chip.

[0030] The bonding of the chip and the wafer is preferably carried out in a reducing atmosphere. The reducing atmosphere is not particularly limited and can be appropriately selected depending on the purpose. Examples of the reducing atmosphere include formic acid and hydrogen.

[0031] After the chip is fitted in the recess, it is preferable to apply at least one of pressure and heat using a flip chip bonder or the like having ceramic heaters attached to the head and stage.

[0032] The heating temperature is not particularly limited and can be appropriately selected depending on the purpose, but is preferably from 100° C. to 300° C. The heating temperature refers to the surface temperature of the head and stage of a flip chip bonder.

[0033] The load for the pressurization is not particularly limited and can be appropriately selected depending on the purpose, but is preferably 1N or more and 200N or less. EXAMPLES

[0034] Examples of the present invention will be described below, but the present invention is not limited to these examples.

[0035] Example 1 A chip-shaped layer was partially placed on an 8-inch wafer having metal wiring (Au / Ni / Cu / Ti), a SiO2 film (thickness: 500 nm), and a substrate (Si substrate, thickness: 525 μm) to form a recess. As the chip-shaped layer, a positive resist with a thickness of 5 μm was formed in the same direction and with a size of 100.6%. Thereafter, a 5 mm×5 mm chip having metal wiring (Au / Ni / Cu / Ti), a SiO 2 film (thickness: 500 nm), and a substrate (Si substrate, thickness: 525 μm) was placed in the recess. In addition, on the SiO2 film of the chip and the wafer, Au (diameter 5 μm) bonding sites were formed by electroplating on the Au / Ni / Cu / Ti wiring formed by electron beam evaporation, with 100 pins at a pitch of 20 μm, and the surface was polished by CMP to adjust to less than 5 nm. Thereafter, bonding was performed using a flip chip bonder (FC2000, Toray Engineering Co., Ltd.) Both the head and stage of the flip chip bonder were equipped with ceramic heaters, and the Au bumps of the chip and wafer were brought into contact under the following conditions: the temperature of both the head and stage was 30°C, the load was 100 N, and the pressure time was 5 seconds. Next, while maintaining the pressure, the temperatures of both the head and stage of the flip chip bonder were raised to 150° C. and maintained at this temperature for 300 seconds, and finally the bonder head temperature was raised to 250° C. to harden the bond.

[0036] Comparative Example 1 Bonding was performed in the same manner as in Example 1, except that the chip-shaped layer was not formed.

[0037] In Example 1 and Comparative Example 1, the positional deviation of the chip was measured and evaluated by the following method.

[0038] In Example 1 and Comparative Example 1, the chip and wafer after bonding were cut, and the deviation of 5 μm of Au metallic bonds and Cu metallic bonds on the chip and wafer on the cross section was measured and the average overlap area was calculated for 10 points. The chip misalignment was evaluated based on the average overlap area and in accordance with the following evaluation criteria. The results are shown in Table 1 below. [Evaluation Results] ○: The average overlap area is 90% or more △: The average overlap area is between 80% and 90% ×: The average overlap area is less than 80%

[0039] [Table 1] [Explanation of symbols]

[0040] 10 Wafers 11A, 11B Board 12A, 12B SiO2 film 13A, 13B Metal wiring 20 Chip-like layers 30 Recess 40 Chip

Claims

1. A bonding process comprising the steps of partially placing a chip-shaped layer on a substrate having metal wiring to form a recess, and then placing a chip having metal wiring in the recess.

2. the chip-shaped layer is a resin layer containing a resin, The bonding process according to claim 1 , wherein the resin layer is formed by coating, exposing, and developing.

3. 3. The bonding process according to claim 1 or 2, carried out under a reducing atmosphere.

4. 3. The bonding process according to claim 1, further comprising applying pressure or heating after placing the chip having the metal wiring in the recess.

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