Semiconductor device and manufacturing method for the same

Abstract

To provide a semiconductor device in which a film for covering a chip can be formed suitably, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device in the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area that is smaller than the first area in the plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film. The first film includes a first part provided at a side surface of the second chip. A predetermined longitudinal cross section of the first part includes an upper side with a first length and a lower side with a second length that is longer than the first length.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD An embodiment of the present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] When manufacturing a semiconductor device such as a photodetector, for example, a WoW (Wafer on Wafer) process or a CoW (Chip on Wafer) process is adopted.

[0003] When the WoW process is adopted, an upper wafer and a lower wafer are bonded together, and these wafers are divided into a plurality of chips (semiconductor devices) by dicing. Each semiconductor device manufactured by the WoW process includes an upper chip derived from the upper wafer and a lower chip derived from the lower wafer.

[0004] On the other hand, when the CoW process is adopted, the upper wafer is divided into a plurality of upper chips by dicing, these upper chips and the lower wafer are bonded together, and the lower wafer is divided into a plurality of lower chips by dicing. Each semiconductor device manufactured by the CoW process includes the upper chips divided before bonding and the lower chips divided after bonding. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2023-060563 A [Patent Document 2] Patent Publication No. 2022-077181 Summary of the Invention [Problem to be solved by the invention]

[0006] In general, when using the CoW process, after bonding the upper chip and the lower wafer, a film covering the upper chip is formed on the lower wafer, and then the lower wafer is divided into the lower chips. This makes it possible to fill the gaps between the upper chips with this film. However, if a seam occurs in this film, the mechanical strength of the semiconductor device may be reduced by the seam.

[0007] In view of this, the present disclosure provides a semiconductor device capable of suitably forming a film covering a chip, and a manufacturing method thereof. [Means for solving the problem]

[0008] A semiconductor device according to a first aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, the first film including a first portion provided on a side surface of the second chip, the first portion having a predetermined vertical cross section with an upper side having a first length and a lower side having a second length longer than the first length. This makes it possible to preferably form the second film by, for example, suppressing the occurrence of a seam in the second film by the first portion.

[0009] In addition, in the first aspect, the predetermined longitudinal section may further have a hypotenuse with an angle of 30 to 60 degrees with respect to the longitudinal direction, which makes it possible to, for example, prevent the size of the first portion from becoming too large and suppress the occurrence of seams by the first portion.

[0010] In addition, in this first aspect, when the angle is θ, the first length is A, the second length is B, and the height of the predetermined longitudinal section is C, C≦(BA) / tan θ may be satisfied. This makes it possible to, for example, prevent the size of the first portion from becoming too large, while suppressing the occurrence of seams by the first portion.

[0011] In addition, in the first side, the shape of the predetermined vertical cross section may be a trapezoid with the upper side as the upper base and the lower side as the lower base. This makes it easier to prevent the size of the first portion from becoming too large, for example, compared to when the vertical cross section shape is other than a trapezoid (for example, a triangle). In addition, by reducing the size of the first portion, it becomes possible to alleviate, for example, stress caused by the first portion.

[0012] In addition, in the first aspect, the first film may further include a second portion spaced apart from the second chip, which allows, for example, the second film to be suitably formed by reinforcing the mechanical strength of the semiconductor device by the second portion.

[0013] In addition, in the first side surface, the first portion may be in contact with the second portion and may be provided between the second chip and the second portion, which makes it possible to form, for example, the second portion that extends linearly or spreads out in a plane from the first portion.

[0014] In addition, in this first aspect, the first portion may be separated from the second portion, which makes it possible to form the second portion at a position far away from the first portion, for example.

[0015] In addition, in the first side surface, the top surface of the first portion may be located lower than the top surface of the second chip, which makes it possible to prevent the first portion from covering the edge between the top surface and the side surface of the second chip, for example.

[0016] Furthermore, in the first side surface, the top surface of the first portion may be located at a position higher than the top surface of the second chip, which makes it possible to make the height of the first portion sufficiently large, for example.

[0017] Furthermore, in the first side surface, the first portion may include a portion provided on the top surface of the second chip, which makes it possible, for example, to cover an edge between the top surface and the side surface of the second chip with the first portion.

[0018] In the first aspect, the second chip may include a substrate including silicon or a compound semiconductor substrate, which makes it possible to manufacture the second chip on a substrate suitable for use as a semiconductor device, for example.

[0019] A semiconductor device according to a second aspect of the present disclosure includes a first chip having a first area in a plan view, a second chip provided on the first chip and having a second area smaller than the first area in a plan view, a first film provided on the first chip, and a second film provided on the first chip, the second chip, and the first film, and the first film may include a second portion provided at a distance from the second chip. This makes it possible to suitably form the second film by, for example, reinforcing the mechanical strength of the semiconductor device with the second portion.

[0020] In the second aspect, the first film may further include a first portion provided on a side surface of the second chip, which makes it possible to preferably form the second film by, for example, suppressing the occurrence of a seam in the second film by the first portion.

[0021] In addition, in the second aspect, the predetermined vertical cross section of the first portion may have an upper side having a first length and a lower side having a second length longer than the first length, which makes it possible, for example, for the first portion to more effectively suppress the occurrence of seams in the second film.

[0022] In addition, in this second aspect, the shape of the predetermined vertical cross section may be a trapezoid with the upper side as the upper base and the lower side as the lower base. This makes it easier to prevent the size of the first portion from becoming too large, for example, compared to when the vertical cross section shape is other than a trapezoid (for example, a triangle). In addition, by reducing the size of the first portion, it becomes possible to alleviate, for example, stress caused by the first portion.

[0023] In addition, in the second side surface, the shape of the predetermined vertical cross section of the first portion may be a triangle having a first side facing the top surface of the first chip, a second side facing the side surface of the second chip, and a third side located between the first side and the second side, which makes it possible to form, for example, a first portion with a simple shape.

[0024] A method for manufacturing a semiconductor device according to a third aspect of the present disclosure includes mounting a second chip on a first wafer, forming a first film on the first wafer, forming a second film on the first wafer, the second chip, and the first film, and processing the first wafer into a first chip, the first film being formed to include at least one of a first portion provided on a side surface of the second chip and a second portion provided at a distance from the second chip, the first portion being formed such that a predetermined vertical cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length. This makes it possible to preferably form the second film by, for example, suppressing the occurrence of a seam in the second film by the first portion or reinforcing the mechanical strength of the semiconductor device by the second portion.

[0025] In the third aspect, the first chip may have a first area in a plan view, and the second chip may have a second area smaller than the first area in a plan view. This makes it possible to preferably form the second film when, for example, a CoW process is employed.

[0026] In the third aspect, the first film may be formed by printing, deposition, or coating, which makes it possible to easily form the first film capable of forming the first portion, for example.

[0027] In the third aspect, the first portion may be formed by processing the first film by etching back, which makes it possible to easily form the first portion, for example. [Brief description of the drawings]

[0028] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view showing a structure of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 2 is a cross-sectional view for explaining details of the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view showing a structure of a semiconductor device of a comparative example to the first embodiment. FIG. [Diagram 5] FIG. 4 is a cross-sectional view for explaining details of a semiconductor device as a comparative example of the first embodiment. [Figure 6] 6 is a cross-sectional view (1 / 6) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 6 is a cross-sectional view (2 / 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 6 is a cross-sectional view (3 / 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 4 is a cross-sectional view (4 / 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 5 is a cross-sectional view (5 / 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 6 is a cross-sectional view (6 / 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 5 is a cross-sectional view (1 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13]5 is a cross-sectional view (2 / 5) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 14] 5 is a cross-sectional view (3 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 4 is a cross-sectional view (4 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 5 is a cross-sectional view (5 / 5) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 17] 11 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 18] 11 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 19] 11 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device according to a second modified example of the first embodiment. FIG. [Figure 20] 11 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device according to a second modified example of the first embodiment. FIG. [Figure 21] 11 is a cross-sectional view (3 / 3) showing a method for manufacturing a semiconductor device according to a second modified example of the first embodiment. FIG. [Figure 22] 13 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a third modified example of the first embodiment. FIG. [Diagram 23] 13 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a third modified example of the first embodiment. FIG. [Figure 24] 1A to 1C are plan views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Diagram 25] FIG. 13 is a plan view showing structures of semiconductor devices according to fourth and fifth modifications of the first embodiment. [Figure 26] FIG. 13 is a plan view showing structures of semiconductor devices according to sixth and seventh modifications of the first embodiment. [Figure 27] FIG. 13 is a plan view showing structures of semiconductor devices according to eighth and ninth modifications of the first embodiment. [Figure 28] 13A to 13C are cross-sectional views showing structures of semiconductor devices according to tenth and eleventh modifications of the first embodiment. [Figure 29]13A to 13C are cross-sectional views showing structures of semiconductor devices according to twelfth and thirteenth modifications of the first embodiment. [Diagram 30] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Diagram 31] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. [Diagram 32] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. [Diagram 33] FIG. 13 is a block diagram showing a configuration of a semiconductor device according to a fifth embodiment. [Diagram 34] FIG. 1 is a block diagram showing an example of the configuration of an electronic device. [Diagram 35] FIG. 1 is a block diagram showing a configuration example of a mobile object control system. [Diagram 36] 36 is a plan view showing a specific example of the setting position of the imaging unit in FIG. 35. [Figure 37] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 38] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0030] (First embodiment) (1) Structure of semiconductor device FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0031] The semiconductor device of the present embodiment is, for example, a photodetector such as a solid-state imaging device, but may be other devices, for example, a light-emitting device such as a surface-emitting laser device, or a control device such as a logic circuit device.

[0032] FIG. 1 shows X-axis, Y-axis, and Z-axis that are perpendicular to each other. The X-axis and Y-axis correspond to the lateral direction (horizontal direction), and the Z-axis corresponds to the longitudinal direction (vertical direction). The +Z-direction corresponds to the upward direction, and the -Z-direction corresponds to the downward direction. Note that the -Z-direction may or may not strictly coincide with the direction of gravity.

[0033] The semiconductor device of this embodiment includes a lower chip 1, an upper chip 2, a lower film 3, and an upper film 4. The lower chip 1 and the upper chip 2 are examples of the first and second chips of the present disclosure, respectively. The lower film 3 and the upper film 4 are examples of the first and second films of the present disclosure, respectively. The semiconductor device of this embodiment is manufactured by, for example, a CoW process.

[0034] The lower chip 1 includes a substrate 11, an interlayer insulating film 12, a multilayer wiring structure 13, etc., and the multilayer wiring structure 13 includes a wiring layer 13a including a plurality of wirings, a plurality of via plugs 13b, and a plurality of metal pads 13c. Similarly, the upper chip 2 includes a substrate 21, an interlayer insulating film 22, a multilayer wiring structure 23, etc., and the multilayer wiring structure 23 includes a wiring layer 23a including a plurality of wirings, a plurality of via plugs 23b, and a plurality of metal pads 23c. The lower film 3 includes an outer peripheral portion 3a and a reinforcing portion 3b. The outer peripheral portion 3a and the reinforcing portion 3b are examples of the first and second portions of the present disclosure. FIG. 1 shows a vertical cross section of two portions of one outer peripheral portion 3a and a vertical cross section of two portions of one reinforcing portion 3b.

[0035] FIG. 2 is a plan view showing the structure of the semiconductor device of the first embodiment.

[0036] Fig. 2 shows the above-mentioned lower chip 1, upper chip 2, and lower film 3, and omits the illustration of the upper film 4. In Fig. 2, the lower chip 1 is shown in white, the upper chip 2 is shown by dot hatching, and the lower film 3 is shown by thick oblique hatching. Fig. 1 shows a vertical cross section taken along line A-A' shown in Fig. 2.

[0037] The semiconductor device of this embodiment will be described in detail below with reference to Fig. 1. In this description, Fig. 2 will also be referred to as appropriate.

[0038] [Lower Chip 1] In the lower chip 1, an interlayer insulating film 12 is provided on a substrate 11, and a multilayer wiring structure 13 is provided in the interlayer insulating film 12. The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The multilayer wiring structure 13 includes one or more wiring layers in the interlayer insulating film 12. The wiring layer 13a is one of these wiring layers. A via plug 13b is provided on the wiring layer 13a, and a metal pad 13c is provided on the via plug 13b.

[0039] [Upper tip 2] In the upper chip 2, an interlayer insulating film 22 is provided under a substrate 21, and a multilayer wiring structure 23 is provided in the interlayer insulating film 22. The substrate 21 is, for example, a semiconductor substrate such as a Si substrate. The multilayer wiring structure 23 includes one or more wiring layers in the interlayer insulating film 22. The wiring layer 23a is one of these wiring layers. A via plug 23b is provided under the wiring layer 23a, and a metal pad 23c is provided under the via plug 23b.

[0040] Upper chip 2 is bonded to lower chip 1, and is therefore stacked on lower chip 1. In Fig. 1, interlayer insulating film 22 and metal pad 23c are disposed on interlayer insulating film 12 and metal pad 13c, and metal pad 23c is bonded to metal pad 13c.

[0041] In this embodiment, the lower chip 1 has a large area in a plan view, and the upper chip 2 has a small area in a plan view (FIG. 2). Therefore, in FIG. 2, the contour (side) of the upper chip 2 is located inside the contour (side) of the lower chip 1. The area of ​​the lower chip 1 is an example of the first area of ​​the present disclosure. The area of ​​the upper chip 2 is an example of the second area of ​​the present disclosure.

[0042] [Lower membrane 3] The lower film 3 is provided on the lower chip 1. The lower film 3 is, for example, an insulating film. The lower film 3 of this embodiment includes an outer peripheral portion 3a provided on the side surface of the upper chip 2, and a reinforcing portion 3b provided at a distance from the upper chip 2. The lower film 3 of this embodiment has a lattice (mesh) shape in a plan view (FIG. 2).

[0043] 2, the boundary between the outer peripheral portion 3a and the reinforcing portion 3b is indicated by a dashed line R. In this embodiment, each portion of the lower film 3 extends in the X direction or the Y direction, and the portion extending along the side surface of the upper chip 2 is called the outer peripheral portion 3a, and the other portion is called the reinforcing portion 3b. In this embodiment, the outer peripheral portion 3a is in contact with the reinforcing portion 3b, and is provided between the upper chip 2 and the reinforcing portion 3b. That is, the outer peripheral portion 3a and the reinforcing portion 3b in this embodiment are not separated but integrated.

[0044] The outer peripheral portion 3a is disposed along the outer periphery of the upper chip 2 (FIG. 2). In FIG. 1, the shape of the vertical cross section of the outer peripheral portion 3a is a triangle. This vertical cross section is an example of a predetermined vertical cross section of the present disclosure. This triangle has a side X1 facing the upper surface of the lower chip 1, a side X2 facing the side of the upper chip 2, and a side X3 located between the sides X1 and X2. In this embodiment, this triangle is a right-angled triangle. The sides X1, X2, and X3 are examples of the first, second, and third sides of the present disclosure, respectively. In FIG. 1, the side X1 is in contact with the upper surface of the lower chip 1, and the side X2 is in contact with the side of the upper chip 2. Note that the shape of the vertical cross section of the outer peripheral portion 3a may be a shape other than a triangle (for example, a trapezoid), as described later.

[0045] The reinforcing portion 3b is disposed at a position away from the upper chip 2 (FIG. 2). The reinforcing portion 3b has a function of reinforcing the mechanical strength of the semiconductor device of this embodiment. In FIG. 2, the lower chip 1 has four corners, and the upper chip 2 is disposed near one corner of the lower chip 1. Therefore, the mechanical strength of the semiconductor device of this embodiment may be strong near this one corner, but weak near the other three corners. Similarly, the mechanical strength of the semiconductor device of this embodiment may be weak at a position away from the upper chip 2. Therefore, in this embodiment, the reinforcing portion 3b is disposed at a position away from the upper chip 2. The reinforcing portion 3b of this embodiment functions as a beam that reinforces the mechanical strength of the semiconductor device. Therefore, it is desirable that the lower film 3 is a hard film. The shape of the longitudinal section of the reinforcing portion 3b is trapezoidal in FIG. 1, but may be other shapes.

[0046] The function of reinforcing the mechanical strength of the semiconductor device may be provided not only by the reinforcing portion 3b but also by the outer peripheral portion 3a. Although the outer peripheral portion 3a has a ring-shaped planar shape in FIG. 2, it may have a non-ring-shaped planar shape. The reinforcing portion 3b may also have a shape other than the shape shown in FIG. 2.

[0047] [Upper membrane 4] The upper film 4 is provided on the lower chip 1, the upper chip 2, and the lower film 3. The upper film 4 is, for example, an insulating film different from the lower film 3. The upper film 4 in this embodiment is formed so as to cover the upper surface of the lower chip 1, the upper surface of the upper chip 2, and the upper surface of the lower film 3.

[0048] The strength of the upper film 4 may be weaker than that of the lower film 3. This is because the mechanical strength of the semiconductor device can be reinforced by the reinforcing portion 3b. This allows for greater freedom in selecting the material for the upper film 4 and makes it possible to suppress damage to the upper film 4 by the reinforcing portion 3b.

[0049] 3 is a cross-sectional view for explaining details of the semiconductor device according to the first embodiment, in which the multilayer wiring structures 13 and 23 and the reinforcing portion 3b are omitted.

[0050] In this embodiment, the shape of the vertical cross section of the outer peripheral portion 3a may be a trapezoid as shown in FIG. 3, instead of a triangle as shown in FIG. 1. This vertical cross section is also an example of a predetermined vertical cross section of the present disclosure. This trapezoid has sides X1, X2, and X3 corresponding to sides X1, X2, and X3 of the above-mentioned triangle, respectively, and an additional side X4. Side X4 is the upper side of the vertical cross section and corresponds to the upper base of the trapezoid. Side X1 is the lower side of the vertical cross section and corresponds to the lower base of the trapezoid. Side X2 is located between side X4 and side X1, and is located on the upper chip 2 side in the vertical cross section. Side X3 is located between side X4 and side X1, and is located on the opposite side of the upper chip 2 in the vertical cross section.

[0051] In this embodiment, sides X4 and X1 are perpendicular to the Z direction, side X2 is parallel to the Z direction, and side X3 is inclined at an angle θ with respect to the Z direction. The angle θ in this embodiment is 30 to 60 degrees (30°≦θ≦60°), for example, about 45 degrees (θ≒45°). Side X3 is a hypotenuse inclined with respect to the Z direction. Side X3 is a straight line in FIG. 3, but may be a curved line instead. Similarly, side X4 is a straight line in FIG. 3, but may be a curved line instead. Additionally, sides X4 and X1 are parallel to each other in FIG. 3, but may be non-parallel to each other instead.

[0052] FIG. 3 shows the length A of side X4, the length B of side X1, and the length C of side X2. The lengths A, B, and C correspond to the upper base length, lower base length, and height of the trapezoid, respectively. The lengths A and B are examples of the first and second lengths of the present disclosure. In this embodiment, the length B is set to be longer than the length A (B>A). Furthermore, the lengths A, B, C, and the angle θ of this embodiment are set so that the relationship C≦(BA) / tan θ is established.

[0053] FIG. 3 further shows the thickness T of the upper film 4, the thickness T1 of the upper chip 2, and the thickness T2 of the upper film 4 above the upper chip 2. The relationship T=T1+T2 is established among the thicknesses T, T1, and T2. In this embodiment, it is desirable to set the thickness T sufficiently larger than the thickness T1 so that the value of the thickness T2 is sufficiently large. This makes it possible to sufficiently cover the upper chip 2 with the upper film 4. The thickness T2 is set to, for example, 1 / 2 or more times the thickness T1 (T2≧T1 / 2), and may even be set to be greater than or equal to the thickness T1 (T2≧T1).

[0054] The relationship C≦(BA) / tan θ may be applied to the outer peripheral portion 3a of Fig. 1 by setting A=0. Similarly, the relationship 30°≦θ≦60° may be applied to the outer peripheral portion 3a of Fig. 1. Similarly, the relationships T2≧T1 / 2 and T2≧T1 may be applied to the semiconductor device of Fig. 1.

[0055] FIG. 4 is a cross-sectional view showing the structure of a semiconductor device as a comparative example of the first embodiment.

[0056] The semiconductor device of this comparative example has a structure in which the lower film 3 is removed from the semiconductor device of the first embodiment. In this case, a seam S may occur in the upper film 4 due to a step between the top surface of the lower chip 1 and the top surface of the upper chip 2. As a result, the mechanical strength of the semiconductor device may be reduced due to the seam S. In FIG. 4, the seam S occurs near the interface between the lower chip 1 and the upper chip 2.

[0057] FIG. 5 is a cross-sectional view for explaining details of a semiconductor device as a comparative example of the first embodiment.

[0058] As shown in Fig. 5, when the upper film 4 is formed, film portions 4a and 4b which are parts of the upper film 4 are gradually formed on the surfaces of the lower chip 1 and the upper chip 2. In Fig. 5, film portion 4a is formed on the surface of the lower chip 1, and film portion 4b is formed on the surface of the upper chip 2.

[0059] Film portions 4a and 4b are then integrated to form upper film 4. However, because there is a step between the top surface of lower chip 1 and the top surface of upper chip 2, it is difficult to form upper film 4 at the point indicated by dashed line S'. This is the cause of the above-mentioned seam S.

[0060] Therefore, when manufacturing the semiconductor device of this embodiment, peripheral portion 3a is formed on the side surface of upper chip 2, and then upper film 4 is formed on lower chip 1 and upper chip 2 (see FIGS. 1 and 3). As a result, the step between the top surface of lower chip 1 and the top surface of upper chip 2 is reduced by peripheral portion 3a, making it possible to suppress the occurrence of seam S. According to this embodiment, by forming peripheral portion 3a, it is possible to form a suitable upper film 4 in which the occurrence of seam S is suppressed. Furthermore, according to this embodiment, by forming reinforcing portion 3b, it is possible to form a suitable upper film 4 reinforced by reinforcing portion 3b.

[0061] In this embodiment, the length B of the side X1 in FIG. 3 is longer than the length A of the side X4. This allows the inclination of the side X3 to be a forward taper, and the step can be alleviated by the outer peripheral portion 3a. The relationship B>A is also established in FIG. 1 by setting A=0, so this effect can also be obtained in the structure of FIG. 1. On the other hand, setting A≠0 as in FIG. 3 has the advantage of reducing the stress caused by the outer peripheral portion 3a and the advantage of suppressing the occurrence of seams S in the outer peripheral portion 3a with a small area or volume. Therefore, in FIG. 3, by setting A≠0, the shape of the vertical cross section of the outer peripheral portion 3a is set to be trapezoidal.

[0062] The angle θ in Fig. 3 is preferably set to 30 to 60 degrees. This is because if the angle θ is small, the step is not alleviated, and if the angle θ is large, the area and volume of the outer peripheral portion 3a may become excessively large. Furthermore, it is preferable that the lengths A, B, C and the angle θ in Fig. 3 are set so that the relationship C≦(BA) / tan θ is satisfied. This makes it possible to prevent the area of ​​the side X3 in the outer peripheral portion 3a from becoming excessively large. These relationships may also be applied to the semiconductor device in Fig. 1.

[0063] In order to achieve the above-mentioned effects, it is desirable to form the lower film 3 from a material having high heat resistance. Various examples of materials for the lower film 3 will be described later.

[0064] (2) Manufacturing method of semiconductor device 6 to 11 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0065] First, the lower wafer 1 is fabricated by forming an interlayer insulating film 12 and a multilayer wiring structure 13 on a substrate 11 (FIG. 6A). Next, the upper wafer 2 is fabricated by forming an interlayer insulating film 22 and a multilayer wiring structure 23 on a substrate 21 (FIG. 6A). Next, the upper wafer 2 is divided into a plurality of upper chips 2 by dicing, and these upper chips 2 and the lower wafer 1 are bonded together (FIG. 6A). FIG. 6A shows how one of these upper chips 2 is loaded on the lower wafer 1. In the description of this embodiment, the symbol "1" is used as a common symbol for the lower chip and the lower wafer, and the symbol "2" is used as a common symbol for the upper chip and the upper wafer. The lower wafer 1 is an example of the first wafer of the present disclosure.

[0066] The lower wafer 1 and the upper chip 2 are then annealed (FIG. 6B), so that the metal pads 23c in the upper chip 2 are bonded to the metal pads 13c in the lower wafer 1.

[0067] Next, a paste 3', which is a material of the lower film 3, is formed on the lower wafer 1 (FIG. 7A). The paste 3' is, for example, a glass paste containing glass particles, and is formed on the lower wafer 1 by glass paste printing. FIG. 7A shows a screen mask 31 and a squeegee 32 used for glass paste printing. The screen mask 31 has an opening P1a for passing the paste 3'. The squeegee 32 is used to push the paste 3' into the opening P1a. According to the process of FIG. 7A, the paste 3' having a pattern similar to that of the outer peripheral portion 3a and the reinforcing portion 3b is formed on the lower wafer 1. Note that the material of the particles in the paste 3' may be other than glass, and may be, for example, silicon oxide, silicone, or alumina.

[0068] Next, the paste 3' is reflowed (FIG. 7B). As a result, the paste 3' is transformed into the lower film 3 including the peripheral portion 3a and the reinforcing portion 3b (not shown). This reflow is performed at a temperature at which the resin in the paste 3' melts. As a result, the peripheral portion 3a is formed to have a triangular vertical cross section, as shown in FIG. 7B.

[0069] Next, the lower film 3 is baked (FIG. 8A). As a result, the resin is released from the lower film 3, and the lower film 3 is baked and hardened.

[0070] Next, the upper film 4 is formed on the lower wafer 1, the upper chip 2, and the lower film 3 (FIG. 8B). FIG. 8B shows a protrusion P2a formed on the upper film 4. The protrusion P2a is formed above the upper chip 2 and the lower film 3 because the upper surfaces of the upper chip 2 and the lower film 3 are higher than the upper surface of the lower wafer 1.

[0071] Next, a resist film 33 is formed on the upper film 4, and the resist film 33 is patterned (FIG. 9A). As a result, an opening P3a is formed in the resist film 33 on the protrusion P2a.

[0072] Next, recesses P4a are formed in the protrusions P2a of the upper film 4 by etching using the resist film 33 (FIG. 9B). As a result, most of the protrusions P2a are removed from the upper film 4.

[0073] Next, the resist film 33 is removed (FIG. 10A). FIG. 10A shows the convex portion P2a of the upper film 4 and the concave portion P4a formed in the convex portion P2a.

[0074] Next, the surface of the upper film 4 is planarized by CMP (Chemical Mechanical Polishing) (FIG. 10B). As a result, the convex portions P2a and the concave portions P4a are removed from the upper film 4.

[0075] Next, the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 are bonded to a support substrate 5 (FIG. 11A). The support substrate 5 is, for example, a semiconductor wafer such as a Si wafer. The orientations of the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 shown in FIG. 11A are opposite to the orientations of the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 shown in FIG. 10B.

[0076] Next, the substrate 11 is thinned by grinding, and then the lower wafer 1 (and the supporting substrate 5) is divided into a plurality of lower chips 1 by dicing (FIG. 11B). In this manner, a semiconductor device including the lower chip 1 and the upper chip 2 is manufactured.

[0077] The semiconductor device shown in FIG. 11B is the same as the semiconductor device shown in FIG. 1. However, FIG. 1 does not show the support substrate 5. The orientation of the semiconductor device shown in FIG. 1 is opposite to that of the semiconductor device shown in FIG. 11B. As described above, the lower chip 1 has a large area in a plan view, and the upper chip 2 has a small area in a plan view. As described above, the semiconductor device of this embodiment is manufactured to include the lower chip 1 processed from the lower wafer 1 and the upper chip 2 processed from the upper wafer 2.

[0078] 12 to 16 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0079] 6 to 11 show the process of forming the outer peripheral portion 3a, whereas FIGS. 12 to 16 show the process of forming the reinforcing portion 3b. In this embodiment, the process shown in FIGS. 6 to 11 and the process shown in FIGS. 12 to 16 are simultaneously performed to form the outer peripheral portion 3a and the reinforcing portion 3b at the same time. On the other hand, the outer peripheral portion 3a and the reinforcing portion 3b may be formed in sequence. For example, the process shown in FIGS. 6 to 11 and the process shown in FIGS. 12 to 16 may be performed in sequence to form the outer peripheral portion 3a and the reinforcing portion 3b in sequence.

[0080] First, after performing the steps of Figures 6A and 6B, a paste 3', which is the material of the lower film 3, is formed on the lower wafer 1 (Figure 12A). Figure 12A shows the above-mentioned screen mask 31 and squeegee 32. The screen mask 31 has an opening P1b in addition to the above-mentioned opening P1a (not shown). The opening P1a is used to form a pattern corresponding to the outer peripheral portion 3a, and the opening P1b is used to form a pattern corresponding to the reinforcing portion 3b.

[0081] Next, the paste 3' is reflowed (FIG. 12B). As a result, the paste 3' changes into the lower film 3 including the peripheral portion 3a (not shown) and the reinforcing portion 3b. This reflow forms the reinforcing portion 3b so as to have a trapezoidal cross section. Note that the cross section of the reinforcing portion 3b may have a shape other than a trapezoid, for example, a semicircular or semielliptical shape.

[0082] Next, the lower film 3 is baked (FIG. 13A). As a result, the resin is released from the lower film 3, and the lower film 3 is baked and hardened.

[0083] Next, the upper film 4 is formed on the lower wafer 1, the upper chip 2, and the lower film 3 (FIG. 13B). FIG. 13B shows a protrusion P2b formed on the upper film 4. While the above-mentioned protrusion P2a (not shown) is formed above the upper chip 2 and the outer peripheral portion 3a, the protrusion P2b is formed above the reinforcing portion 3b.

[0084] Next, a resist film 33 is formed on the upper film 4, and the resist film 33 is patterned (FIG. 14A). As a result, an opening P3b is formed in the resist film 33 on the protrusion P2b.

[0085] Next, recesses P4b are formed in the protrusions P2b of the upper film 4 by etching using the resist film 33 (FIG. 14B). As a result, most of the protrusions P2b are removed from the upper film 4.

[0086] Next, the resist film 33 is removed (FIG. 15A). FIG 15A shows the convex portion P2b of the upper film 4 and the concave portion P4b formed in the convex portion P2b.

[0087] Next, the surface of the upper film 4 is planarized by CMP (FIG. 15B). As a result, the convex portions P2a and the concave portions P4a are removed from the upper film 4.

[0088] Next, the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 are bonded to a support substrate 5 (FIG. 16A). The orientations of the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 shown in FIG. 16A are opposite to the orientations of the lower wafer 1, the upper chip 2, the lower film 3, and the upper film 4 shown in FIG. 15B.

[0089] Next, the substrate 11 is thinned by grinding, and then the lower wafer 1 (and the supporting substrate 5) is divided into a plurality of lower chips 1 by dicing (FIG. 16B). In this manner, a semiconductor device including the lower chip 1 and the upper chip 2 is manufactured. The semiconductor device shown in FIG. 16B is the same as the semiconductor device shown in FIG.

[0090] (3) First to third modified examples 17 and 18 are cross-sectional views showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment. In this modification, a lower film 41 is formed instead of the lower film 3. The lower film 41 is an example of the first film of the present disclosure.

[0091] First, after performing the steps of FIG. 6A and FIG. 6B, a lower film 41 is conformally formed on the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 17A). The lower film 41 of this modification is formed by CVD (Chemical Vapor Deposition), for example, ALD (Atomic Layer Deposition). As a result, the lower film 41 is deposited on the surfaces of the lower wafer 1 and the upper chip 2. The lower film 41 is, for example, a SiO2 (silicon oxide) film, a SiN (silicon nitride) film, a SiC (silicon carbide) film, or a SiCN (silicon carbonitride) film.

[0092] Next, the lower film 41 is etched back (FIG. 17B). As a result, the lower film 41 forms the outer peripheral portion 41a. The outer peripheral portion 41a of this modification has a shape similar to that of the outer peripheral portion 3a shown in FIG. 3, for example, a trapezoidal cross section. The reinforcing portion of this modification may be formed simultaneously with the outer peripheral portion 41a, or may be formed in sequence with the outer peripheral portion 41a. The outer peripheral portion 41a and the reinforcing portion are examples of the first and second portions of the present disclosure, respectively.

[0093] 8B to 10B are then performed, as a result of which an upper film 4 is formed on the lower wafer 1, the upper chip 2, and the lower film 41 as shown in FIG.

[0094] 11A and 11B are then carried out, thus completing the manufacture of a semiconductor device including lower chip 1 and upper chip 2 (FIG. 18B).

[0095] According to this modification, it is possible to form the lower film 41 by CVD, which is widely used in semiconductor processes. Moreover, according to this modification, by employing CVD, it is possible to form the lower film 41 with good film quality.

[0096] 19 to 21 are cross-sectional views showing a method for manufacturing a semiconductor device according to a second modified example of the first embodiment. In this modified example, a lower film 42 is formed instead of the lower film 3. The lower film 42 is an example of the first film of the present disclosure.

[0097] First, after performing the steps of Figures 6A and 6B, a lower film material 42', which is the material of the lower film 42, is applied to the surfaces of the lower wafer 1 and the upper chip 2 (Figure 19A). The lower film material 42' contains an organic material such as a resin. Examples of the resin include polyimide, silicone, and amorphous fluororesin (Cytop (registered trademark)).

[0098] Next, the lower film material 42' is patterned (FIG. 19B). As a result, the lower film material 42' is processed into a pattern similar to that of the peripheral portion 42a described below. The lower film material 42' may be processed into a pattern similar to that of the peripheral portion 42a and the reinforcing portion described below.

[0099] Next, the lower film material 42' is reflowed (baked) (FIG. 20A). As a result, the lower film material 42' changes into the lower film 42 including the peripheral portion 42a. This reflow is performed at a temperature at which the resin in the lower film material 42' melts. As a result, as shown in FIG. 20A, the peripheral portion 42a is formed to have a generally triangular vertical cross section. Note that the reinforcing portion of this modified example may be formed simultaneously with the peripheral portion 42a, or may be formed in sequence with the peripheral portion 42a. The peripheral portion 42a and the reinforcing portion are examples of the first and second portions of the present disclosure, respectively.

[0100] Next, the lower film 42 is baked (FIG. 20B). As a result, the resin is released from the lower film 42, and the lower film 42 is baked and hardened.

[0101] 8B to 10B are then performed, as a result of which an upper film 4 is formed on the lower wafer 1, the upper chip 2, and the lower film 42 as shown in FIG.

[0102] 11A and 11B are then carried out, thus completing the manufacture of a semiconductor device including lower chip 1 and upper chip 2 (FIG. 21B).

[0103] According to this modification, it is possible to form the lower film 42 by a coating method that is widely used in semiconductor processes. For example, when the lower film material 42' contains polyimide, it is possible to form the lower film 42 having high heat resistance.

[0104] 22 and 23 are cross-sectional views showing a method for manufacturing a semiconductor device according to a third modified example of the first embodiment. In this modified example, a lower film 43 is formed instead of the lower film 3. The lower film 43 is an example of the first film of the present disclosure.

[0105] 6A and 6B, a lower film 43 is formed by coating on the surfaces of the lower wafer 1 and the upper chip 2 (FIG. 22A). The lower film 43 is, for example, an inorganic film such as an SOG (Spin on Glass) film.

[0106] Next, the lower film 43 is etched back (FIG. 22B). As a result, the lower film 43 forms the outer peripheral portion 43a. The outer peripheral portion 43a of this modification has a shape similar to that of the outer peripheral portion 3a shown in FIG. 3, for example, a trapezoidal cross section. The reinforcing portion of this modification may be formed simultaneously with the outer peripheral portion 43a, or may be formed in sequence with the outer peripheral portion 43a. The outer peripheral portion 43a and the reinforcing portion are examples of the first and second portions of the present disclosure, respectively.

[0107] 8B to 10B are then performed, As a result, an upper film 4 is formed on the lower wafer 1, the upper chip 2, and the lower film 41 as shown in FIG.

[0108] 11A and 11B are then carried out, thus completing the manufacture of a semiconductor device including lower chip 1 and upper chip 2 (FIG. 23B).

[0109] According to this modification, the lower film 43 can be formed by a coating method that is widely used in semiconductor processes.

[0110] (4) Manufacturing method of semiconductor device Fig. 24 is a plan view showing the method for manufacturing the semiconductor device of the first embodiment. In the explanation of Fig. 24, in order to distinguish between the lower chip and the lower wafer, the lower chip will be represented by the symbol "1" and the lower wafer will be represented by the symbol "W".

[0111] FIG. 24 shows the lower wafer W before being divided into a plurality of lower chips 1. The lower wafer W has a plurality of chip regions W1 each having a rectangular planar shape, and a scribe (dicing) region W2 having a mesh-like planar shape. Each chip region W1 is an area that will become a lower chip 1 after division. Therefore, each chip region W1 has the same structure as the lower chip 1 shown in FIG. 2. For example, each chip region W1 is bonded to one upper chip 2 that has already been divided.

[0112] In this embodiment, the lower wafer W is divided into a plurality of chip regions W1 (lower chips 1) by cutting the lower wafer W at the scribe region W2. In this manner, a plurality of semiconductor devices are manufactured from the lower wafer W. Each semiconductor device includes a lower chip 1 and an upper chip 2.

[0113] Each semiconductor device may have a structure, in plan view, different from the structures shown in Figures 2 and 24. Various examples of such structures will be described below.

[0114] (5) Fourth to Ninth Modifications FIG. 25 is a plan view showing the structures of semiconductor devices according to the fourth and fifth modifications of the first embodiment.

[0115] 25A shows a semiconductor device according to a fourth modification. The lower film 3 of this modification includes an outer peripheral portion 3a and a plurality of reinforcing portions 3b separated from the outer peripheral portion 3a. These reinforcing portions 3b are arranged in a staggered arrangement. Thus, the outer peripheral portion 3a may be in contact with the reinforcing portions 3b or may be separated from the reinforcing portions 3b.

[0116] 25B shows a semiconductor device according to a fifth modified example. The lower film 3 of this modified example includes an outer peripheral portion 3a and a reinforcing portion 3b in contact with the outer peripheral portion 3a. The reinforcing portion 3b has the same planar shape as the upper chip 2. According to this modified example, the reinforcing portion 3b can be formed by simple patterning.

[0117] FIG. 26 is a plan view showing the structures of semiconductor devices according to the sixth and seventh modifications of the first embodiment.

[0118] 26A shows a semiconductor device of the sixth modified example. The lower film 3 of this modified example includes the reinforcing portion 3b but does not include the peripheral portion 3a. In other words, the lower film 3 of this modified example does not include a portion provided on the side of the upper chip 2. In this way, the lower film 3 may or may not include the peripheral portion 3a.

[0119] 26B shows a semiconductor device according to the seventh modification. The lower film 3 of this modification includes the outer peripheral portion 3a but does not include the reinforcing portion 3b. In other words, the lower film 3 of this modification does not include a portion spaced apart from the upper chip 2. In this manner, the lower film 3 may or may not include the reinforcing portion 3b.

[0120] FIG. 27 is a plan view showing the structures of semiconductor devices according to eighth and ninth modifications of the first embodiment.

[0121] 27A shows a semiconductor device according to the eighth modification. The lower film 3 of this modification also includes a reinforcing portion 3b, but does not include a peripheral portion 3a. However, the reinforcing portion 3b of this modification has a planar shape similar to that of the reinforcing portion 3b of the fourth modification.

[0122] 27B shows a semiconductor device according to the ninth modification. The lower film 3 of this modification also includes a reinforcing portion 3b, but does not include a peripheral portion 3a. However, the reinforcing portion 3b of this modification has a planar shape similar to that of the reinforcing portion 3b of the fifth modification.

[0123] Thus, the lower membrane 3 can include reinforcing portions 3b of various shapes, whether or not it includes a peripheral portion 3a.

[0124] (6) 10th to 13th Modifications FIG. 28 is a cross-sectional view showing the structures of semiconductor devices according to tenth and eleventh modifications of the first embodiment.

[0125] 28A shows a semiconductor device of a tenth modification. The semiconductor device of this modification has a structure similar to that of the semiconductor device shown in FIG. 1. However, in this modification, the cross-sectional shape of the outer peripheral portion 3a is trapezoidal rather than triangular. This is similar to the outer peripheral portion 3a shown in FIG.

[0126] 28A shows the upper surface S1 of the upper chip 2 and the upper surface S2 of the outer peripheral portion 3a. The above-mentioned side X4 corresponds to a part of the upper surface S2 (see FIG. 3). In this modification, the upper surface S2 of the outer peripheral portion 3a is located at a lower position than the upper surface S1 of the upper chip 2.

[0127] Fig. 28B shows a semiconductor device of Modification 11. The semiconductor device of this modification has a structure similar to that of the semiconductor device shown in Fig. 1. However, in this modification, the cross-sectional shape of the outer peripheral portion 3a is a shape other than a triangle or a trapezoid.

[0128] 28B also shows the upper surface S1 of the upper chip 2 and the upper surface S2 of the outer circumferential portion 3a. In this modification, the upper surface S2 of the outer circumferential portion 3a is provided at a position higher than the upper surface S1 of the upper chip 2.

[0129] In this manner, the upper surface S2 of the outer peripheral portion 3a may be provided at a position lower than the upper surface S1 of the upper chip 2, or may be provided at a position higher than the upper surface S1 of the upper chip 2. Furthermore, the upper surface S2 of the outer peripheral portion 3a may be provided at the same height as the upper surface S1 of the upper chip 2.

[0130] FIG. 29 is a cross-sectional view showing structures of semiconductor devices according to the twelfth and thirteenth modifications of the first embodiment.

[0131] 29A shows a semiconductor device of the twelfth modification. The semiconductor device of this modification has a structure similar to that of the semiconductor device of the eleventh modification. However, the peripheral portion 3a of this modification includes a portion provided on the upper surface S1 of the upper chip 2. Therefore, the upper surface S2 of the peripheral portion 3a of this modification is also provided at a position higher than the upper surface S1 of the upper chip 2.

[0132] 29B shows a semiconductor device of a thirteenth modification. The semiconductor device of this modification has a structure similar to that of the semiconductor device shown in FIG. 1. However, in this modification, the cross-sectional shape of the outer peripheral portion 3a is rectangular rather than triangular, and the cross-sectional shape of the reinforcing portion 3b is rectangular rather than trapezoidal. In this way, the cross-sectional shape of the outer peripheral portion 3a and the cross-sectional shape of the reinforcing portion 3b can be various shapes.

[0133] The lower film 3 shown in FIGS. 28A to 29B may be replaced with any one of the lower films 41, 42, and 43.

[0134] As described above, the semiconductor device of this embodiment includes the lower chip 1, the upper chip 2, the lower film 3, and the upper film 4, and the lower film 3 includes the outer periphery portion 3a provided on the side of the upper chip 1 and the reinforcing portion 3b provided at a distance from the upper chip 1. Therefore, according to this embodiment, it is possible to prevent the occurrence of a seam S in the upper film 4 by the outer periphery portion 3a, and to reinforce the mechanical strength of the semiconductor device by the reinforcing portion 3b. This makes it possible to suitably form the upper film 4 that covers the upper chip 2, etc.

[0135] Second embodiment FIG. 30 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0136] The semiconductor device of this embodiment has a structure similar to that of the semiconductor device of the first embodiment shown in Fig. 3. However, the upper chip 2 of this embodiment includes a substrate 21 and a bonding film 24 instead of the substrate 21, the interlayer insulating film 22, and the multilayer wiring structure 23. Note that Fig. 30 omits the illustration of the multilayer wiring structure 13.

[0137] The upper chip 2 of this embodiment is a bare chip that does not include a circuit. The substrate 21 is, for example, a Si substrate, but may be a semiconductor substrate other than a Si substrate. For example, the substrate 21 may be a compound semiconductor substrate such as an InGaAs substrate or a GaN substrate (In represents indium, Ga represents gallium, As represents arsenic, and N represents nitrogen). The bonding film 24 is formed on the lower surface of the substrate 21 and is bonded to the upper surface of the lower chip 1. The bonding film 24 is, for example, a SiO2 film or a SiN film.

[0138] According to this embodiment, when an upper chip 2 having a structure different from that of the upper chip 2 of the first embodiment is adopted, it is possible to suppress the occurrence of a seam S in the upper film 4 by the peripheral portion 3a, and to reinforce the mechanical strength of the semiconductor device by the reinforcing portion 3b.

[0139] Third embodiment FIG. 31 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0140] The semiconductor device of this embodiment functions as, for example, a SWIR (short wavelength infrared) image sensor. Fig. 31 shows an upper chip 2, a lower film 3, and an upper film 4 provided on a support substrate 6. The upper chip 2 of this embodiment is, for example, an InGaAs chip including an InGaAs substrate.

[0141] The support substrate 6 includes a substrate 61, an interlayer insulating film 62 provided on the substrate 61, and a multilayer wiring structure 63 provided in the interlayer insulating film 62. The multilayer wiring structure 63 is electrically connected to the upper chip 2 via contact plugs 51 in the upper film 4, etc.

[0142] According to this embodiment, the semiconductor device of the first or second embodiment can be suitably applied to a SWIR image sensor.

[0143] (Fourth embodiment) FIG. 32 is a cross-sectional view showing the structure of the semiconductor device of the fourth embodiment.

[0144] The semiconductor device of this embodiment functions as, for example, a micro LED (light emitting diode) display. Figure 32 shows an upper chip 2 and a lower film 3 provided on a support substrate 7. The upper chip 2 of this embodiment is, for example, a GaN chip including a GaN substrate.

[0145] The support substrate 7 includes a substrate 71, an interlayer insulating film 72 provided on the substrate 71, and a multilayer wiring structure 73 provided in the interlayer insulating film 72. The multilayer wiring structure 73 is electrically connected to the upper chip 2 via the wiring layer 52 between the support substrate 7 and the upper chip 2, etc.

[0146] According to this embodiment, the semiconductor device of the first or second embodiment can be suitably applied to a micro LED display.

[0147] Fifth embodiment FIG. 33 is a block diagram showing a configuration of a semiconductor device according to the fifth embodiment.

[0148] The semiconductor device of this embodiment corresponds to an example of the semiconductor device of any one of the first to fourth embodiments. The semiconductor device of this embodiment is a photodetector such as a solid-state imaging device, for example, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor (CIS). The semiconductor device of this embodiment includes a pixel array 82 including a plurality of pixels 81, a control circuit 83, a vertical drive circuit 84, a plurality of column signal processing circuits 85, a horizontal drive circuit 86, an output circuit 87, a plurality of vertical signal lines (VSL) 88, and a horizontal signal line (HSL) 89.

[0149] Each pixel 81 includes a photodiode that functions as a photoelectric conversion unit and a MOS transistor that functions as a pixel transistor. The pixel transistor may be, for example, a transfer transistor, a reset transistor, an amplification transistor, a selection transistor, etc. These pixel transistors may be shared by several pixels 81.

[0150] The pixel array 82 includes a plurality of pixels 81 arranged in a two-dimensional array. The pixel array 82 also includes an effective pixel region that receives light, performs photoelectric conversion, and outputs a signal charge generated by the photoelectric conversion, and a black reference pixel region that outputs optical black that serves as a reference for the black level. In general, the black reference pixel region is arranged on the outer periphery of the effective pixel region.

[0151] The control circuit 83 generates various signals that serve as references for the operation of the vertical drive circuit 84, the column signal processing circuit 85, the horizontal drive circuit 86, etc., based on a vertical synchronization signal, a horizontal synchronization signal, a master clock, etc. The signals generated by the control circuit 83 are, for example, clock signals and control signals, and are input to the vertical drive circuit 84, the column signal processing circuit 85, the horizontal drive circuit 86, etc.

[0152] The vertical drive circuit 84 includes, for example, a shift register, and vertically scans each pixel 81 in the pixel array 82 row by row. The vertical drive circuit 84 further supplies a pixel signal based on the signal charge generated by each pixel 81 to a column signal processing circuit 85 through a vertical signal line 88.

[0153] The column signal processing circuit 85 is arranged, for example, for each column of pixels 81 in the pixel array 82, and performs signal processing for each column of signals output from one row of pixels 81 based on signals from the black reference pixel region. Examples of this signal processing include noise removal and signal amplification.

[0154] The horizontal drive circuit 86 includes, for example, a shift register, and supplies pixel signals from each column signal processing circuit 85 to a horizontal signal line 89 .

[0155] The output circuit 87 processes signals supplied from each column signal processing circuit 85 through a horizontal signal line 89, and outputs the processed signals.

[0156] According to this embodiment, by applying the configuration of this embodiment to the semiconductor device of any one of the first to fourth embodiments, it is possible to realize a suitable photodetector (for example, a solid-state imaging device).

[0157] (Application example) 34 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0158] Camera 100 includes optical section 101 including a lens group and the like, imaging device 102 which is a semiconductor device (for example, a solid-state imaging device) according to any one of the first to fifth embodiments, DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, frame memory 104, display section 105, recording section 106, operation section 107, and power supply section 108. DSP circuit 103, frame memory 104, display section 105, recording section 106, operation section 107, and power supply section 108 are connected to each other via bus line 109.

[0159] The optical unit 101 takes in incident light (image light) from a subject and forms an image on an imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light imaged on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0160] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one screen of a moving image or a still image captured by the imaging device 102.

[0161] The display unit 105 includes a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 in a recording medium such as a hard disk or a semiconductor memory.

[0162] An operation unit 107, under the operation of a user, issues operation commands for various functions of the camera 100. A power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources to these devices.

[0163] By using any one of the semiconductor devices according to the first to fifth embodiments as the imaging device 102, it is possible to expect acquisition of a good image.

[0164] The semiconductor device can be applied to various other products. For example, the semiconductor device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0165] 35 is a block diagram showing a configuration example of a moving object control system. The moving object control system shown in FIG.

[0166] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 35, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 35 further illustrates, as components of the integrated control unit 250, a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253.

[0167] The drivetrain control unit 210 controls the operation of devices related to the drivetrain of the vehicle according to various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0168] The body system control unit 220 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, back lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that substitutes for a key or signals from various switches may be input to the body system control unit 220. The body system control unit 220 receives input of such radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.

[0169] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture an image outside the vehicle, and receives the captured image from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received image.

[0170] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal according to the amount of the received light. The imaging unit 231 can output the electrical signal as an image, and can also output it as distance measurement information. The light received by the imaging unit 231 may be visible light, or may be invisible light such as infrared light. The imaging unit 231 includes the semiconductor device according to any one of the first to fifth embodiments.

[0171] The in-vehicle information detection unit 240 detects information about the inside of the vehicle equipped with the vehicle control system 200. For example, a driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 241, or may determine whether the driver is dozing. This camera may include any of the semiconductor devices of the first to fifth embodiments, and may be, for example, the camera 100 shown in FIG. 34.

[0172] The microcomputer 251 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 230 or the inside-vehicle information detection unit 240, and output a control command to the drive system control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an ADAS (Advanced Driver Assistance System), such as vehicle collision avoidance, impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning, lane departure warning, etc.

[0173] In addition, the microcomputer 251 can perform cooperative control for the purpose of automatic driving, in which the vehicle travels autonomously without being operated by the driver, by controlling the driving force generating device, the steering mechanism, or the braking device based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0174] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 230, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0175] The audio / image output unit 252 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 35, an audio speaker 261, a display unit 262, and an instrument panel 263 are shown as such output devices. The display unit 262 may include, for example, an on-board display or a head-up display.

[0176] FIG. 36 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0177] 36 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 300.

[0178] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or the back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the upper part of the windshield inside the vehicle cabin mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, a leading vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, and the like.

[0179] FIG. 36 shows an example of the imaging ranges of the imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304"). Imaging range 311 indicates the imaging range of the imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of the imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of the imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of the imaging unit 304 provided on the rear bumper or the back door. For example, the image data captured by the imaging units 301 to 304 are superimposed to obtain an overhead image of the vehicle 300 viewed from above. Hereinafter, the imaging ranges 311, 312, 313, and 314 are referred to as "imaging ranges 311 to 314".

[0180] At least one of the imaging units 301 to 304 may have a function of acquiring distance information. For example, at least one of the imaging units 301 to 304 may be a stereo camera including a plurality of imaging devices, or may be an imaging device having pixels for detecting a phase difference.

[0181] For example, the microcomputer 251 (FIG. 35) calculates the distance to each solid object in the imaging range 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, a solid object that is the closest solid object on the traveling path of the vehicle 300 and travels in approximately the same direction as the vehicle 300 at a predetermined speed (for example, 0 km / h or more). Furthermore, the microcomputer 251 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). Thus, according to this example, cooperative control can be performed for the purpose of automatic driving that travels autonomously without the driver's operation.

[0182] For example, the microcomputer 251 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 301 to 304, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. Then, the microcomputer 251 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and there is a possibility of a collision, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drive system control unit 210.

[0183] At least one of the imaging units 301 to 304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 301 to 304. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 301 to 304 as infrared cameras and a procedure of performing a pattern matching process on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the captured images of the imaging units 301 to 304 and recognizes the pedestrian, the audio / image output unit 252 controls the display unit 262 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 252 may also control the display unit 262 to display an icon or the like indicating a pedestrian at a desired position.

[0184] FIG. 37 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0185] 37 shows a state in which an operator (doctor) 531 is performing surgery on a patient 532 on a patient bed 533 using an endoscopic surgery system 400. As shown in the figure, the endoscopic surgery system 400 is composed of an endoscope 500, other surgical tools 510 such as an insufflation tube 511 and an energy treatment tool 512, a support arm device 520 that supports the endoscope 500, and a cart 600 on which various devices for endoscopic surgery are mounted.

[0186] The endoscope 500 is composed of a lens barrel 501, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 532, and a camera head 502 connected to the base end of the lens barrel 501. In the illustrated example, the endoscope 500 is configured as a so-called rigid lens barrel having a rigid lens barrel 501, but the endoscope 500 may be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0187] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 501. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 501, and is irradiated via the objective lens toward an observation target in a body cavity of a patient 532. The endoscope 500 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0188] An optical system and an image sensor are provided inside the camera head 502, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 601 as RAW data.

[0189] The CCU 601 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 500 and the display device 602. Furthermore, the CCU 601 receives an image signal from the camera head 502, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0190] Under the control of the CCU 601 , the display device 602 displays an image based on an image signal that has been subjected to image processing by the CCU 601 .

[0191] The light source device 603 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 500 with irradiation light when photographing an operation site or the like.

[0192] The input device 604 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 400 via the input device 604. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 500.

[0193] The treatment tool control device 605 controls the driving of the energy treatment tool 512 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 606 feeds gas into the body cavity of the patient 532 via the insufflation tube 511 in order to secure the field of view of the endoscope 500 and the working space of the surgeon. The recorder 607 is a device capable of recording various information related to the surgery. The printer 608 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0194] The light source device 603 that supplies irradiation light to the endoscope 500 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 603. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation target with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 502 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0195] Furthermore, the light source device 603 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 502 in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner and synthesizing the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0196] The light source device 603 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, the special light observation may be a fluorescent observation in which an image is obtained by fluorescence generated by irradiating excitation light. In the fluorescent observation, excitation light is irradiated to the body tissue and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescent wavelength of the reagent is irradiated to the body tissue to obtain a fluorescent image. The light source device 603 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0197] FIG. 38 is a block diagram showing an example of a functional configuration of the camera head 502 and the CCU 601 shown in FIG.

[0198] The camera head 502 has a lens unit 701, an imaging section 702, a drive section 703, a communication section 704, and a camera head control section 705. The CCU 601 has a communication section 711, an image processing section 712, and a control section 713. The camera head 502 and the CCU 601 are connected to each other by a transmission cable 700 so as to be able to communicate with each other.

[0199] Lens unit 701 is an optical system provided at a connection portion with lens barrel 501. Observation light taken in from the tip of lens barrel 501 is guided to camera head 502 and enters lens unit 701. Lens unit 701 is configured by combining multiple lenses including a zoom lens and a focus lens.

[0200] The imaging unit 702 is composed of an imaging element. The imaging element constituting the imaging unit 702 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 702 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 702 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 531 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 702 is composed of a multi-plate type, the lens unit 701 may also be provided in multiple systems corresponding to each imaging element. The imaging unit 702 is, for example, a semiconductor device according to any one of the first to fifth embodiments.

[0201] Furthermore, the imaging section 702 does not necessarily have to be provided in the camera head 502. For example, the imaging section 702 may be provided inside the lens barrel 501, immediately behind the objective lens.

[0202] The driving section 703 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera head control section 705. This allows the magnification and focus of the image captured by the imaging section 702 to be appropriately adjusted.

[0203] The communication unit 704 is configured by a communication device for transmitting and receiving various information to and from the CCU 601. The communication unit 704 transmits the image signal obtained from the imaging unit 702 to the CCU 601 via the transmission cable 700 as RAW data.

[0204] Furthermore, the communication unit 704 receives a control signal for controlling the driving of the camera head 502 from the CCU 601, and supplies the control signal to the camera head control unit 705. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0205] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 713 of the CCU 601 based on an acquired image signal. In the latter case, the endoscope 500 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0206] The camera head control unit 705 controls the driving of the camera head 502 based on a control signal received from the CCU 601 via the communication unit 704 .

[0207] The communication unit 711 is configured with a communication device for transmitting and receiving various information to and from the camera head 502. The communication unit 711 receives an image signal transmitted from the camera head 502 via the transmission cable 700.

[0208] Furthermore, the communication unit 711 transmits, to the camera head 502, a control signal for controlling the driving of the camera head 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0209] The image processing unit 712 performs various types of image processing on the image signal, which is RAW data sent from the camera head 502 .

[0210] The control unit 713 performs various controls related to the imaging of the operation site etc. by the endoscope 500 and the display of the captured image obtained by imaging the operation site etc. For example, the control unit 713 generates a control signal for controlling the driving of the camera head 502.

[0211] Further, the control unit 713 causes the display device 602 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 712. At this time, the control unit 713 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 713 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist generated when the energy treatment tool 512 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 713 causes the display device 602 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 531, the burden on the surgeon 531 can be reduced and the surgeon 531 can proceed with the surgery reliably.

[0212] The transmission cable 700 connecting the camera head 502 and the CCU 601 is an electrical signal cable corresponding to communication of electrical signals, an optical fiber corresponding to optical communication, or a composite cable of these.

[0213] Here, in the illustrated example, the communication is performed by wire using the transmission cable 700, but the communication between the camera head 502 and the CCU 601 may be performed wirelessly.

[0214] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications without departing from the scope of the present disclosure. For example, two or more embodiments may be implemented in combination.

[0215] The present disclosure may also be configured as follows.

[0216] (1) a first chip having a first area in a plan view; a second chip provided on the first chip and having a second area smaller than the first area in a plan view; a first film provided on the first chip; the first chip, the second chip, and a second film provided on the first film; the first film includes a first portion provided on a side surface of the second chip; A semiconductor device, wherein the predetermined vertical cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length.

[0217] (2) The semiconductor device according to (1), wherein the predetermined cross section further has a hypotenuse that is at an angle of 30 to 60 degrees with respect to the vertical direction.

[0218] (3) The semiconductor device according to (2), wherein, when the angle is θ, the first length is A, the second length is B, and the height of the specified longitudinal section is C, C≦(BA) / tan θ holds.

[0219] (4) The semiconductor device according to (1), wherein the shape of the specified vertical cross section is a trapezoid with the upper side as an upper base and the lower side as a lower base.

[0220] (5) The semiconductor device according to (1), wherein the first film further includes a second portion spaced apart from the second chip.

[0221] (6) The semiconductor device according to (5), wherein the first portion is in contact with the second portion and is provided between the second chip and the second portion.

[0222] (7) The semiconductor device according to (5), wherein the first portion is separated from the second portion.

[0223] (8) The semiconductor device according to (1), wherein an upper surface of the first portion is located lower than an upper surface of the second chip.

[0224] (9) The semiconductor device according to (1), wherein an upper surface of the first portion is located at a higher position than an upper surface of the second chip.

[0225] (10) The semiconductor device according to (1), wherein the first portion includes a portion provided on an upper surface of the second chip.

[0226] (11) The semiconductor device according to (1), wherein the second chip includes a substrate containing silicon or a compound semiconductor substrate.

[0227] (12) a first chip having a first area in a plan view; a second chip provided on the first chip and having a second area smaller than the first area in a plan view; a first film provided on the first chip; the first chip, the second chip, and a second film provided on the first film; The first film includes a second portion spaced apart from the second chip.

[0228] (13) The semiconductor device according to (12), wherein the first film further includes a first portion provided on a side surface of the second chip.

[0229] (14) The semiconductor device according to (13), wherein the predetermined vertical cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length.

[0230] (15) The semiconductor device according to (14), wherein the shape of the predetermined vertical cross section is a trapezoid with the upper side as an upper base and the lower side as a lower base.

[0231] (16) The semiconductor device described in (13), wherein the shape of a predetermined cross section of the first portion is a triangle having a first side facing the top surface of the first chip, a second side facing the side of the second chip, and a third side located between the first side and the second side.

[0232] (17) A second chip is loaded onto the first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; processing the first wafer into a first chip; Including, the first film is formed to include at least one of a first portion provided on a side surface of the second chip and a second portion provided at a distance from the second chip; The first portion is formed such that a predetermined longitudinal cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length. A method for manufacturing a semiconductor device.

[0233] (18) the first chip has a first area in a plan view; the second chip has a second area smaller than the first area in a plan view; A method for manufacturing a semiconductor device according to (17).

[0234] (19) The method for manufacturing a semiconductor device according to (17), wherein the first film is formed by printing, deposition, or coating.

[0235] (20) The method for manufacturing a semiconductor device according to (17), wherein the first portion is formed by processing the first film by etching back. [Explanation of symbols]

[0236] 1: Lower chip (lower wafer), 2: Upper chip (upper wafer), 3: Lower membrane, 3a: Outer periphery, 3b: Reinforcement, 3': Paste, 4: Upper membrane, 4a: Membrane part, 4b: Membrane part, 5: supporting substrate, 6: supporting substrate, 7: supporting substrate, 11: substrate; 12: interlayer insulating film; 13: multilayer wiring structure; 13a: wiring layer, 13b: via plug, 13c: metal pad, 21: substrate, 22: interlayer insulating film, 23: multilayer wiring structure, 23a: wiring layer, 23b: via plug, 23c: metal pad, 24: bonding film, 31: screen mask, 32: squeegee, 33: resist film, 41: lower membrane, 41a: outer peripheral part, 42: lower membrane, 42a: outer peripheral portion, 42': lower membrane material, 43: lower membrane, 43a: outer peripheral part, 51: contact plug; 52: wiring layer; 61: substrate; 62: interlayer insulating film; 63: multilayer wiring structure; 71: substrate, 72: interlayer insulating film, 73: multilayer wiring structure, 81: pixel; 82: pixel array; 83: control circuit; 84: vertical drive circuit, 85: column signal processing circuit, 86: horizontal drive circuit, 87: output circuit, 88: vertical signal line, 89: horizontal signal line

Claims

1. a first chip having a first area in a plan view; a second chip provided on the first chip and having a second area smaller than the first area in a plan view; a first film provided on the first chip; the first chip, the second chip, and a second film provided on the first film; the first film includes a first portion provided on a side surface of the second chip; A semiconductor device, wherein the predetermined vertical cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length.

2. 2. The semiconductor device according to claim 1, wherein said predetermined vertical cross section further has a hypotenuse that is at an angle of 30 to 60 degrees with respect to the vertical direction.

3. 3. The semiconductor device according to claim 2, wherein, when the angle is θ, the first length is A, the second length is B, and the height of the predetermined vertical cross section is C, C≦(B−A) / tan θ holds.

4. 2. The semiconductor device according to claim 1, wherein the shape of the predetermined vertical cross section is a trapezoid with the upper side as an upper base and the lower side as a lower base.

5. The semiconductor device according to claim 1 , wherein the first film further includes a second portion spaced apart from the second chip.

6. The semiconductor device according to claim 5 , wherein the first portion is in contact with the second portion and is provided between the second chip and the second portion.

7. The semiconductor device according to claim 5 , wherein the first portion is separated from the second portion.

8. The semiconductor device according to claim 1 , wherein an upper surface of said first portion is located lower than an upper surface of said second chip.

9. The semiconductor device according to claim 1 , wherein an upper surface of said first portion is provided at a position higher than an upper surface of said second chip.

10. The semiconductor device according to claim 1 , wherein the first portion includes a portion provided on an upper surface of the second chip.

11. The semiconductor device according to claim 1 , wherein the second chip includes a substrate containing silicon or a compound semiconductor substrate.

12. a first chip having a first area in a plan view; a second chip provided on the first chip and having a second area smaller than the first area in a plan view; a first film provided on the first chip; the first chip, the second chip, and a second film provided on the first film; The first film includes a second portion spaced apart from the second chip.

13. The semiconductor device according to claim 12 , wherein the first film further includes a first portion provided on a side surface of the second chip.

14. 14. The semiconductor device according to claim 13, wherein the predetermined vertical cross section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length.

15. 15. The semiconductor device according to claim 14, wherein the shape of the predetermined vertical cross section is a trapezoid with the upper side as an upper base and the lower side as a lower base.

16. 14. The semiconductor device according to claim 13, wherein a predetermined cross-sectional shape of the first portion is a triangle having a first side facing the top surface of the first chip, a second side facing the side surface of the second chip, and a third side located between the first side and the second side.

17. A second chip is loaded on the first wafer; forming a first film on the first wafer; forming a second film on the first wafer, the second chip, and the first film; processing the first wafer into first chips; Including, the first film is formed so as to include at least one of a first portion provided on a side surface of the second chip and a second portion provided at a distance from the second chip; The first portion is formed such that a predetermined longitudinal section of the first portion has an upper side having a first length and a lower side having a second length longer than the first length. A method for manufacturing a semiconductor device.

18. the first chip has a first area in a plan view; the second chip has a second area smaller than the first area in a plan view; The method for manufacturing a semiconductor device according to claim 17.

19. The method for manufacturing a semiconductor device according to claim 17 , wherein the first film is formed by printing, deposition, or coating.

20. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the first portion is formed by processing the first film by etching back.

Images