Voltage generation circuit and semiconductor memory device

Abstract

To provide a voltage generation circuit capable of suppressing a peak current generated in a booster circuit, and to provide a semiconductor memory device.SOLUTION: A voltage generation circuit 14 according to one embodiment comprises a first transistor T1, a first circuit 53, and a second circuit 52. A reference voltage Vpref is applied to a gate of the first transistor. A power supply voltage VCC is applied to a first terminal of the first transistor. A second terminal of the first transistor is connected to a first node N2. The first circuit is connected to the first node to boost a first voltage Vpsup of the first node, and outputs a boosted second voltage Vpout. The second circuit is connected to the first node to detect a peak of a first current Ipm flowing through the first circuit from the first transistor. The first circuit stops voltage-boosting, based on a detection result FLGP1 by the second circuit.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a voltage generating circuit and a semiconductor memory device. [Background technology]

[0002] A NAND flash memory is known as a semiconductor memory device including memory cells that store data in a non-volatile manner. In the semiconductor memory device, a voltage generating circuit supplies voltages to various wirings connected to the memory cells. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2013 / 0070542 [Patent Document 2] US Patent Application Publication No. 2020 / 0185041 [Patent Document 3] US Patent Application Publication No. 2022 / 0172789 Summary of the Invention [Problem to be solved by the invention]

[0004] A voltage generating circuit and a semiconductor memory device capable of suppressing a peak current generated in a boosting circuit are provided. [Means for solving the problem]

[0005] A voltage generating circuit according to an embodiment includes a first transistor, a first circuit, and a second circuit. A reference voltage is applied to a gate of the first transistor. A power supply voltage is applied to a first terminal of the first transistor. A second terminal of the first transistor is connected to a first node. The first circuit is connected to the first node, boosts a first voltage at the first node, and outputs a boosted second voltage. The second circuit is connected to the first node, and detects a peak of a first current flowing from the first transistor to the first circuit. The first circuit stops boosting the voltage based on a detection result by the second circuit. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of a configuration of a memory system including a semiconductor memory device according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing an example of a configuration of a memory cell array in a semiconductor memory device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array in a semiconductor memory device according to a first embodiment. [Figure 4] 2 is a cross-sectional view showing an example of a cross-sectional structure of a memory pillar in the semiconductor memory device according to the first embodiment. [Diagram 5] 2 is a circuit diagram showing an example of a configuration of a voltage generating circuit in the semiconductor memory device according to the first embodiment. [Figure 6] 2 is a circuit diagram showing an example of a configuration of a boost circuit included in a voltage generating circuit in the semiconductor memory device according to the first embodiment. [Figure 7] 2 is a circuit diagram showing an example of a configuration of a charge pump included in a voltage generating circuit in the semiconductor memory device according to the first embodiment. [Figure 8] 4A to 4C are diagrams illustrating an example of a waveform of a current flowing in a boost circuit in a voltage generating circuit according to the first embodiment, and an example of a waveform of a current flowing in a boost circuit in a voltage generating circuit according to a comparative example. [Figure 9] FIG. 13 is a circuit diagram showing an example of a configuration of a voltage generating circuit in a semiconductor memory device according to a first modified example of the first embodiment. [Figure 10]FIG. 11 is a circuit diagram showing an example of a configuration of a voltage generating circuit in a semiconductor memory device according to a second modification of the first embodiment. [Figure 11] 4 is a diagram illustrating the relationship between a plurality of voltages in the semiconductor memory device according to the first embodiment. FIG. [Figure 12] 11 is a circuit diagram showing an example of a configuration of a voltage generating circuit in a semiconductor memory device according to a second embodiment. [Figure 13] 10 is a flowchart showing an example of a calibration operation of the voltage generating circuit in the semiconductor memory device according to the second embodiment. [Figure 14] 10 is a flowchart showing an example of a setting operation of a voltage generating circuit in a semiconductor memory device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. The dimensions and ratios of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are given the same reference numerals. When elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. First embodiment 1.1 Configuration 1.1.1 Memory System Configuration The configuration of a memory system including a semiconductor memory device according to the first embodiment will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the configuration of a memory system. The memory system is a memory device configured to be connected to an external host device (not shown). The memory system is, for example, a storage device such as an SD TM The memory system 1 includes a memory controller 2 and a semiconductor memory device 3. The memory system 1 may be a memory card such as a card, a universal flash storage (UFS), or a solid state drive (SSD).

[0009] The memory controller 2 is a device that controls the semiconductor memory device 3. The memory controller 2 is, for example, a system-on-a-chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on a request from a host device. Specifically, for example, the memory controller 2 writes data requested to be written by the host device to the semiconductor memory device 3. In addition, the memory controller 2 reads data requested to be read by the host device from the semiconductor memory device 3 and transmits the data to the host device.

[0010] The semiconductor memory device 3 is a memory that stores data in a non-volatile manner, and is, for example, a NAND type flash memory.

[0011] 1.1.2 Configuration of semiconductor memory device The configuration of the semiconductor memory device 3 will be described below with reference to FIG.

[0012] The semiconductor memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a voltage generating circuit 14, a row decoder module 15, and a sense amplifier module 16.

[0013] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). Hereinafter, when the blocks BLK0 to BLKn are not distinguished from one another, each of the blocks BLK0 to BLKn will be simply referred to as a block BLK. The block BLK is a set of a plurality of memory cell transistors capable of storing data in a non-volatile manner. The block BLK is used, for example, as a data erase unit. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. The memory cell array 10 will be described in detail later.

[0014] The command register 11 is a circuit that stores a command CMD that the semiconductor memory device 3 receives from the memory controller 2. The command CMD includes, for example, an instruction to cause the sequencer 13 to execute a write operation, a read operation, an erase operation, and the like.

[0015] The address register 12 is a circuit that stores an address ADD that the semiconductor memory device 3 receives from the memory controller 2. The address ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. The block address BAd, the page address PAd, and the column address CAd are used, for example, to select a block BLK, a word line, and a bit line, respectively.

[0016] The sequencer 13 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 13 controls the operation of the entire semiconductor memory device 3. For example, the sequencer 13 controls the voltage generation circuit 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD stored in the command register 11. For example, the sequencer 13 executes a write operation, a read operation, an erase operation, etc.

[0017] The voltage generation circuit 14 is a circuit that generates voltages used in write operations, read operations, erase operations, etc., based on instructions from the sequencer 13. The voltage generation circuit 14 applies the generated voltage to a signal line corresponding to a selected word line based on, for example, a page address PAd stored in the address register 12.

[0018] The row decoder module 15 is a circuit that selects one block BLK in the memory cell array 10 based on a block address BAd stored in the address register 12. The row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to a selected word line to a selected word line in the selected block BLK.

[0019] The sense amplifier module 16 selects a bit line based on a column address CAd stored in the address register 12. In a write operation, the sense amplifier module 16 applies a voltage based on write data DAT received from the memory controller 2 to the selected bit line. In a read operation, the sense amplifier module 16 determines data stored in a memory cell transistor based on the voltage of the selected bit line. The sense amplifier module 16 transfers the determination result to the memory controller 2 as read data DAT.

[0020] The semiconductor memory device 3 configured as above is connected to the memory controller 2 via a NAND interface (not shown). Signals transmitted and received between the semiconductor memory device 3 and the memory controller 2 include, for example, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, and an input / output signal I / O. The memory controller 2 controls the semiconductor memory device 3 using these signals.

[0021] The signal CLE is a signal indicating that the signal I / O received by the semiconductor memory device 3 is a command CMD. The signal ALE is a signal indicating that the signal I / O received by the semiconductor memory device 3 is an address ADD. The signal WEn is a signal that instructs the semiconductor memory device 3 to input the signal I / O. The signal REn is a signal that instructs the semiconductor memory device 3 to output the signal I / O. The signals CLE, ALE, WEn, and REn are transmitted from the memory controller 2 to the semiconductor memory device 3.

[0022] The signal RBn is a signal indicating whether the semiconductor memory device 3 is in a ready state or a busy state. The signal RBn is set to an "L" level, for example, when the semiconductor memory device 3 is in a busy state. The ready state is a state in which the semiconductor memory device 3 can accept a command CMD from the memory controller 2. The busy state is a state in which the semiconductor memory device 3 cannot accept a command CMD from the memory controller 2. The signal RBn is transmitted from the semiconductor memory device 3 to the memory controller 2.

[0023] The signal I / O is, for example, an 8-bit signal. The signal I / O is data transmitted and received between the semiconductor memory device 3 and the memory controller 2. The signal I / O includes, for example, a command CMD, an address ADD, and data DAT.

[0024] 1.1.3 Memory cell array circuit configuration The circuit configuration of the memory cell array 10 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the configuration of the memory cell array 10. Fig. 2 shows the circuit configuration of a block BLK included in the memory cell array 10 as an example of the circuit configuration of the memory cell array 10. The other blocks BLK also have the same configuration as Fig. 2.

[0025] The block BLK includes, for example, four string units SU0 to SU3. Hereinafter, when the string units SU0 to SU3 are not distinguished from each other, each of the string units SU0 to SU3 is simply referred to as a string unit SU. The string unit SU is, for example, a collection of a plurality of NAND strings NS selected collectively in a write operation or a read operation. The string unit SU includes a plurality of NAND strings NS associated with the bit lines BL0 to BLm (m is an integer equal to or greater than 1). Hereinafter, when the bit lines BL0 to BLm are not distinguished from each other, each of the bit lines BL0 to BLm is simply referred to as a bit line BL. The NAND string NS is a collection of a plurality of transistors connected in series. The plurality of transistors connected in series include, for example, memory cell transistors MC0 to MC7 and selection transistors ST1 and ST2. Hereinafter, when the memory cell transistors MC0 to MC7 are not distinguished from each other, each of the memory cell transistors MC0 to MC7 is simply referred to as a memory cell transistor MC. The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The selection transistors ST1 and ST2 are switching elements, and each of the selection transistors ST1 and ST2 is used to select a string unit SU during various operations.

[0026] In the NAND string NS, the memory cell transistors MC0 to MC7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the memory cell transistors MC0 to MC7. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MC0 to MC7. The source of the selection transistor ST2 is connected to a source line SL.

[0027] In the same block BLK, the control gates of the memory cell transistors MC0 to MC7 are commonly connected to the word lines WL0 to WL7, respectively. Hereinafter, when the word lines WL0 to WL7 are not differentiated from one another, each of the word lines WL0 to WL7 is simply referred to as a word line WL. The gates of the select transistors ST1 in the string units SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. Hereinafter, when the select gate lines SGD0 to SGD3 are not differentiated from one another, each of the select gate lines SGD0 to SGD3 is simply referred to as a select gate line SGD. The gates of the select transistors ST2 included in the same block BLK are commonly connected to a select gate line SGS.

[0028] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by, for example, a plurality of NAND strings NS to which the same column address CAd is assigned in a plurality of string units SU, and the source line SL is shared by, for example, a plurality of blocks BLK.

[0029] A collection of memory cell transistors MC connected to a common word line WL in a string unit SU is called, for example, a cell unit CU. A block BLK includes a plurality of cell units CU. Data stored in a cell unit CU including a plurality of memory cell transistors MC each storing one bit of data according to a threshold voltage corresponds to one page of data. A cell unit CU can store two or more pages of data based on the number of bits of data stored in the memory cell transistors MC.

[0030] Furthermore, the circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string units SU included in the block BLK, and the number of memory cell transistors MC and select transistors ST1 and ST2 included in the NAND string NS may be any number. Hereinafter, the memory cell transistors MC are also referred to as memory cells MC.

[0031] 1.1.4 Memory cell array structure The cross-sectional structure of the memory cell array 10 will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 10. FIG. 3 shows a region corresponding to a block BLK. In FIG. 3, the X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of a semiconductor substrate (not shown) used to form the semiconductor memory device 3.

[0032] The memory cell array 10 includes conductive layers 21 to 26, insulating layers 31 to 34, a plurality of memory pillars MP, and a plurality of members SHE.

[0033] The conductor layer 21 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 21 is used as a source line SL. The conductor layer 21 is made of a conductive material, for example, an N-type semiconductor with impurities added, or a metal material. The conductor layer 21 may have, for example, a laminated structure of a semiconductor and a metal.

[0034] An insulating layer 31 is provided on the upper surface of the conductive layer 21. A conductive layer 22 is provided on the upper surface of the insulating layer 31. The conductive layer 22 is formed, for example, in a plate shape extending along the XY plane. The conductive layer 22 is used as a select gate line SGS. The conductive layer 22 includes, for example, tungsten.

[0035] Eight insulating layers 32 and eight conductive layers 23 are alternately stacked on the upper surface of the conductive layer 22 in the order of insulating layer 32, conductive layer 23, insulating layer 32, ..., insulating layer 32, and conductive layer 23. The conductive layer 23 is formed, for example, in a plate shape extending along the XY plane. The stacked conductive layers 23 are used as word lines WL0 to WL7, respectively, in order from the select gate line SGS side. The conductive layer 23 contains, for example, tungsten.

[0036] An insulating layer 33 is provided on the upper surface of the uppermost conductive layer 23. A conductive layer 24 is provided on the upper surface of the insulating layer 33. The conductive layer 24 is formed, for example, in a plate shape extending along the XY plane. The conductive layer 24 is used as a select gate line SGD. The conductive layer 24 includes, for example, tungsten.

[0037] An insulating layer 34 is provided on the upper surface of the conductive layer 24. A conductive layer 25 is provided on the upper surface of the insulating layer 34. The conductive layer 25 is formed, for example, in a line shape extending in the Y direction. The conductive layer 25 is used as a bit line BL. The conductive layer 25 includes, for example, copper.

[0038] The memory pillar MP is provided to extend along the Z direction. The memory pillar MP penetrates the insulator layers 31 and 33, the multiple insulator layers 32, the conductor layers 22 and 24, and the multiple conductor layers 23.

[0039] The memory pillar MP includes, for example, a core member 40, a semiconductor film 41, insulating films 42 to 44, and a semiconductor portion 45.

[0040] The core member 40 is formed in a columnar shape extending along the Z direction in the center of the memory pillar MP. The upper end of the core member 40 is included in, for example, a layer above the conductive layer 24. The lower end of the core member 40 is included in, for example, a layer below the conductive layer 22. The core member 40 includes, for example, silicon oxide.

[0041] The side and bottom surfaces of the core member 40 are covered with a semiconductor film 41. The semiconductor film 41 functions as channels of the memory cell transistors MC and the select transistors ST1 and ST2. A bottom end of the semiconductor film 41 contacts the conductor layer 21. The semiconductor film 41 includes, for example, polysilicon.

[0042] The side surface of the semiconductor film 41 is covered with a laminate of insulating films 42 to 44.

[0043] A semiconductor portion 45 is formed on the core member 40 and the semiconductor film 41. The semiconductor portion 45 is electrically connected to the semiconductor film 41. The side surface of the semiconductor portion 45 is covered by, for example, a stack of insulating films 42 to 44. The semiconductor portion 45 may be formed integrally with the semiconductor film 41. The upper surface of the semiconductor portion 45 contacts the conductor layer 26. The conductor layer 26 is connected to the conductor layer 25, and the memory pillar MP and the conductor layer 25 are electrically connected. The conductor layer 26 contains, for example, copper.

[0044] In the configuration of the memory pillar MP described above, for example, the portion where the memory pillar MP intersects with the conductive layer 22 functions as a select transistor ST2. The portions where the memory pillar MP intersects with each of the eight conductive layers 23 function as memory cell transistors MC0 to MC7. The portions where the memory pillar MP intersects with the conductive layer 24 function as a select transistor ST1.

[0045] The member SHE extends in the Z direction and divides the conductive layer 24 in the Y direction. The member SHE includes, for example, an insulator. The conductive layer 24 divided by the member SHE corresponds to the selection gate lines SGD0 to SGD3, respectively.

[0046] A plurality of the above configurations are arranged in the depth direction (X direction) of the paper surface of FIG. 3, and a set of a plurality of NAND strings NS arranged in the X direction constitutes a string unit SU.

[0047] Fig. 4 is a cross-sectional view showing an example of the cross-sectional structure of a memory pillar MP, taken along line SS in Fig. 3. Specifically, Fig. 4 shows the cross-sectional structure of the memory pillar MP in a layer that is parallel to the surface of the semiconductor substrate and includes the conductive layer 23.

[0048] As shown in FIG. 4, the insulating film 42 covers the periphery of the semiconductor film 41. The insulating film 42 functions as a tunnel insulating film of the memory cell transistor MC. The insulating film 42 includes, for example, silicon oxide or silicon oxynitride. The insulating film 43 covers the periphery of the insulating film 42. The insulating film 43 functions as a charge storage layer of the memory cell transistor MC. The insulating film 43 includes, for example, silicon nitride. The insulating film 44 covers the periphery of the insulating film 43. The insulating film 44 functions as a block insulating film of the memory cell transistor MC. The insulating film 44 includes, for example, silicon oxide or aluminum oxide. The conductor layer 23 covers the periphery of the insulating film 44.

[0049] 1.1.5 Configuration of the voltage generation circuit The configuration of the voltage generating circuit 14 will be described with reference to Fig. 5. Fig. 5 is a circuit diagram showing an example of the configuration of the voltage generating circuit 14. In the following description, when the source and drain of a transistor are not limited, either the source or the drain of the transistor will be referred to as the "first end of the transistor", and the other either the source or the drain of the transistor will be referred to as the "second end of the transistor".

[0050] The voltage generating circuit 14 includes, for example, a reference voltage generating circuit 51, an n-channel MOS transistor T1, a peak current detecting circuit 52, a logical product circuit (AND circuit) ANDP, and a boosting circuit 53.

[0051] The reference voltage generating circuit 51 is a circuit that generates a reference voltage Vpref to be applied to the gate of the transistor T1. The voltage Vpref is a reference voltage for generating a voltage to be supplied to the boost circuit 53 by a source follower. The reference voltage generating circuit 51 is connected to a node N1. The reference voltage generating circuit 51 supplies the generated reference voltage Vpref to the gate of the transistor T1 and the peak current detection circuit 52 via the node N1. The reference voltage generating circuit 51 will be described in detail later.

[0052] The transistor T1 is a transistor that drives the boost circuit 53. The transistor T1 is, for example, an n-channel MOS transistor having a gate width W. The gate of the transistor T1 is connected to the node N1. That is, the voltage Vpref is applied to the gate of the transistor T1. The power supply voltage VCC is applied to the first terminal of the transistor T1. The second terminal of the transistor T1 is connected to the node N2. The boost circuit 53 is supplied with a voltage clamped by the transistor T1 at the voltage Vpref. Due to a voltage drop caused by the influence of the threshold voltage Vth1 of the transistor T1, the voltage supplied to the boost circuit 53 is a voltage smaller than the voltage VCC. Hereinafter, the voltage supplied to the boost circuit 53, that is, the voltage at the node N2, is referred to as "voltage Vpsup". The current flowing through the boost circuit 53 due to the supply of the voltage Vpsup is referred to as "current Ipmp".

[0053] The voltage generating circuit 14 includes a line CN1 that supplies a voltage VCC to the transistor T1. The voltage VCC is supplied to one end of the line CN1. The other end of the line CN1 is connected to a first end of the transistor T1.

[0054] The voltage Vpsup at the node N2 is controlled to be a substantially constant voltage by controlling the voltage applied to the gate of the transistor T1 to the voltage Vpref by the reference voltage generating circuit 51. This makes it possible to prevent the voltage boosted by the boost circuit 53 from becoming too high, which may damage the boost circuit 53 itself or other circuits.

[0055] The peak current detection circuit 52 is a circuit that detects the peak of the current Ipmp (hereinafter, also referred to as "peak current") flowing from the transistor T1 to the boost circuit 53. The peak current is an excessive current that flows instantaneously (a current that has a peak value when converted into an average value per unit time (for example, 1 μs)). The peak current detection circuit 52 is connected to the nodes N1 to N4. The peak current detection circuit 52 detects the peak of the current Ipmp based on the voltage Vpref supplied from the reference voltage generation circuit 51 via the node N1 and the voltage Vpsup of the node N2. The peak current detection circuit 52 transmits a signal FLGP1 as a detection result of the peak current to the AND circuit ANDP via the node N3. The signal FLGP1 is a signal that indicates whether the boost circuit 53 performs boosting or not based on the detection result of the peak current. The signal FLGP1 is generated by the peak current detection circuit 52. In this specification, not only the result of whether or not a peak current has been detected, but also the signal FLGP1 transmitted from peak current detection circuit 52 is referred to as the "detection result."

[0056] Furthermore, a signal PCK_EN is input from a node N4 to the peak current detection circuit 52. The signal PCK_EN is a signal that controls detection of a peak current. The signal PCK_EN is generated, for example, by the sequencer 13. The sequencer 13 transmits the generated signal PCK_EN to the voltage generation circuit 14 (peak current detection circuit 52).

[0057] For example, when detecting a peak current, the sequencer 13 generates a signal PCK_EN of “H” level. The peak current detection circuit 52 detects a peak current (hereinafter, also referred to as “peak current detection operation”) based on the signal PCK_EN of “H” level. When the peak of the current Ipmp is detected, the peak current detection circuit 52 transmits a signal FLGP1 of “L” level to the logical product circuit ANDP. In this case, the signal FLGP1 of “L” level means that the boost circuit 53 stops boosting. When the peak of the current Ipmp is not detected, the peak current detection circuit 52 transmits a signal FLGP1 of “H” level to the logical product circuit ANDP. In this case, the signal FLGP1 of “H” level means that the boost circuit 53 performs boosting. On the other hand, when the detection of the peak current is not performed, the sequencer 13 generates a signal PCK_EN of “L” level. The peak current detection circuit 52 does not perform the detection of the peak current based on the signal PCK_EN of “L” level. The peak current detection circuit 52 will be described in detail later.

[0058] The logical product circuit ANDP has a first terminal, a second terminal, and a third terminal.

[0059] A first terminal of the AND circuit ANDP receives the detection result (signal FLGP1) from the peak current detection circuit 52 via a node N3.

[0060] A signal FLGP2 is input to a second terminal of the AND circuit ANDP. The signal FLGP2 is a signal that indicates whether or not the boost circuit 53 performs boosting based on the voltage Vpout output from the boost circuit 53. The signal FLGP2 is generated, for example, by a voltage level detection circuit (not shown) based on the voltage Vpout. The voltage level detection circuit transmits the generated signal FLGP2 to the voltage generation circuit 14 (logical AND circuit ANDP).

[0061] For example, the voltage level detection circuit includes a resistor ladder and a comparator. The resistor ladder is composed of a variable resistor whose resistance value can be adjusted by a binary signal supplied from the sequencer 13. This allows the voltage level detection circuit to adjust the detection level by the binary signal. The voltage Vpout is divided by the resistor ladder. The comparator includes a non-inverting input terminal, an inverting input terminal, and an output terminal. A target voltage is applied to the non-inverting input terminal of the comparator. The target voltage is, for example, a voltage VREAD applied to the unselected word lines WL in a read operation, a voltage VPASS applied to the unselected word lines WL in a write operation, a voltage VPGM applied to the selected word line WL in a write operation, or the like. A voltage divided by the resistor ladder (hereinafter, referred to as "voltage Vpout'") is applied to the inverting input terminal of the comparator. The comparator compares the voltage Vpout' with the target voltage and outputs the comparison result as a signal FLGP2 from an output terminal. When the voltage Vpout' is equal to or lower than the target voltage, the comparator outputs a signal FLGP2 of "H" level. On the other hand, when the voltage Vpout' exceeds the target voltage, the comparator outputs a signal FLGP2 of "L" level. The output terminal of the comparator is connected to the second terminal of the AND circuit ANDP. Two inverters may be connected in series between the output terminal of the comparator and the second terminal of the AND circuit ANDP.

[0062] When the voltage Vpout' exceeds the target voltage, the voltage level detection circuit determines that the boost should be stopped, and generates a signal FLGP2 at an "L" level. In this case, the signal FLGP2 at an "L" level means that the boost circuit 53 is stopping the boost. On the other hand, when the voltage Vpout' is equal to or lower than the target voltage, the voltage level detection circuit determines that the boost should not be stopped, and generates a signal FLGP2 at an "H" level. In this case, the signal FLGP2 at an "H" level means that the boost circuit 53 is executing the boost.

[0063] The above-mentioned target voltage value is controlled by a binary signal supplied from the sequencer 13. Basically, the target voltage value is output from the sequencer 13 at the required timing as the value required by the memory cell MC, such as the voltage VREAD, the voltage VPASS, and the voltage VPGM, but in some cases, the target voltage may be counted up at a certain speed toward the target voltage value in time for the required timing (so-called ramp rate control). This type of control is referred to as "first control." The reason for controlling the ramp rate speed in this way is to control the bias applied to the memory cell MC within a certain range, regardless of the variation, inherent difference, and circuit method / configuration of the charge pump described later, or to suppress the peak current by saving the operation of the charge pump.

[0064] At a certain ramp rate, the current Ipmp that the charge pump generates depends on the output load capacitance of the charge pump. Controlling the ramp rate is effective in suppressing the peak current, but because the peak current fluctuates (increases and decreases) in a complex manner in response to the voltage state inside the memory cell MC, such as the memory hole, in the output load capacitance formed by the memory cell MC, it is not possible to guarantee the absolute value of the upper limit of the peak current.

[0065] The AND circuit ANDP performs a logical AND operation on the signals FLGP1 and FLGP2, and generates a signal FLGP3 as a result of the operation. The signal FLGP3 is a signal indicating whether or not the boost circuit 53 performs boosting. More specifically, when both the signals FLGP1 and FLGP2 are at the “H” level, the AND circuit ANDP generates a signal FLGP3 at the “H” level. In this case, the signal FLGP3 at the “H” level means that the boost circuit 53 performs boosting. On the other hand, when at least one of the signals FLGP1 and FLGP2 is at the “L” level, the AND circuit ANDP generates a signal FLGP3 at the “L” level. In this case, the signal FLGP3 at the “L” level means that the boost circuit 53 stops boosting. The third end of the AND circuit ANDP outputs the operation result (signal FLGP3) to the boost circuit 53 via the node N5.

[0066] The boost circuit 53 is a circuit that boosts the voltage Vpsup of the node N2 and outputs the boosted voltage Vpout. The boost circuit 53 is connected to the nodes N2 and N5. A signal FLGP3 is input to the boost circuit 53 from the logical product circuit ANDP via the node N5. The boost circuit 53 executes or stops boosting based on the signal FLGP3.

[0067] For example, when the signal FLGP3 is at the “H” level, the boost circuit 53 performs boosting. The boosted voltage Vpout is a voltage applied to various wirings such as the word line WL and the source line SL in operations such as a write operation, a read operation, and an erase operation. The boosted voltage Vpout is output from the boost circuit 53, and is further output from the voltage generating circuit 14, and then supplied to the memory cell MC via the row decoder module 15. That is, the semiconductor memory device 3 is configured to supply the voltage Vpout to the memory cell MC. On the other hand, when the signal FLGP3 is at the “L” level, the boost circuit 53 stops (does not perform) boosting.

[0068] The signal FLGP3 is a result of a logical AND operation of the signals FLGP1 and FLGP2. That is, the signal FLGP3 is a signal based on the signals FLGP1 and FLGP2. Therefore, the boost circuit 53 stops boosting based on the detection result (signal FLGP1) by the peak current detection circuit 52. Specifically, when the peak current detection circuit 52 detects the peak of the current Ipmp, the boost circuit 53 stops boosting. At this time, the detection result indicates that the peak current detection circuit 52 has detected the peak of the current Ipmp. Furthermore, the boosting by the boost circuit 53 is stopped based on the signal FLGP2. The details of the boost circuit 53 will be described later.

[0069] 1.1.6 Configuration of the reference voltage generation circuit The reference voltage generating circuit 51 includes, for example, an n-channel MOS transistor T11, resistor elements R11 and R12, and an operational amplifier AMP1.

[0070] The gate of the transistor T11 is connected to the node N1. The power supply voltage VCC is applied to a first terminal of the transistor T11. The second terminal of the transistor T11 is connected to the node N11.

[0071] One end of the resistor element R11 is connected to a node N11. The other end of the resistor element R11 is connected to a node N12. One end of the resistor element R12 is connected to the node N12. The other end of the resistor element R12 is grounded. That is, the voltage VN12 of the node N12 is a voltage obtained by dividing the voltage VN11 of the node N11 based on the ratio of the resistance values ​​of the resistor elements R11 and R12.

[0072] The operational amplifier AMP1 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the operational amplifier AMP1 is a non-inverting input terminal. The second input terminal of the operational amplifier AMP1 is an inverting input terminal. A reference voltage Vref1 is applied to the first input terminal of the operational amplifier AMP1. The second input terminal of the operational amplifier AMP1 is connected to a node N12. The output terminal of the operational amplifier AMP1 is connected to a node N1. A voltage VCCA is also supplied to the operational amplifier AMP1. The operational amplifier AMP1 generates a voltage Vpref based on a comparison result between the voltage Vref1 applied to the first input terminal and the voltage VN12 of the node N12 applied to the second input terminal. The operational amplifier AMP1 generates a voltage Vpref such that the voltages Vref1 and VN12 are equal. The operational amplifier AMP1 supplies the generated voltage Vpref to the gate of the transistor T11, the gate of the transistor T1, and the peak current detection circuit 52 via the node N1.

[0073] The reference voltage generation circuit 51 has a source follower in transistor T11, and is a circuit that generates a voltage Vpref which is higher than the voltage VN11 at node N11 by the threshold voltage Vth11 of transistor T11. By configuring the ratio of the gate width W of transistor T1 and the gate width W11 of transistor T11 to be the same as the ratio of the expected current consumption Ipmp of the boost circuit 53 and the current I11 flowing through transistor T11, the voltage Vpsup supplied to the boost circuit 53 can be set to the same voltage level as the voltage VN11.

[0074] 1.1.7 Configuration of Peak Current Detection Circuit The peak current detection circuit 52 includes, for example, n-channel MOS transistors T21 to T25, an operational amplifier AMP2, a low-pass filter LPF1, a current source 61, and inverters INV1 and INV2.

[0075] Transistor T21 is constituted by, for example, an n-channel MOS transistor having a gate width w (w < W). That is, transistor T21 is smaller in size than transistor T1. The gate of transistor T21 is connected to node N1. That is, voltage Vpref is applied to the gate of transistor T21. The power supply voltage VCC is applied to the first terminal of transistor T21. The second terminal of transistor T21 is connected to node N21. A voltage clamped at voltage Vpref by transistor T21 is supplied to node N21. Due to the voltage drop caused by the influence of the threshold voltage Vth21 of transistor T21, the voltage supplied to node N21, that is, the voltage at node N21, becomes a voltage smaller than the voltage VCC.

[0076] A voltage VCC is applied to the first terminals of the transistors T1 and T21. The second terminal of the transistor T1 serves as one input of the operational amplifier AMP2, and the second terminal of the transistor T21 serves as the other input of the operational amplifier AMP2 to which feedback is applied, and the second terminal of the transistor T1 and the second terminal of the transistor T21 are in a virtual ground state. Therefore, the second terminal of the transistor T1 and the second terminal of the transistor T21 are at the same potential. A voltage Vpref is applied to the gates of the transistors T1 and T21.

[0077] In this way, since the transistors T1 and T21 are in a current mirror relationship, the ratio of the currents flowing through the transistors T1 and T21 is the ratio of the sizes of the transistors T1 and T21, specifically, W:w. Therefore, the current flowing from the transistor T21 to the node N21 is Ipmp×(w / W). For example, when W=10000 (μm) and w=10 (μm), the current is Ipmp / 1000. Since the current is smaller than the current Ipmp, the power consumption of the peak current detection circuit 52 can be reduced. Hereinafter, the voltage of the node N21 is referred to as "voltage Vpmrr". The current flowing from the transistor T21 to the node N21 due to the supply of the voltage Vpmrr is referred to as "current Ipmrr".

[0078] The peak current detection circuit 52 has a source follower in the transistor T21. Since the current Ipmrr is expected to be smaller than the current Ipmp (for example, several μA), the gate width w of the transistor T21 is designed to be w=W×(Ipmrr / Ipmp).

[0079] The peak current detection circuit 52 includes a line CN2 that supplies a voltage VCC to the transistor T21. The voltage VCC is supplied to one end of the line CN2. The other end of the line CN2 is connected to a first end of the transistor T21.

[0080] The operational amplifier AMP2 has a first input terminal, a second input terminal, a control terminal, and an output terminal. The first input terminal of the operational amplifier AMP2 is an inverting input terminal. The second input terminal of the operational amplifier AMP2 is a non-inverting input terminal. The first input terminal of the operational amplifier AMP2 is connected to a node N2. The second input terminal of the operational amplifier AMP2 is connected to a node N21. A signal PCK_EN is input to the control terminal of the operational amplifier AMP2 via a node N4. The output terminal of the operational amplifier AMP2 is connected to a node N22.

[0081] When the signal PCK_EN is at the "H" level, the operational amplifier AMP2 operates based on the "H" level signal PCK_EN. The operational amplifier AMP2 generates a voltage Vctrl based on a comparison result between the voltage Vpsup at the node N2 applied to the first input terminal and the voltage Vpmrr at the node N21 applied to the second input terminal. The operational amplifier AMP2 generates a voltage Vctrl such that the voltages Vpsup and Vpmrr are equal. The operational amplifier AMP2 supplies the generated voltage Vctrl from the output terminal to the low-pass filter LPF1 via the node N22.

[0082] On the other hand, when the signal PCK_EN is at the "L" level, the operational amplifier AMP2 does not operate based on the signal PCK_EN at the "L" level.

[0083] One end of the low-pass filter LPF1 is connected to a node N22. That is, one end of the low-pass filter LPF1 is connected to an output terminal of the operational amplifier AMP2 via the node N22. The other end of the low-pass filter LPF1 is connected to a node N23. That is, the other end of the low-pass filter LPF1 is connected to the gate of the transistor T22 via the node N23. The low-pass filter LPF1 supplies a voltage Vctrl', which is obtained by removing noise from the voltage Vctrl supplied from the operational amplifier AMP2, to the gate of the transistor T22 via the node N23. The low-pass filter LPF1 includes a resistive element R21 and a capacitive element C21.

[0084] One end of the resistive element R21 is connected to the node N22. The other end of the resistive element R21 is connected to the node N23. A first electrode of the capacitive element C21 is connected to the node N23. A second electrode of the capacitive element C21 is grounded.

[0085] The gate of the transistor T22 is connected to the node N23. That is, a voltage Vctrl' based on the voltage Vctrl is applied to the gate of the transistor T22. A first end of the transistor T22 is connected to the node N21. A second end of the transistor T22 is connected to the node N24. When the transistor T22 is turned on, a current Ipmrr (=Ipmp×(w / W)) flows from the transistor T22 to the node N24. The voltage Vctrl output from the operational amplifier AMP2, or more precisely, the voltage Vctrl' controls the current Ipmrr flowing through the transistor T22.

[0086] A signal PCK_EN is input to the gate of the transistor T23. A first terminal of the transistor T23 is connected to the node N24. A second terminal of the transistor T23 is grounded. When the signal PCK_EN is at an "H" level, the transistor T23 is turned on. On the other hand, when the signal PCK_EN is at an "L" level, the transistor T23 is turned off.

[0087] When the voltage Vpmrr of the node N21 is greater than the voltage Vpsup of the node N2, the voltage Vctrl output from the operational amplifier AMP2 drops. As a result, the voltage Vctrl' also drops, and the current Ipmrr flowing from the transistor T22 to the node N24 decreases. As a result, the voltage Vpmrr of the node N21 drops. Also, when the voltage Vpmrr of the node N21 is less than the voltage Vpsup of the node N2, the voltage Vctrl output from the operational amplifier AMP2 rises. As a result, the voltage Vctrl' also rises, and the current Ipmrr flowing from the transistor T22 to the node N24 increases. As a result, the voltage Vpmrr of the node N21 rises. In this way, the operational amplifier AMP2 is feedback-controlled so that the voltages Vpsup and Vpmrr are equal. As a result, the current Ipmrr becomes a current that reflects the value of the current Ipmp (a current that corresponds to the current Ipmp).

[0088] The current source 61 is a circuit that supplies a reference current Iref. A power supply voltage VCC is applied to one end of the current source 61. The other end of the current source 61 is connected to a node N25. The current source 61 supplies the current Iref to the node N25.

[0089] The transistor T24 is, for example, the same size as the transistor T22. The gate of the transistor T24 is connected to the node N23. The first end of the transistor T24 is connected to the node N25. The second end of the transistor T24 is connected to the node N26. When the transistor T24 is turned on, a current flows from the transistor T24 to the node N26. The transistor T24 is the same size as the transistor T22, and a voltage Vctrl' is applied to the gate of the transistor T24, so that the current flowing from the transistor T24 to the node N26 is a current (mirror current) having the same magnitude as the current Ipmrr. That is, the current flowing from the transistor T24 to the node N26 is a current reflecting the value of the current Ipmp (a current corresponding to the current Ipmp). Hereinafter, the current flowing from the transistor T24 to the node N26 is referred to as "current Ipmrr'".

[0090] A signal PCK_EN is input to the gate of the transistor T25. A first terminal of the transistor T25 is connected to the node N26. A second terminal of the transistor T25 is grounded. When the signal PCK_EN is at an "H" level, the transistor T25 is turned on. On the other hand, when the signal PCK_EN is at an "L" level, the transistor T25 is turned off.

[0091] The input terminal of the inverter INV1 is connected to the node N25, and the output terminal of the inverter INV1 is connected to the node N27.

[0092] When the current Ipmrr' is greater than the current Iref, the voltage VN25 of the node N25 drops (becomes "L" level). When the current Ipmrr' is smaller than the current Iref, the voltage VN25 of the node N25 rises (becomes "H" level). That is, the voltage VN25 of the node N25 becomes a voltage level (H" level / L" level) that reflects the magnitude relationship between the current Ipmrr' and the current Iref. When the voltage VN25 of the node N25 applied to the input terminal of the inverter INV1 is at the "L" level, the inverter INV1 outputs a signal RES of the "H" level generated based on the voltage VN25. On the other hand, when the voltage VN25 of the node N25 applied to the input terminal of the inverter INV1 is at the "H" level, the inverter INV1 outputs a signal RES of the "L" level generated based on the voltage VN25. That is, the signal RES output from the inverter INV1 also has a logic level (H level / L level) that reflects the magnitude relationship between the current Ipmrr' and the current Iref.

[0093] With the above configuration, the peak current detection circuit 52 can compare whether the current Ipmrr' is greater or smaller than the current Iref. As described above, the current Ipmrr' is a current that reflects the value of the current Ipmp. That is, when the current Ipmp is at its peak, the current Ipmrr' is also at its peak. Therefore, the peak current detection circuit 52 can detect the peak of the current Ipmp based on the current Ipmrr', or more accurately, by comparing the current Ipmrr' with the current Iref. When the current Ipmrr' is greater than the current Iref, the peak current detection circuit 52 determines that the peak of the current Ipmp has been detected. On the other hand, when the current Ipmrr' is equal to or less than the current Iref, the peak current detection circuit 52 determines that the peak of the current Ipmp has not been detected.

[0094] The input terminal of the inverter INV2 is connected to the node N27. The output terminal of the inverter INV2 is connected to the node N3. When the signal RES input to the input terminal of the inverter INV2 is at the “H” level, that is, when the peak current detection circuit 52 detects the peak of the current Ipmp, the inverter INV2 outputs the signal FLGP1 at the “L” level generated based on the signal RES. On the other hand, when the signal RES input to the input terminal of the inverter INV2 is at the “L” level, that is, when the peak current detection circuit 52 does not detect the peak of the current Ipmp, the inverter INV1 outputs the signal FLGP1 at the “H” level generated based on the signal RES.

[0095] When the signal PCK_EN is at the "H" level, the operational amplifier AMP2 operates. In addition, the transistors T23 and T25 are turned on. When the voltage Vpref is applied to the gate of the transistor T21, the transistor T21 is turned on. This also turns the transistors T22 and T24 on, and the currents Ipmrr and Ipmrr' flow. As a result, the voltage VN25 at the node N25 has a voltage level based on the magnitude relationship between the currents Ipmrr' and Iref. Therefore, the peak current detection circuit 52 supplies the signal FLGP1, which has the same logical level as the voltage VN25, to the logical product circuit ANDP.

[0096] On the other hand, when the signal PCK_EN is at the "L" level, the operational amplifier AMP2 does not operate. Also, the transistors T23 and T25 are turned off. This causes the transistors T22 and T24 to be turned off. As a result, the voltage VN25 of the node N25 becomes the "H" level. Therefore, the peak current detection circuit 52 supplies the signal FLGP1 at the "H" level to the AND circuit ANDP.

[0097] The peak current detection circuit 52 detects the peak current, for example, during a specific operation that generates a relatively large peak current, in order to prevent the system circuits that operate the chip from being damaged. That is, the signal PCK_EN is set to the "H" level during the specific operation. The specific operation is, for example, a leak test of the word line WL. When the peak current detection circuit 52 detects a peak current, it stops the boosting by the boost circuit 53. Furthermore, the peak current detection circuit 52 does not detect the peak current during operations other than the specific operation (operations that generate a relatively small peak current). That is, the signal PCK_EN is set to the "L" level during operations other than the specific operation.

[0098] The timing to switch the signal PCK_EN is determined by the semiconductor memory device 3, for example, the sequencer 13. In this case, the sequencer 13 determines the switching timing and switches the signal PCK_EN. Note that the timing to switch the signal PCK_EN may also be determined by the memory controller 2. In this case, the memory controller 2 may determine the switching timing and issue a command CMD for controlling the signal PCK_EN to the semiconductor memory device 3, and the sequencer 13 that receives the command CMD may switch the signal PCK_EN.

[0099] 1.1.8 Boost circuit configuration The configuration of the boost circuit 53 will be described with reference to Fig. 6. Fig. 6 is a circuit diagram showing an example of the configuration of the boost circuit 53.

[0100] The boost circuit 53 is configured to, when the voltage Vpsup is input, output a voltage Vpout higher than the voltage Vpsup from the output terminal in various operations.

[0101] The boost circuit 53 includes, for example, charge pumps CP1 to CP4 and switches SW31 to SW39.

[0102] Charge pump CP1 is connected to nodes N31 and N32. Charge pump CP2 is connected to nodes N33 and N34. Charge pump CP3 is connected to nodes N35 and N36. Charge pump CP4 is connected to nodes N37 and N38. Hereinafter, when there is no need to distinguish between charge pumps CP1 to CP4, each of the charge pumps CP1 to CP4 will be simply referred to as charge pump CP.

[0103] Each of the switches SW31 to SW39 includes a first terminal and a second terminal. The first terminal of the switch SW31 is connected to the node N32. The second terminal of the switch SW31 is connected to the node N38. The first terminal of the switch SW32 is connected to the node N32. The second terminal of the switch SW32 is connected to the node N33. The first terminal of the switch SW33 is connected to the node N31. The second terminal of the switch SW33 is connected to the node N33. The first terminal of the switch SW34 is connected to the node N31. The second terminal of the switch SW34 is connected to the node N35. The first terminal of the switch SW35 is connected to the node N31. The second terminal of the switch SW35 is connected to the node N37. The first terminal of the switch SW36 is connected to the node N34. The second terminal of the switch SW36 is connected to the node N38. The first terminal of the switch SW37 is connected to the node N34. The second terminal of the switch SW37 is connected to the node N35. A first terminal of the switch SW38 is connected to the node N36. A second terminal of the switch SW38 is connected to the node N38. A first terminal of the switch SW39 is connected to the node N36. A second terminal of the switch SW39 is connected to the node N37.

[0104] The connections of the switches SW31 to SW39 are controlled, for example, by the sequencer 13. The sequencer 13 controls the connections of the switches SW31 to SW39 in accordance with the voltage to be boosted.

[0105] For example, in an erase operation, when the voltage Vpsup is boosted to a voltage VERA (for example, 20V) to be applied to the source line SL, the sequencer 13 turns on the switches SW32, SW37, and SW39, and turns off the switches SW31, SW33 to SW36, and SW38. As a result, the charge pumps CP1 to CP4 are connected in series. Also, for example, when the voltage Vpsup is boosted to about 3 or 4V, the sequencer 13 turns on the switches SW31, SW33 to SW36, and SW38, and turns off the switches SW32, SW37, and SW39. As a result, the charge pumps CP1 to CP4 are connected in parallel. This type of control is referred to as "second control." The reason for controlling the connection of the charge pumps in this way is to use the charge pumps efficiently (to effectively output the voltage Vout with a smaller current Ipmp).

[0106] Like the ramp rate control, controlling the connection of the charge pump is effective in suppressing the peak current, but it does not guarantee the absolute value of the upper limit of the peak current.

[0107] 1.1.9 Charge pump configuration The configuration of the charge pump CP will be described with reference to Fig. 7. Fig. 7 is a circuit diagram showing an example of the configuration of the charge pump CP.

[0108] The charge pump CP includes, for example, n-channel MOS transistors T31 to T34 and capacitive elements C31 to C33.

[0109] A voltage VIN is applied to a first terminal and a gate of the transistor T31. The voltage VIN is a voltage input to the charge pump CP. A second terminal of the transistor T31 is connected to a node N41.

[0110] A first end and a gate of the transistor T32 are connected to the node N41, and a second end of the transistor T32 is connected to the node N42.

[0111] A first end and a gate of the transistor T33 are connected to the node N42 and a second end of the transistor T33 are connected to the node N43.

[0112] A first terminal and a gate of the transistor T34 are connected to the node N43. A voltage VOUT is output from a second terminal of the transistor T34. The voltage VOUT is a voltage output from the charge pump CP.

[0113] A signal CLK and its inverted signal, signal CLKn, are input to the charge pump CP. The signals CLK and CLKn are generated by, for example, a driver (not shown) included in the charge pump CP.

[0114] A first electrode of the capacitive element C31 is connected to the node N41. A second electrode of the capacitive element C31 is input with a signal CLKn. A first electrode of the capacitive element C32 is connected to the node N42. A second electrode of the capacitive element C32 is input with a signal CLK. A first electrode of the capacitive element C33 is connected to the node N43. A second electrode of the capacitive element C33 is input with a signal CLKn. Hereinafter, when there is no need to distinguish between the capacitive elements C31 to C33, each of the capacitive elements C31 to C33 will be simply referred to as a capacitive element C.

[0115] When the signal CLK goes to "H" level and its inverted signal, the signal CLKn, goes to "L" level, the transistors T31 and T33 are turned on and the transistors T32 and T34 are turned off. As a result, the first terminal of the transistor T31 is connected to the node N41 and the connection between the node N41 and the node N42 is disconnected. In addition, the node N42 is connected to the node N43 and the connection between the node N43 and the second terminal of the transistor T34 is disconnected.

[0116] That is, when signal CLK goes to "H" level and its inverted signal, signal CLKn, goes to "L" level, a voltage (approximately voltage VIN) dropped from voltage VIN due to the influence of threshold voltage Vth is transferred to node N41. A voltage (approximately (VC2+VD)) dropped from the voltage of node N42 (VC2+VD, as described later) due to the influence of threshold voltage Vth is transferred to node N43. VC2 is the voltage across charged capacitance element C32. VD is the difference between the "H" level voltage and the "L" level voltage of signal CLK (or signal CLKn).

[0117] While the signal CLKn is at the "L" level, the capacitance element C31 is charged by the voltage VIN. As a result, the voltage across the capacitance element C31 becomes VC1. Also, while the signal CLKn is at the "L" level, the capacitance element C33 is charged by the voltage (VC2+VD) of the node N42. As a result, the voltage across the capacitance element C33 becomes VC3.

[0118] Furthermore, when signal CLK goes to "H" level, the voltage of node N42 becomes a voltage (VC1+VD) obtained by boosting voltage VC1 across capacitance element C31 by the difference VD between the "H" level and "L" level of signal CLKn. Voltage VC1 is a voltage (approximately voltage VIN) dropped from voltage VIN due to the influence of threshold voltage Vth, and if difference VD is equal to voltage VIN, then the voltage of node N42 becomes approximately 2×VIN.

[0119] While the signal CLK is at the "H" level, the voltage of the node N42 is maintained at approximately 2×VIN.

[0120] Thereafter, when the signal CLK goes to the "L" level and its inverted signal, the signal CLKn, goes to the "H" level, the transistors T31 and T33 are turned off and the transistors T32 and T34 are turned on. This disconnects the first terminal of the transistor T31 from the node N41 and connects the node N41 to the node N42. In addition, the connection between the node N42 and the node N43 is disconnected and the node N43 is connected to the second terminal of the transistor T34.

[0121] In other words, when signal CLK goes to "L" level and its inverted signal, signal CLKn, goes to "H" level, the voltage at node N41 becomes a voltage (VC1+VD) obtained by boosting the voltage VC1 across capacitive element C31 by the difference VD between the "H" level and "L" level of signal CLKn. The voltage at node N41 becomes approximately 2×VIN.

[0122] Furthermore, when the signal CLKn goes to the “H” level, the voltage of the node N43 becomes a voltage (VC3+VD) obtained by boosting the voltage VC3 across the capacitance element C33 by the difference VD between the “H” level and the “L” level of the signal CLKn. The voltage of the node N43 becomes approximately 3×VIN.

[0123] While the signal CLKn is at the "H" level, the voltage of the node N43 is maintained at approximately 3×VIN.

[0124] Furthermore, when the signal CLKn goes to the "H" level, the voltage of the node N43 (approximately 3×VIN) is transferred as the voltage VOUT.

[0125] When the signal CLK goes to the "L" level, the voltage of the node N41 (approximately 2×VIN) is transferred to the node N42.

[0126] While the signal CLK is at the "L" level, the capacitance element C32 is charged by a voltage of approximately 2×VIN, so that the voltage across the capacitance element C32 becomes VC2.

[0127] As described above, when the signal CLK goes to the "H" level, the voltage VIN is transferred to the node N41, and the voltage of the node N42 (approximately 2×VIN) is transferred to the node N43. The voltage of the node N42 is boosted by VD(VIN) to approximately 2×VIN. After that, when the signal CLK goes to the "L" level, the voltage of the node N41 is boosted by VD(VIN) to approximately 2×VIN. The voltage of the node N43 is boosted by VD(VIN) to approximately 3×VIN. The voltage of the node N41 (approximately 2×VIN) is transferred to the node N42. Then, the voltage of the node N43 (approximately 3×VIN) is output as the voltage VOUT.

[0128] In the example shown in FIG. 7, the charge pump CP includes three capacitive elements C31 to C33, but the number of capacitive elements C included in the charge pump CP is not limited to this. The number of capacitive elements C may be two, four, five or more, and may be changed according to the target value of the voltage to be boosted, etc. In this case, for example, a signal CLKn is input to the second electrode of the capacitive element C(2j-1) (j is a natural number). For example, a signal CLK is input to the second electrode of the capacitive element C(2j). The number of transistors is appropriately changed according to the number of capacitive elements C.

[0129] The configuration of the charge pumps CP1 to CP4 is not limited to the example described with reference to Fig. 7. The charge pump CP may be configured with, for example, p-channel MOS transistors. The charge pump CP may be a Vt cancellation type charge pump configured with transistors whose first terminals and gates are not at the same potential, instead of diode-connected transistors.

[0130] 1.2 Effects of this embodiment According to this embodiment, it is possible to suppress the peak current generated in the boost circuit (the peak current flowing through the boost circuit). This effect will be described below.

[0131] In a semiconductor memory device, for example, when a voltage VERA is applied to a source line SL during an erase operation, and when a voltage VREAD is applied to an unselected word line WL during a read operation, a relatively large peak current may be generated in the boost circuit.

[0132] The board or system on which the semiconductor memory device is mounted is designed to withstand the peak current. For example, the board or system is designed so that the peak current does not cause an excessive rise in temperature and damage the board or system. The board or system is also designed so that a voltage that can withstand the peak current can be supplied. In this way, when designing in consideration of temperature and the amount of voltage supply, there is a possibility that the cost and reliability will be affected.

[0133] For this reason, in the semiconductor memory device, measures are taken to suppress the peak current generated in the boost circuit by the above-mentioned first control and second control.

[0134] However, for example, when the load connected to the boost circuit suddenly changes, the peak current generated in the boost circuit may not be sufficiently suppressed by only the first and second controls described above. The sudden change in the load may occur, for example, when the select gate line SGD is turned on during various operations.

[0135] For this reason, for example, in the first control, it is also possible to further control the rate of increase of the voltage output from the boost circuit in response to the fluctuation of the load. However, in this case, the first control may become complicated.

[0136] In contrast, the voltage generating circuit 14 included in the semiconductor memory device according to this embodiment includes a transistor T1, a peak current detection circuit 52, and a boost circuit 53. A reference voltage Vpref is applied to the gate of the transistor T1. A power supply voltage VCC is applied to a first end of the transistor T1. A second end of the transistor T1 is connected to a node N2. The peak current detection circuit 52 is connected to the node N2 and detects a peak of a current Ipmp flowing from the transistor T1 to the boost circuit 53. The boost circuit 53 is connected to the node N2 and boosts the voltage Vpsup of the node N2 and outputs the boosted voltage Vpout. The boost circuit 53 stops boosting based on the detection result FLGP1 by the peak current detection circuit 52. In other words, when the peak current detection circuit 52 detects a peak of the current Ipmp, it stops boosting by the boost circuit 53. This makes it possible to suppress the peak current generated in the boost circuit 53.

[0137] FIG. 8 is a diagram showing an example of the waveform of the current flowing through the boost circuit 53 in the voltage generating circuit 14 according to this embodiment, and an example of the waveform of the current flowing through the boost circuit 53 in the voltage generating circuit 14 according to the comparative example. The vertical axis represents current. The horizontal axis represents time. Note that FIG. 8 shows the waveform of the current Ipmp_ave obtained by converting the current Ipmp flowing through the boost circuit 53 into an average value per unit time. The waveform of the current Ipmp_ave of the voltage generating circuit 14 according to this embodiment is shown by a solid line. The waveform of the current Ipmp_ave of the voltage generating circuit 14 according to the comparative example is shown by a dashed line.

[0138] The voltage generating circuit 14 according to the comparative example does not include the peak current detection circuit 52 and the logical product circuit ANDP from the voltage generating circuit 14 shown in Fig. 5. Furthermore, a signal FLGP2 is input to a boost circuit 53 in the voltage generating circuit 14 according to the comparative example via a node N5.

[0139] In the voltage generating circuit 14 according to this embodiment, the peak current detection circuit 52 detects the peak of the current Ipmp. When the peak current detection circuit 52 detects the peak of the current Ipmp, it stops the boosting by the boost circuit 53.

[0140] Therefore, the current Ipmp of the boost circuit 53 in the voltage generating circuit 14 according to the present embodiment is suppressed to a current smaller than the current Ipmp of the boost circuit 53 in the voltage generating circuit 14 according to the comparative example in which the peak current detection circuit 52 is not provided. Also, the current Ipmrr (Ipmrr') of the peak current detection circuit 52 in the voltage generating circuit 14 according to the present embodiment is suppressed to a current equal to or smaller than the reference current Iref. Therefore, as shown in FIG. 8, in the portion surrounded by the dashed line, the peak of the current Ipmp_ave of the boost circuit 53 in the voltage generating circuit 14 according to the present embodiment is suppressed to a value smaller than the peak of the current Ipmp_ave of the boost circuit 53 in the voltage generating circuit 14 according to the comparative example. In this way, according to the present embodiment, the peak current flowing through the boost circuit 53 can be suppressed.

[0141] 1.3 First variant A memory system including a semiconductor memory device according to a first modification of the first embodiment will be described. The semiconductor memory device according to the first modification of the first embodiment differs from the first embodiment shown in FIG. 5 in the configuration of a peak current detection circuit 52 in a voltage generation circuit 14. FIG. 9 is a circuit diagram showing an example of the configuration of the voltage generation circuit 14. The following description will focus on the differences from the first embodiment.

[0142] 1.3.1 Peak current detection circuit configuration 9, one end of the low-pass filter LPF1 is connected to a node N2. The other end of the low-pass filter LPF1 is connected to a first input terminal of an operational amplifier AMP2. The low-pass filter LPF1 removes noise from the voltage Vpsup of the node N2 to obtain a voltage Vpsup', which is supplied to the first input terminal of the operational amplifier AMP2 via a node N51.

[0143] One end of the resistive element R21 is connected to the node N2. The other end of the resistive element R21 is connected to the node N51. A first electrode of the capacitive element C21 is connected to the node N51. A second electrode of the capacitive element C21 is grounded.

[0144] The output terminal of the operational amplifier AMP2 is connected to the node N23. The operational amplifier AMP2 outputs the generated voltage Vctrl from the output terminal to the gate of the transistor T22 via the node N23.

[0145] 1.3.2 Effects of this Modification According to this modification, the same effects as those of the first embodiment are achieved.

[0146] 1.4 Second variant A memory system including a semiconductor memory device according to a second modification of the first embodiment will be described. The semiconductor memory device according to the second modification of the first embodiment differs from the first modification of the first embodiment shown in FIG. 9 in the configuration of a peak current detection circuit 52 in a voltage generation circuit 14. FIG. 10 is a circuit diagram showing an example of the configuration of the voltage generation circuit 14. The following description will focus on the differences from the first modification of the first embodiment.

[0147] 1.4.1 Peak current detection circuit configuration As shown in FIG. 10, the peak current detection circuit 52 further includes a low-pass filter LPF2.

[0148] One end of the low-pass filter LPF2 is connected to a node N21. The other end of the low-pass filter LPF2 is connected to a second input terminal of the operational amplifier AMP2. The low-pass filter LPF2 supplies a voltage Vpmrr', which is obtained by removing noise from the voltage Vpmrr of the node N21, to the second input terminal of the operational amplifier AMP2 via a node N52. The low-pass filter LPF2 includes a resistive element R22 and a capacitive element C22.

[0149] One end of the resistive element R22 is connected to the node N21. The other end of the resistive element R22 is connected to the node N52. A first electrode of the capacitive element C22 is connected to the node N52. A second electrode of the capacitive element C22 is grounded.

[0150] 1.4.2 Effects of this modification According to this modification, the same effects as those of the first embodiment are achieved.

[0151] 2. Second embodiment A memory system including a semiconductor memory device according to a second embodiment will be described.

[0152] 2.1 Relationship between voltage VCC and voltages Vpref and Vpsup Before describing the semiconductor memory device according to the second embodiment, the relationship between the power supply voltage VCC, the reference voltage Vpref, and the voltage Vpsup supplied to the boost circuit 53 in the semiconductor memory device according to the first embodiment will be described with reference to FIG. 11 and FIG. 5 shown in the first embodiment. FIG. 11 is a diagram for explaining the relationship between the power supply voltage VCC, the reference voltage Vpref, and the voltage Vpsup in the semiconductor memory device according to the first embodiment. The vertical axis represents the reference voltage Vpref and the voltage Vpsup. The horizontal axis represents the power supply voltage VCC.

[0153] The voltage VCC can take a value in the range of, for example, 2.3 V to 3.6 V. The voltage VCCmin is the lower limit of the voltage VCC. When the voltage VCC takes a value in the range of 2.3 V to 3.6 V, the voltage VCCmin is 2.3 V.

[0154] The voltage vpsup_min is the value of the voltage vpsup when the voltage is VCCmin.

[0155] The voltage Vpsup_target is a preset target value of the voltage Vpsup. The voltage Vpsup_target is set to an upper limit value at which the voltage boost circuit 53 does not violate its withstand voltage. As described above, this is to prevent the voltage boosted by the boost circuit 53 from becoming too high, which may damage the boost circuit 53 itself or other circuits. The voltage Vpsup_target is set to a value relatively close to the voltage VCCmin. This is because, when the voltage Vpsup_target is set as high as possible, the current efficiency of the current Ipmp flowing through the boost circuit 53 is improved, and power consumption can be reduced.

[0156] Hereinafter, the region where the voltage VCC is equal to or higher than the voltage Vpsup_target is referred to as a “first voltage region A1.” The region where the voltage VCC is equal to or higher than the voltage VCCmin and lower than the voltage Vpsup_target is referred to as a “second voltage region A2.”

[0157] When the voltage VCC is in the first voltage region A1 (the voltage VCC is sufficiently greater than the voltage VCCmin), the reference voltage Vpref becomes a voltage (constant value) that is higher than the voltage VN11 of the node N11 by the threshold voltage Vth11 of the transistor T11 due to the source follower as described above. The voltage Vpsup is controlled to the same voltage level as the voltage VN11 and becomes a preset voltage Vpsup_target.

[0158] That is, when the voltage VCC is a value in the first voltage region A1, the voltage Vpsup is regulated by the source follower. The voltage Vpmrr at the node N21 is also regulated by the source follower. Therefore, the voltage Vpsup is not affected by the resistance on the first end side of the transistor T1 (the parasitic resistance of the wiring CN1 and the on-resistance of the transistor T1). Similarly, the voltage Vpmrr is not affected by the resistance on the first end side of the transistor T21 (the parasitic resistance of the wiring CN2 and the on-resistance of the transistor T21). Therefore, when the voltage VCC is a value in the first voltage region A1, the peak current detection circuit 52 can detect the peak current regardless of the parasitic resistance of the wirings CN1 and CN2 and the on-resistance of the transistors T1 and T21.

[0159] On the other hand, when the voltage VCC is in the second voltage region A2 (the voltage VCC is relatively close to the voltage VCCmin), the voltage VN11 at the node N11 drops. When the voltage VN11 drops, the reference voltage Vpref rises as a result of the feedback and becomes the maximum voltage VCCA (for example, 3.8 V) that the amplifier AMP1 can supply. This causes the voltage Vpsup to drop and become lower than the voltage Vpsup_target.

[0160] That is, when the voltage VCC is a value in the second voltage region A2, the voltage Vpsup is not regulated and has a value based on the resistance of the first end side of the transistor T1 (the parasitic resistance of the wiring CN1 and the on-resistance of the transistor T1). Similarly, the voltage Vpmrr is not regulated and has a value based on the resistance of the first end side of the transistor T21 (the parasitic resistance of the wiring CN2 and the on-resistance of the transistor T21). This is because the transistors T1 and T21 simply operate as switches. When the reference voltage Vpref is relatively large (for example, the voltage VCCA), the on-resistance of the transistors T1 and T21 approaches 0. However, the parasitic resistance of the wirings CN1 and CN2 cannot be ignored. For this reason, when the voltage VCC is a value in the second voltage region A2, the current Ipmrr (Ipmrr') does not become Ipmp×(w / W) due to the influence of the parasitic resistance of the wirings CN1 and CN2, and it may be difficult for the peak current detection circuit 52 to detect the peak current.

[0161] The semiconductor memory device according to the second embodiment has a configuration capable of detecting a peak current not only when the voltage VCC is a value in the first voltage region A1, but also when the voltage VCC is a value in the second voltage region A2. The semiconductor memory device according to the second embodiment differs from the first embodiment shown in FIG. 5 in the configuration of the voltage generating circuit 14. Hereinafter, the voltage generating circuit 14 in the semiconductor memory device according to the second embodiment will be referred to as a "voltage generating circuit 14A". The peak current detection circuit 52 in the voltage generating circuit 14A will be referred to as a "peak current detection circuit 52A". The current source 61 in the peak current detection circuit 52A will be referred to as a "current source 61A". FIG. 12 is a circuit diagram showing an example of the configuration of the voltage generating circuit 14A. In the following description, the differences from the first embodiment will be mainly described.

[0162] 2.2 Configuration of the voltage generation circuit The voltage generating circuit 14A includes a line CN1 that supplies a voltage VCC to the transistor T1, similarly to the first embodiment. Hereinafter, the parasitic resistance of the line CN1 is represented as R1.

[0163] A voltage VCC is supplied to one end of the line CN1, and the other end of the line CN1 is connected to a first end of the transistor T1.

[0164] The wiring CN1 from the power supply pad of the power supply voltage VCC to the first terminal of the transistor T1 can be a relatively small wiring, so that the parasitic resistance R1 can be made relatively small.

[0165] 2.3 Peak current detection circuit configuration The peak current detection circuit 52A includes the line CN2 that supplies the voltage VCC to the transistor T21, similarly to the first embodiment. Hereinafter, the parasitic resistance of the line CN2 is represented as r1.

[0166] The current source 61A is a variable current source.

[0167] The peak current detection circuit 52A further includes a resistive element r2 and calibration circuits 71 and 72 in addition to the configuration of FIG.

[0168] The resistor element r2 is a variable resistor element.

[0169] A voltage VCC is supplied to one end of the wiring CN2. The other end of the wiring CN2 is connected to one end of a resistor element r2. The other end of the resistor element r2 is connected to a first end of a transistor T21.

[0170] The wiring CN2 from the power supply pad of the power supply voltage VCC to the first end of the transistor T21 may be larger than the wiring CN1, so a resistive element r2 is provided to make the resistance on the first end side of the transistor T21 adjustable.

[0171] The calibration circuit 71 is a circuit that calibrates the current value of the current source 61A in a state where the voltage VCC is set to a voltage value equal to or higher than the voltage Vpsup_target (the value in the first voltage region A1 shown in FIG. 11). As described above, when the voltage VCC is a value in the first voltage region A1, the voltage Vpsup is not affected by the resistance on the first end side of the transistor T1. The voltage Vpmrr is not affected by the resistance on the first end side of the transistor T21. For this reason, the calibration circuit 71 calibrates the current value of the current source 61A to a current Ipmp×(size (gate width w) of the transistor T21 / size (gate width W) of the transistor T1) in a state where the voltage VCC is set to a value in the first voltage region A1, for example.

[0172] The calibration circuit 72 is a circuit that calibrates the resistance value of the resistive element r2 in a state where the voltage VCC is set to a voltage value (a value in the second voltage region A2 shown in FIG. 11) less than the voltage Vpsup_target. As described above, when the voltage VCC is a value in the second voltage region A2, the voltage Vpsup becomes a voltage based on the resistance on the first end side of the transistor T1. The voltage Vpmrr becomes a voltage based on the resistance on the first end side of the transistor T21. For this reason, the calibration circuit 72 calibrates the resistance value of the resistive element r2 such that, for example, in a state where the voltage VCC is set to a value in the second voltage region A2, the ratio of the parasitic resistance R1 of the wiring CN1 to the combined resistance of the parasitic resistance r1 of the wiring CN2 and the resistive element r2 becomes the inverse ratio of the ratio of the size W of the transistor T1 to the size w of the transistor T21.

[0173] When the logic level of the signal FLGP1 is inverted, the current Ipmrr (current Ipmrr') becomes equal to the current Iref. That is, the resistance value of the resistor element r2 when the logic level of the signal FLGP1 is inverted is a resistance value at which the current Ipmrr (current Ipmrr') and the current Iref become equal when the voltage VCC is at the value of the second voltage region A2. Therefore, when the logic level of the signal FLGP1 is inverted, the calibration circuit 72 can determine that the ratio of the parasitic resistance R1 to the combined resistance of the parasitic resistance r1 and the resistor element r2 becomes the inverse ratio of the size W of the transistor T1 to the size w of the transistor T21. Therefore, the calibration circuit 72 monitors the signal FLGP1 in a state where the voltage VCC is set to the value of the second voltage region A2, and calibrates the resistance value of the resistor element r2 to the resistance value of the resistor element r2 when the logic level of the signal FLGP1 is inverted.

[0174] 2.4 Operation of the voltage generation circuit The operation of the voltage generating circuit 14A according to this embodiment further includes a calibration operation and a setting operation in addition to the peak current detection operation described in the first embodiment.

[0175] The calibration operation is an operation for calibrating the current value of the current source 61A and the resistance value of the resistive element r2. The calibration operation is performed, for example, during testing after manufacture and before shipment. The setting operation is an operation for setting the current value of the current source 61A and the resistance value of the resistive element r2 to values ​​calibrated by the calibration operation. The setting operation is performed, for example, when the power is turned on after shipment.

[0176] (Calibration operation) The calibration operation will be described with reference to Fig. 13. Fig. 13 is a flowchart showing an example of the calibration operation of the voltage generating circuit 14A.

[0177] When the pre-shipment test is started, the voltage generating circuit 14A supplies an arbitrary current Ipmp (e.g., 10 mA) to the boost circuit 53 with the voltage VCC set to a voltage value equal to or higher than the voltage Vpsup_target (the value in the first voltage region A1 shown in FIG. 11) (S101).

[0178] Next, the calibration circuit 71 changes the current value of the current source 61A. Then, the calibration circuit 71 calibrates the current value of the current source 61A to a current Ipmp×(size w of the transistor T21 / size W of the transistor T1) (S102). Hereinafter, the calibrated current value (digital value) of the current source 61A is represented as “Ica”.

[0179] Next, the calibration circuit 71 stores the current value Ica of the current source 61A obtained in step S102 in the ROM area of ​​the memory cell array 10 (S103).

[0180] Next, the voltage generating circuit 14A sets the current value of the current source 61A to the current value Ica stored in step S103 (S104), whereby the current source 61A supplies the current Ica as the current Iref.

[0181] Next, the voltage generating circuit 14A supplies the boost circuit 53 with a current Ipmp of the same magnitude as in step S101 in a state in which the voltage VCC is set to a voltage value less than the voltage Vpsup_target (the value in the second voltage region A2 shown in FIG. 11) (S105).

[0182] Next, the calibration circuit 72 changes the resistance value of the resistive element r2 and monitors the signal FLGP1. Then, the calibration circuit 72 calibrates the resistance value of the resistive element r2 to the resistance value of the resistive element r2 when the logic level of the signal FLGP1 is inverted (S106). Hereinafter, the calibrated resistance value (digital value) of the resistive element r2 is represented as "rca".

[0183] Next, the calibration circuit 72 stores the resistance value rca of the resistive element r2 obtained in step S106 in the ROM area of ​​the memory cell array 10 (S107).

[0184] It should be noted that steps S101 to S103 may be omitted. In this case, the current value Ica of the current source 61A may be stored in advance in the ROM area of ​​the memory cell array 10, and then steps S104 to S107 may be performed.

[0185] (Settings) The setting operation will be described with reference to Fig. 14. Fig. 14 is a flow chart showing an example of the setting operation of the voltage generating circuit 14A.

[0186] When the semiconductor memory device 3 is powered on, the voltage generating circuit 14A sets the current value of the current source 61A to the current value Ica stored in step S103 (S201). Next, the voltage generating circuit 14A sets the resistance value of the resistive element r2 to the resistance value rca stored in step S107 (S202). As a result, the ratio of the parasitic resistance R1 to the combined resistance of the parasitic resistance r1 and the resistive element r2 becomes the inverse ratio of the ratio of the size W of the transistor T1 to the size w of the transistor T21.

[0187] 2.5 Effects of this embodiment 5 shown in the first embodiment, a peak current detection circuit 52A further includes a resistance element r2, which is a variable resistance element, and calibration circuits 71 and 72. A variable current source is used for a current source 61A of the peak current detection circuit 52A.

[0188] With the above configuration, for example, during testing before shipment, the calibration circuit 71 calibrates the current value of the current source 61A to current Ipmp×(size w of transistor T21 / size W of transistor T1) with the voltage VCC set to a value in the first voltage region A1. After the current value of the current source 61A has been calibrated, the calibration circuit 72 calibrates the resistance value of the resistance element r2 with the voltage VCC set to a value in the second voltage region A2 so that the ratio of the parasitic resistance R1 to the combined resistance of the parasitic resistance r1 and the resistance element r2 becomes the inverse ratio of the size W of the transistor T1 to the size w of the transistor T21.

[0189] Then, for example, when the power is turned on after shipment, the voltage generating circuit 14A sets the current value of the current source 61A to the calibrated current value Ica. The resistance value of the resistive element r2 is set to the calibrated resistance value rca. As a result, the ratio of the parasitic resistance R1 to the combined resistance of the parasitic resistance r1 and the resistive element r2 becomes the inverse ratio of the ratio of the size W of the transistor T1 to the size w of the transistor T21.

[0190] Therefore, the peak current detection circuit 52 can set the current Ipmrr (Ipmrr') to Ipmp×(w / W) not only when the voltage VCC has a value in the first voltage region A1 but also when the voltage VCC has a value in the second voltage region A2, and can therefore detect the peak current in the peak current detection operation. Therefore, according to this embodiment, the peak current generated in the boost circuit 53 can be suppressed not only when the voltage VCC has a value in the first voltage region A1 but also when the voltage VCC has a value in the second voltage region A2.

[0191] Of course, the first and second modified examples of the first embodiment can also be applied to the semiconductor memory device 3 according to this embodiment.

[0192] 3. Modifications As described above, the voltage generating circuit (14 / 14A) according to the embodiment includes a first transistor (T1), a first circuit (53), and a second circuit (52 / 52A). A reference voltage (Vpref) is applied to the gate of the first transistor (T1). A power supply voltage (VCC) is applied to a first terminal of the first transistor (T1). A second terminal of the first transistor (T1) is connected to a first node (N2). The first circuit (53) is connected to the first node (N2), boosts a first voltage (Vpsup) at the first node, and outputs a boosted second voltage (Vpout). The second circuit (52 / 52A) is connected to the first node (N2), and detects a peak of a first current (Ipmp) flowing from the first transistor (T1) to the first circuit (53). The first circuit (53) stops boosting the voltage based on the detection result (FLGP1) by the second circuit (52 / 52A).

[0193] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0194] Furthermore, in the flowcharts described in the above embodiments, the order of the processes can be changed as much as possible.

[0195] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0196] 1...memory system, 2...memory controller, 3...semiconductor memory device, 10...memory cell array, 11...command register, 12...address register, 13...sequencer, 14, 14A...voltage generation circuit, 15...row decoder module, 16...sense amplifier module, 21-26...conductor layer, 31-34...insulator layer, 40...core member, 41...semiconductor film, 42-44...insulator film, 45...semiconductor portion, 51...reference voltage generation circuit, 52, 52A...peak current detection circuit, 53...booster circuit, 61, 61A...current source

Claims

1. a first transistor having a gate to which a reference voltage is applied, a first end to which a power supply voltage is applied, and a second end connected to a first node; a first circuit connected to the first node, boosting a first voltage at the first node and outputting a boosted second voltage; a second circuit connected to the first node and configured to detect a peak of a first current flowing from the first transistor to the first circuit; Equipped with The first circuit stops boosting based on the detection result by the second circuit. Voltage generation circuit.

2. the sensing result indicating that the second circuit has sensed a peak in the first current; 2. The voltage generating circuit according to claim 1.

3. The second circuit is detecting a peak of the first current based on a second current corresponding to the first current; 2. The voltage generating circuit according to claim 1.

4. The second circuit is detecting a peak of the first current by comparing the second current with a reference current; 4. The voltage generating circuit according to claim 3.

5. If the second current is greater than the reference current, the second circuit determines that a peak of the first current has been detected; If the second current is equal to or less than the reference current, the second circuit determines that a peak of the first current has not been detected.

5. The voltage generating circuit according to claim 4.

6. The second circuit performs peak detection of the first current based on a first signal that controls peak detection of the first current.

2. The voltage generating circuit according to claim 1.

7. The second circuit is a second transistor having a gate to which the reference voltage is applied, a first end to which the power supply voltage is applied, and a second end connected to a second node; an operational amplifier having a first input terminal to which the first voltage of the first node is applied, a second input terminal to which a third voltage of the second node is applied, and an output terminal to which a fourth voltage is output based on the first voltage and the third voltage; a third transistor having a gate to which a fifth voltage based on the fourth voltage is applied, a first terminal connected to the second node, and a second terminal connected to a third node; a current source providing a reference current to the fourth node; a fourth transistor having a gate to which the fifth voltage is applied, a first terminal connected to the fourth node, and a second terminal connected to a fifth node; an inverter having an input terminal to which the sixth voltage of the fourth node is applied and outputting a second signal based on the sixth voltage from an output terminal; Including, the detection result is a signal generated by the second circuit based on the second signal; 2. The voltage generating circuit according to claim 1.

8. The second transistor is smaller in size than the first transistor.

8. The voltage generating circuit according to claim 7.

9. The second circuit is a fifth transistor, the gate of which receives a third signal for controlling detection of a peak of the first current, the first terminal of which is connected to the third node, and the second terminal of which is grounded; a sixth transistor having a gate to which the third signal is input, a first end connected to the fifth node, and a second end grounded; Further comprising: the operational amplifier further includes a control terminal, the third signal being input to the control terminal of the operational amplifier; The operational amplifier operates based on the third signal.

8. The voltage generating circuit according to claim 7.

10. The second circuit is filter Further comprising: one end of the filter is connected to the output terminal of the operational amplifier, and the other end of the filter is connected to the gate of the third transistor; 8. The voltage generating circuit according to claim 7.

11. The second circuit is filter Further comprising: one end of the filter is connected to the first node, and the other end of the filter is connected to the first input terminal of the operational amplifier; 8. The voltage generating circuit according to claim 7.

12. The second circuit is A first filter; A second filter Further comprising: one end of the first filter is connected to the first node, and the other end of the first filter is connected to the first input terminal of the operational amplifier; one end of the second filter is connected to the second node, and the other end of the second filter is connected to the second input terminal of the operational amplifier; 8. The voltage generating circuit according to claim 7.

13. The step of boosting the voltage by the first circuit is further stopped based on a fourth signal generated based on the second voltage.

2. The voltage generating circuit according to claim 1.

14. a third circuit, the first terminal of which receives the detection result and the fourth signal, the second terminal of which receives the fourth signal, the third circuit performing a logical AND operation on the detection result and the fourth signal, and outputting the operation result from a third terminal; Further comprising: The step-up by the first circuit is stopped based on the calculation result.

14. The voltage generating circuit according to claim 13.

15. A voltage generating circuit according to claim 1; A memory cell; Equipped with configured to provide the second voltage to the memory cell; Semiconductor memory device.

16. A fourth circuit for controlling the voltage generating circuit Further comprising: the fourth circuit generates a fifth signal for controlling detection of a peak of the first current and transmits the fifth signal to the voltage generating circuit; 16. The semiconductor memory device according to claim 15.

17. 1st wiring Further comprising: the power supply voltage is supplied to one end of the first wiring, and the other end of the first wiring is connected to the first end of the first transistor; The second circuit is A second wiring; A variable resistance element; A first calibration circuit; Further comprising: the power supply voltage is supplied to one end of the second wiring, and the other end of the second wiring is connected to one end of the variable resistance element; the other end of the variable resistance element is connected to the first end of the second transistor; the current source is a variable current source; The first calibration circuit includes: calibrating a current value of the current source to the first current x (size of the second transistor / size of the first transistor); 8. The voltage generating circuit according to claim 7.

18. The second circuit is Second Calibration Circuit Further comprising: The second calibration circuit includes: calibrating a resistance value of the variable resistance element so that a ratio of a parasitic resistance of the first wiring to a combined resistance of the parasitic resistance of the second wiring and the variable resistance element is inversely proportional to a ratio of a size of the first transistor to a size of the second transistor; 18. The voltage generating circuit according to claim 17.

19. The second circuit is Second Calibration Circuit Further comprising: The second calibration circuit includes: calibrating a resistance value of the variable resistance element to a resistance value of the variable resistance element when a logic level of the detection result is inverted; 18. The voltage generating circuit according to claim 17.

20. 1st wiring Further comprising: the power supply voltage is supplied to one end of the first wiring, and the other end of the first wiring is connected to the first end of the first transistor; The second circuit is A second wiring; Variable resistance element Further comprising: the power supply voltage is supplied to one end of the second wiring, and the other end of the second wiring is connected to one end of the variable resistance element; the other end of the variable resistance element is connected to the first end of the second transistor; a ratio of a parasitic resistance of the first wiring to a combined resistance of the parasitic resistance of the second wiring and the variable resistance element is an inverse ratio of a size of the first transistor to a size of the second transistor.

8. The voltage generating circuit according to claim 7.

Images