Semiconductor device and method of manufacturing the same

Abstract

To provide: a semiconductor device that minimizes an increase in impedance of a PDN due to influence of wiring of a layer PCB substrate and influence of resistance of the PDN, and secures improved impedance characteristics and power noise reduction characteristics; and a method of manufacturing the same.SOLUTION: The method according to the invention includes the steps of: providing a semiconductor chip in a wafer state in which a bonding pad is formed; forming a first passivation layer on the semiconductor chip so that the bonding pad is exposed; forming a first rewiring layer connected to the bonding pad and extending from on the first passivation layer; forming a decoupling capacitor so as to be electrically connected to the first rewiring layer at a wafer level before a conductive bump disposed on an electrical signal path connected to the bonding pad, the first rewiring layer, and a substrate is formed; and forming the conductive bump electrically connected to the bonding pad, the first rewiring layer, and a PCB substrate.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as a wafer level package (WLP) or a wafer level chip scale package (WLCSP) and a manufacturing method thereof. [Background technology]

[0002] As the operating voltage of semiconductor integrated circuits (ICs) decreases and the operating frequency increases, there is a demand to reduce power noise to ensure the normal operation of semiconductor ICs. Decoupling capacitors with low ESR (Equivalent Serial Resistance) and low ESL (Equivalent Serial Inductance) are used to reduce the impedance of the PDN (Power Delivery Network) from an external substrate (e.g., multi-layer PCB) to the power input pad of the semiconductor IC, or the PDN from the output pad of the semiconductor IC to the application connection, thereby reducing power noise. As such decoupling capacitors, MLCCs (Multi Layer Ceramic Capacitors), LICCs (Low Inductance Ceramic Capacitors), or 3D silicon capacitors are used.

[0003] To minimize impedance in the PDN, decoupling capacitors are typically placed close to input nodes (input pads), power nodes (power pads), or output nodes (output pads), i.e., in the example of FIG. 1, the decoupling capacitors are placed so that length “A” is as small as possible.

[0004] Fig. 2 shows an example of a structure in which a conventional decoupling capacitor is arranged. Fig. 2A shows a structure in which a decoupling capacitor DCAP is arranged on the side of a multi-layer PCB substrate where a packaged semiconductor chip (DIE) is attached (Die Side Capacitor), Fig. 2B shows a structure in which a decoupling capacitor DCAP is arranged inside the multi-layer PCB substrate (i.e., on the first floor of the multi-layer PCB substrate) (PCB-embedded Capacitor), and Fig. 2C shows a structure in which a decoupling capacitor DCAP is arranged on the side of a multi-layer PCB substrate where a packaged semiconductor chip (DIE) is not attached (Land Side Capacitor).

[0005] In the case of the die side capacitor, PCB-embedded capacitor, and land side capacitor in Figure 2, the PDN between the semiconductor chip (DIE) and the multi-layer PCB substrate (PCB substrate) is located inside the multi-layer PCB substrate, so there is a problem that the impedance of the PDN increases due to the influence of the wiring of the multi-layer PCB substrate, and there is also a limit to reducing the power noise applied to the semiconductor chip (DIE) because it is also affected by the impedance of the bumps of the semiconductor chip (DIE) which are embodied with a conductive material. In addition, the resistance of the PDN is a factor that causes a drop in the voltage applied to the semiconductor chip (DIE). Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been devised to solve the above-mentioned problems, and an object of one aspect of the present invention is to provide a semiconductor device having improved impedance characteristics and power noise reduction characteristics compared to conventional devices, and a method for manufacturing the same. [Means for solving the problem]

[0007] According to one aspect of the present invention, a semiconductor device includes a semiconductor chip in a wafer state having a bonding pad formed thereon; a first passivation layer formed on the semiconductor chip to expose the bonding pad; a first re-distribution layer connected to the bonding pad and extending from the first passivation layer; a conductive bump disposed on an electrical signal path connecting the bonding pad, the first re-distribution layer, and a substrate; and a capacitor formed at the wafer level to be electrically connected to the first re-distribution layer before the conductive bump is formed.

[0008] A method for manufacturing a semiconductor device according to one aspect of the present invention includes forming a first passivation layer on a semiconductor chip to expose bonding pads formed on the semiconductor chip; forming a first redistribution layer connected to the bonding pads and extending from above the first passivation layer; forming a capacitor to be electrically connected to the first redistribution layer at a wafer level; and after the capacitor is formed, forming a conductive bump on an electrical signal path connecting to the bonding pads, the first redistribution layer, and a substrate. Effect of the Invention

[0009] According to the present invention, instead of forming a capacitor (e.g., a decoupling capacitor) on a PCB substrate, a capacitor is formed to be electrically connected to a redistribution layer at a wafer level, and the capacitor is configured to be included in a wafer level package. This allows for a dramatic reduction in the distance between a pad and a capacitor (i.e., the length of the PDN, e.g., "A" in FIG. 1), and thus minimizes the increase in impedance of the PDN due to the influence of the wiring of the multilayer PCB substrate and the influence of the resistance of the PDN. Therefore, improved impedance characteristics and power noise reduction characteristics can be achieved compared to conventional semiconductor devices.

[0010] Furthermore, according to the present invention, since a capacitor is not formed on the PCB board, the area of ​​the PCB board that can be used for the SMT (Surface Mount) process can be increased.

[0011] Furthermore, according to the present invention, a capacitor is directly applied to an I / O pad of a wafer level package, thereby reducing power noise and stabilizing an I / O signal.

[0012] In addition, according to the present invention, the cost required to implement a semiconductor device can be reduced by forming a multi-node of a capacitor using a redistribution layer of a wafer level package to reduce the number of capacitors required for impedance reduction. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is an exemplary diagram showing a PDN of a conventional semiconductor IC. [Figure 2A] FIG. 1 is an exemplary diagram showing a structure in which a conventional decoupling capacitor is arranged; [Figure 2B] FIG. 1 is an exemplary diagram showing a structure in which a conventional decoupling capacitor is arranged; [Figure 2C] FIG. 1 is an exemplary diagram showing a structure in which a conventional decoupling capacitor is arranged; [Diagram 3]1 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4A] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4B] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4C] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4D] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4E] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4F] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4G] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 4H] 1A to 1C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. [Figure 5A] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5B] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5C] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5D] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5E] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5F]10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5G] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5H] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5I] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 5J] 10A to 10C are exemplary diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 6A] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6B] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6C] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6D] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6E] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6F] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6G] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6H] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6I] 11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 6J]11A to 11C are exemplary views for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. [Figure 7A] 1 is an exemplary diagram showing a structure in which a capacitor is arranged in a semiconductor device according to an embodiment of the present invention; [Figure 7B] 1 is an exemplary diagram showing a structure in which a capacitor is arranged in a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, a semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to the accompanying drawings. In this process, the thickness of lines and the size of components illustrated in the drawings may be exaggerated for clarity and convenience of the description. In addition, the terms described below are defined in consideration of the functions of the present invention, and may vary depending on the intention or practice of a user or operator. Therefore, the definitions of such terms should be based on the overall content of this specification.

[0015] In this specification, when a part is described as being "connected (or connected)" to another part, this includes not only the case where the part is "directly connected (or connected)" to another part, but also the case where the part is "indirectly connected (or connected)" to another part through another member in between. In this specification, when a part is described as "including (or equipped with)" a certain component, this does not mean excluding other components, but means that the part may further "include (or equipped with)" other components, unless otherwise specified to the contrary. In addition, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. In addition, when a component is described as being "on" or "above" another component, this includes not only the case where each part is "directly on" or "directly above" the other part, but also the case where there is another component between each component and the other component.

[0016] FIG. 3 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] 3, the method for manufacturing a semiconductor device according to the present embodiment includes a step S110 of providing a semiconductor chip 10 in a wafer state having a bonding pad BP formed thereon, a step S120 of forming a first passivation layer 20 on the semiconductor chip 10 so that the bonding pad BP formed on the semiconductor chip 10 is exposed, a step S130 of forming a first redistribution layer 30 connected to the bonding pad BP and extending from the first passivation layer 20, a step S140 of forming a capacitor DCAP to be electrically connected to the first redistribution layer 30 at the wafer level, a step S150 of forming a conductive bump B on an electrical signal path connected to the bonding pad BP, the first redistribution layer 30, and the PCB substrate after the capacitor DCAP is formed, and a step S160 of dicing the semiconductor chip 10 in a wafer state after the conductive bump B is formed. The capacitor DCAP may be a decoupling capacitor (e.g., MLCC, LICC, or 3D silicon capacitor) configured to reduce the impedance of an electrical signal connected to the bonding pad BP, the first redistribution layer 30, and the PCB substrate.

[0018] A wafer level package (WLP) may be manufactured through steps S110 to S150, and a plurality of chip scale packages may be manufactured through a dicing process for the wafer level package in step S160. Accordingly, the semiconductor device to be manufactured in this embodiment may refer to a wafer level package or a chip scale package.

[0019] In this embodiment, three examples of manufacturing processes are presented according to the design specifications of the semiconductor device to be manufactured, and the manufacturing method of the semiconductor device will be specifically explained below for each example.

[0020] First Example

[0021] 4A to 4H are exemplary views for explaining each process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0022] Referring to FIG. 4A, first, a semiconductor chip 10 in a wafer state in which a pre-designed circuit is integrated is provided (S110). In this embodiment, the semiconductor chip 10 means a chip manufactured in a fab (Fabrication Facility), and is therefore defined as including a die passivation layer (not shown) for protecting the circuit integrated in the semiconductor chip 10 (the die passivation layer may be realized with silicon dioxide (SiO2), silicon nitride (SiN), or a stack structure of silicon dioxide and silicon nitride). A plurality of bonding pads BP serving as power supply and electrical input / output paths for the circuit are formed in the semiconductor chip 10 so as to be exposed to the active surface AS (active surface or active area) side of the semiconductor chip 10 through pad openings, and the die passivation layer is formed in a structure in which the bonding pads BP are exposed to the active surface AS side. As shown in FIG. 4A, among the multiple bonding pads BP formed on the semiconductor chip 10, the bonding pads to be focused on in this embodiment are defined as first and second bonding pads BP1 and BP2. For example, the first bonding pad BP1 may be a pad for power (e.g., VCC) input, and the second bonding pad BP2 may be a pad for ground GND input.

[0023] 4B, a first passivation layer 20 is formed on the semiconductor chip 10 to expose the bonding pads BP (S120). In step S120, the first passivation layer 20 is formed on the active surface AS of the semiconductor chip 10, and the active surface AS of the semiconductor chip 10 except for the area where the bonding pads BP are formed (all or part of the area where the bonding pads BP are formed) is coated with photoresist, and the bonding pads BP are exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist. The first passivation layer 20 may be implemented using a photosensitive polymer or polyimide material (this also applies to the second and third passivation layers 40 and 60 described below).

[0024] Next, as shown in FIG. 4C, a first redistribution layer 30 is formed to be connected to the bonding pad BP and extend from the first passivation layer 20 (S130). That is, the first redistribution layer 30 is connected to the bonding pad BP through the region where the bonding pad BP is exposed by the first passivation layer 20, and is formed to extend from the first passivation layer 20. The first redistribution layer 30 functions as a layer for redistribution of the bonding pad BP and may be implemented with a conductive material such as copper. As is well known, the first redistribution layer 30 having a target layout may be formed through a seed layer formation process, an electroplating process, and a seed layer etching process. As shown in FIG. 4C, a portion of the first redistribution layer 30 connected to the first bonding pad BP1 is defined as a first redistribution line 31, and a portion of the first redistribution layer 30 connected to the second bonding pad BP2 is defined as a second redistribution line 32. Also, as shown in FIG. 4c, additional redistribution lines 33 for rearrangement of additional bonding pads (not shown) may be formed in step S130.

[0025] 4D, a second passivation layer 40 is formed on the first passivation layer 20 and the first redistribution layer 30 so that at least a portion of the first redistribution layer 30 is exposed (S135A). In step S135A, the second passivation layer 40 is formed to cover the first passivation layer 20 and the first redistribution layer 30, and a photoresist is coated on the remaining area except for an area where a conductive member 70 (described later) is to be formed, and then at least a portion of the first redistribution layer 30 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0026] 4E, a conductive member 70 is formed in the region where the first redistribution layer 30 is exposed by the second passivation layer 40 through a plating process (S135B). The conductive member 70 may be an under bump metal (UBM) provided for easy fusion between a conductive bump B and a capacitor DCAP, which will be described later. For clear distinction of terms, a conductive member on which a first conductive bump B1 is formed is defined as a first conductive member 71, a conductive member on which a second conductive bump B2 is formed is defined as a second conductive member 72, a conductive member to which a first power input pad of a capacitor DCAP, which will be described later, is connected is defined as a third conductive member 73, and a conductive member to which a second power input pad of the capacitor DCAP, which will be described later, is connected is defined as a fourth conductive member 74. The first conductive member 71 and the third conductive member 73 are electrically connected through a first redistribution line 31, and the second conductive member 72 and the fourth conductive member 74 are electrically connected through a second redistribution line 32. An additional conductive member 75 may also be formed on the additional redistribution line 33. The "first and second conductive members 71, 72" and the "third and fourth conductive members and additional conductive members 73, 74, 75" are formed through the same process in step S135B, but the physical characteristics (e.g., thickness) of the first and second conductive members 71, 72 and the physical characteristics (e.g., thickness) of the third and fourth conductive members and additional conductive members 73, 74, 75 may be configured to be different from each other. The first and second conductive members 71, 72 have the same physical characteristics, and the third and fourth conductive members and additional conductive members 73, 74, 75 have the same physical characteristics (this is also the same in the third embodiment described below).

[0027] 4F, a capacitor DCAP is formed at the wafer level to be electrically connected to the first redistribution layer 30 (S140). The term "at the wafer level" means that the capacitor DCAP is formed in the wafer level package, not on the PCB substrate to which the packaged semiconductor chip 10 of the present embodiment is attached. The capacitor DCAP may have a plurality of power input pads, for example, a first power input pad (e.g., VCC pad) and a second power input pad (e.g., GND pad). Accordingly, in step S140, the capacitor DCAP may be fused to the third and fourth conductive members 73 and 74 by performing a reflow process while the capacitor DCAP is mounted on the semiconductor chip 10 such that the solder cap of the bump (e.g., copper pillar bump) DCAP_B formed on the first power input pad of the capacitor DCAP contacts the third conductive member 73 electrically connected to the first redistribution line 31, and the solder cap of the bump (e.g., copper pillar bump) DCAP_B formed on the second power input pad of the capacitor DCAP contacts the fourth conductive member 74 electrically connected to the second redistribution line 32. If the capacitor DCAP has an additional power input pad, the additional power input pad of the capacitor DCAP may be formed in contact with the additional conductive member 75 electrically connected to the additional redistribution line 33. Through the above-mentioned method, the first and second redistribution lines 31 and 32 and the additional redistribution line 33 are configured to function as multi-nodes of the capacitor DCAP.

[0028] 4G, a conductive bump B is formed on an electrical signal path extending from the bonding pad BP, the first redistribution layer 30, and a PCB substrate (not shown) to which a packaged semiconductor chip 10 (i.e., a wafer level package) is attached (S150). When an electrical signal path connecting the first bonding pad BP1, the first redistribution line 31, the first conductive member 71, and the PCB substrate is defined as a first electrical signal path, and an electrical signal path connecting the second bonding pad BP2, the second redistribution line 32, the second conductive member 72, and the PCB substrate is defined as a second electrical signal path, the conductive bump B may be configured to include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Accordingly, in step S150, the first and second conductive bumps B1 and B2 are mounted on the semiconductor chip 10 so that the first conductive bump B1 contacts the first conductive member 71 electrically connected to the first redistribution line 31, and the second conductive bump B2 contacts the second conductive member 72 electrically connected to the second redistribution line 32, and a reflow process is performed to fuse the first and second conductive bumps B1 and B2 to the first and second conductive members 71 and 72, respectively.

[0029] Meanwhile, in the drawings of this embodiment, a structure is illustrated in which the first redistribution line 31 is electrically connected to the first conductive bump B1 and the second redistribution line 32 is electrically connected to the second conductive bump B2; however, in addition to the first and second conductive bumps B1, B2, an additional conductive bump (multiple conductive bumps) may be further provided in this embodiment, and accordingly, the first redistribution line 31 or the second redistribution line 32 may be configured to be electrically connected to the additional conductive bump in addition to the first conductive bump B1 or the second conductive bump B2.

[0030] 4G shows an example in which the conductive bump B is implemented as a solder bump, but in some embodiments, as shown in FIG 4H, the conductive bump B may be implemented as a copper pillar bump. That is, when the semiconductor chip 10 consumes a lot of power, requires a high operating current, and requires a small number of I / O pads, it is preferable to use a solder bump having a relatively large size, and when the semiconductor chip 10 consumes a little power, requires a low operating current, and requires a large number of I / O pads, it is preferable to use a copper pillar bump having a relatively small size.

[0031] Through the above steps S110 to S150, a wafer level package (particularly, a Fan-In WLP) can be manufactured. In particular, the capacitor DCAP is configured to be electrically connected to a first electrical signal path (e.g., a VCC power input path) and a second electrical signal path (e.g., a ground path) through the first redistribution layer 30, and configured to reduce the impedance of the first and second electrical signal paths, thereby ensuring improved impedance characteristics and power noise reduction characteristics.

[0032] Meanwhile, after step S150, step S160 may be further performed in which the semiconductor chips 10 in a wafer state are diced into a plurality of chip scale packages.

[0033] 2. Second Example

[0034] 5A to 5J are exemplary views for explaining each process of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[0035] In the manufacturing process of a wafer level package, multiple redistribution layers may be required for rearrangement of the pads depending on the number of pads and the overall layout area of ​​the semiconductor chip 10, and the second embodiment focuses on the structure and process in which the capacitor DCAP is formed inside the passivation layer when the wafer level package is configured to include multiple redistribution layers. Detailed descriptions of the same structures and processes as the first embodiment will be omitted, and structures and processes that are different from the first embodiment will be described. The same process and structures as the first embodiment will be referred to by the same reference numerals.

[0036] 5A, first, a semiconductor chip 10 in a wafer state is provided (S110). The semiconductor chip 10 has first and second bonding pads BP1 and BP2, which serve as power supply and electrical input / output paths for the circuit, formed so as to be exposed on the active surface AS side of the semiconductor chip 10 through pad openings.

[0037] 5B, a first passivation layer 20 is formed on the semiconductor chip 10 such that the bonding pads BP are exposed (S120). In step S120, the first passivation layer 20 is formed on the semiconductor chip 10 such that the first and second bonding pads BP1 and BP2 are exposed on the active surface AS of the semiconductor chip 10.

[0038] 5C, a first redistribution layer 30 is formed to be connected to the bonding pad BP and extend from above the first passivation layer 20 (S130). A portion of the first redistribution layer 30 connected to the first bonding pad BP1 is defined as a first redistribution line 31, and a portion of the first redistribution layer 30 connected to the second bonding pad BP2 is defined as a second redistribution line 32. Also, as shown in FIG. 5C, an additional redistribution line 33 for rearrangement of an additional bonding pad (not shown) may be formed in step S130.

[0039] 5D, a capacitor DCAP is formed at a wafer level to be electrically connected to the first redistribution layer 30 (S140). In step S140, the capacitor DCAP may be formed in contact with the first redistribution layer 30 through a surface mount (SMT) process. Accordingly, the first and second power input pads of the capacitor DCAP may be formed in contact with the first and second redistribution lines 31 and 32, respectively, and if the capacitor DCAP has an additional power input pad, the additional power input pad of the capacitor DCAP may be formed in contact with the additional redistribution line 33 described above. Through the above-mentioned method, the first and second redistribution lines 31 and 32 and the additional redistribution line 33 are configured to function as a multi-node of the capacitor DCAP.

[0040] 5E, a second passivation layer 40 is formed on the first passivation layer 20 and the first redistribution layer 30 so that at least a portion of the first redistribution layer 30 is exposed (S145A). In step S145A, the second passivation layer 40 is formed to cover the first passivation layer 20, the first redistribution layer 30, and the capacitor DCAP, and a photoresist is coated on the remaining area except for the area where the second redistribution layer 50 (described later) is to be formed, and then at least a portion of the first redistribution layer 30 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0041] 5F, a second redistribution layer 50 is formed in an area where the first redistribution layer 30 is exposed by the second passivation layer 40 (S145B). A portion of the second redistribution layer 50 connected to the first redistribution line 31 is defined as a third redistribution line 51, and a portion of the second redistribution layer 50 connected to the second redistribution line 32 is defined as a fourth redistribution line 52. As shown in FIG. 5F, the third and fourth redistribution lines 51 and 52 may have portions extending from above the second passivation layer 40.

[0042] 5G, a third passivation layer 60 is formed on the second passivation layer 40 and the second redistribution layer 50 so as to expose at least a portion of the second redistribution layer 50 (S145C). In step S145C, the third passivation layer 60 is formed to cover the second passivation layer 40 and the second redistribution layer 50, and a photoresist is coated on the remaining area except for an area where a conductive member 70 (described later) is to be formed, and then at least a portion of the second redistribution layer 50 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0043] 5H, a conductive member 70 is formed through a plating process in the area where the second redistribution layer 50 is exposed by the third passivation layer 60 (S145D). The conductive member 70 may be a UBM provided for easy fusion of a conductive bump B, which will be described later. For the sake of clear distinction of terminology, the conductive member on which the first conductive bump B1 is formed is defined as a first conductive member 71, and the conductive member on which the second conductive bump B2 is formed is defined as a second conductive member 72.

[0044] 5I, a conductive bump B is formed on the electrical signal path extending from the bonding pad BP, the first redistribution layer 30, and the PCB substrate (not shown) (S150). When the electrical signal path extending from the first bonding pad BP1, the first redistribution line 31, the third redistribution line 51, the first conductive member 71, and the PCB substrate is defined as a first electrical signal path, and the electrical signal path extending from the second bonding pad BP2, the second redistribution line 32, the fourth redistribution line 52, the second conductive member 72, and the PCB substrate is defined as a second electrical signal path, the conductive bump B may be configured to include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Accordingly, in step S150, the first and second conductive bumps B1 and B2 are mounted on the semiconductor chip 10 such that the first conductive bump B1 contacts the first conductive member 71 electrically connected to the first and third redistribution lines 31 and 51, and the second conductive bump B2 contacts the second conductive member 72 electrically connected to the second and fourth redistribution lines 32 and 52, and a reflow process is performed to fuse the first and second conductive bumps B1 and B2 to the first and second conductive members 71 and 72, respectively. Although FIG. 5I illustrates an example in which the conductive bump B is implemented as a solder bump, as illustrated in FIG. 5J, the conductive bump B may be implemented as a copper pillar bump depending on the embodiment.

[0045] Through the above steps S110 to S150, a wafer level package (particularly, a Fan-In WLP) can be manufactured. In particular, the capacitor DCAP is configured to be electrically connected to a first electrical signal path (e.g., a VCC power input path) and a second electrical signal path (e.g., a ground path) through the first and second redistribution layers 30 and 50 to reduce the impedance of the first and second electrical signal paths, thereby ensuring improved impedance characteristics and power noise reduction characteristics. Furthermore, the capacitor DCAP is disposed between the first passivation layer 20 and the third passivation layer 60 (i.e., the capacitor DCAP is disposed within the passivation layer), so that the low ESR and low ESL characteristics of the capacitor DCAP can be maintained without being affected by external disturbances.

[0046] Meanwhile, after step S150, step S160 may be further performed in which the semiconductor chips 10 in a wafer state are diced into a plurality of chip scale packages.

[0047] 3. Third Example

[0048] 6A to 6J are exemplary views for explaining each process of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0049] As described in the second embodiment, multiple redistribution layers may be required for rearrangement of pads depending on the number of pads and the total layout area of ​​the semiconductor chip 10 during the manufacturing process of the wafer level package. In this case, it may be considered to arrange the capacitor DCAP in the passivation layer as in the second embodiment, but as the complexity of the redistribution layer increases, there may be cases where no space is formed in the passivation layer to arrange the capacitor DCAP. The third embodiment focuses on a structure and process in which the capacitor DCAP is formed outside the passivation layer when the wafer level package is configured to include multiple redistribution layers. A detailed description of the same structures and processes as the first and second embodiments will be omitted, and only structures and processes that are different from the first and second embodiments will be described. The same processes and structures as the first and second embodiments will be designated by the same reference numerals.

[0050] 6A, first, a semiconductor chip 10 in a wafer state is provided (S110). The semiconductor chip 10 has first and second bonding pads BP1 and BP2, which serve as power supply and electrical input / output paths for the circuit, formed so as to be exposed on the active surface AS side of the semiconductor chip 10 through pad openings.

[0051] 6B, a first passivation layer 20 is formed on the semiconductor chip 10 such that the bonding pads BP are exposed (S120). In step S120, the first passivation layer 20 is formed on the semiconductor chip 10 such that the first and second bonding pads BP1 and BP2 are exposed on the active surface AS of the semiconductor chip 10.

[0052] 6C, a first redistribution layer 30 is formed to be connected to the bonding pad BP and extend from above the first passivation layer 20 (S130). A portion of the first redistribution layer 30 connected to the first bonding pad BP1 is defined as a first redistribution line 31, and a portion of the first redistribution layer 30 connected to the second bonding pad BP2 is defined as a second redistribution line 32. Also, as shown in FIG. 6C, an additional redistribution line 33 for rearrangement of an additional bonding pad (not shown) may be formed in step S130.

[0053] 6D, a second passivation layer 40 is formed on the first passivation layer 20 and the first redistribution layer 30 so that at least a portion of the first redistribution layer 30 is exposed (S135C). In step S135C, the second passivation layer 40 is formed to cover the first passivation layer 20 and the first redistribution layer 30, and a photoresist is coated on the remaining area except for the area where the second redistribution layer 50 (described later) is to be formed, and then at least a portion of the first redistribution layer 30 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0054] 6E, a second redistribution layer 50 is formed in an area where the first redistribution layer 30 is exposed by the second passivation layer 40 (S135D). A portion of the second redistribution layer 50 connected to the first redistribution line 31 is defined as a third redistribution line 51, and a portion of the second redistribution layer 50 connected to the second redistribution line 32 is defined as a fourth redistribution line 52. As shown in FIG. 6E, the third and fourth redistribution lines 51 and 52 may have portions extending from above the second passivation layer 40. Also, as shown in FIG. 6E, in step S135D, an additional redistribution line 53 for rearrangement of an additional bonding pad (not shown) may be formed on the additional redistribution line 33 (to clearly distinguish the additional redistribution lines corresponding to the drawing symbols "33" and "53", the additional redistribution line 33 included in the first redistribution layer 30 may be represented as the first additional redistribution line 33, and the additional redistribution line 53 included in the second redistribution layer 50 may be represented as the second additional redistribution line 53).

[0055] 6F, a third passivation layer 60 is formed on the second passivation layer 40 and the second redistribution layer 50 so as to expose at least a portion of the second redistribution layer 50 (S135E). In step S135E, the third passivation layer 60 is formed to cover the second passivation layer 40 and the second redistribution layer 50, and a photoresist is coated on the remaining area except for an area where a conductive member 70 (described later) is to be formed, and then at least a portion of the second redistribution layer 50 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0056] 6G, a conductive member 70 is formed in the area where the second redistribution layer 50 is exposed by the third passivation layer 60 through a plating process (S135F). The conductive member 70 may be a UBM provided for easy fusion of a conductive bump B described later. For clear distinction of terms, the conductive member on which the first conductive bump B1 is formed is defined as a first conductive member 71, the conductive member on which the second conductive bump B2 is formed is defined as a second conductive member 72, the conductive member to which the first power input pad of the capacitor DCAP described later is connected is defined as a third conductive member 73, and the conductive member to which the second power input pad of the capacitor DCAP is connected is defined as a fourth conductive member 74. The first conductive member 71 and the third conductive member 73 are electrically connected through the first redistribution line 31, and the second conductive member 72 and the fourth conductive member 74 are electrically connected through the second redistribution line 32. If the capacitor DCAP has an additional power input pad, an additional conductive member 75 may be formed on the second additional redistribution line 53 to which the additional power input pad of the capacitor DCAP is fused in step S135F.

[0057] 6H, a capacitor DCAP is formed at a wafer level to be electrically connected to the first redistribution layer 30 (S140). In step S140, a reflow process is performed while the capacitor DCAP is mounted on the semiconductor chip 10, so that the solder cap of the bump DCAP_B formed on the first power input pad of the capacitor DCAP contacts the third conductive member 73 electrically connected to the first and third redistribution lines 31 and 51, and the solder cap of the bump DCAP_B formed on the second power input pad of the capacitor DCAP contacts the fourth conductive member 74 electrically connected to the second and fourth redistribution lines 32 and 52. If the capacitor DCAP has an additional power input pad, the additional power input pad of the capacitor DCAP may be formed in contact with the additional conductive member 75 described above. In this manner, the first and second redistribution lines 31 and 32 are configured to function as multi-nodes of the capacitor DCAP.

[0058] 6I, a conductive bump B is formed on an electrical signal path extending from the bonding pad BP, the first redistribution layer 30, and a PCB substrate (not shown) to which a packaged semiconductor chip 10 (i.e., a wafer level package) is attached (S150). When an electrical signal path connecting the first bonding pad BP1, the first redistribution line 31, the third redistribution line 51, the first conductive member 71, and the PCB substrate is defined as a first electrical signal path, and an electrical signal path connecting the second bonding pad BP2, the second redistribution line 32, the fourth redistribution line 52, the second conductive member 72, and the PCB substrate is defined as a second electrical signal path, the conductive bump B may be configured to include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Accordingly, in step S150, the first and second conductive bumps B1 and B2 are mounted on the semiconductor chip 10 such that the first conductive bump B1 contacts the first conductive member 71 electrically connected to the first and third redistribution lines 31 and 51, and the second conductive bump B2 contacts the second conductive member 72 electrically connected to the second and fourth redistribution lines 32 and 52, and a reflow process is performed to fuse the first and second conductive bumps B1 and B2 to the first and second conductive members 71 and 72, respectively. Although FIG. 6I illustrates an example in which the conductive bump B is implemented as a solder bump, as illustrated in FIG. 6J, the conductive bump B may be implemented as a copper pillar bump depending on the embodiment.

[0059] Through the above steps S110 to S150, a wafer level package (particularly, a Fan-In WLP) may be manufactured. After step S150, step S160 may be further performed in which the semiconductor chips 10 in a wafer state are diced into a plurality of chip scale packages.

[0060] 7A and 7B are exemplary diagrams showing a structure in which a capacitor is arranged in a semiconductor device according to this embodiment, and when compared with the conventional capacitor arrangement structure of FIG. 2, it can be seen that the distance between the pad and the capacitor can be significantly reduced by arranging the capacitor within the die. Although only two conductive bumps are illustrated in FIG. 7 to facilitate a clear understanding of the embodiment, in the actual manufacturing process of a semiconductor device, a semiconductor chip can be attached to a PCB substrate through two or more conductive bumps.

[0061] In this way, according to the present invention, instead of forming a capacitor (e.g., a decoupling capacitor) on a PCB substrate, a capacitor is formed to be electrically connected to a redistribution layer at a wafer level, and the capacitor is configured to be included in a wafer level package. This allows for a dramatic reduction in the distance between a pad and a capacitor (i.e., the length of the PDN, e.g., "A" in FIG. 1), and thus minimizes the increase in impedance of the PDN due to the influence of the wiring of the multilayer PCB substrate and the influence of the resistance of the PDN. Therefore, improved impedance characteristics and power noise reduction characteristics can be achieved compared to conventional semiconductor devices.

[0062] Furthermore, according to the present invention, since a capacitor is not formed on the PCB board, the area of ​​the PCB board that can be used for the SMT (Surface Mount) process can be increased.

[0063] Furthermore, according to the present invention, a capacitor is directly applied to an I / O pad of a wafer level package, thereby reducing power noise and stabilizing an I / O signal.

[0064] In addition, according to the present invention, the cost required to implement a semiconductor device can be reduced by forming a multi-node of a capacitor using a redistribution layer of a wafer level package to reduce the number of capacitors required for impedance reduction.

[0065] Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely illustrative, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of the present invention should be determined by the following claims. [Explanation of symbols]

[0066] BP: Bonding pad BP1, BP2: 1st and 2nd bonding pads B: Conductive bump B1, B2: First and second conductive bumps DCAP: Capacitor AS: Active surface 10: Semiconductor chips 20: First passivation layer 30: 1st redistribution layer 31, 32: 1st and 2nd rewiring lines 40: Second passivation layer 50: 2nd redistribution layer 51, 52: 3rd and 4th rewiring lines 60: 3rd passivation layer 70: Conductive material 71, 72, 73, 74: first to fourth conductive members

Claims

1. A semiconductor chip in a wafer state on which bonding pads are formed; a first passivation layer formed on the semiconductor chip such that the bonding pads are exposed; a first re-distribution layer connected to the bonding pad and extending from the first passivation layer; a conductive bump disposed on the bonding pad, the first redistribution layer, and an electrical signal path leading to a substrate; and a capacitor formed at a wafer level before the conductive bumps are formed, the capacitor being electrically connected to the first redistribution layer.

2. the bonding pads include first and second bonding pads; the first passivation layer is formed on the semiconductor chip such that the first and second bonding pads are exposed; the first redistribution layer includes first and second redistribution lines respectively connected to the first and second bonding pads and extending from the first passivation layer; the conductive bumps include a first conductive bump disposed on a first electrical signal path connected to the first bonding pad, the first redistribution line, and the substrate, and a second conductive bump disposed on a second electrical signal path connected to the second bonding pad, the second redistribution line, and the substrate; 2. The semiconductor device of claim 1, wherein the capacitor is electrically coupled to the first and second redistribution lines and is disposed between the first and second conductive bumps.

3. a second passivation layer formed on the first passivation layer and the first redistribution layer such that at least a portion of the first redistribution layer is exposed; and a conductive member formed in an area where the first redistribution layer is exposed by the second passivation layer; 3. The semiconductor device of claim 2, wherein said first and second conductive bumps and said capacitor are formed on and in contact with said conductive member.

4. a second passivation layer formed on the first passivation layer and the first redistribution layer such that at least a portion of the first redistribution layer is exposed; a second redistribution layer formed in an area where the first redistribution layer is exposed by the second passivation layer; a third passivation layer formed on the second passivation layer and the second redistribution layer such that at least a portion of the second redistribution layer is exposed; and a conductive member formed in an area where the second redistribution layer is exposed by the third passivation layer; the capacitor is formed on and in contact with the first redistribution layer, and is formed between the first passivation layer and the third passivation layer; 3. The semiconductor device of claim 2, wherein said first and second conductive bumps are formed on and in contact with said conductive member.

5. a second passivation layer formed on the first passivation layer and the first redistribution layer such that at least a portion of the first redistribution layer is exposed; a second redistribution layer formed in an area where the first redistribution layer is exposed by the second passivation layer; a third passivation layer formed on the second passivation layer and the second redistribution layer such that at least a portion of the second redistribution layer is exposed; and a conductive member formed in an area where the second redistribution layer is exposed by the third passivation layer; 3. The semiconductor device of claim 2, wherein said first and second conductive bumps and said capacitor are formed on and in contact with said conductive member.

6. The first and second redistribution lines function as multi-nodes of the capacitor; 3. The semiconductor device of claim 2, wherein the first redistribution line or the second redistribution line is configured to be electrically connectable to an additional conductive bump in addition to the first conductive bump or the second conductive bump.

7. 2. The semiconductor device of claim 1, wherein the conductive bump is implemented as a solder bump or a copper pillar bump.

8. 10. The semiconductor device of claim 1, wherein the semiconductor device is implemented in a wafer level package (WLP) or a wafer level chip scale package (WLCSP).

9. forming a first passivation layer on the semiconductor chip such that a bonding pad formed on the semiconductor chip is exposed; forming a first redistribution layer connected to the bonding pad and extending from above the first passivation layer; forming a capacitor electrically connected to the first redistribution layer at a wafer level; and forming a conductive bump on the bonding pad, the first redistribution layer, and an electrical signal path leading to a substrate after the capacitor is formed.

10. the bonding pads include first and second bonding pads; the first passivation layer is formed on the semiconductor chip such that the first and second bonding pads are exposed; the first redistribution layer includes first and second redistribution lines respectively connected to the first and second bonding pads and extending from the first passivation layer; the conductive bumps include a first conductive bump disposed on a first electrical signal path connected to the first bonding pad, the first redistribution line, and the substrate, and a second conductive bump disposed on a second electrical signal path connected to the second bonding pad, the second redistribution line, and the substrate; 10. The method of claim 9, wherein the capacitor is electrically connected to the first and second redistribution lines and is disposed between the first and second conductive bumps.

11. After forming the first redistribution layer, forming a second passivation layer on the first passivation layer and the first redistribution layer such that at least a portion of the first redistribution layer is exposed; and forming a conductive member in an area where the first redistribution layer is exposed by the second passivation layer; In the forming of the capacitor, the capacitor is formed by contacting a conductive member electrically connected to the first redistribution line and a conductive member electrically connected to the second redistribution line, respectively; 11. The method of claim 10, wherein, in the forming of the conductive bumps, the first conductive bump is formed in contact with a conductive member electrically connected to the first redistribution line, and the second conductive bump is formed in contact with a conductive member electrically connected to the second redistribution line.

12. In the step of forming the capacitor, the capacitor is formed on and in contact with the first redistribution layer; After forming the capacitor, forming a second passivation layer on the first passivation layer and the first redistribution layer such that at least a portion of the first redistribution layer is exposed; forming a second redistribution layer in an area where the first redistribution layer is exposed by the second passivation layer; forming a third passivation layer on the second passivation layer and the second redistribution layer such that at least a portion of the second redistribution layer is exposed; and forming a conductive member in an area where the second redistribution layer is exposed by the third passivation layer; 11. The method of claim 10, wherein, in the forming of the conductive bumps, the first conductive bump is formed in contact with a conductive member electrically connected to the first redistribution line, and the second conductive bump is formed in contact with a conductive member electrically connected to the second redistribution line.

13. After forming the first redistribution layer, forming a second passivation layer on the first passivation layer and the first redistribution layer such that at least a portion of the first redistribution layer is exposed; and forming a second redistribution layer in an area where the first redistribution layer is exposed by the second passivation layer; forming a third passivation layer on the second passivation layer and the second redistribution layer such that at least a portion of the second redistribution layer is exposed; and forming a conductive member in an area where the second redistribution layer is exposed by the third passivation layer; In the forming of the capacitor, the capacitor is formed by contacting a conductive member electrically connected to the first redistribution line and a conductive member electrically connected to the second redistribution line, respectively; 11. The method of claim 10, wherein, in the forming of the conductive bumps, the first conductive bump is formed in contact with a conductive member electrically connected to the first redistribution line, and the second conductive bump is formed in contact with a conductive member electrically connected to the second redistribution line.

14. 10. The method of claim 9, further comprising: dicing the semiconductor chips in a wafer state into a plurality of chip scale packages after the conductive bumps are formed.

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