Method for manufacturing semiconductor device from wafer using carrier wafer

Abstract

To provide a method for manufacturing a semiconductor device from a wafer using a carrier wafer.SOLUTION: A method for manufacturing a semiconductor element, in particular a power semiconductor device, from a wafer, includes the steps of providing a wafer substrate (101), processing a structured wafer surface (102), depositing a carrier wafer (103) on the wafer substrate (101), and reducing the thickness of the wafer substrate (101) by wafer thinning.SELECTED DRAWING: Figure 1c

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing semiconductor devices from a wafer using a carrier wafer, in particular a carrier wafer deposited by a dam-and-fill method step. [Background technology]

[0002] To manufacture power semiconductors or semiconductor chips, wafers made of materials such as silicon (Si), silicon carbide or sapphire, for example with a diameter of 150 mm, 200 mm or 300 mm, are usually processed in several individual steps. Here, for the manufacture of products in the field of MEMS and power semiconductor technology, it is known to bond a substrate to the wafer for performance reasons in the manufacturing process, for example to support a very thin grinding of the wafer. Here, the provision of a temporary carrier wafer, made for example from a robust material such as quartz or silicon carbide, serves, among other things, for the mechanical stabilization and easy handling of the wafer during processing. Furthermore, the curvature of the wafer or the so-called wafer bow can be minimized. In particular, wafers with deep trench structures or thick passivation and metallization, which are responsible for the wafer bow, are almost impossible to process without a carrier wafer for chip thicknesses of less than 150 μm.

[0003] A disadvantage of the known methods is that extreme thinning or multiple bonding of wafers and substrates of different materials (wafer stacks) leads to very high stresses, especially in connection with thick layers such as metals, passivations and deep trenches common in power semiconductor technology, which make the substrates very fragile and therefore unable to be further processed at all or only with great effort. Summary of the Invention

[0004] The present invention relates to a method for producing semiconductor devices, in particular power semiconductor devices, from a wafer, comprising the steps of: - providing a wafer substrate; - treating a structured wafer surface; - depositing a carrier wafer on the wafer substrate; - reducing a thickness of the wafer substrate by wafer thinning; According to the invention, the deposition of the carrier wafer on the wafer surface is performed by a dam-and-fill method step. It concerns the method.

[0005] Advantageous developments of the method according to the invention for producing a plurality of semiconductor components from a wafer are set forth in the dependent claims. By the deposition of the carrier wafer on the wafer surface by a dam-and-fill method step or a dam-and-fill process according to the invention, a carrier layer stabilizing the wafer can be applied very effectively to the fully processed wafer front side, where the wafer can be mechanically stabilized in a subsequent method step, in particular during wafer thinning to reduce the thickness of the substrate. In addition to the simple application method, the provision of the carrier wafer according to the invention compensates for stresses in the system. Here, in contrast to a purely additively manufactured carrier layer, a much higher fill layer thickness can be applied, which offers great advantages in terms of shrinkage behavior during curing and in terms of possible CTE mismatch between the carrier system and the wafer. Furthermore, the printed carrier layer simultaneously acts as an insulator, which reduces the risk of electrical flashover at breakdown voltages of up to about 1600 volts during electrical testing, and thus allows the use of multiple test heads for higher test speeds. Moreover, in comparison with other existing carrier technologies, the carrier can remain on the wafer until the final process step of wafer dicing, i.e. separation of the wafer into individual semiconductor devices, which greatly facilitates handling of the thinnest wafers in the final process sequence, improving processability and thus reducing error costs. The method according to the invention therefore allows optimized process control and more reliable production of semiconductor devices.

[0006] Here, the dam-and-fill method step comprises depositing, advantageously by digital printing techniques known per se, at least one defining frame or edge structure in the form of a dam having a predetermined height and enclosing a volume, and filling the volume thus produced or defined by the frame structure with a filling material, preferably by a dispensing or dispensing step known per se. The frame structure and the filling material can be hardened separately or together by methods known per se, for example UV or heat.

[0007] Here, the deposition of the ink to provide the dam or frame structure can be carried out in a manner known per se with a corresponding print head arranged movably relative to the wafer surface or to the working surface supporting the wafer. Advantageously, this step comprises the application of an organic or inorganic ink, followed by curing. Here, advantageously, an organic (e.g. polymer-based) ink or an inorganic ink, with a preferred layer thickness of 5 to 25 μm, is printed onto the finished structured wafer surface. The ink may advantageously contain organic and / or inorganic, e.g. mineral or ceramic, fillers to improve the thermal and mechanical properties.

[0008] Advantageously, a filler material, preferably having a low shrinkage and thermal expansion coefficient or CTE, is filled into the volume defined by the frame structure as a carrier layer by a dispensing step known per se, which can then be levelled and / or hardened by a levelling process, for example by vibration or ultrasound.

[0009] The resulting carrier wafer serves as a mechanical carrier during backside thinning and backside metallization as well as during the handling processes in between, does not deform, is suitable for high vacuum and has high temperature stability. The carrier wafer can be removed again before or during the wafer singulation process using a wafer saw or laser. The removal of the carrier wafer can take place, for example, in a water or solvent bath and / or by the addition of additives. Alternatively, the carrier wafer can also be removed by thermal or photoexcitation.

[0010] The deposition of the carrier wafer may comprise a number of dam-and-fill method steps for applying a number of overlapping layers, the layers being applied in sequence, each with a subsequent curing, advantageously so as to provide a carrier wafer having a layer thickness of 5 to 500 μm.

[0011] The dam-and-fill method step can advantageously deposit at least one frame structure surrounding the metallization side of the wafer surface and provide openings in the filling material. Here, an additional inner frame structure surrounding the respective metallization side can be deposited or printed as a dam in the outer frame structure before the volume located between the frame structures is filled with the dam-and-fill process. This ensures that the respective metallization side is not covered by the carrier wafer and thus the wafer can be electrically contacted and tested during further methods. This allows further testing of the wafer both after backside thinning and after sputtering of the backside metallization.

[0012] Furthermore, advantageously, the openings provided here in the filling material of the carrier wafer can be filled or printed with a separate, again removable filling or support material, preferably by digital printing techniques during the dam-and-fill method step. This can improve the contour sharpness of the carrier wafer in the area of ​​the openings, so that smaller openings can be realized, especially when the layer thickness is large. After the deposition of the carrier wafer, the support material can be removed again, for example in a water or solvent bath or by using thermal excitation.

[0013] Furthermore, the method may comprise a step of selectively removing the filler material, whereby a metallization surface arranged on the wafer surface is exposed from the filler material of the carrier wafer arranged thereon, whereby selective removal of the filler material deposited in areas of the metallization surface can be performed, for example by means of laser irradiation, which can be electrically contacted and tested during further methods.

[0014] Advantageously, the method comprises a planarization step after application of the printed carrier wafer, in which a defined, preferably uniform layer thickness of the carrier wafer is generated or achieved on the wafer surface. This can be done, for example, by means of a squeegee. Here, in particular, excess ink can also be removed or the surface of the applied layer can be smoothed.

[0015] Advantageously, in the dam and fill method step, the frame structure and / or the filler material is deposited in the rounded outer areas of the wafer substrate, eliminating the rounded areas and in particular planarizing them with the surface of the wafer substrate, so that the rounding occurring in the edge areas is eliminated and a flat carrier wafer can be applied closer to the edge areas, in particular to avoid the risk of breakouts during the backside thinning process. In these areas, counter pressure cannot normally be applied by the carrier wafer.

[0016] Furthermore, advantageously, the method may comprise, prior to the deposition of the filler material on the carrier wafer, the application of a support layer on the wafer surface, which is water-soluble, preferably laterally defined by a pre-deposited frame structure, which can be dissolved or removed by process fluids in the singulation process, thereby also allowing the now singulated carrier wafer layer to be simply removed from the individual semiconductor elements.

[0017] More advantageously, the method may further comprise depositing an abrasive film on the carrier wafer, which in particular covers the openings provided in the carrier wafer, in order to avoid premature dissolution of the support layer during a wafer thinning or backside thinning process, in which process fluids are also used.

[0018] According to the invention, the step of depositing the carrier wafer is performed prior to a wafer thinning or backside thinning process of the wafer, in which the wafer is reduced from its original wafer thickness to a component thickness desired or required for subsequent use of the semiconductor device or chip. Depending on the specific requirements of the manufacturing process and the desired thickness of the wafer, this can be done, for example, by polishing, chemical mechanical polishing (CMP), or etching. In a preferred embodiment, the backside thinning of the wafer is performed to a thickness of less than 300 μm, more preferably less than 200 μm, and even more preferably less than 150 μm.

[0019] Furthermore, the invention relates to a semiconductor device, in particular a power semiconductor device, which is or can be produced according to the method described above. Further advantages and details of the invention will become apparent from the following description of preferred embodiments of the invention and from the drawings, which are shown only diagrammatically. [Brief description of the drawings]

[0020] [Figure 1a] 1A-1D are schematic side views of a wafer illustrating method steps of a first preferred embodiment of the method according to the invention; [Figure 1b] 1A-1D are schematic side views of a wafer illustrating method steps of a first preferred embodiment of the method according to the invention; [Figure 1c] 1A-1D are schematic side views of a wafer illustrating method steps of a first preferred embodiment of the method according to the invention; [Figure 1d] 1A-1D are schematic side views of a wafer illustrating method steps of a first preferred embodiment of the method according to the invention; [Figure 1e] 1A-1D are schematic side views of a wafer illustrating method steps of a first preferred embodiment of the method according to the invention; [Figure 2a] 5A-5D show method steps of a further preferred embodiment of the method during deposition of a separate soluble support layer. [Figure 2b] 5A-5D show method steps of a further preferred embodiment of the method during deposition of a separate soluble support layer. [Figure 2c] 5A-5D show method steps of a further preferred embodiment of the method during deposition of a separate soluble support layer. [Figure 3a] FIG. 13 is a detailed view of the deposition of a carrier wafer on the edge area of ​​the wafer. [Figure 3b] FIG. 13 is a detailed view of the deposition of a carrier wafer on the edge area of ​​the wafer. [Figure 3c] FIG. 13 is a detailed view of the deposition of a carrier wafer on the edge area of ​​the wafer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] In the figures, identical elements or elements having identical functions are provided with the same reference numbers. As shown in Fig. 1a, first a wafer substrate 101, for example made of silicon (Si), silicon carbide (SiC) or gallium nitride (GaN), is prepared as a basis for processing semiconductor elements that may be formed on the wafer. In a manner known per se, desired layers and structures 102 or layers and structures 102 predetermined in a process are then formed on the wafer substrate surface in order to produce semiconductor elements such as transistors, diodes or integrated circuits.

[0022] As shown in Figures 1b and 1c, in the next step the deposition of a carrier wafer 103 on the wafer substrate 101 takes place by a dam-and-fill method step. Here firstly dam or frame structures 103a, 103b made of organic or inorganic inks with typical layer thicknesses of 5-25 μm and preferred wall thicknesses of preferably 50 to several hundreds of μm are printed structured on the fully treated wafer surface, preferably by digital printing or inkjet techniques. The inks are cured or sintered (e.g. by UV or heat) during or after the printing of the layers.

[0023] After printing, a planarization step can optionally be performed, for example with a squeegee, to generate a layer that is as flat as possible. This process is repeated multiple times, similar to inkjet-based 3D printing known per se, so that larger layer thicknesses, for example in the range of 50-500 μm, can be realized. Optionally, after the printing of each layer, a final curing or sintering step is further performed to achieve complete cross-linking and improve the mechanical properties. Preferably, the ink contains organic and / or inorganic, for example mineral or ceramic, fillers to improve the thermal properties.

[0024] The volume 104 defined by the frame structure is then filled by dispensing a high loading amount of filler material 105. The filler material may be an underfill material or may be formed as a glob top, advantageously having a low shrinkage rate and a low coefficient of thermal expansion or CTE. It may then be leveled using a planarization process, for example vibration or ultrasonic.

[0025] Here, the filler material 105 is preferably introduced in such a way that openings 107 for the metallization surfaces 106 of the wafer remain free. For this purpose, the deposited frame structure preferably comprises an inner frame structure 103b, which surrounds one or more metallization surfaces 106 of the structured wafer surface 102.

[0026] Optionally, in parallel with the deposition of the carrier wafer 103, a removable filling or support material 108 can again be simultaneously deposited, in particular printed, in the region of the opening 107. This is shown by way of example in FIG. 1b for the right opening. This allows the contour sharpness of the carrier wafer 103 in the region of the opening 107 to be improved and therefore allows smaller openings to be realized, especially in the case of large layer thicknesses. The support material 108 can again be removed after printing of the carrier wafer 103, for example in a water bath, in a solvent bath or by thermal excitation.

[0027] Prior to the backside thinning step of the wafer substrate 101, an abrasive film 111 can optionally be deposited on the wafer front side, as shown in FIG. 1d. As shown in Fig. 1e, the method includes a further step of backside thinning or wafer thinning, where the wafer substrate 101 is reduced to a predetermined thickness. Here, backside thinning can be performed, for example, by polishing with a suitable abrasive 112. In a preferred embodiment, the backside thinning of the wafer is performed to a thickness of less than 300 μm, preferably less than 200 μm, and even more preferably less than 150 μm. After the backside thinning process, the optionally deposited polishing film 111 can be removed and a backside metal contact of the wafer can be deposited.

[0028] A subsequent manufacturing step (not shown) involves separation or singulation of the wafer substrate 101 into individual semiconductor devices. As an alternative to the previously described embodiment, the method may also comprise covering the entire surface of the wafer front side 102 with a filler material 105 in a printed frame structure 103a, a wafer thinning or backside thinning step being performed after the deposition of the carrier wafer 103. Openings 107 may then be created in the carrier wafer 103, for example by selective removal with a laser, such that one or more metallization surfaces 106 arranged on the wafer front side are exposed from the filler material of the carrier wafer 103 arranged thereon for contacts for wafer testing.

[0029] Figures 2a-2c show a further preferred embodiment of the method. It differs from the method according to Figures 1a-e in that after treatment of the structured wafer surface 102 similar to that shown in Figure 1a, a dissolvable, in particular water-soluble, support layer 110 is printed onto the wafer surface, preferably by digital printing techniques. This can be done during deposition of a frame structure 103a by printing techniques, which now preferably surrounds the support layer 110 laterally. This is followed by deposition and formation of the carrier wafer 103 by a dam-and-fill method step, as is shown diagrammatically in Figure 2c.

[0030] The support layer 110 can be dissolved or removed by processing liquids in a subsequent wafer singulation step, which also removes the singulated carrier wafer layer. The laterally provided frame structure 103a protects the support layer 110 in the backside thinning process, in which processing liquids are also used, so that the support layer 110 is not dissolved prematurely. Furthermore, an optional polishing film 111 (see FIG. 1d) can be arranged in the area of ​​the opening 107 to protect the support layer 110 from contact with process fluids.

[0031] 3a-3c show an edge region 109 of the wafer substrate 101. The edge region 109 is rounded in the first 100-300 μm area, which increases the risk of breakout during the backside thinning process of the wafer substrate. Advantageously, in the method according to the invention, during deposition of the carrier wafer 103, a frame structure 103a is deposited or printed such that the rounded region is eliminated, in particular planarized with the front surface 113 of the wafer substrate. This can be done by multi-layer formation or printing of the frame structure 103a, as shown diagrammatically in FIGS. 3a-3c. Planarization in the rounded region 109 of the wafer 101 allows the carrier wafer 103 to be placed closer to the outer wafer edge. [Explanation of symbols]

[0032] 101 Wafer Substrate 102 Structured Wafer Surface 103 Carrier Wafer 103a, 103b Frame structure 104 Volume 105 Filler 106 Metallization Surface 107 Opening 108 Filling material 109 Rounded outer area 110 Support layer 111 Polishing film 112 Abrasives 113 Surface

Claims

1. 1. A method for manufacturing semiconductor devices, in particular power semiconductor devices, from a wafer, comprising the steps of: - providing a wafer substrate (101); - treating the structured wafer surface (102), - depositing a carrier wafer (103) on said wafer substrate (101); - reducing the thickness of said wafer substrate (101) by wafer thinning; In a method comprising: said deposition of said carrier wafer (103) on said wafer surface (102) is performed by a dam-and-fill method step; method.

2. The dam-and-fill method steps include depositing at least one frame structure (103a, 103b) on the wafer surface (102) by digital printing techniques, and filling a volume (104) defined by the frame structure (103a, 103b) with a filler material (105) by dispensing.

2. The method of claim 1 .

3. The dam-and-fill method step includes depositing a framework (103b) surrounding at least one metallization surface (106) of the wafer surface (102) and providing an opening (107) in the fill material (105).

3. The method according to claim 1 or 2.

4. characterised in that the openings (107) of the filling material (105) of the carrier wafer (103) are filled with a separate, again removable filling material (108), preferably by digital printing techniques. The method according to claim 3.

5. 5. The method according to claim 1, further comprising a step of selectively removing a filler material, preferably by means of a laser, such that at least one metallization surface (106) arranged on the wafer surface (102) is exposed from the filler material (105) of the carrier wafer (103) arranged thereon.

6. characterized in that the deposition of the carrier wafer (103) comprises the application of an organic or inorganic ink, followed by curing.

6. The method according to any one of claims 1 to 5.

7. characterised in that the deposition of the carrier wafer (103) comprises a number of dam-and-fill method steps for applying a number of overlapping layers, the layers being applied in sequence, each with a subsequent curing.

7. The method according to any one of claims 1 to 6.

8. 8. The method according to claim 1, characterized in that in the dam-and-fill method step a framework and / or a filling material is deposited on the rounded outer regions (109) of the wafer substrate (101) to eliminate said rounded regions, in particular to be planarized with a surface (113) of the wafer substrate (101).

9. characterised in that it comprises, prior to the deposition of the filler material (105) of the carrier wafer (103), applying to the wafer surface (102), preferably by digital printing techniques, a water-soluble support layer (110), preferably laterally defined by a frame structure (103a).

9. The method according to any one of claims 1 to 8.

10. 10. The method according to claim 9, further comprising depositing a polishing film (111) on the carrier wafer (103), the polishing film (111) covering in particular openings (107) provided in the carrier wafer (103).

11. A semiconductor device manufactured according to the method of any one of claims 1 to 10.

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