Power module and power conversion unit

Abstract

To reduce parasitic inductance of a power module to equalize currents.SOLUTION: A power module includes a first metal brazing substrate 32, a chip set arranged on the substrate and including at least two chips 330, and a clip covering a side of the chip set away from the first metal brazing substrate. A plurality of connection units are individually electrically connected to corresponding chips. Every set including two adjacent connection units are connected via a body 341 along a first direction. Connection arms 343 are each arranged for every set including two adjacent connection units and electrically connected to the first metal brazing substrate. When the minimal length from the connection arm to one of the two adjacent chips is defined as first minimal length B1 and the minimal length from the connection arm to the other of the two adjacent chips is defined as second minimal length B2, the difference is less than 30% of the first minimal length. Accordingly, the balance of current paths between the chips is maintained, the difference between the parasitic parameters of chips is reduced, and the dynamic current equalization characteristics of parallel chips is improved.SELECTED DRAWING: Figure 13B

Description

[Technical field]

[0001] This application relates to the field of semiconductor technology, and more particularly to power modules and power conversion equipment. [Background technology]

[0002] With the development of power electronics technology, power modules have been attracting more and more attention. The electrical connection of semiconductor chips in power modules is mainly realized by using aluminum wire welding technology. The electrodes of the semiconductor chips are connected to the metal layer on the surface of the substrate through aluminum wires. However, when a large number of chips are arranged in the power module, the amount of aluminum wires also increases accordingly. A large amount of aluminum wires increases the parasitic inductance of the power module. In addition, when multiple chips are connected in parallel, multiple aluminum wires are used for connection. This causes uneven currents between multiple chips connected in parallel. This uneven current causes uneven heating by the chips connected in parallel. The intense localized heating affects the performance of the chips and therefore the performance of the power module. Summary of the Invention

[0003] SUMMARY OF THE DISCLOSURE Embodiments of the present application provide power modules and power conversion devices that help reduce parasitic inductance and improve current equalization.

[0004] According to a first aspect, an embodiment of the present application provides a power module, comprising: A first metal brazing substrate; a chip set disposed on the first metal brazing substrate, the chip set including at least two chips linearly disposed along a first direction, the first direction being parallel to a plane in which the chips are spaced apart from the first metal brazing substrate; a clip covering a side of the chipset away from the first metal brazing substrate, the clip including a body, at least two connection units, and at least one connection arm, each connection unit being electrically connected to a corresponding chip, and every two adjacent connection units being connected along the first direction via the body; Including, Each connection arm is positioned with respect to two adjacent chips in the chipset, the connection arm is connected to the first metal brazing substrate, a shortest distance between the connection arm and one of the two adjacent chips in the chipset is a first shortest distance, a shortest distance between the connection arm and the other of the two adjacent chips is a second shortest distance, and a difference between the first shortest distance and the second shortest distance is less than or equal to 30% of the first shortest distance.

[0005] The chips in the chipset are connected in parallel through the clips, which are wider and have larger flow paths than commonly used aluminum wires, providing stronger connections between multiple chips and better matching between the parasitic parameters of parallel chips, thus optimizing dynamic current equalization between multiple parallel chips.

[0006] The contact between the aluminum wire and the chip is a point contact, and the aluminum wire is likely to peel off from the chip. However, in the present application, the contact between the clip and the chip is a surface contact, so the connection strength between the clip and the chip is improved. This improves the structural reliability between multiple chips and ensures the stability of current transmission. In addition, the chips in the chipset are arranged in a straight line along the first direction, and the clip covers the side of the chipset away from the first metal brazing substrate. This connects two adjacent chips in the shortest straight path. The clip and the chip are in surface contact. This also helps improve the transient heat dissipation capability of the power module.

[0007] Each connection unit is electrically connected to a corresponding chip, and every two adjacent connection units are connected along a first direction through the body. Specifically, two adjacent chips are connected through the body in the shortest straight path. Multiple parallel chips in a chipset are connected through clips in the shortest straight path to reduce interconnect parasitic inductance between chips.

[0008] Each connection arm is disposed relative to two adjacent chips in the chipset. The shortest distance between the connection arm and one chip is a first shortest distance, and the shortest distance between the connection arm and the other chip is a second shortest distance. The difference between the first shortest distance and the second shortest distance is not more than 30% of the first shortest distance. One of the two adjacent chips, the clip and the first metal brazing substrate form a first interconnection path, and the other chip, the clip and the first metal brazing substrate form a second interconnection path. The first interconnection path and the second interconnection path are approximately symmetrical. This can balance the current paths between the chips and reduce the difference between the parasitic parameters of the chips, and further improve the dynamic current equalization characteristics of the parallel chips.

[0009] According to a first aspect, in a possible implementation, each chip includes a first source and a second source arranged along the first direction, the first source of one chip and the second source of the other chip of two adjacent chips in the chip set are arranged adjacent to each other, the connection unit is electrically connected to the first source and second source of the corresponding chip, the connection arm is arranged convexly on the body and extends at a bend toward the first metal brazing substrate, and the connection arm extends to a position prior to connection with the first metal brazing substrate.

[0010] In a possible implementation, the joint between the connection arm and the first metal brazing substrate is located on the mid-line of the shortest connection line between the two adjacent chips, and the first shortest distance and the second shortest distance can be considered to be identical.

[0011] According to a first aspect, in a possible implementation, the chip further includes a gate line, and the first source, the gate line, and the second source are arranged along the first direction; The connection unit further includes a first contact portion, an avoidance space, and a second contact portion arranged sequentially along the first direction, the first contact portion contacting the first source, the second contact portion contacting the second source, the avoidance space having an avoidance opening arranged toward the gate line, and a position of the avoidance opening is arranged relative to a position of the gate line.

[0012] The chip is very small in size, and the gate line is easily damaged by stress, leading to chip failure. In a possible implementation, the position of the avoidance opening of the avoidance space is located relative to the position of the gate line. In this way, the clip is located away from the gate line, so that the stress that the clip exerts on the gate line is reduced. This helps to reduce the possibility of the gate line being damaged and to extend the cycle life of the power module.

[0013] According to a first aspect, in a possible implementation, at least two connection holes are formed in the body, each connection unit is disposed in a corresponding connection hole, the first contact portion is connected to the hole wall of the connection hole, and the second contact portion is connected to the hole wall of the connection hole.

[0014] According to a first aspect, in a possible implementation, the body and the first metal brazing substrate are spaced apart. At least one of the first contact portion and the second contact portion of each connection unit is connected to the body. The first contact portion connected to the body and the second contact portion connected to the body each include a connection section and a contact section. At least a portion of the connection section is bent relative to the body. The connection section is connected between the body and the contact section. The contact section of the first contact portion contacts a corresponding first source. The contact section of the second contact portion contacts a corresponding second source.

[0015] In this possible embodiment, the bend section is bent relative to the body, the contact section is connected to the body via the bend section, and the body is above and spaced from the chip, which provides greater flexibility in the layout of the power module.

[0016] According to a first aspect, in a possible implementation, the power module further includes a plastic package body, the plastic package body enclosing the first metal brazing substrate, the chipset and the clip, and a first locking hole is provided at a joint between the connection section and the body, and the first locking hole is filled with the plastic package body.

[0017] The plastic package body delaminates at the bending position of the mechanical part or at the continuous large-area flat area of ​​the mechanical part, which affects the sealing performance of the power module. In this possible implementation, the first locking hole is provided at the joint between the connection section and the body, and the first locking hole is filled with the plastic package body, thereby reducing the possibility of the plastic package body delaminating at the joint between the body and the connection section and / or the possibility of the plastic package body delaminating and spreading to the surface of the chip, which helps to improve the sealing performance of the power module.

[0018] According to a first aspect, in a possible implementation, the power module further includes a plastic package body, the plastic package body enclosing the first metal brazing substrate, the chipset and the clip, and a second locking hole is provided in the body, and the second locking hole is filled with the plastic package body.

[0019] The plastic package body will delaminate at the bending position of the mechanical part or at the continuous large-area flat area of ​​the mechanical part, which will affect the sealing performance of the power module. In this possible implementation, the body is provided with the second locking hole, and the second locking hole is filled with the plastic package body, which reduces the possibility of the plastic package body delaminating on the body or the plastic package body delaminating and spreading to the surface of the chip, which helps to improve the sealing performance of the power module.

[0020] According to a first aspect, in a possible implementation, the first contact portion and the second contact portion of the at least one connection unit are spaced apart along the first direction, and the avoidance space is a groove passing through the clip along a second direction, the second direction being perpendicular to a plane in which the side of the chip away from the first metal brazing substrate lies.

[0021] In a possible implementation, the avoidance space is a groove passing through the clip along the second direction, which further reduces the stress that the clip applies to the gate line.

[0022] According to the first aspect, in a possible implementation, the at least one connection unit further includes a bent portion, the bent portion being connected between the first contact portion and the second contact portion along the first direction, the bent portion protruding along a direction away from the first metal brazing substrate, and the first contact portion, the bent portion and the second contact portion surrounding the avoidance space.

[0023] In this possible implementation, the first contact portion is fixed to the second contact portion via the bent portion, which helps to increase the strength of the clip.

[0024] According to the first aspect, in a possible implementation, the bend is provided with a buffer hole passing through the bend along the second direction, the second direction being perpendicular to a plane in which the side of the chip opposite the first metal brazing substrate lies.

[0025] In this possible implementation, the buffer holes are configured to reduce and buffer the stress applied by the clip to the chip, thereby reducing the possibility of the chip being damaged by the stress applied by the clip and extending the cycle life of the power module.

[0026] According to a first aspect, in a possible implementation, the first metal brazing substrate includes the first insulating substrate and a mounting metal layer covering the first insulating substrate, and the chipset is disposed on the side of the mounting metal layer opposite the first insulating substrate. There are a plurality of mounting metal layers. The plurality of mounting metal layers are disposed on the first insulating substrate at intervals. The plurality of mounting metal layers includes the first mounting metal layer, the second mounting metal layer, the third mounting metal layer, and the fourth mounting metal layer. The second mounting metal layer includes a first extension, a groove, and a second extension. An end of the first extension is connected to an end of the second extension. The first mounting metal layer, the first extension, the groove, the second extension, and the third mounting metal layer are sequentially disposed along a third direction. At least a portion of the fourth mounting metal layer is located in the groove. The third direction is parallel to a plane in which a side of the chip away from the first metal brazing substrate lies, and the third direction is perpendicular to the first direction.

[0027] In this possible implementation, multiple chipsets help improve the operating efficiency of the power module.

[0028] According to a first aspect, in a possible implementation, the power module further includes an input terminal and an output terminal. The input terminal and the output terminal are arranged at opposite ends of the first metal brazing substrate along the first direction. The power module having the metal brazing substrate is a half-bridge type power module. The input terminal includes a first positive power pin, a second positive power pin, and a third negative power pin. The first positive power pin is electrically connected to the first mounting metal layer. The second positive power pin is electrically connected to the third mounting metal layer. The third negative power pin is electrically connected to the fourth mounting metal layer. The output terminal is electrically connected to the second mounting metal layer.

[0029] In this possible implementation, three power pins are placed at the input terminal, which helps to increase the amount of current flow path of the power module at the input terminal, reduce parasitic inductance in the power loop, and reduce switching losses.

[0030] According to a first aspect, the plurality of chipsets include a first chipset, a second chipset, a third chipset, and a fourth chipset. The first chipset is disposed on the first mounting metal layer, the second chipset is disposed on the second mounting metal layer, the third chipset is disposed on the third mounting metal layer, and the fourth chipset is disposed on the second extension. A connection arm on the first chipset is electrically connected to the second mounting metal layer, a connection arm on the second chipset is electrically connected to the fourth mounting metal layer, and a connection arm on the third chipset is electrically connected to the second mounting metal layer. The first chipset, the second chipset, the fourth chipset, and the third chipset are sequentially disposed along the third direction. The connection arm on the first chipset is electrically connected to the first extension portion, the connection arm on the second chipset is electrically connected to the fourth mounting metal layer, the connection arm on the third chipset is electrically connected to the second extension portion, and the connection arm on the fourth chipset is electrically connected to the fourth mounting metal layer.

[0031] In this possible embodiment, the power module is a half-bridge power module, and the power module further includes an upper bridge section and a lower bridge section. The upper bridge section includes the first chipset, the third chipset, the first positive power pin, and the second positive power pin. The lower bridge section includes the second chipset, the fourth chipset, and the third negative power pin. Along the third direction, the upper bridge section of the half-bridge power module is located in two outer rows, and the lower bridge section is located in two middle rows, with the upper bridge section having two power pins located on the outside and the lower bridge section having one power pin located in the middle. The three power pins and the clip are designed to reduce the parasitic inductance and switching loss of the power loop.

[0032] According to the first aspect, in a possible implementation, the power module further includes a second metal brazing substrate and an electronic component, the second metal brazing substrate being disposed on the first metal brazing substrate, and the electronic component being disposed on a side of the second metal brazing substrate away from the first metal brazing substrate and electrically connected to the second metal brazing substrate.

[0033] Electronic components are usually small. Therefore, when the electronic components are directly welded to the first metal brazing substrate, it is necessary to provide an insulating trench in the metal layer of the first metal brazing substrate, and two electrodes of the electronic components are electrically connected to the metal layer on both sides of the insulating trench. When the insulating trench is provided in the first metal brazing substrate, the layout space of the chips is reduced. In addition, since a large number of chips are arranged on the first metal brazing substrate, providing a trench by etching in the metal layer of the first metal brazing substrate may damage the pre-arranged chips and other electronic components.

[0034] In this case, the electronic components are connected via the second metal brazing substrate, so that the welding process of the electronic components is simple. Compared to the case where the electronic components are directly welded to the metal layer of the first metal brazing substrate, the process of providing the insulating trench in the metal layer of the first metal brazing substrate can be omitted, so that the circuit design of the first metal brazing substrate is simplified. Note that the insulating trench may be provided in advance in the second metal brazing substrate based on the size of the electronic components and the positions of the two electrodes of the electronic components. The insulating trench is provided on the second metal brazing substrate by etching so as not to affect the performance of the chip on the first metal brazing substrate. The electronic components are then electrically connected to the second metal brazing substrate.

[0035] According to a first aspect, in a possible implementation, a terminal metal layer is further arranged on a surface of the first metal brazing substrate facing the chip, the terminal metal layer is located at an end of the first metal brazing substrate along the first direction, the second metal brazing substrate is arranged adjacent to the terminal metal layer, and the terminal metal layer is connected to the second metal brazing substrate via a second conductive wire.

[0036] In this possible implementation, the second metal brazing substrate is disposed close to the terminal metal layer, shortening the length of the line between the second metal brazing substrate and the terminal metal layer, which helps to improve the space utilization of the power module.

[0037] According to a first aspect, in a possible implementation, the electronic component includes a thermistor, the thermistor configured to monitor a temperature of the chip.

[0038] According to a first aspect, in a possible implementation, at least one chip further includes a gate, the electronic component is a gate resistor, and the second metal brazing substrate includes a first substrate electrode and a second substrate electrode insulated and spaced apart from each other. Both ends of the gate resistor are electrically connected to the first substrate electrode and the second substrate electrode, respectively. The first substrate electrode is configured to receive a drive current. The second substrate electrode is electrically connected to the gate of the chip via a first conductive line.

[0039] In this possible implementation, the gate resistor is connected via the second metal brazing substrate, so the welding process of the gate resistor is simple.

[0040] According to a first aspect, in a possible implementation, a first bonding layer is further provided along the second direction between the first metal brazing substrate and a side of the chip remote from the clip, the first bonding layer comprising at least one of a solder and a sintered material.

[0041] In this possible implementation, the chip is fixed to the first metal brazing substrate by sintering or welding, which helps to improve the stability of the connection between the chip and the first metal brazing substrate.

[0042] According to the first aspect, in a possible implementation, the power module further includes a heat sink, the heat sink being located on a side of the first metal braze substrate away from the chip.

[0043] According to the first aspect, in a possible implementation, the power module further comprises a fixing layer. Along the second direction, the fixing layer is located between the heat sink and a side of the first metal brazing substrate away from the chip. The fixing layer comprises at least one of a solder and a sintering material. The second direction is perpendicular to a plane in which the side of the chip away from the first metal brazing substrate lies.

[0044] In order to improve the heat dissipation effect, the heat sink may be fixed to the side of the first metal brazing substrate away from the chip via the fixing layer, which has a better heat conduction effect than thermally conductive silicone compared to a method in which the heat sink is bonded to the first metal brazing substrate by sintering or welding via thermally conductive silicone.

[0045] According to the first aspect, in a possible implementation, said clip is of one-piece construction.

[0046] In this possible implementation, the integral structure can improve current flow smoothness, reduce current flow resistance, improve current equalization, reduce inductance, and further improve the reliability of the clip.

[0047] According to a first aspect, in a possible implementation, the power module further includes a power pin, the power pin being electrically connected to the first metal braze substrate, the power pin including at least one bend structure.

[0048] During application of the power module, the power pins may be subjected to large stress. For example, when the power pins are connected to a battery pack, the power pins may be subjected to large stress. Since the power pins are provided with a bent structure, the bent structure helps to buffer the stress. This reduces the possibility that the plastic package body will be cracked due to the stress applied to the power pins, or that the input terminals or the output terminals will be damaged due to the stress applied to the power pins.

[0049] According to a first aspect, in a possible implementation, when the number of chips in the chipset is three or more, all chips in the chipset are equally spaced along the first direction, which further optimizes dynamic current equalization between multiple parallel chips due to improved matching between parasitic parameters of parallel chips.

[0050] According to a second aspect, the present application provides a power conversion device, comprising a circuit board and the power module according to the first aspect, the power module being disposed on the circuit board.

[0051] According to a third aspect, the present application provides a power transmission system including the power conversion device according to the second aspect, and a drive motor connected to the power conversion device.

[0052] According to a fourth aspect, the present application provides a photovoltaic power generation system including a photovoltaic cell module and the power conversion device according to the second aspect. [Brief description of the drawings]

[0053] [Figure 1] FIG. 1 is a diagram of a vehicle structure according to an embodiment of the present application.

[0054] [Diagram 2] FIG. 1 is a block diagram of a driveline architecture according to an embodiment of the present application.

[0055] [Diagram 3] FIG. 1 is a diagram of the structure of a photovoltaic system according to an implementation of the present application.

[0056] [Figure 4] FIG. 2 is a three-dimensional view of an assembly of a power module according to an embodiment of the present application.

[0057] [Diagram 5] FIG. 5 is a three-dimensional view of the assembly of the power module shown in FIG. 4 from another perspective.

[0058] [Figure 6] FIG. 5 is a schematic three-dimensional exploded view of the power module shown in FIG. 4.

[0059] [Figure 7] FIG. 2 is a diagram of a stack structure of a power module according to an embodiment of the present application.

[0060] [Figure 8] FIG. 2 is a diagram of a chipset disposed on a first metal brazing substrate.

[0061] [Figure 9] FIG. 2 is a schematic plan view of a chip according to an embodiment of the present application.

[0062] [Figure 10A] FIG. 1 is a diagram of an assembly of a first metal brazing substrate, a chipset, and a clip.

[0063] [Figure 10B] FIG. 10B is a schematic enlarged view of a partial region A1 of FIG. 10A.

[0064] [Figure 11A] FIG. 13 is another view of the assembly of the first metal braze substrate, chipset, and clip.

[0065] [Figure 11B] FIG. 11B is a schematic enlarged view of a partial region A2 of FIG. 11A.

[0066] [Figure 12] FIG. 2 is a three-dimensional view of a clip according to an embodiment of the present application.

[0067] [Figure 13A] FIG. 2 is a perspective view of an assembly of a first metal braze substrate, a chip set, and a clip.

[0068] [Figure 13B] FIG. 13B is a schematic enlarged view of a partial region A3 of FIG. 13A.

[0069] [Figure 14] FIG. 2 is a top view of an assembly of a first metal braze substrate, a chip set, and a clip.

[0070] [Figure 15]FIG. 2 is a top view of an assembly of a first metal braze substrate and a chipset.

[0071] [Figure 16A] FIG. 2 is a three-dimensional view of the assembly of a power module without a plastic package body.

[0072] [Figure 16B] FIG. 16B is a schematic enlarged view of a partial region A4 of FIG. 16A.

[0073] [Figure 17] FIG. 2 is a three-dimensional view of a clip according to an embodiment of the present application.

[0074] [Figure 18] 1 is a diagram of a connection between a clip and a portion of a clip according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0075] 1 is a diagram of a vehicle structure according to an embodiment of the present application. The vehicle 1000 includes a vehicle body 300, a battery pack 200, and a powertrain 100. Both the battery pack 200 and the powertrain 100 are mounted on the vehicle body 300. The battery pack 200 is configured to provide direct current to the powertrain 100. The powertrain 100 is configured to provide electrical power to the vehicle 1000. The vehicle 1000 includes further structures, which may or may not be required, and which will not be described in detail herein.

[0076] FIG. 2 is a block diagram of the structure of a power transmission system according to an embodiment of the present application. The power transmission system 100 includes a power conversion device 101 and a driving motor 103. The power conversion device 101 includes a circuit board 10 and a power module 30 arranged on the circuit board 10. The power module 30 includes an input terminal 301 and an output terminal 303. The input terminal 301 is a DC input terminal, and the output terminal 303 is an AC output terminal. The input terminal 301 of the power module 30 is electrically connected to the battery pack 200, and the output terminal 303 of the power module 30 is electrically connected to the driving motor 103. The power module 30 is configured to convert the DC output from the battery pack 200 into AC and transmit it to the driving motor 103. The power module 30 is a semiconductor device that converts the voltage, current, period, etc. of the DC output from the battery pack 200.

[0077] 3 is a diagram of the structure of a photovoltaic system according to the implementation of the present application. The power module 30 of the present application may also be used in the photovoltaic system. The photovoltaic system includes a power conversion device 101 and a photovoltaic cell module 105. The photovoltaic cell module 105 is electrically connected to the power conversion device 101. The direct current generated by the photovoltaic cell module 105 is converted to alternating current by the power module 30. The alternating current output by the power module 30 is transmitted to an electric device, such as a base station or a data center.

[0078] A power module usually includes a copper-clad substrate and multiple chips. The electrical connection of the semiconductor chips in the power module is mainly realized by using aluminum wire welding technology. The electrodes of the semiconductor chips are connected to the metal layer on the substrate surface through aluminum wires. However, when a large number of chips are arranged in the power module, the amount of aluminum wires increases accordingly. A large amount of aluminum wires increases the parasitic inductance of the power module. In addition, when multiple chips are connected in parallel, multiple aluminum wires are used for connection. This causes uneven currents between the multiple chips connected in parallel. This uneven current causes uneven heating by the chips connected in parallel. The intense localized heating affects the performance of the chips and therefore the performance of the power module.

[0079] Based on this, an embodiment of the present application provides a power module 30. FIG. 4 is a three-dimensional view of the assembly of the power module according to the embodiment of the present application. FIG. 5 is a three-dimensional view of the assembly of the power module shown in FIG. 4 from another perspective. FIG. 6 is a schematic three-dimensional exploded view of the power module shown in FIG. 4. The power module 30 further includes a heat sink 31, a first metal brazing substrate 32, a chip set 33, a clip 34, and a plastic package body 35. The first metal brazing substrate 32 is attached to the side of the heat sink 31. The heat sink 31 is configured to dissipate heat of the power module 30. The chip set 33 is disposed on the first metal brazing substrate 32. The chip set 33 includes a plurality of chips 330. The clip 34 is disposed on the side of the corresponding chip set 33 away from the first metal brazing substrate 32, and is configured to connect the plurality of chips 330 in the chip set 33 in parallel. The plastic package body 35 surrounds the first metal brazing substrate 32, the chip set 33, and the clip 34. It can be seen that the chip set 33 includes at least two chips 330. Both the input terminals 301 and the output terminals 303 are connected to the first metal braze substrate 32.

[0080] 4, in a possible implementation, the input terminal 301 and the output terminal 303 each include a power pin 360, the input terminal 301 is connected to the battery pack 200 via the power pin 360, and the output terminal 303 is connected to the battery pack 200 via the power pin 360. The power pin 360 includes at least one flex structure 3601, which is configured to buffer stress. The power pins 360 of the input terminal 301 and the output terminal 303 are partially exposed from the plastic package body 35.

[0081] During application of the power module 30, the power pin 360 may be subjected to a large stress. For example, when the power pin 360 is connected to the battery pack 200, the power pin 360 may be subjected to a large stress. Since the power pin 360 is provided with the flex structure 3601, the flex structure 3601 helps to buffer the stress. This reduces the possibility that the stress applied to the power pin 360 will crack the plastic package body, or that the stress applied to the power pin 360 will damage the input terminal 301 or the output terminal 303.

[0082] The power pin 360 may be made of a copper bar, an aluminum bar, or the like. The power pin 360 usually has a large width due to excessive current. The power pin 360 is connected to an external connection bar (or metal terminal) by a bolt or laser welding or other methods. The power pin 360 may be partially exposed from the plastic package body 35.

[0083] FIG. 7 is a diagram of a stacked structure of a power module according to an embodiment of the present application. The heat sink 31 is disposed on the side of the first metal brazing substrate 32 away from the chip 330. The heat sink 31 may be a water-cooled heat sink or an air-cooled heat sink. This is not limited here. The heat sink 31 is configured to dissipate heat for the power module 30 so as to improve the power density of the power module 30. Along the second direction, the heat sink 31 is connected to the side of the first metal brazing substrate 32 away from the chip 330 through a fixing layer 310. In this embodiment, the fixing layer 310 is solder so as to improve the heat dissipation effect. Specifically, the heat sink 31 may be welded to the side of the first metal brazing substrate 32 away from the chip 330 through solder. Compared with the method of joining the heat sink 31 to the first metal brazing substrate 32 through thermally conductive silicone, the welding method has a better heat conduction effect of the welding material than the thermally conductive silicone.

[0084] It is understood that the fixing layer 310 may alternatively be a sintered material. The fixing layer 310 includes at least one of a solder and a sintered material.

[0085] The heat sink 31 includes a heat sink base plate 311 and heat sink fins 313 disposed on the heat sink base plate 311. The heat sink fins 313 may be exposed from the plastic package body .

[0086] The first metal brazing substrate 32 includes a first insulating substrate 321, a mounting metal layer 323, and a fixing metal layer 325, which are laminated. In some implementations of the present application, the first metal brazing substrate 32 may be an active metal brazed (AMB) substrate. The AMB substrate has good comprehensive properties such as thermal conductivity and mechanical strength. The first insulating substrate 321 may be a ceramic substrate. The ceramic substrate may be a Si3N4 or AlN ceramic substrate, etc. The mounting metal layer 323 and the fixing metal layer 325 may be copper (Cu). The Cu may be welded to the first insulating substrate 321 using a welding process. It should be noted that in the present application, the first insulating substrate 321 is not limited to a ceramic substrate, and may be an insulating substrate made of other materials. The mounting metal layer 323 may be aluminum or other metals, and the fixing metal layer 325 may be aluminum or other metals. A wire is disposed on the mounting metal layer 323. The devices on the first metal braze substrate 32 may be connected to the metal layer of the first metal braze substrate 32 by one or more welds.

[0087] The chip set 33 is disposed on the side of the mounting metal layer 323 away from the first insulating substrate 321. FIG. 8 is a diagram of the chip set disposed on the first metal layer substrate. The chips 330 in the chip set 33 are disposed linearly along the first direction. The chips 330 in the chip set 33 are disposed equally spaced along the first direction to improve the consistency between the parasitic parameters of the parallel chips 330 in the chip set 33 and to further optimize the dynamic current equalization between the parallel chips 330. The first direction is parallel to a plane on which the side of the chip 330 away from the first metal brazing substrate 32 lies. The second direction is perpendicular to a plane on which the side of the chip 330 away from the first metal brazing substrate 32 lies. The third direction is parallel to a plane on which the side of the chip 330 away from the first metal brazing substrate 32 lies. Any two of the first direction, second direction, and third direction are perpendicular to each other. In some implementations of the present application, the first direction may be the Y direction shown in Fig. 8, the third direction may be the direction in which the first insulating substrate 321 and the mounting metal layer 323 are stacked, and the third direction may be the X direction shown in Fig. 8. When the number of chips 330 in the chip set 33 is three or more, all the chips 330 in the chip set 33 are arranged at equal intervals along the first direction. In the present application, the multiple chips 330 in the chip set 33 do not necessarily need to be arranged at equal intervals along the first direction.

[0088] 9 is a schematic plan view of a chip according to an embodiment of the present application. Each chip 330 includes a chip body 3301, a first source 3302, a second source 3303, a gate line 3305, a gate 3306, a first Kelvin source 3307, and a second Kelvin source 3308. The first source 3302, the second source 3303, the gate line 3305, the gate 3306, the first Kelvin source 3307, and the second Kelvin source 3308 are all disposed on the chip body 3301. The gate line 3305 is disposed within the chip 330.

[0089] The first source 3302, the second source 3303, the gate line 3305, the gate 3306, the first Kelvin source 3307, and the second Kelvin source 3308 are all electrically connected to the mounting metal layer 323. The first source 3302, the second source 3303, the gate line 3305, the gate 3306, the first Kelvin source 3307, and the second Kelvin source 3308 may be arranged in two rows on the chip body 3301. The first source 3302, the second source 3303, and the gate line 3305 are sequentially arranged in a first row along a first direction. The gate 3306, the first Kelvin source 3307, and the second Kelvin source 3308 are sequentially arranged in a second row along the first direction. The first row and the second row are arranged along a third direction. The second direction, the first direction, and the third direction are different from each other.

[0090] In some implementations of the present application, the chip 330 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). The material of the chip body 3301 is silicon carbide (SIC). SIC can increase the operating frequency of the chip 330 and reduce the size of the chip 330 at the same operating frequency, so that more space can be secured on the first metal brazing substrate 32 for mounting electronic components such as thermistors or gate resistors of the power module 30. Furthermore, the higher operating frequency of the chip 330 helps to reduce the size of electronic components such as capacitors and coils around the power module 30.

[0091] In some implementations of the present application, the first row formed by the first sources 3302, the second sources 3303, and the gate lines 3305 on all chips 330 in one chipset 33 are located on the same side of the chips 330. Specifically, all chips 330 in one chipset 33 face the same direction.

[0092] FIG. 10A is a diagram of an assembly of the first metal brazing substrate, the chip set, and the clip. FIG. 10B is a schematic enlarged view of a partial region A1 of FIG. 10A. FIG. 11A is a diagram of the assembly of the first metal brazing substrate, the chip set, and the clip from another perspective. FIG. 11B is a schematic enlarged view of a partial region A2 of FIG. 11A. The clip 34 covers the side of the chip set 33 away from the first metal brazing substrate 32. The clip 34 is electrically connected to a first source 3302, and the clip 34 is electrically connected to a second source 3303.

[0093] In the related art, the electrical connection of semiconductor chips in a power module is mainly realized by using aluminum wire welding technology. When a large number of chips are arranged in a power module, the amount of aluminum wires increases accordingly. A large amount of aluminum wires increases the parasitic inductance of the power module. In addition, when multiple chips are connected in parallel, multiple aluminum wires are used for connection. This causes uneven currents between multiple chips connected in parallel. This uneven current causes uneven heating by the chips connected in parallel. The intense localized heating affects the performance of the chips, and therefore the performance of the power module.

[0094] In the present application, multiple chips 330 in a chipset 33 are connected in parallel through one clip 34. The connection path on the clip 34 is larger than the connection path on the aluminum wire. This strengthens the connection between the multiple chips 330 in the chipset 33, improves the consistency between the parasitic parameters of the parallel chips 330, and thus optimizes the dynamic current equalization between the multiple parallel chips 330. In addition, the clip 34 can further improve the structural reliability of the interconnection between the multiple chips 330 and ensure the stability of current transmission. In addition, compared with the case where the multiple chips 330 are connected in parallel through multiple aluminum wires, the structure of the power module 30 can be simplified when the clip 34 is arranged.

[0095] The aluminum wire and the chip make a point contact, and there is a high possibility that the aluminum wire will peel off from the chip. However, the clip 34 and the chip 330 make a surface contact, and therefore the connection strength between the clip 34 and the chip 330 is improved. This improves the structural reliability between the multiple chips 330, and ensures the stability of current transmission.

[0096] Additionally, the chips 330 in the chip set 33 are arranged linearly along the first direction, and the clip 34 covers the side of the chip set 33 away from the first metal brazing substrate, thereby connecting two adjacent chips 330 along the shortest linear path.

[0097] Please refer to Figures 10A, 10B, 11A, 11B, and 12. Figure 12 is a three-dimensional view of a clip according to an embodiment of the present application. The clip 34 includes a body 341, a plurality of connection units 342, and at least one connection arm 343. The body 341 covers the side of the mounting metal layer 323 away from the first insulating substrate 321. The plurality of connection units 342 are fixed to the body 341. Every two adjacent connection units 342 are connected via the body 341 along a first direction. In some implementations of the present application, every two adjacent chips 330 in the chip set 33 (as shown in Figure 8) form a gap 3300 along the first direction. An orthogonal projection of the body 341 connected between the two connection units 342 along the first direction falls at least partially within the area on the first metal brazing substrate 32 where the corresponding gap 3300 is located. The connection unit 342 contacts the first source 3302 and the second source 3303 to realize a parallel connection between all the chips 330 in the chipset 33. The connection arm 343 is connected to the mounting metal layer 323.

[0098] The clip 34 connects the first sources 3302 of the multiple chips 330 in the chip set 33 to the first metal brazing substrate 32, and connects the second sources 3303 of the multiple chips 330 to the first metal brazing substrate 32. Each connection unit 342 is electrically connected to a corresponding chip 330. Every two adjacent connection units 342 are connected via the body 341 along the first direction. Specifically, the clip 34 realizes the connection between the first sources 3302 of every two chips 330 and the connection between the second sources 3303 of every two chips 330 through the shortest straight path. This can minimize the interconnection parasitic inductance between the multiple chips 330 in the chip set 33, and reduce the risk of high-frequency oscillation during switching process or short-circuit operation condition at high voltage and high current.

[0099] In some embodiments of the present application, the clip 34 is a metal sheet, and the clip 34 is an integral structure formed by pressing. Note that the material of the clip 34 is not limited in the present application, and the method of forming the clip 34 is not limited in the present application, as long as the clip 34 is conductive.

[0100] In some implementations of the present application, the body 341 is a generally flat structure, and the body 341 includes a plurality of connection holes 3411 spaced apart along the first direction and used for disposing the connection units 342 .

[0101] The number of the connection units 342 corresponds to the number of the chips 330 in the chipset 33. Each connection unit 342 is disposed relative to one connection hole 3411. The connection unit 342 includes a first contact portion 3424, an avoidance space 3425, and a second contact portion 3426, which are sequentially disposed along a first direction. The first contact portion 3424 is connected to the hole wall of the connection hole 3411, and the second contact portion 3426 is connected to the hole wall of the connection hole 3411. The first contact portion 3424 contacts the first source 3302, and the second contact portion 3426 contacts the second source 3303. The avoidance space 3425 and the gate line 3305 are disposed along a second direction. The avoidance space 3425 has an avoidance opening disposed toward the gate line 3305. The position of the avoidance opening is disposed relative to the position of the gate line 3305.

[0102] In some implementations of the present application, the first contact portion 3424 and the second contact portion 3426 are solder pads, and the first contact portion 3424 is connected to the first source 3302 by welding, and the second contact portion 3426 is connected to the first source 3302 by welding.

[0103] The chip is very small in size, and the gate line is easily damaged by stress, leading to chip failure. In the present application, the avoidance space 3425 and the gate line 3305 are arranged along the second direction. Specifically, the avoidance space 3425 is provided at a position corresponding to the gate line 3305 on the clip 34. In this way, the clip 34 is arranged away from the gate line 3305, so that the stress applied by the clip 34 to the gate line 3305 is reduced. This helps to reduce the possibility of the gate line 3305 being damaged and to extend the cycle life of the power module 30.

[0104] In some implementations of the present application, the avoidance space 3425 is a groove that penetrates the clip 34 along the second direction, and the avoidance space 3425 extends from the end of the contact section 3429 of the second contact portion 3426 away from the connection section 3427 of the second contact portion 3426 to the end connected to the connection hole 3411 of the connection section 3427 of the second contact portion 3426, increasing the length of the avoidance space 3425 and further reducing the stress that the clip 34 applies to the gate line 3305.

[0105] In some implementations of the present application, the first contact portion 3424 and the second contact portion 3426 each include a connection section 3427 and a contact section 3429 that are fixed to each other. The connection section 3427 is bent with respect to the body 341. The connection section 3427 of the first contact portion 3424 is connected between the hole wall of the connection hole 3411 and the contact section 3429 of the first contact portion 3424. The connection section 3427 of the second contact portion 3426 is connected between the hole wall of the connection hole 3411 and the contact section 3429 of the second contact portion 3426. The vertical distance between the contact section 3429 and the chip 330 along the second direction is smaller than the vertical distance between the body 341 and the chip 330 along the second direction. The contact section 3429 is connected to the body 341 via the connection section 3427. In this manner, the body 341 and the mounting metal layer 323 are separated by the plastic package body 35. In some implementations of the present application, the connection section 3427 includes a curved structure. The curved structure can reduce the possibility of damaging the clip 34 during molding. It can be understood that the connection section 3427 can alternatively be a flat structure.

[0106] The plastic package body will delaminate at the bending position of the mechanical part or at the continuous large-area flat area of ​​the mechanical part, which will affect the sealing performance of the power module. A first locking hole 3415 is provided at the joint between the connection section 3427 and the body 341, and a second locking hole 3417 is provided on the body 341. The first locking hole 3415 and the second locking hole 3417 are filled with the plastic package body 35. The first locking hole 3415 is provided at the joint between the connection section 3427 and the body 341, and the first locking hole 3415 is filled with the plastic package body 35, which reduces the possibility of the plastic package body 35 delaminating at the joint between the body 341 and the connection section 3427 and / or the plastic package body 35 delaminating and spreading to the surface of the chip 330. This helps to improve the sealing performance of the power module 30. The second locking hole 3417 is provided in the body 341, and the plastic package body 35 is filled in the second locking hole 3417, thereby reducing the possibility of the plastic package body 35 delaminating on the body 341 or the possibility of the plastic package body 35 delaminating and spreading to the surface of the chip 330. This helps to improve the sealing performance of the power module 30. The shape of the first locking hole 3415 is not limited to a circle, an ellipse, a slot hole shape, etc. The shape of the second locking hole 3417 is not limited to a circle, an ellipse, a slot hole shape, etc.

[0107] FIG. 13A is a perspective view of an assembly of a first metal brazing substrate, a chip set, and a clip. FIG. 13B is a schematic enlarged view of a partial region A3 of FIG. 13A. Each connection arm 343 is disposed for two adjacent chips 330 in the chip set 33, and the connection arm 343 is connected to the first metal brazing substrate 32. The shortest distance between the connection arm 343 and one of the two adjacent chips 330 is a first shortest distance B1. The shortest distance between the connection arm 343 and the other of the two adjacent chips 330 is a second shortest distance B2. The difference between the first shortest distance B1 and the second shortest distance B2 is not more than 30% of the first shortest distance.

[0108] One of the two adjacent chips 330, the clip 34 and the first metal brazing substrate 32 form a first interconnection path, and the other chip 330, the clip 34 and the first metal brazing substrate 32 form a second interconnection path. The first interconnection path and the second interconnection path are approximately symmetrical. This can balance the current paths between the chips 330, reduce the difference between the parasitic parameters of the chips 330, and further improve the dynamic current equalization characteristics of the parallel chips 330. The shortest distance between the connection arm 343 and one of the two adjacent chips 330 along the first direction is equal to or approximately equal to the shortest distance between the connection arm 343 and the other of the two adjacent chips 330 along the first direction.

[0109] The chip 330 is substantially square-shaped. The chip 330 includes four connected chip edges 3309. The joint between each two chip edges 3309 forms an intersection. An intersection of a first chip 330 of two adjacent chips 330 in the chip set 33 that is closest to the connection arm 343 corresponding to the first chip 330 is defined as E1. An intersection of a second chip 330 of two adjacent chips 330 that is closest to the connection arm 343 corresponding to the second chip 330 is defined as E2. E1 and E2 are disposed substantially along the first direction. E2 is located on the side of the second chip 330 that is closer to the first chip 330 along the first direction. E1 is located on the side of the first chip 330 that is closer to the connection arm 343 along the third direction.

[0110] The joint between the connecting arm 343 and the first metal brazing substrate 32 is located on the midline C2 of the shortest connecting line C1 between two adjacent chips 330. In some implementations of the present application, the connecting arm 343 includes a first edge 3431 and a second edge 3433 arranged to face each other along a first direction. Both the first edge 3431 and the second edge 3433 are fixed to the body 341. The connection point between the first edge 3431 and the body 341 is D1, and the connection point between the second edge 3433 and the body 341 is D2. The shortest distance between D1 and E1 is the first shortest distance B1. The connection point between the second edge 3433 and the body 341 is D2, and the shortest distance between D1 and E2 is the second shortest distance B2.

[0111] In some implementations of the present application, the connecting arm 343 is bent relative to the body 341 , and a third locking groove 3418 is provided at the joint between the connecting arm 343 and the body 341 .

[0112] In some implementations of the present application, the connection arm 343 is axisymmetric about the midline C2, and multiple clips 34 of the same structure can be used in the power module 30. This facilitates assembly of the power module 30 and reduces the cost of the power module 30. It can be understood that the connection arm 343 does not have to be axisymmetric about the midline C2.

[0113] It is understood that the structure of the connecting arm 343 is not limited in this application.

[0114] In some implementations of the present application, FIG. 14 is a top view showing an assembly of the first metal brazing substrate, the chip set, and the clip, and FIG. 15 is a top view showing an assembly of the first metal brazing substrate and the chip set. There are a plurality of mounting metal layers 323, and the plurality of mounting metal layers 323 are spaced apart on the first insulating substrate 321. A trench 3230 is formed between every two adjacent mounting metal layers 323 so that the plurality of mounting metal layers 323 are insulated from each other. The plurality of mounting metal layers 323 includes a first mounting metal layer 3231, a second mounting metal layer 3232, a third mounting metal layer 3233, and a fourth mounting metal layer 3234. The first mounting metal layer 3231 and the third mounting metal layer 3233 are electrically connected to the input terminal 301. The second mounting metal layer 3232 is electrically connected to the output terminal 303. The fourth mounting metal layer 3234 is electrically connected to the input terminal 301. The first mounting metal layer 3231, the second mounting metal layer 3232, and the third mounting metal layer 3233 are sequentially arranged along the third direction. The second mounting metal layer 3232 includes a first extension 3235, a groove 3236, and a second extension 3237. An end of the first extension 3235 is connected to an end of the second extension 3237. The first extension 3235 and the second extension 3237 surround a groove 3236 that accommodates the fourth mounting metal layer 3234. At least a portion of the fourth mounting metal layer 3234 is located within the groove 3236. Along the third direction, the first mounting metal layer 3231 and the first extension 3235 are located on a first side of the fourth mounting metal layer 3234, and the third mounting metal layer 3233 and the second extension 3237 are located on a second side of the fourth mounting metal layer 3234. It is understood that the positions of the first mounting metal layer 3231, the second mounting metal layer 3232, the third mounting metal layer 3233 and the fourth mounting metal layer 3234 are not limited in this application.

[0115] In some implementations of the present application, there are multiple chipsets 33 that help improve the operating efficiency of the power module 30. The multiple chipsets 33 include a first chipset 331, a second chipset 332, a third chipset 333, and a fourth chipset 334. The first chipset 331 is disposed on the first mounting metal layer 3231. The second chipset 332 is disposed on the C3235. The third chipset 333 is disposed on the third mounting metal layer 3233. The fourth chipset 334 is disposed on the second extension 3237. The first chipset 331, the second chipset 332, the fourth chipset 334, and the third chipset 333 are disposed sequentially along the third direction.

[0116] In some implementations of the present application, the spacing between every two adjacent chips 330 in all chip sets 33 along the first direction is the same to improve consistency between the parasitic parameters of the parallel chips 330 in all chip sets 33 in the power module 30. For example, the spacing between every two adjacent chips 330 along the first direction in the first chip set 331 is a first spacing, the spacing between every two adjacent chips 330 along the first direction in the second chip set 332 is a second spacing, the spacing between every two adjacent chips 330 along the first direction in the third chip set 333 is a third spacing, and the spacing between every two adjacent chips 330 along the first direction in the fourth chip set 334 is a fourth spacing, and the first spacing, the second spacing, the third spacing, and the fourth spacing are the same. It is understood in the present application that the spacing between every two adjacent chips 330 in all chip sets 33 along the first direction does not need to be the same.

[0117] Clips 34 are arranged on the side of each of the first chipset 331, the second chipset 332, the third chipset 333, and the fourth chipset 334 that is farther from the first insulating substrate 321. The clips 34 on the first chipset 331 are electrically connected to the second mounting metal layer 3232. The clips 34 on the second chipset 332 are electrically connected to the fourth mounting metal layer 3234. The clips 34 on the third chipset 333 are electrically connected to the second extension portion 3237. The clips 34 on the fourth chipset 334 are electrically connected to the fourth mounting metal layer 3234.

[0118] The connection arm 343 of the clip 34 on the first chipset 331 is electrically connected to the first extension 3235. The connection arm 343 of the clip 34 on the second chipset 332 is electrically connected to the fourth mounting metal layer 3234. The connection arm 343 of the clip 34 on the third chipset 333 is electrically connected to the second extension 3237. The connection arm 343 of the clip 34 on the fourth chipset 334 is electrically connected to the fourth mounting metal layer 3234. The clip 34 is connected to the corresponding mounting metal layer 323 through the connection arm 343. There are one or more connection points between the clip 34 and the corresponding mounting metal layer 323. The distance between each connection arm 343 and the two chips 330 closest to the connection arm 343 is equal or approximately equal, and the path is symmetrical. This achieves symmetry in the interconnection paths between the chips 330 and the mounting metal layers 323 connected to the chips 330, helps balance the current paths of the chips 330, and reduces the differences between the parasitic parameters of the chips 330, thus improving the dynamic current equalization characteristics of the parallel chips 330.

[0119] In some implementations of the present application, along the third direction, the first source 3302 of the chip 330 in the first chipset 331 is disposed on a side of the chip 330 closer to the third chipset 333, the first source 3302 of the chip 330 in the second chipset 332 is disposed on a side of the chip 330 closer to the third chipset 333, the first source 3302 of the chip 330 in the third chipset 333 is disposed on a side of the chip 330 closer to the first chipset 331, and the first source 3302 of the chip 330 in the fourth chipset 334 is disposed on a side of the chip 330 closer to the first chipset 331. Specifically, the first chipset 331 and the second chipset 332 face in the same direction, and the third chipset 333 and the fourth chipset 334 face in the same direction. The connection arm 343 of the clip 34 on the first chipset 331 is disposed on a side facing the first extension portion 3235 of the main body 341 on the first chipset 331. The connection arm 343 of the clip 34 on the second chipset 332 is disposed on a side facing the second extension portion 3237 of the main body 341 on the second chipset 332. The connection arm 343 of the clip 34 on the third chipset 333 is disposed on a side facing the second extension portion 3237 of the main body 341 on the third chipset 333. The connection arm 343 of the clip 34 on the fourth chipset 334 is disposed on a side facing the first extension portion 3235 of the main body 341 on the fourth chipset 334. Specifically, the clip 34 on the first chipset 331 and the clip 34 on the second chipset 332 face in the same direction, and the clip 34 on the third chipset 333 and the clip 34 on the fourth chipset 334 face in the same direction.

[0120] The clips 34 on the first chipset 331 and the clips 34 on the second chipset 332 face the same direction, the clips 34 on the third chipset 333 and the clips 34 on the fourth chipset 334 face the same direction, the first chipset 331 and the second chipset 332 face the same direction, and the third chipset 333 and the fourth chipset 334 face the same direction. In this manner, the interconnection path between the clips 34 on the first chipset 331 and the first extension 3235 is approximately mirror symmetrical to the interconnection path between the clips 34 on the third chipset 333 and the second extension 3237, and the interconnection path between the clips 34 on the second chipset 332 and the fourth mounting metal layer 3234 is approximately mirror symmetrical to the interconnection path between the clips 34 on the fourth chipset 334 and the fourth mounting metal layer 3234. This balances the current paths of the chip set 33 and reduces the difference between the parasitic parameters of the chips 330 , thus further improving the dynamic current equalization characteristics of the parallel chips 330 .

[0121] In some implementations of the present application, the input terminal 301 is disposed at a first end of the power module 30, and the output terminal 303 is disposed at a second end of the power module 30. The power pins of the input terminal 301 include a first positive power pin 361, a second positive power pin 363, and a third negative power pin 365. The first positive power pin 361 is electrically connected to the first mounting metal layer 3231. The second positive power pin 363 is electrically connected to the third mounting metal layer 3233. The third negative power pin 365 is electrically connected to the fourth mounting metal layer 3234. The output terminal 303 is electrically connected to the second mounting metal layer 3232. Along the third direction, the third negative power pin 365 is located between the first positive power pin 361 and the second positive power pin 363.

[0122] In some implementations of the present application, the power module 30 is a half-bridge type power module, and the power module 30 further includes an upper bridge section and a lower bridge section. The upper bridge section includes a first chipset 331, a third chipset 333, a first positive power pin 361, and a second positive power pin 363. The lower bridge section includes a second chipset 332, a fourth chipset 334, and a third negative power pin 365. The three power pins are located at the input terminal 301. This helps to increase the amount of current flow of the power module 30 at the input terminal 301, reduce the parasitic inductance in the power loop, and reduce switching losses.

[0123] The first positive power pin 361, the first mounting metal layer 3231, the first chipset 331, the clip 34 on the first chipset 331, the first extension 3235, and the output terminal 303 may form a first current flow path. The second positive power pin 363, the third mounting metal layer 3233, the third chipset 333, the clip 34 on the third chipset 333, the second extension 3237, and the output terminal 303 may form a second current flow path. The output terminal 303, the first extension 3235, the second chipset 332, the clip 34 on the second chipset 332, the fourth mounting metal layer 3234, and the third negative power pin 365 may form a third current flow path. The output terminal 303, the second extension 3237, the fourth chipset 334, the clip 34 on the fourth chipset 334, the fourth mounting metal layer 3234, and the third negative power pin 365 may form a fourth current path. The first current path is generally symmetrical to the second current path, and the third current path is generally symmetrical to the fourth current path.

[0124] The direction of the current may be the first positive power pin 361 , the first mounting metal layer 3231 , the first chipset 331 , the clip 34 on the first chipset 331 , the first extension 3235 , and the output terminal 303 .

[0125] The direction of the current may be through the second positive power pin 363 , the third mounting metal layer 3233 , the third chipset 333 , the clip 34 on the third chipset 333 , the second extension 3237 , and the output terminal 303 .

[0126] The direction of the current may be through the output terminal 303 , the first extension 3235 , the second chipset 332 , the clip 34 on the second chipset 332 , the fourth mounting metal layer 3234 , and the third negative power pin 365 .

[0127] The direction of the current may be through the output terminal 303 , the second extension 3237 , the fourth chipset 334 , the clip 34 on the fourth chipset 334 , the fourth mounting metal layer 3234 , and the third negative power pin 365 .

[0128] It can be understood that two of the first positive power pin 361, the second positive power pin 363, and the third negative power pin 365 are negative pins, and the other of the first positive power pin 361, the second positive power pin 363, and the third negative power pin 365 is a positive pin.

[0129] It can be understood that the number of power pins in the input terminal 301 is not limited, provided that the input terminal 301 includes pins of different polarities.

[0130] Further, as shown in FIG. 7, a first bonding layer 36 is further provided between the mounting metal layer 323 and the side of the chip 330 away from the clip 34. The first bonding layer 36 is configured to fix the chip 330 to the corresponding mounting metal layer 323. In a possible implementation, the first bonding layer 36 is a sintered material. Specifically, the chip 330 is connected to the mounting metal layer 323 through the sintered material. For example, the sintered material may be composed of silver paste, copper paste, or silver film. The silver paste may include at least one of micrometer silver particle paste and nanometer silver particle paste. The micrometer silver particle paste is a silver paste prepared using micrometer silver particles and an organic solvent, which is cost-effective and safe. The sintering is usually performed under pressure. The sintered material has a high density, and the interface of the joint is firmly bonded, resulting in high joint reliability.

[0131] The sintering material in this application may use micrometer silver particle paste to improve the reliability of the bond during sintering and reduce the cost.

[0132] In order to improve the reliability of the bond during sintering, a material can be added to the sintering material to adjust the elastic modulus, coefficient of thermal expansion (CTE), etc. of the sintering material. For example, the sintering material includes a main material and a filler added to the main material. The main material includes at least one of silver paste, copper paste, and silver film. The filler is made of a material that can be well bonded to the main material, and the thermal expansion coefficient of the filler is smaller than that of the main material. This improves the reliability of the bond during sintering.

[0133] For example, the main material is a micrometer silver particle paste. By adding a filler to the micrometer silver particle paste, the thermal expansion coefficient of the micrometer silver particle paste is reduced, and the bonding stress is reduced, thereby improving the reliability of the bonding during silver sintering. The filler can include, for example, at least one of nickel (Ni), Ni alloy, copper (Cu), copper-plated nickel, titanium (Ti), Ti alloy, iron (Fe), Fe alloy, Kovar alloy (Kovar, Fe-Ni-Co alloy 4J29), SiC powder, etc. This is not limited here.

[0134] In the present application, the mounting metal layer 323 is usually made of copper. In addition, when the sintering material is made of silver paste or silver film, the mounting metal layer 323 may be silver plated at the sintering position to improve the performance of the joint between the sintering material and the mounting metal layer 323. Specifically, the area of ​​the mounting metal layer 323 corresponding to the sintering material is covered with a silver plating layer. For example, the thickness of the silver plating layer can be 0.1 μm to 30 μm. If the sintering material itself can be well joined to the first metal brazing substrate 32, it is alternatively possible to not apply silver plating. For example, when the sintering material is copper paste, it is not necessary to apply silver plating to the sintering position of the first metal brazing substrate 32.

[0135] It will be appreciated that the first bonding layer 36 may alternatively be solder. Specifically, the chip 330 is connected to the mounting metal layer 323 using a welding process.

[0136] It can be seen that the first bonding layer 36 comprises at least one of a solder and a sintered material.

[0137] Please refer to Fig. 7, Fig. 16A, Fig. 16B. Fig. 16A is a three-dimensional view of the assembly of the power module without the plastic package body. Fig. 16B is a schematic enlarged view of the partial area A4 of Fig. 16A. In a possible implementation, the power module 30 further includes a second metal brazing substrate 37 and an electronic component 38 (as shown in Fig. 16B). The second metal brazing substrate 37 is located on the side of the mounting metal layer 323 of the first metal brazing substrate 32 away from the first insulating substrate 321. The electronic component 38 is located on the side of the second metal brazing substrate 37 away from the first metal brazing substrate 32 and is electrically connected to the second metal brazing substrate 37.

[0138] Electronic components are usually small. Therefore, when an electronic component is directly welded to the first metal brazing substrate 32, it is necessary to provide an insulating trench in the metal layer of the first metal brazing substrate 32 and electrically connect two electrodes of the electronic component to the metal layer on both sides of the insulating trench. When an insulating trench is provided in the first metal brazing substrate 32, the layout space of the chip 330 becomes small. In addition, since a large number of chips 330 are arranged on the first metal brazing substrate 32, if a trench is provided by etching in the metal layer of the first metal brazing substrate 32, the chips 330 and other electronic components arranged in advance may be damaged. In this mounting, the electronic components are connected via the second metal brazing substrate 37, so the welding process of the electronic components is simple. Compared to the case where an electronic component is directly welded to the metal layer of the first metal brazing substrate 32, the process of providing an insulating trench in the metal layer of the first metal brazing substrate 32 can be omitted, so the circuit design of the first metal brazing substrate 32 is simplified. Depending on the size of the electronic component and the positions of the two electrodes of the electronic component, an insulating trench may be provided in advance in the second metal brazing substrate 37. The insulating trench is provided by etching on the second metal brazing substrate 37 so as not to affect the performance of the chip 330 on the first metal brazing substrate 32. The electronic component is then electrically connected to the second metal brazing substrate 37.

[0139] The second metal brazing substrate 37 includes a second insulating substrate 371 and metal layers located on both sides of the second insulating substrate 371. The electronic component 38 is electrically connected to the metal layers on the side of the second insulating substrate 371 away from the first metal brazing substrate 32.

[0140] In a possible implementation, the electronic component 38 includes a gate resistor 381 (as shown in FIG. 7 and FIG. 16b), and the second metal brazing substrate 37 is disposed on the mounting metal layer 323, and the second metal brazing substrate 37 includes a first substrate electrode 375 and a second substrate electrode 377 that are insulated and spaced apart from each other. Both ends of the gate resistor 381 are electrically connected to the first substrate electrode 375 and the second substrate electrode 377, respectively. The first substrate electrode 375 is configured to receive a drive current. The second substrate electrode 377 is electrically connected to the gate 3306 of the chip 330 via the first conductive wire 380. Since the gate resistor 381 is connected via the second metal brazing substrate 37, the welding process of the gate resistor 381 is simple.

[0141] The first substrate electrode 375 and the second substrate electrode 377 are part of a metal layer on the second insulating substrate 371. The insulation between the first substrate electrode 375 and the second substrate electrode 377 is arranged based on the size of the gate resistor 381, so that the first substrate electrode 375 and the second substrate electrode 377 are insulated and spaced apart from each other.

[0142] For example, a trench is provided between the first board electrode 375 and the second board electrode 377, and the first board electrode 375 and the second board electrode 377 are insulated and separated from each other based on the trench. The first board electrode 375, the second board electrode 377 and the trench may be formed by performing an etching process on a metal layer on one surface of the second metal brazing substrate 37.

[0143] In some implementations of the present application, as shown in FIG. 16B, a terminal metal layer 324 is further disposed on the surface of the first metal brazing substrate 32 facing the chip 330. The terminal metal layer 324 is located at the end of the first metal brazing substrate 32 where the output terminal 303 is located. The second metal brazing substrate 37 is disposed adjacent to the terminal metal layer 324. The terminal metal layer 324 is electrically connected to the second metal brazing substrate 37 via a second conductive wire 391. The second metal brazing substrate 37 is disposed adjacent to the terminal metal layer 324 to shorten the wiring length between the second metal brazing substrate 37 and the terminal metal layer 324. This helps to improve the space utilization of the power module 30.

[0144] The power module 30 further includes a signal terminal 392 (as shown in FIG. 16B). The signal terminal 392 is disposed on the terminal metal layer 324. An external control circuit sends a driving current to the signal terminal 392. After the first substrate electrode 375 receives the driving current, the driving current sequentially passes through the signal terminal 392, the terminal metal layer 324, the second conductive line 391, the first substrate electrode 375, the gate resistor 381, the second substrate electrode 377, and the first conductive line 380, as shown in FIG. 16B, and then flows to the gate 3306 of the chip 330. After receiving the driving current, the gate 3306 can drive the conduction between the first source 3302 and the second source 3303. The gate resistor 381 is configured to improve the switching performance of the chip 330, and can suppress high-frequency oscillations that occur when multiple chips 330 are connected in parallel. The first conducting wire 380 and the second conducting wire 391 are transmission wiring such as aluminum wire or copper wire.

[0145] The second metal brazing substrate 37 further includes a metal layer located on the side of the second insulating substrate 371 away from the first substrate electrode 375 and the second substrate electrode 377. The metal layer is welded to the mounting metal layer 323 on the surface of the first metal brazing substrate 32 via solder. The solder may be at least one of tin solder and lead solder. The tin solder may be at least one of SnSb5, SnSb8, SnSbAg, SAC305, multi-component reinforced SAC, and SnSb10.

[0146] The gate resistor 381 may be welded to the first substrate electrode 375 and the second substrate electrode 377 via solder.

[0147] The signal terminal 392 may be welded to the terminal metal layer 324 at the end of the first metal brazing substrate 32 via solder. The solder may be at least one of tin solder and lead solder. The tin solder may be at least one of SnSb5, SnSb8, SnSbAg, SAC305, multi-component reinforced SAC, and SnSb10.

[0148] Specifically, when there is one gate resistor 381 and one second metal brazing substrate 37, the gates 3306 of the multiple chips 330 of the first chip set 331 are electrically connected to the gate resistor 381 on the same second metal brazing substrate 37 via conductive wires. Specifically, the one gate resistor 381 controls the conduction or cutoff between the first source 3302 and the second source 3303 of the multiple chips 330.

[0149] Specifically, there are a plurality of gate resistors 381 and a plurality of second metal brazing substrates 37, and when each gate resistor 381 is disposed on the second metal brazing substrate 37, the gate 3306 of each chip 330 is electrically connected to the gate resistor 381 on the second metal brazing substrate 37 via a conductive wire. Specifically, one gate resistor 381 controls the conduction or cutoff between the first source 3302 and the second source 3303 of one chip 330. For example, there are a plurality of gate resistors 381, the plurality of gate resistors 381 including a first gate resistor 3811, a second gate resistor 3812, a third gate resistor 3813, and a fourth gate resistor 3814, the first chipset 331 is connected in series with the first gate resistor 3811, the second chipset 332 is connected in series with the second gate resistor 3812, the third chipset 333 is connected in series with the third gate resistor 3813, and the fourth chipset 334 is connected in series with the fourth gate resistor 3814. It is understood that one or more of the first chipset 331, the second chipset 332, the third chipset 333, and the fourth chipset 334 are connected in series with the gate resistor 381, or the power module 30 is not provided with the gate resistor 381.

[0150] When an electronic component is directly welded to the first metal brazing substrate 32, it is necessary to pass a current through the electronic component, and therefore it is necessary to arrange two connection electrodes on the first metal brazing substrate 32 that are insulated from each other and spaced apart. For example, a connection metal layer is provided by etching on the metal layer on the side of the first metal brazing substrate 32 that is far from the first insulating substrate 321. The connection metal layer is insulated from and spaced apart from other parts of the other mounting metal layers. Next, a trench is provided on the connection metal layer by etching to form two connection electrodes that are insulated from each other and spaced apart. In this case, it is necessary to remove a part of the connection metal layer between the two connection electrodes and a part of the metal weld layer by etching. The size of the etching along the third direction Z is large. As a result, the opening size of the trench between the two connection electrodes becomes large. That is, the size between the two connection electrodes becomes large. However, the electronic component (e.g., the gate resistor 381) is small in size and cannot be welded to the two connection electrodes, or the reliability of the welding may be low.

[0151] Therefore, in this mounting, the electronic component 38 is connected via the second metal brazing substrate 37. Since the metal on the second metal brazing substrate 37 is directly bonded to the second insulating substrate 371, the formed first substrate electrode 375 and second substrate electrode 377 are also directly attached to the surface of the second insulating substrate 371. No metal weld layer is provided between the first substrate electrode 375 and the second insulating substrate 371, or between the second substrate electrode 377 and the second insulating substrate 371. When forming the first substrate electrode 375 and the second substrate electrode 377 by providing a trench by etching, it is not necessary to form a metal weld layer by etching, so that the size between the first substrate electrode 375 and the second substrate electrode 377 can be controlled to be small. This makes it easier to weld electronic components (for example, the gate resistor 381).

[0152] In the implementation, the first metal brazing substrate 32 is an active metal welded substrate. The active metal welded substrate is obtained by welding metal layers such as copper layers and aluminum layers to both sides of an insulating substrate with metal solder. The circuits required for the power module 30, such as the mounting metal layer 323 and the terminal metal layer 324, are obtained by etching the copper layer. The first insulating substrate 321 on the first metal brazing substrate 32 can be made of materials such as Si3N4 and AlN, so that the welding between the first insulating substrate 321 and the metal layers on both sides is more reliable and good thermal conductivity is achieved. This can improve the heat dissipation effect of the power module 30.

[0153] In the implementation, the second metal brazing substrate 37 is a copper-clad ceramic substrate. The second insulating substrate 371 is an Al2O3 ceramic substrate or an AlN ceramic substrate, and a metal layer (e.g., copper foil) is directly bonded to the second insulating substrate 371 at high temperature. For example, copper foil is directly bonded to the Al2O3 ceramic substrate at high temperature, and the first substrate electrode 375 and the second substrate electrode 377 are formed by the copper foil as necessary. Since no other metal layer is provided between the copper foil and the Al2O3 ceramic substrate, the distance between the first substrate electrode 375 and the second substrate electrode 377 is small. This makes it easier to weld the gate resistor 381.

[0154] In a possible implementation, the first metal brazing substrate 32 is an insulating metal substrate. The insulating metal substrate includes an insulating resin layer and a metal layer located on both sides of the insulating resin layer. When the thickness value of the metal layer is 0.6 mm or more, the power module 30 has a high power density, and the second metal brazing substrate 37 may be arranged to connect electronic components, so as to reduce the difficulty of the welding process of the electronic components.

[0155] 16B, in a possible implementation, the power module 30 includes two second metal brazing substrates 37, both of which may be used to weld the gate resistor 381, and one of the second metal brazing substrates 37 may further be used to weld the thermistor 383. In some implementations, one second metal brazing substrate 37 may be used to weld the thermistor 383.

[0156] In this embodiment, the electronic component 38 further includes a thermistor 383, the thermistor 383 is disposed proximate to the chip 330, and the thermistor 383 is configured to monitor the temperature of the chip 330. The second metal brazing substrate 37 further includes a third substrate electrode 378 and a fourth substrate electrode 379 insulated and spaced apart from each other. Both ends of the thermistor 383 are electrically connected to the third substrate electrode 378 and the fourth substrate electrode 379, respectively. In some implementations, the second metal brazing substrate 37 is disposed on a side of the third mounting metal layer 3233 away from the first insulating substrate 321 and adjacent to the chip 330 disposed on the third mounting metal layer 3233, and the thermistor 383 is configured to monitor the temperature of the chip 330. Specifically, the second metal brazing substrate 37 connecting the chip 330 and the thermistor 383 is disposed on the same metal layer. For example, both are disposed on the third mounting metal layer 3233, both are disposed on the first mounting metal layer 3231, or both are disposed on the second mounting metal layer 3232. In the present application, it is not necessary that the second metal brazing substrate 37 for connecting the thermistor 383 is disposed on the third mounting metal layer 3233. In another implementation, both the chip 330 and the second metal brazing substrate 37 for connecting the thermistor 383 are disposed on another metal layer according to the design requirements of the power module 30.

[0157] Thermistor 383 may be welded to first board electrode 375 and second board electrode 377 via solder.

[0158] The second metal brazing substrate 37 may be welded to the surface of the mounting metal layer 323 remote from the first insulating substrate 321 via solder.

[0159] In this implementation, the first metal braze substrate 32 is one of an active metal weld substrate and an insulated metal substrate, and the second metal braze substrate 37 is a copper clad ceramic substrate.

[0160] In some implementations, the metal layer on the second metal brazing substrate 37 may function as a signal line. This helps to improve the flexibility of the wiring distribution in the power module 30. Some wiring may be made using the metal layer on the first metal brazing substrate 32 and some wiring may be made using the metal layer on the second metal brazing substrate 37 so that the wiring distribution is more flexible.

[0161] In a possible implementation, FIG. 17 is a three-dimensional view of a clip according to an embodiment of the present application, and FIG. 18 is a connection view of a part of a clip with a chip according to an embodiment of the present application. The body 341 and the connection unit 342 are alternately arranged along the first direction, and one body 341 is connected between two connection units 342. This can reduce the width of the body 341 along the third direction, and can reduce the manufacturing cost of the clip 34. Along the first direction, the first contact portion 3424 of the connection unit 342 at the first end of the clip 34 is fixed to the adjacent body 341, the second contact portion 3426 of the connection unit 342 at the second end of the clip 34 is fixed to the adjacent body 341, and both the first contact portion 3424 and the second contact portion 3426 of the connection unit 342 at the non-end position of the clip 34 are fixed to the body 341. The first contact 3424 is in contact with and electrically connected to the first source 3302 , and the second contact 3426 is in contact with and electrically connected to the second source 3303 .

[0162] The connection unit 342 further includes a bent portion 3428. The bent portion 3428 is connected between the first contact portion 3424 and the second contact portion 3426 along the first direction. The bent portion 3428 protrudes along a direction away from the first insulating substrate 321. The first contact portion 3424, the bent portion 3428 and the second contact portion 3426 surround an avoidance space 3425. The avoidance space 3425 and the gate line 3305 are arranged along the second direction. The avoidance space 3425 has an avoidance opening arranged toward the corresponding chip 330, and a gap is formed between the bent portion 3428 and the corresponding chip 330, and the bent portion 3428 does not contact the gate line 3305 of the chip 330. The first contact portion 3424 is fixed to the second contact portion 3426 through the bent portion 3428. This helps to increase the strength of the clip 34. The bent portion 3428 is provided with a buffer hole 3435 penetrating the bent portion 3428 along the second direction. The buffer hole 3435 is configured to relieve and buffer the stress applied by the clip 34 to the chip 330. This reduces the possibility that the chip 330 is damaged by the stress applied by the clip 34, and can extend the cycle life of the power module 30. The buffer hole 3435 may be a through hole penetrating the bent portion 3428 along the second direction. The buffer hole 3435 may alternatively not be a through hole. The buffer hole 3435 may be circular, square, etc. The shape of the buffer hole 3435 is not limited in this application.

[0163] The power module 30 provided in the present application uses a design with three power pins, and the sources (including the first source 3302 and the second source 3303) on the surface of the chip 330 away from the first metal brazing substrate 32 are connected via a clip 34, realizing the interconnection between multiple chips 330, and no built-in gate resistor is used, or the amount of gate resistor used is less than that of parallel chips. Thus, higher electrical performance is achieved.

[0164] The power module 30 provided herein uses a solution having one-sided direct cooling, chips sintered with silver onto a first metal braze substrate (AMB) 32, sources of parallel chips 330 connected to a metal layer on the first metal braze substrate 32 via clips 34, and a second metal braze substrate (DBC) 37, which further improves the power density and reliability of the power module 30.

[0165] In this application, a design with three power pins and a design with multiple chips connected in parallel to a clip are provided, which greatly reduces the parasitic inductance and switching loss of the power loop and greatly improves the current equalization characteristics of the power loop.

[0166] In this application, a clip design for the power module 30 is provided, which improves dynamic current equalization, avoids the risk of high frequency oscillation during switching process and under short circuit operating conditions at high voltage and current, extends the power cycle life of the power module 30, increases the bonding area between the clip 34 and the plastic package body 35, and reduces the possibility of delamination of the plastic package.

[0167] A design is used that does not have gate resistors 381 or has less gate resistors 381 built in than parallel chips, which reduces the amount of components in the package, thereby reducing the module failure rate due to potential component failures, saving layout space on the first metal braze substrate (AMB), and simplifying the packaging process.

[0168] The small-area second metal brazing board 37 can be used for drawing out thermistors 383 and gate resistors 381 and for arranging jumpers for signal loops, which greatly saves layout space on the first metal brazing board, solves the problem that such small surface mounted devices (SMD) on the first metal brazing board (AMB) 32 with thick copper cannot be directly welded, and ensures the reliability of SMD devices.

[0169] The power bars of the power pins are bent, which can effectively reduce the force applied to the plastic package body during module application and improve the reliability of the module.

[0170] The module with heat sink is sintered or welded and then plastic packaged to improve the module reliability. The present application provides a highly reliable plastic packaged module with strong heat dissipation and high power density and a manufacturing solution.

[0171] It should be understood that expressions such as "comprise" and "may include" as used herein indicate the presence of a disclosed feature, operation, or component, and are not limited to one or more additional features, operations, or components. In this application, terms such as "comprise" and / or "having" may be interpreted to indicate a particular feature, amount, operation, component, part, or combination thereof, but should not be interpreted as excluding the possible presence or addition of one or more other features, amounts, operations, components, parts, or combinations thereof.

[0172] Furthermore, as used herein, the term "and / or" includes any and all combinations of the associated listed terms. For example, the term "A and / or B" can include A, can include B, or can include both A and B.

[0173] In the present application, expressions including ordinal numbers such as "first" and "second" may modify an element. However, such elements are not limited by the expressions. For example, these expressions do not limit the order and / or importance of the elements. These expressions are used only to distinguish one element from another element. For example, a first user device and a second user device refer to different user devices, although both the first user device and the second user device are user devices. Similarly, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present application.

[0174] When an element is referred to as being "connected to" or "accessing" another element, it should be understood that the element may be directly connected to or accessing the other element, or that there may be other elements between the element and the other element. Further, when an element is referred to as being "directly connected to" or "directly accessing" another element, it should be understood that there are no elements between the element and the other element.

[0175] The above description is merely a specific implementation of the present application, and is not intended to limit the scope of protection of the present application. Any variations or replacements that are readily conceived by those skilled in the art within the technical scope disclosed in the present application should be encompassed within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims. [Explanation of symbols]

[0176] 30 Power Module 31 Heat sink 32 First metal brazing substrate 33 Chipset 34 clips 35 Plastic package body

Claims

1. 1. A power module, comprising: A first metal brazing substrate; a chip set disposed on the first metal brazing substrate, the chip set including at least two chips linearly disposed along a first direction, the first direction being parallel to a plane in which the chips are spaced apart from the first metal brazing substrate; a clip covering a side of the chipset away from the first metal brazing substrate, the clip including a body, at least two connection units and at least one connection arm, each connection unit being electrically connected to a corresponding chip, each two adjacent connection units being connected along the first direction via the body, the connection arm being arranged convexly on the body; Including, A power module, wherein each connection arm is positioned with respect to two adjacent chips in the chipset, the connection arms are electrically connected to the first metal brazing substrate, a shortest distance between the connection arm and one of the two adjacent chips is a first shortest distance, a shortest distance between the connection arm and the other of the two adjacent chips in the chipset is a second shortest distance, and a difference between the first shortest distance and the second shortest distance is less than or equal to 30% of the first shortest distance.

2. 2. The power module of claim 1, wherein each chip includes a first source and a second source arranged along the first direction, the first source of one chip and the second source of the other chip of two adjacent chips in the chipset are arranged adjacent to each other, the connection unit is electrically connected to the first source and the second source of the corresponding chip, and the connection arm is arranged convexly on the body and extends in a bent manner toward the first metal brazing substrate.

3. Each chip further includes a gate line, the first source, the gate line, and the second source are arranged along the first direction; 3. The power module of claim 2, wherein the connection unit further includes a first contact portion, an avoidance space, and a second contact portion arranged sequentially along the first direction, the first contact portion contacting the first source, the second contact portion contacting the second source, the avoidance space having an avoidance opening arranged toward the gate line, and a position of the avoidance opening being arranged relative to a position of the gate line.

4. 4. The power module of claim 3, wherein at least two connection holes are formed in the body, each connection unit corresponds to one connection hole, the first contact portion is connected to the corresponding hole wall of the connection hole, and the second contact portion is connected to the corresponding hole wall of the connection hole.

5. the main body and the first metal brazing substrate are spaced apart from each other, and at least one of the first contact portion and the second contact portion of each connection unit is connected to the main body; 4. The power module of claim 3, wherein the first contact portion connected to the body and the second contact portion connected to the body each have a connection section and a contact section, at least a portion of the connection section is bent relative to the body, the connection section is connected between the body and the contact section, the contact section of the first contact portion contacts a corresponding first source, and the contact section of the second contact portion contacts a corresponding second source.

6. The power module further includes a plastic package body, the plastic package body surrounding the first metal braze substrate, the chipset and the clip; The power module according to claim 5 , wherein a first locking hole is provided at a junction between the connection section and the body, and the first locking hole is filled with the plastic package body.

7. The power module further includes a plastic package body, the plastic package body surrounding the first metal braze substrate, the chipset and the clip; The power module according to claim 2 , wherein the body is provided with a second locking hole, and the second locking hole is filled with the plastic package body.

8. 4. The power module of claim 3, wherein the first contact portion and the second contact portion of at least one connection unit are spaced apart along the first direction, the avoidance space is a groove penetrating the clip along a second direction, and the second direction is perpendicular to a plane in which the side of the chip away from the first metal brazing substrate is located.

9. 9. The power module of claim 8, wherein at least one of the connection units further includes a bent portion, the bent portion being connected between the first contact portion and the second contact portion along the first direction, the bent portion protruding along a direction away from the first metal brazing substrate, and the first contact portion, the bent portion and the second contact portion surrounding the avoidance space.

10. The power module according to claim 9 , wherein the bent portion is provided with a buffer hole penetrating the bent portion along the second direction.

11. the first metal brazing substrate includes a first insulating substrate and a mounting metal layer covering the first insulating substrate, the chipset being disposed on a side of the mounting metal layer away from the first insulating substrate; 3. The power module of claim 2, further comprising: a plurality of mounting metal layers, the plurality of mounting metal layers being spaced apart on the first insulating substrate, the plurality of mounting metal layers including a first mounting metal layer, a second mounting metal layer, a third mounting metal layer, and a fourth mounting metal layer, the second mounting metal layer including a first extension, a groove, and a second extension, an end of the first extension being connected to an end of the second extension, the first mounting metal layer, the first extension, the groove, the second extension, and the third mounting metal layer being sequentially arranged along a third direction, at least a portion of the fourth mounting metal layer being located in the groove, the third direction being parallel to a plane in which a side of the chip away from the first metal brazing substrate is located, and the third direction being perpendicular to the first direction.

12. the power module further includes an input terminal and an output terminal, the input terminal and the output terminal being disposed at opposite ends of the first metal brazing substrate along the first direction; 12. The power module of claim 11, wherein the power module is a half-bridge type power module, the input terminals include a first positive power pin, a second positive power pin, and a third negative power pin, the first positive power pin electrically connected to the first mounting metal layer, the second positive power pin electrically connected to the third mounting metal layer, the third negative power pin electrically connected to the fourth mounting metal layer, and the output terminals electrically connected to the second mounting metal layer.

13. a plurality of chipsets including a first chipset, a second chipset, a third chipset, and a fourth chipset, the first chipset being disposed on the first mounting metal layer, the second chipset being disposed on the second mounting metal layer, the third chipset being disposed on the third mounting metal layer, and the fourth chipset being disposed on the second extension; 13. The power module of claim 12, wherein a connection arm on the first chipset is electrically connected to the first extension, a connection arm on the second chipset is electrically connected to the fourth mounting metal layer, a connection arm on the third chipset is electrically connected to the second extension, and a connection arm on the fourth chipset is electrically connected to the fourth mounting metal layer.

14. 2. The power module of claim 1, further comprising a second metal brazing substrate and an electronic component, the second metal brazing substrate being disposed on the first metal brazing substrate, the electronic component being disposed on a side of the second metal brazing substrate away from the first metal brazing substrate and electrically connected to the second metal brazing substrate.

15. 15. The power module of claim 14, wherein a terminal metal layer is further disposed on a surface of the first metal brazing substrate facing the chip, the terminal metal layer being located on an end of the first metal brazing substrate along the first direction, the second metal brazing substrate being disposed adjacent to the terminal metal layer, and the terminal metal layer being connected to the second metal brazing substrate via a second conducting wire.

16. 15. The power module of claim 14, wherein at least one chip further includes a gate, the electronic component is a gate resistor, the second metal braze substrate includes a first substrate electrode and a second substrate electrode insulated and spaced apart from each other, both ends of the gate resistor are electrically connected to the first substrate electrode and the second substrate electrode, respectively, the first substrate electrode is configured to receive a drive current, and the second substrate electrode is electrically connected to the gate of the chip via a first conductive line.

17. The power module of claim 1 , wherein when the number of chips in the chipset is three or more, all the chips in the chipset are equally spaced along the first direction.

18. A power conversion device comprising: a circuit board; and a power module according to any one of claims 1 to 17, the power module being disposed on the circuit board.

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