Output circuit

Abstract

To provide an output circuit capable of suppressing stress for a transistor while suppressing an occurrence of malfunction.SOLUTION: In a pulse output circuit having a function of outputting a pulse signal and having a transistor for controlling whether or not the pulse signal is set to a high level, a potential of one of a source and a drain of the transistor is set to be higher than a low-level potential of a clock signal and be higher than a high-level potential while the pulse signal output from the pulse output circuit is at a low level. Thereby, stress on the transistor is suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a pulse output circuit. Further, the present invention relates to a display device. The invention relates to electronic devices. [Background technology]

[0002] In recent years, in order to simplify the manufacturing process, all transistors are of the same conductivity type. Development of circuits that can accommodate this (also called unipolar circuits) is underway.

[0003] An example of the unipolar circuit is a pulse output circuit that constitutes a shift register.

[0004] For example, in Patent Document 1, the pulse of a clock signal is used to generate the pulse of a pulse signal. A shift register having multiple stages of pulse output circuits is disclosed. By using bootstrap, the output pulse width is adjusted to the amplitude of the clock signal. A shift register is disclosed that suppresses the decrease in amplitude of a shift signal. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2002-335153 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional pulse output circuit configuration, when the amplitude of the clock signal is large, the This causes a problem that the transistor deteriorates and the electrical characteristics of the transistor change.

[0007] For example, in the shift register of Patent Document 1, the pulse signal output from the pulse output circuit is A transistor that controls whether to set the output pulse signal to a high level when the The potential of the gate of a transistor (for example, the transistor 15 in FIG. 1(B) of Patent Document 1) is equal to the potential VS S for a certain period of time. At this time, the source or In this case, the drain potential is repeatedly changed, which causes stress on the transistor. This causes the transistors to deteriorate. Since the stress is applied for a very long time, the transistor is easily deteriorated and the electrical The fluctuation of the characteristics continues.

[0008] In order to suppress the influence of the above-mentioned stress on the transistor, for example, However, the output pulse signal is If the channel length of the transistor that controls whether to set the signal to a high level is increased, e.g. Parasitic capacitance and other factors can cause delays in the output pulse signal, increasing the possibility of malfunction. Other problems such as the above may arise.

[0009] In view of the above problem, one aspect of the present invention provides a pulse signal output device that outputs a pulse signal while suppressing the occurrence of operational errors. This reduces the stress on the transistor that controls whether the signal is set to a high level. One of the challenges is to: [Means for solving the problem]

[0010] In one embodiment of the present invention, during a period in which a pulse signal outputted from a pulse output circuit is at a low level, The source and drain of a transistor that controls whether or not the pulse signal is set to a high level The potential of one of the inputs is set lower than the high level potential of the clock signal. The aim is to reduce stress on transistors.

[0011] According to one aspect of the present invention, a pulse signal is generated according to a set signal, a reset signal, and a clock signal. The potential of one of the source and drain is changed according to a clock signal. a first transistor, one of the source and drain of which is the source and drain of the second transistor; The potential of the other of the source and drain is the potential of the pulse signal. a second transistor whose gate potential changes in response to a set signal and a reset signal; A first potential is applied to one of the source and the drain, and a second potential is applied to the other of the source and the drain. The transistor is electrically connected to the other of the source and drain of the transistor, and is turned on and off depending on the potential of the gate. By turning on or off the input, the pulse signal is controlled to be set to a low level or not. a third transistor having a source and a drain to which a second potential is applied, The other of the drain and the drain is electrically connected to the gate of the first transistor, and the potential of the gate is set to the sensing potential. A fourth transistor whose source and drain change according to a start signal and a reset signal. One of the potentials changes in response to a set signal and a reset signal, and the other of the source and drain Electrically connected to the gate of the first transistor, the potential of the gate changes according to the set signal. and a fifth transistor having a first conductivity type and a second conductivity type, The second potential is higher than the low level potential of the clock signal and is higher than the high level potential of the clock signal. The potential difference between the second potential and the low level potential of the clock signal is , the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor. Effect of the Invention

[0012] According to one aspect of the present invention, a transistor for controlling whether or not to set an output pulse signal to a high level is provided. The stress on the transistor can be reduced without increasing the channel length of the transistor. Therefore, deterioration of the transistor can be suppressed, and fluctuation in electrical characteristics can be suppressed. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Diagram 2] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Diagram 3] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 4] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Diagram 5] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 6] FIG. 2 is a diagram for explaining an example of a pulse output circuit. [Figure 7] 1A and 1B are diagrams illustrating examples of display devices. [Figure 8] 1A and 1B are diagrams illustrating examples of display devices. [Figure 9] 1A and 1B are diagrams illustrating examples of display devices. [Figure 10] 1A and 1B are diagrams illustrating examples of display devices. [Figure 11] 1A to 1C are diagrams illustrating examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] An embodiment of the present invention will be described. It is easy for a person skilled in the art to modify the content of the embodiment without modifying it. For example, the present invention is not limited to the description of the following embodiment.

[0015] The contents of each embodiment can be appropriately combined with each other. The contents of these can be substituted for each other as appropriate.

[0016] In addition, ordinal numbers such as 1st and 2nd are used to avoid confusion between components. The number is not limited to ordinal numbers.

[0017] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle between 80° and 100°. This includes cases where the angle is between 85° and 95°.

[0018] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0019] (Embodiment 1) In this embodiment, an example of a pulse output circuit will be described.

[0020] FIG. 1 is a diagram for explaining an example of a pulse output circuit according to the present embodiment. As shown in FIG. 1A, the circuit SR receives a set signal S, a reset signal R, and It has a function of generating a pulse signal (output signal OUT) according to the clock signal CK. A plurality of types of clock signals may be input to the pulse output circuit SR.

[0021] Furthermore, the pulse output circuit SR shown in FIG. 1(A) is a transistor as shown in FIG. For example, transistors 11 to 15 Each of the transistors 11 to 15 has the same conductivity type. Conduction is controlled according to one or more of a signal S, a reset signal R, and a clock signal CK. In addition, the pulse output circuit SR shown in FIG. Other elements may also be provided.

[0022] The potential of one of the source and drain of the transistor 11 changes in accordance with the clock signal CK. The transistor 11 controls the high-level potential of the pulse signal (output signal OUT). For example, the transistor 11 outputs a pulse signal (output signal OUT) to the first It has a function of controlling whether or not to set the first high level and whether or not to set the second high level. At this time, the second high level potential is lower than the first high level potential.

[0023] Note that "potential changes according to a signal" means that "a signal is directly input and the potential changes according to the signal" For example, the switch is turned on in response to a signal. "When the potential changes due to the capacitance coupling, "When the potential changes" is also included in "when the potential changes in accordance with a signal."

[0024] Furthermore, the "potential according to the signal" is not limited to only the "potential having the same value as the potential of the signal." For example, a value in which the potential of a signal has changed due to a voltage drop is also included in the "potential according to the signal."

[0025] One of the source and drain of transistor 12 is connected to the source and drain of transistor 11. The potential of the other terminal becomes the potential of the pulse signal (output signal OUT). Furthermore, the potential of the gate of the transistor 12 is set according to the set signal S and the reset signal R. The transistor 12 sets the pulse signal (output signal OUT) to a high level. It has a function to control whether or not

[0026] A potential VSS is applied to one of the source and drain of the transistor 13, and a potential VSS is applied to the other of the source and drain of the transistor 13. The other of the source and drain of the transistor 12 is electrically connected to the The potential of the gate of the transistor 13 changes in response to a set signal S and a reset signal R. The potential of the gate of the transistor 13 is controlled by a clock signal different from the clock signal CK. The transistor 13 is turned on or off depending on the potential of the gate. This enables the function to control whether or not to set the pulse signal (output signal OUT) to a low level. do.

[0027] A potential Va is applied to one of the source and drain of the transistor 14, and the other is The potential of the gate of the transistor 14 is electrically connected to the gate of the transistor 11. changes according to the set signal S and the reset signal R, or changes according to the clock signal CK. The transistor 14 sets the potential of the gate of the transistor 11 to a value corresponding to the potential Va. It has the function of controlling whether or not

[0028] Note that the "value according to the potential" is not limited to the "value equal to the potential". For example, Any change from the above potential value due to a drop is also included in the "value according to potential."

[0029] The potential of one of the source and drain of the transistor 15 is set by a set signal S and a reset signal R, and the other is electrically connected to the gate of transistor 11. The potential of the gate of the transistor 15 changes in accordance with the set signal S. The transistor 15 It has a function of controlling whether the gate of the transistor 11 is in a floating state or not.

[0030] The transistors 11 to 15 each have a channel formation region made of, for example, silicon. The wide band gap allows the application of transistors that include semiconductors with a wider band gap than the conventional transistors. As the semiconductor, for example, an oxide semiconductor can be used. However, the present invention is not limited to this. For example, For example, a transistor containing a semiconductor having an element of group 14 (such as silicon) is called a transistor 1. In this case, a semiconductor having a group 14 element may be used for the transistors 1 to 15. The material may be crystalline, polycrystalline, or amorphous.

[0031] Examples of the oxide semiconductor include In-based metal oxides, Zn-based metal oxides, and In-Zn-based Metal oxides, In-Ga-Zn-based metal oxides, etc. can be used. a-Zn-based metal oxides that contain other metal elements in place of all or part of the Ga contained in the oxides Metal oxides may also be used.

[0032] The structure of the oxide semiconductor film will be described below.

[0033] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline This refers to films such as oxide semiconductor films.

[0034] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in a microscopic area, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0035] The microcrystalline oxide semiconductor film is, for example, a microcrystal having a size of 1 nm or more and less than 10 nm (nanocrystal). Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher molecular weight than the amorphous oxide semiconductor film. Also, the defect level density is low.

[0036] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. The crystals contained in the S film are in the form of cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than a microcrystalline oxide semiconductor film. The CAAC-OS film has a low density of recessed states. .

[0037] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a quartz microscope, clear boundaries between the crystals were observed. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0038] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0039] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0040] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0041] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0042] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0043] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0044] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0045] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0046] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0047] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0048] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0049] This completes the description of the structure of the oxide semiconductor film.

[0050] Furthermore, a configuration example of the pulse output circuit according to this embodiment will be described with reference to FIG.

[0051] The pulse output circuit shown in FIG. 2(A) outputs a set signal LIN corresponding to the set signal S, a reset signal a reset signal RIN corresponding to the reset signal R; clock signals CK1 to CK3; It also has the function of generating and outputting a pulse signal (output signal OUT) according to the initialization signal RES. It should be noted that the initialization signal RES does not necessarily have to be used.

[0052] The pulse output circuit shown in FIG.

[0053] A potential VDD is applied to one of the source and drain of the transistor 61. The gate of the transistor 61 receives a set signal LIN.

[0054] A potential VSS is applied to one of the source and drain of the transistor 62, and a potential VSS is applied to the other of the source and drain of the transistor 62. It is electrically connected to the other of the source and drain of the transistor 61 .

[0055] One of the source and drain of the transistor 63 is connected to the source and drain of the transistor 61. The gate of the transistor 63 is electrically connected to the other of the inputs. IN is input. The transistor 63 corresponds to the transistor 15 shown in FIG. .

[0056] One of the source and drain of transistor 64 is connected to the source and drain of transistor 61. Further, the gate of the transistor 64 is electrically connected to the other terminal of the terminal 65. Given.

[0057] It should be noted that the transistor 64 does not necessarily have to be provided.

[0058] The transistor 65 receives the clock signal CK1 at one of its source and drain. Furthermore, the gate of the transistor 65 is connected to the other of the source and drain of the transistor 63. The transistor 65 corresponds to the transistor 11 shown in FIG. do.

[0059] One of the source and drain of transistor 66 is connected to the source and drain of transistor 65. The potential of the other terminal becomes the potential of the pulse signal (output signal OUT). The transistor 66 corresponds to the transistor 12 shown in FIG.

[0060] Furthermore, between the gate of the transistor 65 and the other of the source and drain of the transistor 66 A capacitance C1 is formed between the first and second terminals 11 and 12. It should be noted that the capacitance C1 does not necessarily have to be formed.

[0061] Also, between the gate of the transistor 66 and the other of the source and drain of the transistor 66 A capacitance C2 is formed. Note that the gate of the transistor 66 and the other of the source and drain The parasitic capacitance between the capacitor C2 and the capacitor C3 may be used as the capacitor C2. good.

[0062] A potential VSS is applied to one of the source and drain of the transistor 67, and a potential VSS is applied to the other of the source and drain of the transistor 67. The transistor 67 is electrically connected to the other of the source and drain of the transistor 66. 1B corresponds to the transistor 13 shown in FIG.

[0063] The transistor 68 receives the clock signal CK1 at one of its source and drain. Furthermore, the gate of the transistor 68 is connected to the other of the source and drain of the transistor 63. are electrically connected.

[0064] One of the source and drain of transistor 69 is connected to the source and drain of transistor 68. The potential of the other terminal is the potential of the pulse signal (output signal SROUT). Furthermore, the gate of transistor 69 is connected to the source and drain of transistor 64. It is electrically connected to the other.

[0065] Furthermore, between the gate of the transistor 68 and the other of the source and drain of the transistor 69 A capacitance C3 is formed between the first terminal and the second terminal. It should be noted that the capacitance C3 does not necessarily have to be formed.

[0066] Also, between the gate of the transistor 69 and the other of the source and drain of the transistor 69 A capacitance C4 is formed. The gate of the transistor 69 and the other of the source and drain The parasitic capacitance between the capacitor C1 and the capacitor C2 may be used as the capacitor C4. good.

[0067] A potential VSS is applied to one of the source and drain of the transistor 70, and a potential VSS is applied to the other of the source and drain of the transistor 70. The other of the source and drain of the transistor 69 is electrically connected to the The gate of the transistor 70 is electrically connected to the gate of the transistor 62 .

[0068] Note that the transistors 68 to 70 do not necessarily have to be provided.

[0069] A potential Va is applied to one of the source and drain of the transistor 71, and the other The gate of the transistor 65 and the gate of the transistor 68 are electrically connected to each other. The potential of the gate of the transistor 71 is a set signal LIN, a reset signal RIN, and an initialization signal RES, clock signal CK2, and clock signal CK3. Transistor 7 The reference numeral 1 corresponds to the transistor 14 shown in FIG.

[0070] A potential VDD is applied to one of the source and drain of the transistor 72, and a potential The gate of the transistor 67 and the gate of the transistor 70 are electrically connected to each other. The gate of the transistor 72 receives a reset signal RIN.

[0071] A potential VDD is applied to one of the source and drain of the transistor 73, and a potential The gate of the transistor 67 and the gate of the transistor 70 are electrically connected to each other. The initialization signal RES is input to the gate of the transistor 72 .

[0072] A potential VSS is applied to one of the source and drain of the transistor 74, and a potential VSS is applied to the other of the source and drain of the transistor 74. The gate of the transistor 67 and the gate of the transistor 70 are electrically connected to each other. The gate of the transistor 74 receives a set signal LIN.

[0073] A potential VDD is applied to one of the source and drain of the transistor 75. The gate of the transistor 75 receives the clock signal CK3.

[0074] One of the source and drain of transistor 76 is connected to the source and drain of transistor 75. The other is electrically connected to the gate of transistor 67 and the gate of transistor 70. In addition, the gate of transistor 76 is electrically connected to the gate of clock signal CK2 is entered.

[0075] A potential VSS is applied to one of a pair of electrodes of the capacitor C5, and a potential VSS is applied to the other of the pair of electrodes of the transistor 71. The capacitor C5 is electrically connected to the gate. Furthermore, the capacitor C5 may not be provided.

[0076] The transistors 61 to 76 are each formed of, for example, a material having the above oxide A transistor including a semiconductor can be used.

[0077] Next, as an example of a method for driving the pulse output circuit according to the present embodiment, the pulse output shown in FIG. An example of a method for driving the output circuit will be described with reference to a timing chart in FIG. Here, as an example, each of the transistors 61 to 76 is an N-channel The potential VDD is a positive potential, the potential VSS is a negative potential, and the value of the potential Va is The explanation will be given assuming that the set signal LIN and reset signal The high-level potentials of RIN and the clock signals CK1 to CK3 are V The low level potential is the same as the potential VSS. The threshold voltage of the transistor 65 is the same as that of the transistor 68. The threshold voltage of the transistor 66 is the same as that of the transistor 69. The potential difference between the potential Va and the low level potential of the clock signal CK1 is the threshold voltage of the transistor 65. Also, before the period T1, a pulse of the initialization signal RES is input. , transistor 73 is turned on, and transistors 67, 70, The pulse output circuit may be initialized by turning on the transformer 71. The connection point between the gate of the transistor 66 and other elements is a node NA, and the gate of the transistor 67 is The connection point between the gate and other elements is a node NB, and the gate of transistor 65 and other elements The connection point between the source and drain of the transistor 65 and the other of the source and drain of the transistor 65 is a node NC. The connection point of the transistor 66 with one of the source and drain is designated as a node ND.

[0078] In this specification, the potential VSS is a potential that is necessary to operate the circuit. The higher of the two power supply potentials is The potential is VDD.

[0079] In the example of the method for driving the pulse output circuit shown in FIG. 2A, The bit signal LIN goes high, and the transistors 72 and 74 are turned on. In addition, since the reset signal RIN is at a low level, the transistor 72 is in an off state. In addition, since the clock signals CK1 to CK3 are at a low level, Transistor 75 and transistor 76 are turned off.

[0080] At this time, the potential of the node NC rises to a value equivalent to the potential VDD, and the transistors 65 and The transistor 68 is turned on, and the potential of the node ND becomes the low level of the clock signal CK1. In addition, the transistor 63 is turned off. The potential of NA rises to a value equivalent to the potential VDD, and the transistors 66 and 69 In addition, the transistor 64 is turned off. In this manner, the pulse output shown in FIG. The power circuit is in a set state.

[0081] Next, during the period T2, the set signal LIN remains at a high level, so that the transistor The transistor 61 and the transistor 74 remain on. Also, the reset signal RIN, clock signal CK2, and clock signal CK3 are Since the transistors 72, 75, and 76 remain at a low level, remains in the off state.

[0082] At this time, the transistors 62, 67, 70, and 71 In addition, transistors 65 and 66 remain in the on state. The capacitance C1 and the capacitance C2 cause a capacitive coupling between the nodes NA and N If the potential of C becomes higher than the sum of the potential VDD and the threshold voltage (Vth65) of transistor 65, This rises to a very high value, i.e., VDD+Vth65+Vx (Vx is an arbitrary value). As a result, the potential of the output signal OUT becomes equal to the high level potential of the clock signal CK1. Furthermore, the transistors 68 and 69 remain on, and the output signal S The potential of ROUT becomes equal to the high level potential of the clock signal CK1.

[0083] Next, during a period T3, the set signal LIN goes to a low level, and the transistors 61 and The transistor 72 and the transistor 74 are turned off. The clock signal CK2 goes high and the transistor 76 is turned on. Also, the reset signal RIN and the clock signal CK3 are at the low level. As a result, transistors 72 and 75 remain in the off state.

[0084] At this time, the transistors 62, 67, 70, and 71 The gates and drains of transistors 66 and 69 remain in the off state. The voltage between the inputs is maintained at VDD+Vx, and the potential of the output signals OUT and SROUT remains equal to the high level potential of the clock signal CK1. OUT and the output signal SROUT are maintained at a high level.

[0085] Next, during a period T4, the reset signal RIN goes high, and the transistor 72 The clock signal CK1 goes to the low level. The clock signal C Since K2 remains high, transistor 76 remains high. The clock signal CK3 goes high, and the transistor 75 goes on. Since the set signal LIN remains at a low level, the transistors 61 and 63 , transistor 74 remains off.

[0086] At this time, the potential of the node NB becomes equal to the potential VDD, and the transistor 62, The transistor 67, the transistor 70, and the transistor 71 are turned on. The potential of the transistor 65 and the transistor 68 are turned on. In addition, the potential of the node NA becomes a value corresponding to the potential VSS, so that the transistor The transistor 66 and the transistor 69 are turned off. The output signal OUT and the output signal CK1 are set to a value according to the low level potential. The potential of SROUT becomes a value according to the low level potential of the clock signal CK1, and the output signal OUT, the output signal SROUT goes to low level. This causes the pulse shown in FIG. The output circuit is in a reset state.

[0087] Next, during a period T5, the reset signal RIN remains at a high level. The transistor 72 remains on. Also, the clock signal CK2 goes low. The transistor 76 is turned off. Also, since the clock signal CK3 remains at a high level, Therefore, the transistor 75 remains in the on state. Since the signal CK1 remains at a low level, the transistors 61, 63, and Transistor 74 remains in the off state.

[0088] At this time, the potential of the node NB remains at a value corresponding to the potential VDD, and the transistor 62, The transistors 67, 70, and 71 remain on. The potential of the node NC remains equal to the potential Va, and the transistor 65 The transistor 68 remains on. Also, the potential of the node NA remains equal to the potential VSS. Therefore, the transistors 66 and 69 remain in the off state. The potential of the output node ND becomes equal to the low level potential of the clock signal CK1. The potentials of the input signal OUT and the output signal SROUT are the same as the low level potential of the clock signal CK1. The values ​​become equal, and the output signals OUT and SROUT become low level.

[0089] Next, during a period T6, the reset signal RIN goes to a low level, and the transistor 72 The clock signal CK1 goes to the high level. The clock signal C K3 goes low, turning off the transistor 75. Furthermore, the set signal LI N, since the clock signal CK2 remains at a low level, the transistor 61, Transistor 63 and transistor 74 remain in the off state.

[0090] At this time, the potential of the node NB remains equal to the potential VDD, so that the transistor 6 2. Transistor 67, transistor 70, and transistor 71 remain on. In addition, since the potential of the node NC remains equal to the potential Va, the transistors 65 and The transistor 68 remains on. Also, the potential of the node NA becomes equal to the potential VSS. Since the output voltage Vcc remains at the same value, transistors 66 and 69 remain in the off state. In addition, the gate potential of the transistor 65 is a potential Va lower than the potential VDD. The potential of the node ND becomes Va-Vth65. This is because the potential of the clock signal CK1 becomes The potential is higher than the high level potential and lower than the high level potential. The potential of the signal SROUT becomes equal to the low level of the clock signal CK1. As shown in the period T6, when the output signal OUT and the output signal SROUT are at a low level, The potential of the node ND is higher than the potential VSS and the low level potential of the clock signal CK1. The potential changes alternately to Va-Vth65, which is lower than the high level potential. Compared to the case where the drain potential of the transistor 66 alternates between the potential VDD and the potential VSS, Therefore, the stress on the transistor can be suppressed.

[0091] The above is a description of the pulse output circuit shown in FIG.

[0092] The configuration of the pulse output circuit according to the present embodiment is not limited to the above configuration, and may be other configurations. It is also possible.

[0093] For example, the pulse output circuit shown in FIG. 3(A) is a transformer of the pulse output circuit shown in FIG. 2(B). The gate of the transistor 62 is electrically connected to the other of the source and drain of the transistor 72. Instead, the reset signal RIN is input to the gate of the transistor 62. When the pulse output circuit is reset, the potential of the node NA is set to the same potential as the VSS potential. You can speed up the speed at which values ​​such as

[0094] As shown in FIG. 3B, the transistor 64 of the pulse output circuit shown in FIG. Transistor 68, transistor 69, transistor 70, transistor 73, transistor The transistor 75 and the transistor 76 do not necessarily have to be provided.

[0095] As shown in FIG. 4, each of the transistors 62 to 76 is provided with a backgate. By controlling the potential of the back gate, the transistors 62 to For example, the threshold voltage of the N-channel transistor may be controlled. Applying a negative potential to the gate shifts the threshold voltage of the N-channel transistor in the positive direction. In the pulse output circuit shown in FIG. transistor 64, transistor 72, transistor 73, transistor 75, and transistor 7 A potential BG1 is applied to the back gates of the transistors 62 and 6. The back gates of transistors 63, 65 to 71, and 74 A potential BG2 is applied to each of the gates. When a potential is used, the value of the potential BG2 is preferably lower than the value of the potential BG1. If the threshold voltage of the transistor to which 1 is supplied is too high, the pulse output circuit will malfunction. Because it is likely to occur.

[0096] In addition, in the configuration shown in FIG. 3(A) or FIG. 3(B), a backgate is also provided to the transistor. A port may also be provided.

[0097] Further, an example of a shift register including a plurality of stages of the pulse output circuit shown in FIG. This will be explained with reference to 5.

[0098] The shift register 30 shown in FIG. 5A includes a plurality of pulse output circuits (pulse output circuits 31 5A, the pulse output circuit 31 includes a pulse output circuit 31_1 to a pulse output circuit 31_N (N is a natural number of 2 or more). As an example, we will show the case where N=4 or more.

[0099] Each of the pulse output circuits 31_1 to 31_N has a pulse The pulse output circuits 31_1 to 31_N correspond to the pulse output circuits shown in FIG. As shown in (B), the set signal LIN, the reset signal RIN, the initialization signal RES, The output signal OUT is generated according to the clock signal CK1, the clock signal CK2, and the clock signal CK3. , and has the function of generating and outputting a plurality of pulse signals as the output signal SROUT.

[0100] A start pulse signal SP is input to the pulse output circuit 31_1 as a set signal LIN. Furthermore, a set signal is input to a pulse output circuit 31_K (K is a natural number between 2 and N). The pulse signal output from the pulse output circuit 31_K-1 as LIN (output signal SROU T) is entered.

[0101] A pulse output circuit 31_M (M is a natural number equal to or smaller than N-1) receives a pulse as a reset signal RIN. The pulse signal (output signal SROUT) output from the pulse output circuit 31_M+2 is input. do.

[0102] Furthermore, the pulse output circuit 31_1 receives the clock signal CLK1 as the clock signal CK1. is input as the clock signal CK2, and the clock signal CLK2 is input as the clock signal CK3. A clock signal CLK3 is input as CK3. As a standard, the clock signal CK1 is set to every third pulse output circuit, and the clock signal CLK is set to every third pulse output circuit. 1 is input, the clock signal CLK2 is input as the clock signal CK2, and the clock signal The clock signal CLK3 is input as the clock signal CK3.

[0103] Furthermore, the pulse output circuit 31_2 receives the clock signal CLK2 as the clock signal CK1. is input as the clock signal CK2, the clock signal CLK3 is input as the clock signal CK3, and the clock signal The clock signal CLK4 is input as CK3. As a standard, the clock signal CK1 is set to every third pulse output circuit, and the clock signal CLK is set to every third pulse output circuit. 2 is input, the clock signal CLK3 is input as the clock signal CK2, and the clock signal The clock signal CLK4 is input as the clock signal CK3.

[0104] Furthermore, the pulse output circuit 31_3 receives the clock signal CLK3 as the clock signal CK1. is input, the clock signal CLK4 is input as the clock signal CK2, and the clock signal The clock signal CLK1 is input as CK3. As a standard, the clock signal CK1 is set to every third pulse output circuit, and the clock signal CLK is set to every third pulse output circuit. 3 is input, clock signal CLK4 is input as clock signal CK2, and clock signal The clock signal CLK1 is input as the clock signal CK3.

[0105] The clock signal CLK4 is input to the pulse output circuit 31_4 as the clock signal CK1. The clock signal CLK1 is input as the clock signal CK2, and the clock signal CK3 is The clock signal CLK2 is input as a reference. The clock signal CLK4 is input as the clock signal CK1 to every third pulse output circuit. The clock signal CLK1 is input as the clock signal CK2, and the clock signal CK3 is input as the clock signal CK3. In FIG. 5A, the clock signal CLK2 is input as a pulse The clock signal CK1, the clock signal CK2, and the clock The clock signal CK3 is a clock signal CK1 input to the pulse output circuit 31_4, The clock signals CK1 and CK2 are assumed to be the same as the clock signals CK3.

[0106] Furthermore, the configurations of the pulse output circuit 31_N+1 and the pulse output circuit 31_N+2 are The pulse output circuit shown in FIG. 2A does not include the transistor 72. The pulse signal output from the pulse output circuit 31_N+1 (output signal SROUT_N+1 ) is input to the pulse output circuit 31_N-1 as a reset signal RIN. The pulse signal (output signal SROUT_N+2) output from the pulse output circuit 31_N+2 is The reset signal RIN is input to the pulse output circuit 31_N. 31_N+1 and the pulse output circuit 31_N+2 are not provided, and a pulse signal generated separately is The output circuit 31_N-1 and the pulse output circuit 31_N may be input. It is also possible that the input signal OUT_N+1 and the output signal OUT_N+2 do not need to be output.

[0107] Furthermore, each of the pulse output circuits 31_1 to 31_N+2 is initially As the initialization signal RES, the initialization signal INI_RES is input.

[0108] Next, an example of a driving method of the shift register 30 shown in FIG. 5(A) will be described with reference to the timing of FIG. Here, as an example, the potential VDD is a positive potential. In this example, the potential VSS is a negative potential, and the potential Va is (VDD+VSS) / 2. As an example, a set signal LIN, a reset signal RIN, and a clock signal CL The high-level potential of the clock signal CLK4 through K1 is the same as the potential VDD, and the low-level The potential of the bell is assumed to be the same as the potential VSS. 1 to CLK4 have a duty ratio of 50%. Assume that the clock signal CLK2 is delayed by 1 / 4 cycle from the clock signal CLK1. Assume that the clock signal CLK3 is delayed by 1 / 4 cycle from the clock signal CLK2. Assume that the signal CLK4 is delayed by 1 / 4 cycle from the clock signal CLK3. As a result, the pulse width of the start pulse signal SP is The width of the pulse is the same as that of CLK4. Also, each pulse output circuit is set. Before this, input the initialization signal INI_RES pulse to initialize the pulse output circuit. do.

[0109] As shown in FIG. 5C, the shift register 30 shown in FIG. 5A starts at time T11. When the pulse signal SP goes high, the clock signal CLK1 goes high at time T12. Furthermore, the shift register 30 receives the clock signals CLK1 to CLK The pulses of the output signals SROUT_1 to SROUT_N are sequentially generated in accordance with the signal CLK4. Next, pulses of the output signals OUT_1 to OUT_N are output in sequence.

[0110] This concludes the description of the example of the method for driving the shift register 30 shown in FIG.

[0111] A protection circuit may be provided in the shift register 30 shown in FIG. The shift register 30 shown in FIG. 5A is a shift register shown in FIG. signal INI_RES, clock signals CLK1 to CLK4, and a start pulse signal In this configuration, a protection circuit 32 is electrically connected to the wiring for inputting the signal SP.

[0112] The shift register 30 shown in FIG. 6B is different from the shift register 30 shown in FIG. A protection circuit 33 is connected to wiring for outputting the output signals OUT_1 to OUT_N. It is an electrically connected configuration.

[0113] 5A is connected to a protection circuit 32 shown in FIG. 6A and a protection circuit 33 shown in FIG. A protection circuit 33 shown in B) may be provided.

[0114] The protection circuits 32 and 33 are connected to a wiring that is not within a certain range of potential. When the protection circuit 32 detects a power supply line, the protection circuit 32 connects the power supply line to the other power supply line. The path 33 is formed using, for example, a diode.

[0115] As shown in FIG. 6, a protection circuit is provided to prevent electrostatic discharge in the shift register. It is possible to improve electrical resistance to overvoltage caused by electrostatic discharge (ESD) and other phenomena.

[0116] As described with reference to FIGS. 1 to 6, in an example of the pulse output circuit according to the present embodiment, In the period when the output pulse signal is at a low level, the transistor 11 is turned on. The potential of one of the source and drain of the transistor 12 is set to the potential of the clock signal This makes the potential lower than the high level. This causes the stress applied to the transistor 12. Since the above can be suppressed, deterioration of the transistor can be suppressed.

[0117] (Embodiment 2) In this embodiment, an example of a display device using the pulse output circuit according to the first embodiment is shown. 7 to 10.

[0118] The display device shown in FIG. 7A includes a pixel portion 201 and a driver circuit portion 202. The pixel portion 201 and the driver circuit portion 202 are arranged in a pixel region.

[0119] The pixel section 201 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driving circuit section 202 includes a gate driver 221, a source driver 222, a The device is equipped with a driving circuit such as driver 223.

[0120] The gate driver 221 is a shift register having multiple stages of the pulse output circuit shown in the first embodiment. For example, the gate driver 221 is a shift register that shifts the scanning lines GL_1 to GL_ A function of controlling the potential of X. The scanning lines GL_1 to GL_X may be divided and controlled by the light source driver 221.

[0121] An image signal is input to the source driver 223. The source driver 223 receives the image signal Based on the data, the source driver 211 generates a data signal to be written to the pixel circuit 211. The driver 223 has a function of controlling the potentials of the data lines DL_1 to DL_Y.

[0122] The source driver 223 is configured using, for example, a plurality of analog switches. The image driver 223 sequentially switches on a plurality of analog switches to generate an image signal. The signal can be output as a data signal by time-sharing the signal. In this case, the shift register may be configured as a source driver 223. A shift register having multiple stages of the pulse output circuit shown in embodiment 1 (for example, the shift register shown in FIG. 5(A)) A resistor 30) can be used.

[0123] Each of the pixel circuits 211 receives a pulse signal via one of the scanning lines GL. A data signal is input via one of the plurality of data lines DL. 1, data of a data signal is written and held by the gate driver 221. For example, the pixel circuit 211 in the mth row and nth column is connected to the scanning line GL_m (m is an integer less than or equal to X). A pulse signal is input from the gate driver 221 via the gate driver 222, and the potential of the scanning line GL_m is In response to the signal, the source driver 223 outputs a data signal via a data line DL_n (n is a natural number equal to or smaller than Y). A data signal is input.

[0124] Each of the pixel circuits 211 includes, for example, a liquid crystal element 2 as shown in FIG. 30, a transistor 231_1, and a capacitor 233_1.

[0125] The potential of one of the pair of electrodes of the liquid crystal element 230 is appropriately set according to the specifications of the pixel circuit 211. The alignment state of the liquid crystal element 230 is set by the written data. A common potential ( A common potential may be applied to the pair of liquid crystal elements 230 for each row of pixel circuits 211. A different potential may be applied to one of the electrodes.

[0126] For example, a display method of a display device having a liquid crystal element is Twisted Nem (TN). atic) mode, IPS (In Plane Switching) mode, STN ( Super Twisted Nematic) mode, VA(Vertical Al ignment) mode, ASM (Axially Symmetric Alignment) mode d Micro-cell mode, OCB (Optically Compensated ed Birefringence mode, FLC (Ferroelectric L iquid Crystal mode, AFLC (AntiFerroelectric) Liquid Crystal mode, MVA (Multi-Domain Ver tical Alignment) mode, PVA(Patterned Vertic) mode al Alignment) mode, FFS (Fringe Field Switch) ing) mode, or TBA (Transverse Bend Alignment) Modes etc. may also be used.

[0127] In addition, a liquid crystal element may be formed using a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. Liquid crystals that exhibit a blue phase have a short response time of 1 msec or less and are optically isotropic. Therefore, no alignment treatment is required and viewing angle dependency is small.

[0128] In the pixel circuit 211 in the mth row and the nth column, One is electrically connected to the data line DL_n, and the other is the other of the pair of electrodes of the liquid crystal element 230. The gate of the transistor 231_1 is electrically connected to the scanning line GL_m. The transistor 231_1 is electrically connected to the It has a function of controlling the writing of data of a data signal.

[0129] One of a pair of electrodes of the capacitor 233_1 is electrically connected to the potential supply line VL, and the other The potential supply line VL is electrically connected to the other of the pair of electrodes of the liquid crystal element 230. The value of the capacitance is appropriately set according to the specifications of the pixel circuit 211. It functions as a storage capacitor for storing the data stored in the memory.

[0130] In a display device including the pixel circuit 211 of FIG. 7(B-1), each The pixel circuits 211 in the row are sequentially selected, the transistors 231_1 are turned on, and a data signal is input. Write the data.

[0131] In the pixel circuit 211 to which the data is written, the transistor 231_1 is turned off. By repeating this process for each row, an image can be displayed.

[0132] The pixel circuit shown in FIG. 7B-2 includes a transistor 231_2 and a capacitor 233_ 2, a transistor 234, and a light-emitting element (also referred to as EL) 235.

[0133] One of the source and drain of the transistor 231_2 is electrically connected to the data line DL_n. Furthermore, the gate of the transistor 231_2 is electrically connected to the gate signal line GL_m. is connected to.

[0134] The transistor 231_2 is turned on or off to convert the data of the data signal into a It has the function of controlling the writing of data.

[0135] One of a pair of electrodes of the capacitance element 233_2 is electrically connected to the power supply line VL_a, and the other , is electrically connected to the other of the source and drain of the transistor 231_2.

[0136] The capacitor 233_2 functions as a storage capacitor for storing written data.

[0137] One of the source and drain of the transistor 234 is electrically connected to the power supply line VL_a. In addition, the gate of the transistor 234 is connected to the source and drain of the transistor 231_2. The other input is electrically connected to the other input.

[0138] One of the anode and the cathode of the light-emitting element 235 is electrically connected to the power supply line VL_b. The other one is electrically connected to the other of the source and drain of the transistor 234 .

[0139] The light emitting element 235 may be, for example, an organic electroluminescence element. Cut.

[0140] A potential VDD is applied to one of the power supply lines VL_a and VL_b, and a potential VDD is applied to the other. , a potential VSS is applied.

[0141] In a display device including the pixel circuit 211 of FIG. 7(B-2), each The pixel circuits 211 in the row are sequentially selected, the transistors 231_2 are turned on, and a data signal is input. Write the data.

[0142] In the pixel circuit 211 to which the data is written, the transistor 231_2 is turned off. Furthermore, the transistor 234 is turned on in response to the potential of the written data signal. The amount of current flowing between the source and drain of the light emitting element 235 is controlled by the amount of current flowing. By performing this process row by row, an image can be displayed.

[0143] Further, the display device shown in FIG. 7A is driven in a manner capable of operating in a low power consumption mode. An example of the method will be described with reference to the timing chart of FIG. 2, the shift register shown in the first embodiment is used for the gate driver 221. do.

[0144] The operation of the display device shown in FIG. 7A is divided into a normal mode and a low power consumption mode.

[0145] The operation in the normal mode will be described. At this time, as shown in period 311 of FIG. A start pulse signal SP, a power supply voltage PWR, and clock signals CLK1 to CLK4. When CLK4 is input to the shift register, the shift register receives the start pulse signal SP. According to the pulse, the pulses of the output signals SROUT_1 to SROUT_N are output in sequence. The pulses of the output signals OUT_1 to OUT_N are output in sequence. The voltage PWR is a power supply voltage consisting of potential VDD and potential VSS, and a voltage The power supply voltages include:

[0146] Next, the operation when the normal mode is changed to the low power consumption mode will be described. As shown in period 312 of FIG. 8, the power supply voltage PWR for the shift register, the clock signal The output of the clock signals CLK1 through CLK4 and the start pulse signal SP is stopped.

[0147] At this time, the input of the start pulse signal SP to the shift register is first stopped, and then The input of the clock signals CLK1 to CLK4 is stopped in sequence, and then the power supply voltage P It is preferable to stop the input to WR. This will prevent the shift register from malfunctioning. Cut.

[0148] Power supply voltage PWR for the shift register, clock signals CLK1 to CLK 4, and when the input of the start pulse signal SP is stopped, the output signals SROUT_1 to SROUT_2 are The output of the pulses of the output signal SROUT_N stops, and the output signals OUT_1 to OUT The output of the _N pulse stops, and the display device goes into a low power consumption mode.

[0149] Thereafter, when the shift register is to be returned to the normal mode, as shown in the period 313 of FIG. In addition, a start pulse signal SP for the shift register, a clock signal CLK1 to Then, the input of the clock signal CLK4 and the power supply voltage PWR is resumed.

[0150] At this time, first the input of the power supply voltage PWR is restarted to the shift register, and then the clock The input of the signals CLK1 to CLK4 is resumed, and then the start pulse signal SP At this time, the input of the clock signals CLK1 to CLK4 is resumed. After setting the potential of the wiring to which the clock signals CLK1 to CLK It is preferable to restart the input of signal CLK4 in sequence.

[0151] A start pulse signal SP for the shift register, a clock signal CLK1 to a clock signal When the input of the CLK4 signal and the power supply voltage PWR is resumed, the shift register The pulses of the output signals SROUT_1 to SROUT_N are changed in accordance with the pulses of the pulse signal SP. The pulses of the output signals OUT_1 to OUT_N are output in sequence. The display device then returns to the normal mode.

[0152] The above is a description of the example of the display device.

[0153] As described with reference to FIG. 8, in an example of the display device according to the present embodiment, The operation of the driver circuit having the shift register can be stopped. By using a transistor with low off-state current as a transistor, some or all of the pixels can be turned on when displaying an image. If the circuit does not need to rewrite the data signal, the driver circuit is stopped and the By increasing the interval, power consumption can be reduced.

[0154] As shown in FIG. 9, between the gate driver 221 and the pixel circuit 211 (the gate signal line G A protection circuit 225 may be connected to the source driver 223 and the pixel circuit 211. A protection circuit 225 may be connected between the data signal lines DL. When a potential outside a certain range is applied to the wiring to which it is connected, the wiring is electrically connected to another power supply line. The protection circuit 225 is configured using, for example, a diode.

[0155] As shown in Figure 9, by providing a protection circuit, it is possible to protect against overvoltage caused by ESD, etc. This makes it possible to improve the resistance of the display device to light.

[0156] As described with reference to FIGS. 1 to 9, in an example of the display device according to the present embodiment, A driving circuit such as a gate driver, a source driver, etc., is formed by using the pulse output circuit shown in FIG. In the above-mentioned driving circuit, the stress on the transistor is small, so that the display The reliability of the system can be improved.

[0157] Furthermore, a structural example of the display device according to the present embodiment will be described with reference to FIG.

[0158] The display device shown in FIG. 10A is a vertical electric field type liquid crystal display device.

[0159] The conductive layers 703a and 703b are provided on one surface of the substrate 700 with the insulating layer 701 interposed therebetween. .

[0160] The conductive layer 703a is provided in the driving circuit section 202. The conductive layer 703a is It functions as the gate of the transistor.

[0161] The conductive layer 703b is provided in the pixel portion 201. The conductive layer 703b is a transistor of the pixel circuit. It functions as a gate for the star.

[0162] An insulating layer 704 is provided on the conductive layers 703a and 703b. As a gate insulating layer for a transistor in a circuit and a gate insulating layer for a transistor in a pixel circuit It has the following functions.

[0163] The semiconductor layer 705a overlaps with the conductive layer 703a with the insulating layer 704 interposed therebetween. a is a layer in which the channel of the driver circuit transistor is formed (also called a channel formation layer), It has the function of

[0164] The semiconductor layer 705b overlaps with the conductive layer 703b with the insulating layer 704 interposed therebetween. The layer b functions as a channel formation layer of a transistor in a pixel circuit.

[0165] The conductive layer 706a is electrically connected to the semiconductor layer 705a. The gate has a function as one of the source and drain of a transistor in the path.

[0166] The conductive layer 706b is electrically connected to the semiconductor layer 705a. The gate has a function as the other of the source and drain of the transistor in the path.

[0167] The conductive layer 706c is electrically connected to the semiconductor layer 705b. The gate has a function as one of the source and drain of a transistor in the path.

[0168] The conductive layer 706d is electrically connected to the semiconductor layer 705b. The gate has a function as the other of the source and drain of the transistor in the path.

[0169] An insulating layer 707 is disposed on the semiconductor layers 705a and 705b and on the conductive layers 706a to The insulating layer 707 is provided on the conductive layer 706d. It functions as a protective insulating layer.

[0170] An insulating layer 708 is provided on the insulating layer 707. The insulating layer 708 functions as a planarizing layer. By providing the insulating layer 708, the insulating layer 708 can be insulated from the conductive layer below the insulating layer 708. It is possible to suppress the occurrence of parasitic capacitance between the layer 708 and the conductive layers above it.

[0171] The conductive layer 709a and the conductive layer 709b1 are provided on the insulating layer 708.

[0172] The conductive layer 709a overlaps with the semiconductor layer 705a with the insulating layer 707 and the insulating layer 708 interposed therebetween. The conductive layer 709a functions as a gate of a transistor in the driver circuit. For example, The conductive layer 709a may function as a back gate of a transistor in a driver circuit. For example, in the case of an N-channel transistor, a negative potential is applied to the back gate. In this way, the threshold voltage of the transistor can be shifted in the positive direction. The gate may be grounded.

[0173] The conductive layer 709b1 functions as one of a pair of electrodes of a capacitor in a pixel circuit. do.

[0174] The insulating layer 710 is provided on the surface of the insulating layer 708 and on the conductive layer 709b1. By removing the portion of the edge layer 710 that is formed over the transistors of the driving circuit, Since hydrogen and water in the insulating layer 708 can be released to the outside, the insulating layer 708 can be The insulating layer 710 functions as a protective insulating layer. The insulating layer 710 also functions as a dielectric layer for the capacitor element of the pixel circuit.

[0175] The conductive layer 711 is provided on the insulating layer 710, and the insulating layers 707, 708, and An opening through layer 710 electrically connects to conductive layer 706d. The conductive layer 711 overlaps with the conductive layer 709b1 with the insulating layer 710 interposed therebetween. One of a pair of electrodes of a liquid crystal element of a pixel circuit and one of a pair of electrodes of a capacitor element It has the function of the other.

[0176] The coloring layer 722 is provided on a part of one surface of the substrate 720. It functions as a filter.

[0177] The insulating layer 723 is provided on one surface of the substrate 720 with the colored layer 722 sandwiched therebetween. has a function as a planarizing layer.

[0178] The conductive layer 721 is provided on one surface of the insulating layer 723. The conductive layer 721 is The conductive layer 721 functions as the other of the pair of electrodes of the element. A border layer may also be provided.

[0179] The liquid crystal layer 750 is provided between the conductive layer 711 and the conductive layer 721 using a sealant 751. In addition, the insulating layer 707 and the insulating layer 710 are not covered with the insulating layer 707 except for the portions located under the sealing material 751. You may remove it.

[0180] Furthermore, the display device shown in FIG. 10B is a display device of a horizontal electric field type (FFS mode). 10A, the display device has an additional conductive layer 703c and a conductive layer 70 9b1, and conductive layer 712 instead of conductive layer 711. The display device shown in FIG. For the same parts as those in the display device shown in FIG. 10(A), the description thereof will be cited as appropriate.

[0181] The conductive layer 703c is provided on the insulating layer 701. At this time, the conductive layer 706d is The conductive layer 703c overlaps with a layer 704 therebetween.

[0182] The conductive layer 709b2 is provided on the insulating layer 708. The conductive layer 709b2 is a The conductive layer 709b2 functions as one of a pair of electrodes of the liquid crystal element. The second electrode functions as one of a pair of electrodes of a capacitor element of a pixel circuit.

[0183] The conductive layer 712 is provided on the insulating layer 710, and the insulating layers 707, 708, and An opening through layer 710 electrically connects to conductive layer 706d. The conductive layer 712 has a comb-tooth portion, and each of the combs of the comb-tooth portion sandwiches the insulating layer 710 between the conductive layer 712 and the insulating layer 710. The conductive layer 712 overlaps with the other of a pair of electrodes of a liquid crystal element in a pixel circuit. Further, the conductive layer 712 functions as a pair of electrodes of a capacitor of a pixel circuit. It functions as the other pole.

[0184] The liquid crystal layer 760 is provided over the conductive layer 711 and the conductive layer 712 with a sealant 751. .

[0185] In addition, in FIG. 10(A) and FIG. 10(B), the transistor is a channel etch type transistor. However, the present invention is not limited to this, and may be applied to, for example, a channel stop type transistor. A top-gate type transistor may also be used.

[0186] Furthermore, each component of the display device shown in FIG. 10(A) and FIG. 10(B) will be described. Each layer may have a laminated structure.

[0187] The substrates 700 and 720 may be, for example, glass substrates or plastic substrates. do.

[0188] The insulating layer 701 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide A layer containing materials such as aluminum or hafnium oxide can be applied.

[0189] The conductive layers 703a to 703c may be made of, for example, molybdenum, titanium, chromium, tantalum, Magnesium, silver, tungsten, aluminum, copper, neodymium, scandium, etc. A layer containing a metallic material such as

[0190] The insulating layer 704 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide For example, a layer containing a material such as aluminum or hafnium oxide may be applied. A lamination of a silicon nitride layer and a silicon oxynitride layer can be applied as 4. The silicon nitride layer may be a laminate of a plurality of silicon nitride layers having different compositions. An oxide layer may be used as the edge layer 704. The oxide layer may be, for example, In:Ga For example, a layer of an oxide having an atomic ratio of Zn=1:3:2 can be used.

[0191] For example, an oxide semiconductor layer can be used as the semiconductor layer 705a and the semiconductor layer 705b. can.

[0192] As the oxide semiconductor, as shown in the first embodiment, for example, an In-based metal oxide, Zn In-Zn based metal oxide, In-Ga-Zn based metal oxide, etc. are applied. In addition, a part or all of the Ga contained in the In-Ga-Zn-based metal oxide can be Alternatively, a metal oxide containing another metal element may be used. For example, the oxide semiconductor may be polycrystalline or single crystalline. The oxide semiconductor may be amorphous.

[0193] The other metal element is, for example, a metal element capable of bonding with more oxygen atoms than gallium. For example, titanium, zirconium, hafnium, germanium, and tin can be used. One or more of these elements may be used. In addition, the other metal element may be lanthanum. Cr, Cerium, Praseodymium, Neodymium, Samarium, Europium, Gadolinium, Thermo Rubium, Dysprosium, Holmium, Erbium, Thulium, Ytterbium, and One or more of the metal elements may be used. The amount of these metal elements added is determined based on the amount of metal oxide that is semiconductor. It can form more bonds with oxygen atoms than gallium. By using a metal element and supplying oxygen to the metal oxide, the acid in the metal oxide can be It is possible to reduce elementary defects.

[0194] Further, a first oxide semiconductor layer having an atomic ratio of In:Ga:Zn=1:1:1, for example, A second oxide semiconductor layer having an atomic ratio of n:Ga:Zn=3:1:2, and an In:Ga:Z The third oxide semiconductor layer having an atomic ratio of n=1:1:1 is stacked to form the semiconductor layer 705a and The semiconductor layer 705a and the semiconductor layer 705b may be formed by the above-mentioned lamination. By forming the 05b, for example, the field effect mobility of a transistor can be increased. do.

[0195] The transistor including the oxide semiconductor has a wide band gap and therefore has low leakage current due to thermal excitation. The current is small. In addition, the effective mass of the hole is large, more than 10, and the tunnel barrier height is 2.8 eV or more. This reduces the tunnel current. Furthermore, the carriers in the semiconductor layer Therefore, the off-current can be reduced. For example, the off-current at room temperature (25°C) is 1×10 per μm of channel width -19 A (100zA) or less. More preferably, 1 ×10 -22 A (100yA) or less. The lower the off-state current of a transistor, the better. However, the lower limit of the off-state current of a transistor is about 1×10 -30 Estimated to be A / μm Note that the present invention is not limited to the above-described oxide semiconductor layer, and the semiconductor layer 705a and the semiconductor layer 70 A semiconductor layer having an element of group 14 (such as silicon) may be used as 5b. For example, The semiconductor layer containing silicon may be a single crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer. A layer of corn or the like can be used.

[0196] For example, impurities such as hydrogen or water are removed as much as possible, and oxygen is supplied to fill the oxygen vacancies as much as possible. By reducing the amount of the oxide semiconductor as much as possible, a transistor including the oxide semiconductor can be manufactured. In the channel formation region, the amount of hydrogen, known as donor impurities, is measured using secondary ion mass spectrometry. (also known as SIMS) measurement value is 1×10 19 / cm 3 Less than or equal to 1×10 18 / cm 3 It is preferable to reduce it to the following:

[0197] By using a highly purified oxide semiconductor layer in a field effect transistor, The carrier density of the layer is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than , and more preferably 1×10 11 / cm 3 In this way, the carrier density can be reduced to less than By eliminating the 10 -19 A (100zA) or less, preferably 1×10 -22 A (100yA) or less The lower the off-state current of a field-effect transistor, the better. The lower limit of the off-state current of an effective transistor is approximately 1×10 -30 It is estimated to be A / μm. do.

[0198] Note that the oxide semiconductor may be a CAAC-OS.

[0199] For example, an oxide semiconductor layer which is a CAAC-OS can be formed by a sputtering method. At this time, sputtering is performed using a polycrystalline oxide semiconductor sputtering target. When the ions collide with the sputtering target, The crystal region in the target is cleaved from the ab plane, forming a flat plate with a plane parallel to the ab plane. Or, it may peel off as pellet-shaped sputtered particles. The sputtering particles reach the substrate while maintaining the above-mentioned state. The crystalline state of the target is transferred to the substrate, forming a CAAC-OS.

[0200] In addition, in order to form the CAAC-OS, it is preferable to apply the following conditions:

[0201] For example, by forming a CAAC-OS with a reduced impurity concentration, the acid For example, impurities (hydrogen, It is preferable to reduce impurities in the deposition gas. For example, the deposition gas has a dew point of -80°C or less, preferably - It is preferable to use a deposition gas having a temperature of 100° C. or less.

[0202] It is also preferable to increase the substrate temperature during film formation. When the plate-shaped sputtered particles reach the substrate, the migration of the sputtered particles occurs. The sputtering particles can be attached to the substrate by facing the flat surface. For example, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or higher and 500° C. or lower. An oxide semiconductor film is formed at a temperature of 0.degree. C. or lower to form an oxide semiconductor layer.

[0203] In addition, the oxygen ratio in the deposition gas is increased and the power is optimized to suppress plasma damage during deposition. For example, the oxygen ratio in the deposition gas is preferably 30% by volume or more. It is preferable that the volume percentage is 100%.

[0204] The conductive layers 706a to 706d can be formed of, for example, molybdenum, titanium, chromium, or titanium. Ta, magnesium, silver, tungsten, aluminum, copper, neodymium, scandium, Alternatively, a layer containing a metallic material such as ruthenium can be applied.

[0205] The insulating layer 707 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide A layer containing materials such as aluminum or hafnium oxide can be applied.

[0206] The insulating layer 708 may be, for example, a layer of an organic insulating material or an inorganic insulating material. For example, the insulating layer 708 may be made of an acrylic resin.

[0207] The conductive layer 709a, the conductive layer 709b1, and the conductive layer 709b2 may be, for example, a conductor. A layer of a metal oxide that has the function of transmitting light can be applied. For example, indium oxide Zinc oxide or indium tin oxide, etc., can be used.

[0208] For the insulating layer 710, for example, a material applicable to the insulating layer 704 can be used.

[0209] The conductive layers 711, 712, and 721 are, for example, made of a metal oxide that transmits light. For example, indium oxide, zinc oxide, or indium tin oxide may be used. can be applied.

[0210] The color layer 722 transmits light having one of the colors red (R), green (G), and blue (B), for example. The colored layer 722 may be a layer containing a dye or a pigment.

[0211] The insulating layer 723 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide A layer containing a material such as aluminum or hafnium oxide can be applied. Also, the insulating layer 723 A layer of material applicable to the substrate may be used.

[0212] The liquid crystal layer 750 may be, for example, a TN liquid crystal, an OCB liquid crystal, an STN liquid crystal, a VA liquid crystal, or an ECB type. Use of a layer containing liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, discotic liquid crystal, or the like can be done.

[0213] As the liquid crystal layer 760, for example, a layer containing liquid crystal exhibiting a blue phase can be used.

[0214] The layer containing the liquid crystal exhibiting a blue phase may be, for example, a liquid crystal exhibiting a blue phase, a chiral agent, a liquid crystal monomer, or the like. The liquid crystal composition includes a liquid crystal layer, a non-liquid crystal monomer, and a polymerization initiator. The liquid crystal shown in Fig. 1 has a short response time and is optically isotropic, so no alignment treatment is required and the viewing angle is large. Therefore, by using a liquid crystal that exhibits a blue phase, the operation of a liquid crystal display device can be improved. can be done faster.

[0215] The above is a description of the structural example of the display device shown in FIG.

[0216] As described with reference to FIG. 10, in one example of the display device according to the present embodiment, a pixel circuit and A driving circuit is provided on the same substrate. This allows wiring to connect the pixel circuits and the driving circuit. The number of can be reduced.

[0217] (Embodiment 3) In this embodiment, an example of an electronic device including a panel using the display device of the second embodiment will be described. This will be described with reference to FIG.

[0218] The electronic device shown in FIG. 11A is an example of a portable information terminal.

[0219] The electronic device shown in FIG. 11A includes a housing 1011 and a panel 10 provided in the housing 1011. 12, a button 1013, and a speaker 1014.

[0220] The housing 1011 is provided with a connection terminal for connecting to an external device and an operation button. It's fine.

[0221] Furthermore, the panel 1012 may be formed using the display device of the second embodiment.

[0222] Furthermore, the panel 1012 may be configured using a touch panel. The touch panel can detect touches on the touch panel 12. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0223] The button 1013 is provided on the housing 1011. For example, the button 1013 is a power button. If present, pressing the button 1013 can control the on state of the electronic device.

[0224] The speaker 1014 is provided in the housing 1011. The speaker 1014 outputs sound. do.

[0225] A microphone may be provided in the housing 1011. By doing so, for example, the electronic device shown in FIG. 7(A) can function as a telephone. .

[0226] The electronic device shown in FIG. 11(A) is, for example, a telephone, an electronic book, a personal computer, and and functions as one or more of the gaming machines.

[0227] The electronic device shown in FIG. 11B is an example of a foldable information terminal.

[0228] The electronic device shown in FIG. 11B includes a housing 1021a, a housing 1021b, and a housing 1021a. A panel 1022a provided on the housing 1021b, a panel 1022b provided on the housing 1021b, and a shaft A portion 1023, a button 1024, a connection terminal 1025, a recording medium insertion portion 1026, and a switch It is equipped with a speaker 1027.

[0229] The housing 1021 a and the housing 1021 b are connected by a shaft portion 1023 .

[0230] Furthermore, even if the panels 1022a and 1022b are constructed using the display device of the second embodiment, good.

[0231] Furthermore, the panels 1022a and 1022b may be configured using a touch panel. This allows touch detection on the panels 1022a and 1022b. Examples of touch panels include optical touch panels, capacitive touch panels, and resistive touch panels. Chipanel, etc. can be applied.

[0232] The electronic device shown in FIG. 11B has a shaft portion 1023, so that the panel 1022a and the panel 1022b can be folded in opposition to each other.

[0233] The button 1024 is provided on the housing 1021b. For example, if the button 1024 is a power button, pressing the button 1024 By doing so, the on state of the electronic device can be controlled.

[0234] The connection terminal 1025 is provided on the housing 1021a. In addition, the connection terminal 1025 may be provided between the housing 1021a and the housing 1021b. A plurality of connection terminals 1025 may be provided on one or both of the terminals 21b. This is a terminal for connecting the electronic device shown in FIG. 1 to other devices.

[0235] The recording medium insertion section 1026 is provided in the housing 1021a. The recording medium insertion section 1026 may be provided in the housing 1021a. For example, a plurality of recording medium inserts may be provided on one or both of the housings 1021a and 1021b. By inserting a card-type recording medium into the card slot, data on the card-type recording medium can be read by electronic equipment. It is possible to read data from the electronic device or write data in the card-type recording medium.

[0236] The speaker 1027 is provided in the housing 1021b. The speaker 1027 outputs sound. Note that a speaker 1027 may be provided on the housing 1021a.

[0237] A microphone may be provided in the housing 1021a or the housing 1021b. By providing a microphone in the housing 1021b, the electronic device shown in FIG. It can function as a telephone.

[0238] The electronic device shown in FIG. 11(B) is, for example, a telephone, an electronic book, a personal computer, and and functions as one or more of the gaming machines.

[0239] The electronic device shown in FIG. 11C is an example of a stationary information terminal. The electronic device includes a housing 1031, a panel 1032 provided on the housing 1031, and a button 10 33 and a speaker 1034.

[0240] Furthermore, the panel 1032 may be formed using the display device of the second embodiment.

[0241] Furthermore, the panel 1032 may be configured using a touch panel. 032, touch detection can be performed. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0242] In addition, a panel similar to the panel 1032 may be provided on the deck portion 1035 of the housing 1031.

[0243] Furthermore, the housing 1031 is provided with a ticket output section for outputting tickets, a coin input section, a bill input section, etc. It may be provided.

[0244] The button 1033 is provided on the housing 1031. For example, the button 1033 is a power button. If present, pressing the button 1033 can control the on state of the electronic device.

[0245] The speaker 1034 is provided in the housing 1031. The speaker 1034 outputs sound. do.

[0246] The electronic device shown in FIG. 11C is, for example, an automatic teller machine, a machine for ordering tickets, etc. Functions as an information and communication terminal (also called a multimedia station) for playing games or as a gaming machine has.

[0247] FIG. 11(D) is an example of a stationary information terminal. The electronic device shown in FIG. 11(D) is a casing. A body 1041, a panel 1042 provided on the housing 1041, and a support for supporting the housing 1041. The device includes a holder 1043, a button 1044, a connection terminal 1045, and a speaker 1046. can.

[0248] The housing 1041 may be provided with a connection terminal for connecting to an external device.

[0249] Furthermore, the panel 1042 may be formed using the display device of the second embodiment.

[0250] Furthermore, the panel 1042 may be configured using a touch panel. 042, touch detection can be performed. Touch panels, capacitive touch panels, resistive touch panels, etc. can be applied.

[0251] The button 1044 is provided on the housing 1041. For example, the button 1044 is a power button. If present, pressing button 1044 can control the on state of the electronic device.

[0252] The connection terminal 1045 is provided on the housing 1041. The connection terminal 1045 is shown in FIG. For example, the connection terminal 1045 is a terminal for connecting the electronic device shown in FIG. When the electronic device shown in FIG. 11(D) is connected to a personal computer, An image corresponding to a data signal input from a computer can be displayed on the panel 1042. For example, the panel 1042 of the electronic device shown in FIG. 11D may be connected to a panel of another electronic device. If the screen size is larger than the other electronic device, the image displayed on the other electronic device can be enlarged and multiple people can use the same screen at the same time. Sometimes it's easier to see.

[0253] The speaker 1046 is provided in the housing 1041. The speaker 1046 outputs sound. do.

[0254] The electronic device shown in FIG. 11(D) is, for example, an output monitor, a personal computer, and a television. It has one or more functions as a vision device.

[0255] The above is a description of the example of the electronic device shown in FIG.

[0256] As described with reference to FIG. 11, in the electronic device according to the present embodiment, the panel By providing a panel using the display device of the second embodiment, a highly reliable electronic device can be provided. . [Explanation of symbols]

[0257] 11 Transistor 12 Transistor 13. Transistor 14 Transistor 15 Transistor 31 Pulse output circuit 32 Protection circuit 33 Protection circuit 61 Transistor 62 Transistor 63 Transistor 64 Transistor 65 Transistor 66 Transistor 67 Transistor 68 Transistors 69 Transistor 70 Transistor 71 Transistor 72 Transistor 73 Transistor 74 Transistor 75 Transistors 76 Transistor 201 Pixel section 202 Drive circuit section 211 Pixel circuit 221 Gate Driver 223 Source Driver 225 Protection circuit 230 Liquid crystal element 231_1 Transistor 231_2 Transistor 233_1 Capacitor element 233_2 Capacitor element 234 Transistor 235 Light-emitting element 311 period 312 period 313 period 700 Substrates 701 Insulation layer 703a conductive layer 703b conductive layer 703c conductive layer 704 Insulating layer 705a Semiconductor layer 705b Semiconductor layer 706a conductive layer 706b Conductive layer 706c conductive layer 706d Conductive layer 707 Insulation Layer 708 Insulation Layer 709a conductive layer 709b1 Conductive layer 709b2 conductive layer 710 Insulating layer 711 Conductive layer 712 Conductive layer 720 Substrate 721 Conductive layer 722 Colored layer 723 Insulation Layer 750 Liquid crystal layer 751 Sealing material 760 Liquid crystal layer 1011 Case 1012 Panel 1013 Button 1014 Speaker 1021a Housing 1021b Case 1022a Panel 1022b Panel 1023 Shaft 1024 Button 1025 Connection terminal 1026 Recording medium insertion section 1027 Speaker 1031 Case Panel 1032 1033 Button 1034 Speaker 1035 Deck section 1041 Case Panel 1042 1043 Support stand 1044 Button 1045 Connection terminal 1046 Speaker

Claims

[Claim 1] The transistors include first to sixth transistors of the same conductivity type, each of the first to sixth transistors has a back gate; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to a wiring to which a clock signal is supplied; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is electrically connected to a wiring through which an output signal is output; the other of the source and the drain of the third transistor is electrically connected to a wiring to which a first potential is supplied; one of a source and a drain of the fourth transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the fourth transistor is electrically connected to a wiring to which a second potential is supplied; one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the fifth transistor is electrically connected to a wiring to which a third potential is supplied; a gate of the fifth transistor is electrically connected to a gate of the third transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to a wiring to which the first potential is supplied; a gate of the sixth transistor is electrically connected to a gate of the third transistor; back gates of the first to sixth transistors are electrically connected to a wiring to which a fourth potential is supplied; When the fifth transistor is in an on state, the fourth transistor is in an off state; An output circuit, wherein when the sixth transistor is in an on state, the second transistor is in an off state.

Images