Semiconductor device

Abstract

To suppression an insulation failure in a transfer mold type power module of a lead frame type.SOLUTION: A semiconductor device 101 comprises: at least one of control chips 1a and 1b that is provided to a position that is overlapped with a first die pad 3 in a pan view and is electrically connected to the first die pad 3; a plurality of power chips 2a to 2f that is mounted onto a plurality of second die pads 4c to 4f; a plurality of circuit patterns 7 and a plurality of wire pads 12 that are formed onto an upper surface of an insulation substrate 11 provided onto the upper surface of the first die pad 3; a plurality of first control wires 9 that electrically connects the plurality of wire pads 12 with at least one of the control chips 1a and 1b; and a plurality of second control wires 14 that electrically connects at least one of the control chips 1a and 1b with the plurality of power chips 2a to 2f.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a transfer mold type power module. [Background technology]

[0002] A transfer mold type power module has a structure in which a power chip and a control chip that controls the power chip are built in and sealed with insulating molded resin. Among transfer mold type power modules, there is a lead frame type in which the die pad and terminals of the control chip are configured with a lead frame formed from a copper plate, and connections between circuits are made with wires (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-141237 Summary of the Invention [Problem to be solved by the invention]

[0004] In a lead frame type transfer mold power module, there is a problem that the wires connecting the control chip and power chip are deformed when the molding resin is injected and come into contact with the lead frame, causing poor insulation.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to suppress insulation failure in a lead frame type transfer mold power module. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a first die pad, at least one control chip provided on the upper surface of the first die pad at a position overlapping the first die pad in a plan view and electrically connected to the first die pad, a plurality of control-side terminals for supplying signals to the at least one control chip, a plurality of second die pads, a plurality of power chips mounted on the plurality of second die pads respectively and controlled by the at least one control chip, a plurality of power-side terminals connected to the plurality of second die pads respectively, an insulating substrate provided on the upper surface of the first die pad, and a plurality of conductive terminals formed on the upper surface of the insulating substrate and electrically connected to the control-side terminals. The device comprises a circuit pattern, a plurality of wire pads formed on the upper surface of an insulating substrate and electrically connected to each of the plurality of circuit patterns, a plurality of first control wires electrically connecting the plurality of wire pads to at least one control chip, a plurality of second control wires electrically connecting at least one control chip to first connection regions of a plurality of power chips, and a molding resin that encapsulates at least one control chip, a plurality of power chips, a plurality of first control wires and a plurality of second control wires, wherein the first die pad, the plurality of second die pads, the plurality of control side terminals and the plurality of power side terminals are formed by a lead frame. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, control signals are transmitted from a plurality of control-side terminals to at least one control chip via a plurality of circuit patterns, a plurality of wire pads, and a plurality of first control wires. With this configuration, the plurality of wire pads are arranged close to the at least one control chip, thereby shortening the plurality of first control wires. Therefore, deformation of the plurality of first control wires and the resulting insulation failure can be suppressed when molding resin is injected. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a top view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] It is a top view of the semiconductor device according to Embodiment 2. [Figure 4] It is a cross-sectional view of the semiconductor device according to Embodiment 2. [Figure 5] It is a top view of the semiconductor device according to Embodiment 3.

Embodiments for Carrying Out the Invention

[0009] <A. Embodiment 1> <A-1. Structure> FIG. 1 is a top view of a semiconductor device 101 according to Embodiment 1. FIG. 2 is a cross-sectional view of the semiconductor device 101. The semiconductor device 101 is a transfer molded power module.

[0010] As shown in FIGS. 1 and 2, the semiconductor device 101 of Embodiment 1 includes a plurality of control chips 1a, 1b, a plurality of power chips 2a, 2b, 2c, 2d, 2e, 2f, a first die pad 3, a plurality of second die pads 4c, 4d, 4e, 4f, a plurality of control side terminals 5, a plurality of power side terminals 6, an insulating substrate 11, a plurality of circuit patterns 7, a plurality of wire pads 12, an insulating layer 13, and a mold resin 15. The first die pad 3, the plurality of second die pads 4c, 4d, 4e, 4f, the plurality of control side terminals 5, and the plurality of power side terminals 6 are formed by a lead frame. In this specification, when referring to the plurality of control chips 1a, 1b as a whole without individually specifying them, they may be referred to as control chip 1. Similarly, for the plurality of power chips 2a, 2b, 2c, 2d, 2e, 2f or the plurality of second die pads 4c, 4d, 4e, 4f, they may be referred to as power chip 2 or second die pad 4.

[0011] The control-side terminals 5 and the power-side terminals 6 are terminals for electrically connecting the semiconductor device 101 to an external device provided outside the semiconductor device 101. The control-side terminals 5 are terminals for controlling the operation of the power chip 2 and for notifying the external device of an abnormality in the semiconductor device 101. For example, the control-side terminals 5 are connected to a microcomputer. The power-side terminals 6 are a path for the main current flowing through the semiconductor device 101 and are terminals for flowing the main current to the external device.

[0012] The semiconductor device 101 of the first embodiment has a built-in three-phase AC output inverter circuit. Here, the three phases refer to the U-phase, V-phase, and W-phase. The control chip 1b is an LVIC (Low Voltage Integrated Circuit) that controls the driving of the U-phase power chip 2d, the V-phase power chip 2e, and the W-phase power chip 2f. The three power chips 2a, 2b, and 2c form the P side. The control chip 1a is an HVIC (High Voltage Integrated Circuit) that controls the driving of the power chips 2a, 2b, and 2c. Note that the control chips 1a and 1b may be integrated into one control chip. That is, the semiconductor device 101 is required to include at least one control chip.

[0013] The power chips 2a, 2b, and 2c are mounted on the second die pad 4c. Of the power-side terminals 6, the one connected to the second die pad 4c is the P terminal. The power chip 2d is mounted on the second die pad 4d. Of the power-side terminals 6, the one connected to the second die pad 4d is the U terminal. The power chip 2e is mounted on the second die pad 4e. Of the power-side terminals 6, the one connected to the second die pad 4e is the V terminal. The power chip 2f is mounted on the second die pad 4f. Of the power-side terminals 6, the one connected to the second die pad 4f is the W terminal. If the power-side terminals 6 and the second die pad 4 are integrated, material can be minimized and the manufacturing process can be simplified. However, they do not have to be integrated. For example, the power-side terminals 6 and the second die pad 4 may be formed of separate members and connected by soldering, US bonding, or the like.

[0014] The control chip 1 is mounted on a first die pad 3. The first die pad 3 may be integrated with some of the control-side terminals 5. By integrating the first die pad 3 with some of the control-side terminals 5, misalignment is suppressed.

[0015] An insulating substrate 11 is provided on the upper surface of the first die pad 3. The insulating substrate 11 is, for example, a PCB substrate. Since the insulating substrate 11 does not require heat dissipation, an inexpensive substrate may be used. A circuit pattern 7 made of a conductive material is provided on the upper surface of the insulating substrate 11. Furthermore, the insulating substrate 11 is provided with a plurality of through holes 8 that penetrate the insulating substrate 11 in the thickness direction. A conductive material is disposed in the through holes 8. Furthermore, wire pads 12 are provided on the upper surface of the insulating substrate 11.

[0016] Some of the circuit patterns 7 are joined to the control-side terminals 5 via through holes 8, and are electrically connected to the control-side terminals 5. Solder, for example, is used to join the circuit patterns 7 to the control-side terminals 5 at the through holes 8. Some of the through holes 8 are not electrically connected to the circuit patterns 7. The through holes 8 that are not electrically connected to the circuit patterns 7 are joined to the first die pad 3 by solder or the like, and serve to fix the insulating substrate 11 to the first die pad 3.

[0017] A portion of the circuit patterns 7 is electrically connected to wire pads 12. One end of a first control wire 9 is connected to the wire pad 12. The other end of the first control wire 9 is connected to the control chip 1. With this configuration, in the semiconductor device 101, a signal for controlling the power chip 2 is transmitted from the control-side terminal 5 to the control chip 1 via the through-hole 8, the circuit patterns 7, the wire pads 12, and the first control wire 9.

[0018] The control chip 1 transmits a control signal to the power chip 2 via the second control wire 14 to control the operation of the power chip 2 as a three-phase AC output inverter. The second control wire 14 connects the control chip 1 and the power chip 2. The region of the power chip 2 to which the second control wire 14 is connected is called the first connection region 21. If the power chip 2 includes a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the first connection region 21 is a gate pad, and the second control wire 14 is a gate wire. Note that the power chip 2 is not limited to a MOSFET, and may also be an SBD (Schottky Barrier Diode), an IGBT (Insulated Gate Bipolar Transistor), or a PN diode. The control chip 1 is connected to the first die pad 3 via a through hole 8 provided in the insulating substrate 11 and solder.

[0019] The power chip 2 and the power-side terminal 6 are connected by the main wire 10. The area of the power chip 2 to which the main wire 10 is connected is referred to as the second connection area 22. Since a large current flows through the main wire 10, which is different from the first control wire 9 and the second control wire 14, it is configured to have a thicker diameter than the first control wire 9 and the second control wire 14 in order to suppress heat generation. Since the plurality of wire pads 12 are arranged close to the control chip 1, the longest first control wire 9 is shorter than the longest second control wire 14.

[0020] The control chip 1, the power chip 2, the first die pad 3, the second die pad 4, the insulating substrate 11, the plurality of circuit patterns 7, the plurality of wire pads 12, the first control wire 9, the main wire 10, the second control wire 14, and the insulating layer 13 are sealed by the mold resin 15. Thereby, internal circuits such as the control chip 1 and the power chip 2 are fixed, and insulation from the outside of the semiconductor device 101 is ensured. However, the control-side terminal 5 and the power-side terminal 6 protrude so as to be exposed from the mold resin 15 so that electrical connection to the outside is possible. The second die pad 4 is connected to the insulating layer 13. The insulating layer 13 is made of a member having a better thermal conductivity than the mold resin 15, whereby the heat generated in the power chip 2 is efficiently dissipated.

[0021] Although not shown in FIGS. 1 and 2, the semiconductor device 101 may incorporate a BSD (Boot Strap Diode). In this case, an opening may be provided in the insulating substrate 11 at a position overlapping the position of the first die pad 3 on which the BSD is mounted in a plan view, and the BSD may be connected to the control-side terminal 5 by soldering or the like through the opening.

[0022] <A-2. Effect> The semiconductor device 101 according to the first embodiment includes a first die pad 3, a plurality of control chips 1a and 1b, a plurality of control-side terminals 5, a plurality of second die pads 4c-4f, a plurality of power chips 2a-2f, a plurality of power-side terminals 6, an insulating substrate 11, a plurality of conductive circuit patterns 7, a plurality of wire pads 12, a plurality of first control wires 9, a plurality of second control wires 14, and a molding resin 15. The plurality of control chips 1a and 1b are provided on the upper surface of the first die pad 3 at positions overlapping the first die pad 3 in a plan view and are electrically connected to the first die pad 3. The plurality of control-side terminals 5 are terminals for supplying signals to the plurality of control chips 1a and 1b. The plurality of power chips 2a-2f are mounted on the plurality of second die pads 4c-4f, respectively, and are controlled by the plurality of control chips 1a and 1b. The plurality of power-side terminals 6 are connected to the plurality of second die pads 4c-4f, respectively. An insulating substrate 11 is provided on the upper surface of the first die pad 3. A circuit pattern 7 is formed on the upper surface of the insulating substrate 11 and electrically connected to the control-side terminals 5. A plurality of wire pads 12 are formed on the upper surface of the insulating substrate 11 and electrically connected to each of the plurality of circuit patterns 7. A plurality of first control wires 9 electrically connect the plurality of wire pads 12 to the plurality of control chips 1a and 1b. A plurality of second control wires 14 electrically connect the plurality of control chips 1a and 1b to first connection regions 21 of the plurality of power chips 2. A molding resin 15 encapsulates the plurality of control chips 1a and 1b, the plurality of power chips 2, the plurality of first control wires 9, and the plurality of second control wires 14. The first die pad 3, the plurality of second die pads 4, the plurality of control-side terminals 5, and the plurality of power-side terminals 6 are formed of a lead frame.

[0023] With the above configuration, in the semiconductor device 101, a control signal is transmitted from the control-side terminal 5 to the control chips 1a and 1b via the circuit pattern 7, wire pad 12, and first control wire 9. By arranging the wire pad 12 near the control chips 1a and 1b, the first control wires 9 can be shortened. It is also possible to make the longest first control wire 9 among the multiple first control wires 9 shorter than the longest second control wire 14 among the multiple second control wires 14. Therefore, deformation of the first control wires 9 during sealing with the mold resin 15 can be suppressed, and the resulting insulation failure can be suppressed.

[0024] 2, the second control wire 14 extends from the control chip 1 in the first direction D1 to reach the power chip 2. The end 11E of the insulating substrate 11 in the first direction D1 protrudes further toward the first connection regions 21 of the power chips 2 than the end 3E of the first die pad 3 in the first direction D1. With the above configuration, even if the second control wire 14 is deformed during the molding process, it will come into contact with the end 11E of the insulating substrate 11 as shown by the dashed line in FIG. 2. This prevents the second control wire 14 from coming into contact with the end 3E of the first die pad 3 and the resulting insulation failure.

[0025] In the semiconductor device 101, multiple control chips 1a, 1b are mounted on the upper surface of an insulating substrate 11 and are electrically connected to the first die pad 3 via through holes 8 provided in the insulating substrate 11. In this way, because the control chips 1a, 1b are mounted on the insulating substrate 11 instead of the first die pad 3, there is no need to change the lead frame for small-lot production, making it possible to suppress cost increases by standardizing components. Furthermore, multiple elements with different reference voltages, such as floating electrodes or isolated drives, which are difficult to form on a lead frame, can be mounted on the insulating substrate 11.

[0026] Furthermore, by forming the circuit pattern 7 on the insulating substrate 11 finely, the area of ​​the control chips 1a and 1b can be reduced, and as a result, the area of ​​the power chip 2 and its die area can be increased.

[0027] Furthermore, without changing the outer shape of the general-purpose package, it is possible to increase the current capacity, that is, improve the power density.

[0028] <A-3. Variation> For the insulating substrate 11, a high heat-resistant material having heat resistance equal to or higher than the curing temperature of the mold resin 15 may be used. Thereby, it becomes possible to form a power semiconductor device with a general-purpose package or a general-purpose pin arrangement. Also, cost reduction is possible by the commonality of materials and processes, and total cost reduction is possible by substrate commonality in an application set.

[0029] The power chip 2 may be equipped with a MOSFET made of a wide bandgap material such as SiC, GaN, or Ga2O3. Since this MOSFET is a high breakdown voltage unipolar device, it has low switching loss and enables high carrier operation. However, by using a gate driver with high narrow pulse reactivity (such as a micro transformer method, etc.), it is possible to improve the pulse response and the efficiency of waveform generation.

[0030] Also, when configuring with packages of the same size, by using a control board, the wiring area can be reduced, so it becomes possible to increase the output capacity of the IC driver. That is, it becomes possible to increase the speed of the power semiconductor chip. Also, in a gate driver with a multi-chip configuration such as a micro transformer, a floating electrode or power supply is required, but by using the insulating substrate 11, freedom in the mounting position is provided, so it becomes possible to reduce the module area.

[0031] <B. Embodiment 2> <B-1. Configuration> FIG. 3 is a top view of the semiconductor device 102 according to Embodiment 2. FIG. 4 is a cross-sectional view of the semiconductor device 102.

[0032] The semiconductor device 102 is different from the semiconductor device 101 according to the first embodiment in that the control chips 1a and 1b are joined to the first die pad 3 with a conductive bonding material such as solder. The insulating substrate 11 has an opening 11A, and the control chips 1a and 1b are joined to the upper surface of the first die pad 3 in the opening 11A. In other words, the control chips 1a and 1b are provided at positions overlapping the opening 11A of the insulating substrate 11 in a plan view.

[0033] <B-2. Effect> In the semiconductor device 102 according to the second embodiment, the control chips 1a and 1b are mounted on the upper surface of the first die pad 3 within the opening 11A provided in the insulating substrate 11. Since the first die pad 3 made of a lead frame such as copper has higher heat dissipation than the insulating substrate 11, the semiconductor device 102 is configured to have higher heat dissipation than the semiconductor device 101 according to the first embodiment. Therefore, the temperature rise of the semiconductor device 102 is suppressed even during high voltage or high carrier operation.

[0034] <C. Third Embodiment> <C-1. Configuration> FIG. 5 is a top view of the semiconductor device 103 according to the third embodiment.

[0035] The semiconductor device 103 is different from the semiconductor device 102 according to the second embodiment in that a part of each of the plurality of power chips 2 and the plurality of second die pads 4 is disposed below the insulating substrate 11 so as to overlap the insulating substrate 11 in a plan view. Note that the semiconductor device 103 may be such that a part of each of the plurality of power chips 2 and the plurality of second die pads 4 on which the plurality of power chips 2 are mounted is disposed below the insulating substrate 11 with respect to the semiconductor device 101 according to the first embodiment.

[0036] On the other hand, in the plurality of power chips 2, the first connection region 21 to which the second control wire 14 is connected and the second connection region 22 to which the main wire 10 is connected do not overlap the insulating substrate 11 in a plan view.

[0037] In semiconductor device 103 according to the third embodiment, the multiple power chips 2 and multiple second die pads 4c-4f are arranged below insulating substrate 11 so that a portion of each of them overlaps insulating substrate 11 in a plan view. The connection regions of the multiple power chips 2 do not overlap insulating substrate 11 in a plan view. With the above configuration, semiconductor device 103 can increase the area of ​​power chip 2 in a general-purpose package, thereby enabling an improvement in power density.

[0038] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims.

[0039] Various aspects of the present disclosure are summarized below as appendices.

[0040] (Appendix 1) a first die pad; at least one control chip provided on the upper surface side of the first die pad at a position overlapping the first die pad in a plan view and electrically connected to the first die pad; a plurality of control-side terminals for supplying signals to the at least one control chip; a plurality of second die pads; a plurality of power chips mounted on the plurality of second die pads, respectively, and controlled by the at least one control chip; a plurality of power-side terminals connected to the plurality of second die pads, respectively; an insulating substrate provided on an upper surface of the first die pad; a plurality of conductive circuit patterns formed on an upper surface of the insulating substrate and electrically connected to the control-side terminals; a plurality of wire pads formed on the upper surface of the insulating substrate and electrically connected to the plurality of circuit patterns, respectively; a plurality of first control wires electrically connecting the plurality of wire pads and the at least one control chip; a plurality of second control wires electrically connecting the at least one control chip and the first connection regions of the plurality of power chips; a molding resin that seals the at least one control chip, the plurality of power chips, the plurality of first control wires, and the plurality of second control wires; the first die pad, the plurality of second die pads, the plurality of control-side terminals, and the plurality of power-side terminals are formed of a lead frame; Semiconductor device.

[0041] (Appendix 2) The longest first control wire among the plurality of first control wires is shorter than the longest second control wire among the plurality of second control wires; 2. The semiconductor device according to claim 1.

[0042] (Appendix 3) the second control wire extends from the at least one control chip in a first direction to the power chip; an end portion of the insulating substrate in the first direction protrudes toward the first connection region of the plurality of power chips more than an end portion of the first die pad in the first direction; 10. The semiconductor device according to claim 1 or 2.

[0043] (Appendix 4) the at least one control chip is mounted on the upper surface of the insulating substrate and is electrically connected to the first die pad via a through hole provided in the insulating substrate; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film.

[0044] (Appendix 5) the at least one control chip is mounted on the top surface of the first die pad within an opening in the insulating substrate; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film.

[0045] (Appendix 6) the plurality of power chips and the second die pad are disposed below the insulating substrate so that a portion of each of the power chips and the second die pad overlaps the insulating substrate in a plan view; the first connection regions of the plurality of power chips do not overlap the insulating substrate in a plan view; 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film.

[0046] (Appendix 7) the insulating substrate is made of a material having heat resistance equal to or higher than the hardening temperature of the molding resin; 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0047] (Appendix 8) The power chip includes a MOSFET made of a wide bandgap material. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer. [Explanation of symbols]

[0048] 1, 1a, 1b control chip, 2, 2a, 2b, 2c, 2d, 2e, 2f power chip, 3 first die pad, 3E end, 4, 4c, 4d, 4e, 4f second die pad, 5 control side terminal, 6 power side terminal, 7 circuit pattern, 8 through hole, 9 first control wire, 10 main wire, 11 insulating substrate, 11A opening, 11E end, 12 wire pad, 13 insulating layer, 14 second control wire, 15 molding resin, 21 first connection region, 22 second connection region, 101, 102, 103 semiconductor device.

Claims

1. A first die pad; at least one control chip provided on an upper surface side of the first die pad at a position overlapping the first die pad in a plan view and electrically connected to the first die pad; A plurality of control side terminals for supplying signals to the at least one control chip; A plurality of second die pads; a plurality of power chips mounted on the plurality of second die pads, respectively, and controlled by the at least one control chip; a plurality of power side terminals connected to the plurality of second die pads, respectively; an insulating substrate provided on an upper surface of the first die pad; a plurality of conductive circuit patterns formed on an upper surface of the insulating substrate and electrically connected to the control-side terminals; a plurality of wire pads formed on an upper surface of the insulating substrate and electrically connected to the plurality of circuit patterns, respectively; a plurality of first control wires electrically connecting the plurality of wire pads and the at least one control chip; a plurality of second control wires electrically connecting the at least one control chip and the first connection regions of the plurality of power chips; a molding resin that encapsulates the at least one control chip, the plurality of power chips, the plurality of first control wires, and the plurality of second control wires; the first die pad, the plurality of second die pads, the plurality of control side terminals, and the plurality of power side terminals are formed of a lead frame; Semiconductor device.

2. a longest first control wire of the plurality of first control wires is shorter than a longest second control wire of the plurality of second control wires; The semiconductor device according to claim 1 .

3. the second control wire extends from the at least one control chip in a first direction to the power chip; an end portion of the insulating substrate in the first direction protrudes toward the first connection region of the power chips further than an end portion of the first die pad in the first direction; The semiconductor device according to claim 1 .

4. the at least one control chip is mounted on an upper surface of the insulating substrate and is electrically connected to the first die pad via a through hole provided in the insulating substrate; The semiconductor device according to claim 1 .

5. the at least one control chip is mounted on a top surface of the first die pad within an opening in the insulating substrate; The semiconductor device according to claim 1 .

6. the plurality of power chips and the second die pad are disposed below the insulating substrate such that a portion of each of the power chips and the second die pad overlaps with the insulating substrate in a plan view; the first connection regions of the plurality of power chips do not overlap with the insulating substrate in a plan view; The semiconductor device according to claim 1 .

7. the insulating substrate is made of a material having heat resistance equal to or higher than the hardening temperature of the molding resin; The semiconductor device according to claim 1 .

8. The power chip includes a MOSFET made of a wide bandgap material. The semiconductor device according to claim 1 .

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