Display device

Abstract

To reduce a parasitic capacitance of a signal line in a liquid crystal display device.SOLUTION: A transistor which includes an oxide semiconductor layer is applied as a transistor provided in each pixel. The oxide semiconductor layer is the oxide semiconductor layer whose purity is increased by thoroughly removing impurities (hydrogen, water or the like) being an electron donor (donor). With this, a leakage current (OFF-state current) in a case where the transistor is in the off-state can be reduced. Therefore, voltage applied to a liquid crystal element can be held without providing a capacitive element in each pixel. In association with this, capacitance wiring which extends in a pixel part of the liquid crystal display device can be deleted. Therefore, the parasitic capacitance in a region where the signal line and the capacitance wiring three-dimensionally cross each other can be deleted.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a liquid crystal display device. [Background technology]

[0002] An active matrix type liquid crystal display device having a plurality of pixels arranged in a matrix. Generally, the pixel has a gate electrically connected to a scan line and a source and a transistor having one of its drains electrically connected to a signal line, and one of its terminals connected to the transistor The other terminal is electrically connected to the other of the source and drain of the transistor, and the other terminal provides a common potential. A capacitance element electrically connected to a wiring (hereinafter also referred to as a capacitance wiring) that supplies The pixel electrode is connected to the other of the source and drain of the transistor and one of the terminals of the capacitance element. and the other terminal (opposite electrode) is electrically connected to the wiring that supplies the opposite potential. and a liquid crystal element.

[0003] An example of the structure of the pixel described above is shown in FIG. 13. FIG. 13(A) is a top view of the pixel. In FIG. 13, a part of the liquid crystal element (liquid crystal layer, counter electrode, etc.) is omitted. (This shows a so-called active matrix substrate). The pixel 100 shown in FIG. 100 is a scanning line 1001, 1002 and a scanning line 1001, 1003 arranged parallel or approximately parallel to each other. 1002. The pixel 1000 includes a transistor 1005, a capacitor 1006, and a pixel An electrode layer 1007 is provided. The layer (capacitor wiring 1008) is arranged parallel or approximately parallel to the scanning lines 1001 and 1002, and It is provided so as to cross a plurality of pixels.

[0004] FIG. 13B is a cross-sectional view taken along line AB in FIG. The gate electrode 1005 is a gate layer 1011 provided on a substrate 1010. A gate insulating layer 1012 is provided on the semiconductor layer 1012. 1013 and one of the source layer and drain layer 101 provided on one end of the semiconductor layer 1013 4a, and the other of the source and drain layers 1014 provided on the other end of the semiconductor layer 1013. The capacitance element 1006 is composed of a part of the capacitance wiring 1008 and the capacitance wiring 1009. 008 and a gate insulating layer (gate insulating layer 1012) provided on the insulating layer. The other of the source layer and the drain layer 1014b is also included. The other drain layer 1014b is provided on the transistor 1005 and the capacitor element 1006. In the contact hole 1016 formed in the insulating layer 1015, the pixel electrode layer 1007 is electrically connected to

[0005] 13C is a cross-sectional view taken along line CD shown in FIG. 003, the scanning line 1001 in the region 1017a and the capacitance wiring in the region 1017b 1008, and in the region 1017c, the scanning line 1002 and the gate insulating layer 1012 are Therefore, the signal line 1003 is connected to the areas 1017a, 1017b, and 1017c. 7c has a convex upper surface. Note that it has a similar top surface shape to 1003.

[0006] In addition, the liquid crystal display device having the pixel 1000 shown in FIG. The gate of the transistor 1005 and the capacitor wiring 1008 are formed from the same conductive film. The insulating layer 1012 is also used as a dielectric in the capacitance element 1006. It can be said that this liquid crystal display device is a liquid crystal display device in which the manufacturing process is simplified.

[0007] In the pixel 1000 shown in FIG. 13, a transistor 1005 is connected to a liquid crystal element. A function for controlling the input of a data signal that determines the voltage (electric potential applied to the pixel electrode layer 1007) The capacitance element 1006 has a function of detecting a voltage applied to the liquid crystal element (applied to the pixel electrode layer 1007). The device has the function of maintaining the potential at which the voltage is applied to the device.

[0008] For example, when the dielectric of the capacitance element 1006 is made of a silicon oxide film having a thickness of 0.1 μm, The area of ​​the capacitance element 1006 having a capacitance value of 0.4 pF is about 1160 μm 2 Here, the image If the pixel size is 42μm×126μm (4-inch VGA pixel), the pixel area is Therefore, the proportion of the capacitance element 1006 is about 22%, which causes a problem of a decrease in the aperture ratio. In addition, the capacitor element 1006 can be omitted from the above pixel configuration. Since the capacitor 1006 is not provided, a certain amount of charge can be stored. However, the relative dielectric constant of the liquid crystal is low, about 3, and the cell gap is 3 to 4 μm. m, a capacitance element 1006 with a silicon oxide film of 0.1 μm in thickness as a dielectric is used. The capacitance is about 1 / 50 of the original capacitance, so the area of ​​the liquid crystal element is 58,000μ m 2 In other words, this size is equivalent to a pixel of 140 μm × 420 μm. Therefore, the resolution is about 60 ppi, and LCD displays with a resolution lower than that Conversely, if the pixel is configured with a resolution of 60 ppi or more, In this case, a capacitive element 1006 is required.

[0009] In a liquid crystal display device, the potential of the scanning line 1001 is controlled to 1005 is turned on, and the potential of the signal line 1003 is set to the data This controls the liquid crystal element of the pixel 1000 to have a desired voltage. In addition, when the voltage is applied to the capacitor 1006 for a certain period of time, A desired display can be performed in each pixel for a certain period of time. By performing this operation on each pixel in sequence, an image (still image) is formed in the pixel area. Furthermore, the liquid crystal display device changes the images sequentially (for example, every second). The video is displayed by scanning the image 60 times (the frame frequency is 60 Hz).

[0010] As described above, the video is composed of many still images. In the strict sense, they are not continuous. Therefore, when displaying fast-moving video, there may be residual images on the display. In particular, in a liquid crystal display device, a data signal is input to each pixel. Each pixel maintains its display until the next data signal is input. This causes image retention. Patent Document 1 describes a technology for reducing image retention (commonly known as "double speed drive" technology). Specifically, in Patent Document 1, two consecutively displayed images are interpolated. By creating an image that matches the background and inserting it between two images that are displayed consecutively, There is disclosed a technique for reducing image lag by using the above-mentioned method. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 4-302289 Summary of the Invention [Problem to be solved by the invention]

[0012] The above-mentioned techniques increase the number of data signals input to each pixel per unit time. Therefore, in order to apply this technology to liquid crystal displays, It is necessary to drive the signal lines that supply data signals to the A parasitic capacitance occurs between a signal line extending to a pixel area and other lines extending to the pixel area. The parasitic capacitance can be an obstacle to high-speed driving of the signal line.

[0013] In view of the above, one embodiment of the present invention is to reduce parasitic capacitance of a signal line in a liquid crystal display device. This is one of the challenges. [Means for solving the problem]

[0014] In the liquid crystal display device of one embodiment of the present invention, a transistor provided in each pixel is A transistor including an oxide semiconductor layer is used. Note that the oxide semiconductor layer High purity by thoroughly removing donor impurities (such as hydrogen or water) The highly purified oxide semiconductor layer contains hydrogen, oxygen vacancies, and the like. The carrier density is 1×10 12 / cm 3 Less than 1 x 10 11 / cm3 That is, the hydrogen concentration of the oxide semiconductor layer is less than 100%. The carrier density due to oxygen vacancies and other factors is reduced to almost zero. Since there are very few carriers due to oxygen vacancies, etc., the transistor is in the off state. This can reduce the leakage current (off-state current).

[0015] This allows the voltage applied to the liquid crystal element to be held without providing a capacitance element in each pixel. In addition, it is possible to reduce the capacitance wiring extending to the pixel portion of the liquid crystal display device. Therefore, in the conventional liquid crystal display device, the signal lines and the scanning lines are eliminated. Parasitic capacitance occurs in areas where lines cross over each other and where signal lines and capacitance lines cross over each other. In contrast, in the liquid crystal display device according to one embodiment of the present invention, the parasitic capacitance caused by the latter is In other words, the parasitic capacitance of the signal line can be reduced.

[0016] That is, the liquid crystal display device according to one embodiment of the present invention has first scanning electrodes arranged in parallel or approximately in parallel. a first scanning line and a second scanning line, and a second scanning line arranged perpendicular or substantially perpendicular to the first scanning line and the second scanning line. The first signal line and the second signal line, and the gate are electrically connected to the first scanning line, and the source and One of the drains is electrically connected to a first signal line, and the other of the source and drain is a pixel voltage. and a transistor including an oxide semiconductor layer electrically connected to the electrode layer. The pixel electrode layer is connected to the first scanning line, the second scanning line, the first signal line, and the second signal line. Further, the first signal line and the second signal line are provided in the first scanning The first and second scanning lines are connected to each other through an insulating layer provided on the first and second scanning lines. The first signal line crosses the first scanning line in a first region and a second scanning line in a second region. In the second region where the scanning line crosses the upper surface, the upper surface has a convex shape. The upper surface has a planar or substantially planar shape in a region between the first region and the second region. That is, the upper surface of the first signal line is the same in the entire region between the first region and the second region. They exist on the same plane or approximately on the same plane. Effect of the Invention

[0017] In the liquid crystal display device according to one embodiment of the present invention, a transistor provided in each pixel is an oxide semiconductor A transistor having a conductor layer is applied. This allows a capacitance element provided in each pixel to be Specifically, if the LCD device has a resolution of 60 ppi or more, Even in a liquid crystal display device having a capacitance element, the voltage applied to the liquid crystal element can be reduced without providing a capacitance element in each pixel. This makes it possible to improve the aperture ratio of each pixel. In addition, it is possible to eliminate the capacitance wiring extending to the pixel portion of the liquid crystal display device. That is, in the liquid crystal display device, the parasitic capacitance of the signal line is reduced. Therefore, in the liquid crystal display device according to one embodiment of the present invention, It is possible to improve the driving frequency of the signal lines compared to the display device. The liquid crystal display device of one embodiment is suitable as a liquid crystal display device that performs double speed driving or higher. [Brief description of the drawings]

[0018] [Figure 1] 1A is a top view showing an example of a pixel structure of a liquid crystal display device, and FIG. 1B and FIG. [Diagram 2] FIG. 13 shows characteristics of a transistor. [Diagram 3] Circuit diagram for evaluating transistor characteristics. [Figure 4] 1 is a timing chart for evaluating transistor characteristics. [Diagram 5] FIG. 13 shows characteristics of a transistor. [Figure 6] FIG. 13 shows characteristics of a transistor. [Figure 7] FIG. 13 shows characteristics of a transistor. [Figure 8] FIG. 1 is a cross-sectional view showing an example of a pixel structure of a liquid crystal display device. [Figure 9] FIG. 1 is a cross-sectional view showing an example of a pixel structure of a liquid crystal display device. [Figure 10] 1A and 1B are cross-sectional views showing an example of a pixel structure of a liquid crystal display device. [Figure 11] 1A to 1D are cross-sectional views illustrating an example of a manufacturing process for a transistor. [Figure 12] 1A to 1F are diagrams showing examples of electronic devices. [Figure 13] 1A is a top view showing an example of a pixel structure of a liquid crystal display device, and FIG. 1B and FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0020] (Example of pixel structure) First, a structural example of a pixel included in a liquid crystal display device of one embodiment of the present invention will be described with reference to FIG. Specifically, one substrate on which pixel electrodes are provided and the other substrate on which a counter electrode is provided are A liquid crystal display device having a structure in which a liquid crystal material is sandwiched between two substrates (a vertical electric field is applied to the liquid crystal material) An example of the structure of a pixel of a liquid crystal display device will be described with reference to FIG.

[0021] FIG. 1A is a top view of a pixel. Note that in FIG. 1A, a part of a liquid crystal element ( The figure shows the structure of the active matrix substrate, with the liquid crystal layer, counter electrode, etc. omitted. The pixel 100 shown in FIG. 1(A) is a pixel having scanning lines arranged parallel or nearly parallel. 101, 102, and a signal line 103 arranged perpendicular or substantially perpendicular to the scanning lines 101, 102; The pixel 100 is provided in an area surrounded by a transistor 104. , and a pixel electrode layer 107. In other words, the pixel 100 shown in FIG. A configuration in which the components related to the capacitor element 1006 are removed from the pixel 1000 shown in FIG. It has a structure.

[0022] Fig. 1B is a cross-sectional view taken along line EF in Fig. 1A. 105 is a gate layer 111 provided on a substrate 110 and a A gate insulating layer 112, an oxide semiconductor layer 113 provided over the gate insulating layer 112, and an oxide semiconductor layer One of the source layer and drain layer 114a provided on one end of the oxide semiconductor layer 113, and the other of the source and drain layers 114b is provided on the other end of the oxide semiconductor layer 113. Note that the transistor 105 shown in FIGS. 1A and 1B is connected to the scan line 1 as a gate. The protruding portion of the signal line 103 is used as either the source or the drain. Therefore, the transistor 105 shown in FIGS. 101, and one of the source and drain is expressed as a part of the signal line 103. In addition, the other of the source layer and drain layer 114b may be a transistor 105. In the contact hole 116 formed in the insulating layer 115 provided thereon, the pixel electrode layer 107 is electrically connected to the

[0023] FIG. 1C is a cross-sectional view taken along line GH in FIG. The scanning line 101 is insulated from the scanning line 102 in the region 117a and the scanning line 102 in the region 117c. Therefore, the signal line 103 is connected to the gate insulating layer 112. The upper surfaces of the signal line 103 are convex in the regions 117a and 117c. In the region 117b between the region 17a and the region 117c, the upper surface has a flat or substantially flat shape. That is, the upper surface of the signal line 103 is in the entire region 117b between the regions 117a and 117c. In the liquid crystal display having the pixel 100, the pixels are on the same plane or approximately on the same plane. This is because the device does not have a capacitance wiring. It should be noted that the signal line 4 also has a similar top surface shape to the signal line 103.

[0024] As described above, the transistor 105 illustrated in FIG. 1 includes an oxide semiconductor layer 113 as a semiconductor layer. The oxide semiconductor used for the oxide semiconductor layer 113 is a quaternary metal oxide. In-Sn-Ga-Zn-O system, which is a ternary metal oxide, In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O system, Sn-Al-Zn-O system, binary metal oxide In-Zn-O system, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, In-M The material is made of In-O, Sn-O, Zn-O, or other single-element metal oxides. The oxide semiconductor may contain SiO2. An In-Ga-Zn-O-based oxide semiconductor is an oxide containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio. In addition, elements other than In, Ga, and Zn may be included. stomach.

[0025] The oxide semiconductor layer 113 is formed of a material represented by the chemical formula InMO3(ZnO). m (m>0) A thin film having a thickness of 100 nm or less can be used. Here, M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M is Ga, Ga and Al, Ga and Mn, Alternatively, Ga and Co can be selected.

[0026] In order to suppress fluctuations in electrical characteristics, the oxide semiconductor described above is designed to be free of hydrogen and moisture, which are factors that cause fluctuations. By intentionally eliminating impurities such as hydroxyl groups or hydrides (also called hydrogen compounds), It is an oxide semiconductor that has been purified and made electrically i-type (intrinsic).

[0027] Therefore, the less hydrogen there is in the oxide semiconductor, the better. There are very few carriers (close to zero) originating from hydrogen or oxygen vacancies in the semiconductor layer. The carrier density is 1×10 12 / cm 3 Less than 1 x 10 11 / cm 3 is less than That is, the carrier density due to hydrogen or oxygen vacancies in the oxide semiconductor layer is reduced to almost zero. Since the number of carriers derived from hydrogen, oxygen vacancies, and the like in the oxide semiconductor layer is extremely small, It is possible to reduce the leakage current (off-state current) when the transistor is in the off state. The smaller the current, the more preferable. The current value of the transistor is 100zA / μm (zeptoampere) per 1μm of channel width (w). a) or less, preferably 10zA / μm or less, or 1zA / μm or less. Since there are no junctions and no hot carrier degradation, the electrical characteristics of the transistor are Not affected.

[0028] In this way, the hydrogen contained in the oxide semiconductor layer is thoroughly removed, resulting in a highly purified oxide semiconductor layer. A transistor that uses an oxide semiconductor for a channel formation region has an extremely low off-state current. That is, when the transistor is off, the oxide semiconductor layer acts as an insulator. On the other hand, the oxide semiconductor layer can be regarded as a conductor for transistors. In the on-state, it is expected to have a higher current supply capacity than a semiconductor layer made of amorphous silicon. It is possible to do so.

[0029] The substrate 110 is made of glass such as barium borosilicate glass or aluminoborosilicate glass. A glass substrate can be used.

[0030] In the transistor 105, an insulating film serving as a base film is provided between the substrate 110 and the gate layer 111. The base film has a function of preventing diffusion of impurity elements from the substrate 110. A silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film is selected. The insulating film may be formed by a laminate structure of one or more films.

[0031] The material of the gate layer 111 is aluminum (Al), copper (Cu), titanium (Ti), tungsten (Te), or the like. Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium ( An element selected from among Nd, scandium (Sc), and an alloy containing the above elements; The nitrides containing the above-mentioned elements can be used. Structures can also be applied.

[0032] The gate insulating layer 112 is formed by using a plasma CVD method, a sputtering method, or the like. Silicon oxide layer, silicon nitride layer, silicon oxynitride layer, silicon nitride oxide layer, silicon oxide layer Aluminum layer, aluminum nitride layer, aluminum oxynitride layer, aluminum oxynitride layer Alternatively, an insulator such as a hafnium oxide layer can be applied. For example, a laminated structure formed by a plasma CVD method may be used as the first gate insulating layer. The silicon nitride layer (SiN y (y>0) A second gate insulating layer having a thickness of 5 nm to 300 nm is formed on the first gate insulating layer. Silicon oxide layer (SiO x (x>0) can be stacked.

[0033] The material of one of the source and drain layers 114a and the other of the source and drain layers 114b The materials are aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), and titanium. (Ti), molybdenum (Mo), tungsten (W), and the above elements An alloy containing the above-mentioned elements or a nitride containing the above-mentioned elements can be used. A laminated structure of these materials can also be applied. Titanium (Ti), molybdenum (M) or other metal layers are placed on either or both of the upper and lower sides of the metal layers. It is also possible to use a laminated structure of a high melting point metal layer such as tungsten (W). Elements that prevent the formation of hillocks and whiskers in aluminum (Al) films (Si, Nd Improve heat resistance by using aluminum alloys containing Cr, Sc, etc. This becomes possible.

[0034] In the above-mentioned liquid crystal display device, one of the source layer and the drain layer 114a is It is a part of the signal line 103. Therefore, from the viewpoint of high-speed driving of the signal line 103, The gate and drain layers are made of a low resistance conductive material so that no signal delay occurs. For example, a low-resistance conductive material such as copper (Cu) or an alloy containing copper as the main component is preferable. It is preferable to use copper (Cu) or an alloy with copper as the main component. It is also possible to use a laminate structure including layers made of the above.

[0035] In the above-described liquid crystal display device, a capacitive element is not provided in the pixel 100. Therefore, from the viewpoint of holding a data signal in the pixel 100, the oxide semiconductor layer In order to suppress the inflow of carriers, it is preferable to apply a metal nitride to the source and drain layers. For example, it is preferable to use nitrides such as titanium nitride and tungsten nitride. In addition, the layer in contact with the oxide semiconductor layer may be made of a nitride such as titanium nitride or tungsten nitride. It is also possible to form a laminated structure in which another conductive layer is formed on the upper layer. For example, For example, it is possible to use a laminated structure of stainless steel and copper (Cu).

[0036] In addition, one of the source and drain layers 114a and the other of the source and drain layers 114 b (including the wiring layer formed in the same layer) is a conductive metal oxide film. The conductive metal oxide may be indium oxide (In2O3), Tin (SnO2), zinc oxide (ZnO), indium oxide tin oxide alloy (In2O3-S nO2, abbreviated as ITO), indium oxide zinc oxide alloy (In2O3-ZnO) or For the insulating layer, a material containing silicon oxide in these metal oxide materials can be used.

[0037] The insulating layer 115 is typically a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An inorganic insulating film such as an aluminum oxynitride film or an aluminum oxide nitride film can be used.

[0038] In addition, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, and a silicon nitride film are formed on the insulating layer 115. An inorganic insulating film such as an aluminum nitride oxide film can be formed.

[0039] Furthermore, a planarization process is performed on the insulating layer 115 to reduce surface irregularities caused by the transistor 105. An insulating film may be formed. The planarizing insulating film may be made of polyimide, acrylic resin, or benzosilane. In addition to the above organic materials, organic materials such as low dielectric constant resins, cyclobutene resins, etc. can be used. A material having a high dielectric constant (low-k material) can be used. A planarizing insulating film may be formed by stacking a plurality of insulating films.

[0040] (Off-state current of the transistor 105) Next, the off-state current of a transistor including a highly purified oxide semiconductor layer was measured. The results will be explained.

[0041] First, the off-state current of a transistor including a highly purified oxide semiconductor layer is sufficiently small. Considering the fact that the channel width W is large enough, 1 m, a transistor is prepared and the off-current The off-current of a transistor with a channel width W of 1 m was measured. In FIG. 2, the horizontal axis is the gate voltage VG, and the vertical axis is the drain current ID. When the voltage VD is +1V or +10V, the gate voltage VG is in the range of -5V to -20V. The off-current of the transistor is 1×10, which is the detection limit. -12 It is clear that it is below A. In addition, the off-state current density of the transistor (here, per unit channel width (1 μm) The value of 1aA / μm (1×10 -18 It was found that the maximum capacitance was less than 1.5 A / μm.

[0042] Next, the off-state current of a transistor including a highly purified oxide semiconductor layer is measured more accurately. As described above, the results obtained by the present invention will be described. The off-state current of the transistor is 1×10 -12 A or below Therefore, we fabricated a device for evaluating the characteristics and obtained a more accurate value of the off-state current ( The results of the determination of the concentration of 100 ppm or less (values ​​below the detection limit of the measuring instrument) are explained below.

[0043] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0044] The characteristic evaluation element shown in FIG. 3 has three measurement systems 800 connected in parallel. 0 is a capacitor element 802, a transistor 804, a transistor 805, and a transistor 806 The transistor 804 and the transistor 808 include a high-purity In the present embodiment, a transistor including a gate insulating film was used.

[0045] In the measurement system 800, one of the source and drain of a transistor 804 and a capacitance element One terminal of 802 and one of the source and drain of the transistor 805 are connected to a power supply (V In addition, the source and drain of the transistor 804 are connected to On the other hand, one of the source and drain of the transistor 808 and the other terminal of the capacitor 802 and the gate of the transistor 805 are electrically connected to each other. The other of the source and drain of transistor 808 and one of the source and drain of transistor 806 The gate of the transistor 806 is electrically connected to a power supply (the power supply that provides V1). In addition, the other of the source and drain of the transistor 805 and the source of the transistor 806 The other of the source and drain is electrically connected to an output terminal.

[0046] The gate of the transistor 804 is connected to a resistor R1, R2, and R3. A potential Vext_b2 is supplied to the gate of the transistor 808 to control the A potential Vext_b1 is supplied to control the ON and OFF states of the switch 808. The potential Vout is output from the output terminal.

[0047] Next, a current measuring method using the above-mentioned characteristic evaluation element will be described.

[0048] First, an outline of the initial period during which a potential difference is applied to measure the off-state current will be described. In the initial period, the gate of the transistor 808 is connected to the transistor 808 to turn the transistor 808 on. A potential Vext_b1 is input to the other of the source and drain of the transistor 804. A node that is electrically connected (i.e., one of the source and drain of the transistor 808, The other terminal of the capacitor 802 and the gate of the transistor 805 are electrically connected to A potential V1 is applied to a node A, which is a power supply (power supply voltage V1). Here, the potential V1 is, for example, a high potential. Moreover, the transistor 804 is kept in an off state.

[0049] Thereafter, a potential V ext_b1 is input to turn off the transistor 808. After the transistor 804 is turned off, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initial period is over, the node A and the source and drain of the transistor 804 A potential difference is generated between node A and the source and drain of transistor 808. Since a potential difference occurs between the drain and the other drain, the transistor 804 and the transistor A small amount of charge flows through the transistor 808. In other words, an off-current occurs.

[0050] Next, an outline of the measurement period of the off-state current will be described. The potential (V2) of one of the source and drain of the transistor 804 and the potential (V3) of the source of the transistor 808 are connected to the The other potential (V1) of the source and drain is fixed at a low potential. The potential of the node A is not fixed (floating state). Charge flows through transistor 804 and transistor 808 and is held at node A over time. The charge stored at node A fluctuates. In other words, the output potential Vout of the output terminal also fluctuates.

[0051] Details of the relationship between the potentials during the initial period in which the potential difference is applied and the subsequent measurement period The details (timing chart) are shown in Figure 4.

[0052] In the initial period, first, the potential Vext_b2 is set to the ON state by the transistor 804. This makes the potential of node A V2, that is, the low potential ( Note that it is not essential to apply a low potential (VSS) to node A. The potential Vext_b2 is set to a potential (low potential) at which the transistor 804 is turned off. Then, the transistor 804 is turned off. The potential (high potential) is set so that the transistor 808 is turned on. The potential of A becomes V1, that is, the high potential (VDD). Then, Vext_b1 is This sets the node A to a floating potential so that the resistor 808 is turned off. The initial period ends when the switching state is reached.

[0053] In the subsequent measurement period, electric charges flow into node A at potentials V1 and V2. Or, the potential is set so that charge flows out from node A. Here, potential V1 and potential V2 is the low potential (VSS). However, at the timing when the output potential Vout is measured, In order to operate the output circuit, V1 must be temporarily set to a high potential (VDD). Note that the period when V1 is at a high potential (VDD) is short enough that it does not affect the measurement. Between.

[0054] When a potential difference is applied as described above and the measurement period is started, the voltage at node A The amount of charge held by the transistor fluctuates, and the potential at node A fluctuates accordingly. This means that the potential of the gate of the resistor 805 fluctuates over time. The potential of the output potential Vout of the transistor also changes.

[0055] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0056] Before calculating the off-state current, the relationship between the potential VA of node A and the output potential Vout is calculated. This makes it possible to obtain the potential VA of the node A from the output potential Vout. From the above relationship, the potential VA of node A is expressed as a function of the output potential Vout as follows: It is possible.

[0057]

number

[0058] The charge QA at node A is determined by the potential VA at node A, the capacitance CA connected to node A, Using a constant (const), it is expressed as follows: The quantity CA is the capacitance of the capacitive element 802 plus the other capacitances.

[0059]

number

[0060] The current IA at node A is the charge flowing into (or out of) node A. Since this is the time derivative of , the current IA at node A is expressed as follows:

[0061]

number

[0062] In this way, the capacitance CA connected to node A and the output potential Vout of the output terminal are The current IA of node A can be calculated.

[0063] By using the method described above, the current that flows between the source and drain of the transistor in the off state The leakage current (off current) can be measured.

[0064] Here, a highly purified oxide film with a channel length L=10 μm and a channel width W=50 μm is used. Transistors 804 and 808 having a semiconductor layer were fabricated. In the system 800, the capacitance values ​​of the capacitive elements 802 were set to 100 fF, 1 pF, and 3 pF.

[0065] In the above measurements, VDD = 5 V and VSS = 0 V. In principle, the potential V1 is set to VSS, and a 100 msec. Vout was measured as VDD for a certain period. The time Δt was set to approximately 30,000 sec.

[0066] FIG. 5 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 5, it can be seen that the potential changes over time.

[0067] FIG. 6 shows the off-state current at room temperature (25° C.) calculated from the above current measurement. 6 shows the source-drain voltage V of the transistor 804 or the transistor 808. , and the off-current I. From FIG. 6, under the condition of a source-drain voltage of 4 V, The off-current was found to be about 40 zA / μm. It was found that the off-state current was 10 zA / μm or less under the condition of a voltage of 3.1 V. In addition, 1zA is 10 -21 Represents A.

[0068] Furthermore, the off-state current calculated from the above current measurement in a temperature environment of 85°C FIG. 7 shows the transistor 804 or the transistor 7 shows the relationship between the source-drain voltage V and the off-current I of the transistor 808. At a source-drain voltage of 3.1 V, the off-state current is 100 zA / μm or less. I realized something.

[0069] As described above, in a transistor including a highly purified oxide semiconductor layer, the off-state current It was confirmed that it was small enough.

[0070] (Regarding a liquid crystal display device having pixel 100) The liquid crystal display device disclosed in this specification includes a transistor 105 having an oxide semiconductor layer. The oxide semiconductor layer is applied to a transistor provided in each pixel. Since the off-current of the transistor 105 is small, in the liquid crystal display device, a capacitance element is provided for each pixel. Therefore, it is possible to hold the voltage applied to the liquid crystal element without providing a In addition, it is possible to improve the aperture ratio in the liquid crystal display device. Therefore, the liquid crystal display device disclosed in this specification can eliminate the capacitance wiring. In this case, there is no parasitic capacitance due to the capacitance wiring. There is no parasitic capacitance in the region where the insulating layer crosses. In the liquid crystal display device disclosed in the document, it is possible to improve the driving frequency of the signal lines. That is, the liquid crystal display device disclosed in this specification is a liquid crystal display device that performs double speed driving or faster. It is suitable as a display device.

[0071] In addition, when driving at double speed or higher, the rewrite frequency of the data signal in each pixel In other words, the voltage applied to the liquid crystal element in each pixel is increased. This shortens the period of time. This reduces the fluctuation of the voltage applied to the liquid crystal element (resulting in poor display in each pixel). It is possible to further reduce the change (change) in the composition of the present specification. The same effect can also be obtained when the liquid crystal display device is driven by a field sequential method. That is, the liquid crystal display device disclosed in this specification is applied to a field sequential method. It is preferable to perform driving by the formula.

[0072] In particular, the liquid crystal display device disclosed in the present specification is suitable for use in a large liquid crystal display device (e.g., a 40-inch liquid crystal display device). The effect is great when used as a large-area display (up to 1000mW). As a result, the probability of data signal delays becoming apparent is high. The liquid crystal display device disclosed in the publication is characterized in that the parasitic capacitance generated in the signal line is reduced, thereby It is possible to reduce delays and other issues. In addition, When the number of pixels is the same, the size of each pixel in a large liquid crystal display device becomes large. This means that the capacitance of the liquid crystal element itself becomes large. In addition to providing a transistor 105 having a solid semiconductor layer in each pixel, By increasing the capacitance, it is possible to further reduce the fluctuation of the voltage applied to the liquid crystal element. It becomes Noh.

[0073] The liquid crystal display device disclosed in this specification is a high-definition (high-pixel count) liquid crystal display device. (For example, full high definition (FHD), 2K4K or higher) As the resolution of liquid crystal display devices increases (the number of pixels increases), the number of wiring lines provided in the pixel area also increases. As the capacitance increases, the probability that the parasitic capacitance generated in the signal line will increase increases. In the liquid crystal display device disclosed in this specification, since no capacitance wiring is provided, the parasitic capacitance is not increased. In addition, it is possible to reduce the number of pixels in a liquid crystal display device. When the sizes of the liquid crystal display devices are the same, the wiring density in the pixel portion of the former is This means that the aperture ratio of each pixel is reduced. In the liquid crystal display device disclosed in the above, since a capacitance element is not provided in each pixel, the aperture ratio is low. It is possible to suppress the decrease.

[0074] In the conventional liquid crystal display device, the retention characteristics of the data signal in each pixel are mainly The off-state current was determined by the characteristics of the transistor installed in each pixel. In addition, a transistor 105 including a highly purified oxide semiconductor layer is provided in each pixel. By using it as a transistor, the characteristics of the liquid crystal element (the current flowing through the liquid crystal element) That is, in the liquid crystal display device disclosed in the present specification, The effect of charge leakage through the liquid crystal element is greater than that of charge leakage through the transistor 105. Therefore, it is preferable to use a substance with a high specific resistivity as the liquid crystal material of the liquid crystal element. Specifically, in the liquid crystal display device disclosed in the present specification, the liquid crystal material is preferably The resistivity is 1×10 12 Ω cm or more, preferably 1×10 13 Exceeds Ω cm More preferably, the concentration is 1×10 14 It is preferable that it exceeds Ω·cm. In addition, when a liquid crystal element is constructed using the liquid crystal material, the resistivity of the liquid crystal element is Considering the possibility of impurities from the alignment film and sealing material being mixed in, 11 Ω·c m or more, more preferably 1×10 12 It is preferable that the resistance exceeds Ω cm. In addition, the resistivity value in this specification is a value measured at 20°C.

[0075] (Modifications of pixel structure) The liquid crystal display device having the above-described structure is one embodiment of the present invention. The present invention also includes a liquid crystal display device having the above-mentioned features.

[0076] For example, in the above-mentioned liquid crystal display device, between the signal line 103 and the scanning lines 101 and 102 1C shows a structure in which only the gate insulating layer 112 is provided. A structure in which an oxide semiconductor layer 201 is provided between the line 103 and the gate insulating layer 112 (see FIG. 8(A)) That is, the oxide semiconductor layer 1 of the transistor 105 may be In the process of forming 13 (photolithography process and etching process), The oxide semiconductor layer is left without being etched even in the region where the line 103 is to be formed. In this way, it is possible to form an oxide semiconductor layer between the signal line 103 and the gate insulating layer 112. By providing the dielectric layer 201, the parasitic capacitance between the signal line 103 and the scanning lines 101 and 102 is can be further reduced.

[0077] In addition, an oxide semiconductor layer is selectively provided between the signal line 103 and the gate insulating layer 112. For example, the signal line 103 and the scanning lines 101 and 102 cross each other in a three-dimensional manner. The oxide semiconductor layers 202a and 202b are selectively provided in the regions 117a and 117c. In addition to the regions 117a and 117c, In the structure, the oxide semiconductor layers 202a and 202b are selectively provided in a part of the region 117b. In this case, the signal line 103 and the gate insulator The oxide semiconductor layer between the edge layers 112 is formed so that the upper surface of the signal line 103 is However, in this specification, the shape of the upper surface is included in the shape of a substantially flat surface. In other words, the scan lines 101 and 102 and the oxide semiconductor layers 202a and 202b are In the entire region between the signal line 103 and the gate insulating layer 11 2 are in direct contact with each other, and the upper surfaces of the signal lines 103 are all on the same plane throughout the entire area. Or they are substantially on the same plane.

[0078] In the above-mentioned liquid crystal display device, a bottom transistor is provided in each pixel. The transistor 105 is a type of channel-etched transistor with a gate structure. However, transistors having other structures may also be used. For example, a channel transistor, which is a type of bottom gate transistor, can be used. A top-type transistor 210 (see FIG. 9A) or a bottom-gate transistor A bottom-contact type transistor 220 (see FIG. 9B), which is a type of transistor, is used. It is possible to do so.

[0079] Specifically, a channel stop type transistor 210 shown in FIG. 0 and a gate insulating layer 112 provided on the gate layer 111. an oxide semiconductor layer 113 provided over the gate insulating layer 112; An insulating layer 211 that functions as a channel protection layer provided on the center of the oxide semiconductor layer One of the source and drain layers 111 is provided on one end of the insulating layer 211 and the other end of the insulating layer 213. 4a, and a source layer and a source layer provided on the other end of the oxide semiconductor layer 113 and the other end of the insulating layer 211. The insulating layer 211 is a silicon oxide film, an oxide Inorganic insulating film such as a silicon nitride film, an aluminum oxide film, or an aluminum oxynitride film The electrode can be formed using:

[0080] In addition, a bottom-contact type transistor 220 shown in FIG. A gate layer 111 is provided, a gate insulating layer 112 is provided on the gate layer 111, and a gate One of the source layer and drain layer 114a provided on the gate insulating layer 112, and a source the other of the source and drain layers 114b, and one end of the source and drain layers 114a, A gate insulating layer 112 is provided on one end of the other of the source and drain layers 114b. and an oxide semiconductor layer 113 formed thereon.

[0081] Furthermore, the transistor provided in each pixel is a channel stop type transistor 210 In this case, the insulating layer 212 is provided between the signal line 103 and the gate insulating layer 112 (see FIG. Note that the insulating layer 212 can be formed as a The insulating layer is formed from the same material as the insulating layer 211 that functions as a channel protection layer. In addition, a structure in which an oxide semiconductor layer is provided between the gate insulating layer 112 and the insulating layer 212 (see FIG. Note that the oxide semiconductor layer may be formed in the transistor 210. The oxide semiconductor layer is formed using the same material as the oxide semiconductor layer 113 included in the first embodiment. The oxide semiconductor layer and the insulating layer are selected only on the scan lines 101 and 102. It is also possible to provide a configuration (not shown) in which the sensor is provided on a surface other than the sensor.

[0082] In addition, a top-gate transistor 230 (FIG. 10A) is used as the transistor 105. Specifically, a top-gate type as shown in FIG. The transistor 230 includes a base insulating layer 231 and a base insulating layer 232 provided on the substrate 110. 1, and a gate electrode 113 provided on the oxide semiconductor layer 113. An insulating layer 112, a gate layer 111 provided on the gate insulating layer 112, and an oxide semiconductor layer 113 and a contact hole 2 formed in an insulating layer 232 provided on the gate layer 111. In the oxide semiconductor layer 113, one of the source layer and the drain layer 114a is in contact with the oxide semiconductor layer 113. In addition, a conductive layer 232 is formed on the oxide semiconductor layer 113 and the gate layer 111. The source and drain layers in contact with the oxide semiconductor layer 113 in the contact hole 233b In addition, the other of the source and drain layers 114b is a transistor. In a contact hole 235 formed in an insulating layer 234 provided on a resistor 230, , and is electrically connected to the pixel electrode layer 107. In this case, the signal line 103 is a, 117c cross the scanning lines 101, 102 through the insulating layer 232. (See FIG. 10B). The base insulating layer 231 is a silicon nitride film, a silicon oxide film, or the like. The insulating layer is made of one or more films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating layer 232 can be formed of a laminated structure. Silicon film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, aluminum nitride film a hafnium film, an aluminum oxynitride film, an aluminum nitride oxide film, or a hafnium oxide film. The insulating layer can be formed by a laminated structure of one or more films selected from any of the inorganic insulators. Note that the insulating layer 234 is formed using an inorganic insulator film similar to that of the insulating layer 232. The material is an organic material such as polyimide, acrylic resin, or benzocyclobutene resin. It can be formed by:

[0083] In the above-described liquid crystal display device, each pixel is provided with one transistor. However, it is also possible to provide a configuration in which two or more transistors are provided in each pixel. For example, a VA (Vertical Alignment) type LCD display Two transistors per pixel to address viewing angle issues with the device In the above, transistors including an oxide semiconductor layer are used as the two transistors. Here, the liquid crystal display device has a transistor connected to each pixel. It can be said that this is a liquid crystal display device having two circuit paths. In the LCD device, the area of ​​the capacitance element is reduced by providing two capacitance elements in each pixel. In other words, the aperture ratio is sacrificed in order to maintain the voltage applied to the liquid crystal element. In contrast, the liquid crystal element disclosed in this specification maintains the voltage applied to the liquid crystal element. In the liquid crystal display device, the leakage of electric charge through a transistor including an oxide semiconductor layer is increased. By reducing the capacitance, it is possible to eliminate the capacitance element itself. The liquid crystal display device has a high aperture ratio even when a plurality of transistors are provided in each pixel. It can be said that this is a liquid crystal display device that can maintain the brightness.

[0084] (Specific examples of transistor manufacturing methods) In the following, one of the transistors provided in each pixel of the liquid crystal display device disclosed in this specification will be described. As an example, a channel-etched transistor 410, which is a type of bottom gate structure, is fabricated. The process will be described with reference to FIG. 11. In this example, a transistor having a single gate structure is However, if necessary, a transistor having a multi-gate structure having multiple channel formation regions may be used. It can be a gistar.

[0085] Hereinafter, with reference to FIGS. 11(A) to 11(D), a transistor 410 is fabricated on a substrate 400. The process will be described below.

[0086] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography process is performed. The gate layer 411 is formed by a resist patterning process. The resist mask may be formed by an ink-jet method. Since no photomask is used, the manufacturing cost can be reduced.

[0087] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least At the very least, it is necessary for the material to have heat resistance sufficient to withstand subsequent heat treatment. For example, Glass substrates such as barium borosilicate glass and aluminoborosilicate glass can be used. In addition, when the temperature of the subsequent heat treatment is high, the distortion point of the glass substrate is 73 It is recommended to use a temperature above 0°C.

[0088] An insulating layer serving as a base layer may be provided between the substrate 400 and the gate layer 411. It has a function of preventing the diffusion of impurity elements from the plate 400, and is a silicon nitride film, a silicon oxide film, A stack of one or more films selected from a silicon oxide nitride film, a silicon oxynitride film, and a silicon nitride film. It can be formed in a layer structure.

[0089] The material of the gate layer 411 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metals such as tin, aluminum, copper, neodymium, and scandium, or alloys containing these as the main components The film may be formed as a single layer or a laminate using the above-mentioned formula (I).

[0090] For example, the two-layered structure of the gate layer 411 may be a molybdenum layer on an aluminum layer. Two-layer structure with a layer of molybdenum on a copper layer, two-layer structure with a layer of titanium nitride on a copper layer or a two-layer structure with a tantalum nitride layer laminated, or a two-layer structure with a titanium nitride layer and a molybdenum layer laminated It is preferable to use a layer structure. As a three-layer laminate structure, a tungsten layer or a tungsten nitride layer is used. a layer of an alloy of aluminum and silicon or a layer of an alloy of aluminum and titanium; It is preferable to laminate a titanium nitride layer or a titanium layer to form a three-layer structure.

[0091] Next, the gate insulating layer 402 is formed on the gate layer 411 .

[0092] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The aluminum layer can be formed as a single layer or a multilayer. Silicon oxide nitride layer is formed by plasma CVD using silicon (SiH4), oxygen and nitrogen. The gate insulating layer 402 may be made of hafnium oxide (HfOx), titanium oxide, or the like. A high-k material such as TaOx may also be used. The thickness is 100 nm to 500 nm. In the case of a multilayer structure, the thickness is, for example, 50 nm to 2 A first gate insulating layer having a thickness of 000 nm or less, and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. A second gate insulating layer having a thickness of 100 Å or less is then laminated thereon.

[0093] Here, a silicon oxynitride layer is formed as the gate insulating layer 402 by the plasma CVD method. Complete.

[0094] In addition, a high-density plasma device was used to form the gate insulating layer 402, and a silicon oxynitride layer was formed. Here, the high density plasma device is a device having a density of 1×10 11 / cm 3 More This refers to a device that can achieve a high plasma density. For example, a device that can apply microwave power of 3kW to 6kW The insulating layer is then deposited by applying a voltage to generate plasma.

[0095] The chamber is filled with silane (SiH4), nitrous oxide (N2O), and rare gases as material gases. By introducing a gas, high-density plasma is generated under a pressure of 10 Pa to 30 Pa, and the plasma is heated on insulating surfaces such as glass. An insulating layer is formed on a substrate having a surface. Then, the supply of silane (SiH4) is stopped, and the insulating layer is removed. Nitrous oxide (N2O) and rare gases are introduced to generate plasma on the surface of the insulating layer without exposing the insulating layer to the atmosphere. The insulating layer that has been subjected to the above process sequence can be used as a transistor even if it is thin. It is an insulating layer that can ensure the reliability of the semiconductor device.

[0096] When forming the gate insulating layer 402, silane (SiH4) and nitrous oxide are introduced into the chamber. The flow ratio of nitrogen (N2O) is in the range of 1:10 to 1:200. The rare gases that can be used include helium, argon, krypton, and xenon. Of these, it is preferable to use argon, which is inexpensive.

[0097] In addition, the insulating layer obtained by the high-density plasma device can be formed with a constant thickness. In addition, the insulating layer obtained by the high-density plasma device is a thin film. The thickness can be precisely controlled.

[0098] The insulating layer obtained by the above process sequence is the same as that obtained by a conventional parallel plate PCVD apparatus. When comparing the etching rates using the same etchant, The insulating film obtained by the parallel plate PCVD apparatus is 10% or more or 20% slower than that obtained by the parallel plate PCVD apparatus. The insulating layer obtained using a high-density plasma device can be said to be a dense film.

[0099] Note that the oxide semiconductor to be made into an i-type or substantially i-type in a later process (highly purified oxide Since the semiconductor (compound semiconductor) is extremely sensitive to interface states and interface charges, Therefore, the gate insulating layer in contact with the highly purified oxide semiconductor must be of high quality. Therefore, high density plasma CVD equipment using microwaves (2.45 GHz) requires precise This is preferable because it allows the formation of a high-quality insulating film that is dense and has a high dielectric strength. The intimate contact between the conductor and the high-quality gate insulating layer reduces the interface state density and improves the interface characteristics. The reason is that the film quality of the gate insulating layer is good. Of course, it is important to reduce the interface state density with the oxide semiconductor and form a good interface. It is essential.

[0100] Next, an oxide semiconductor film 4 with a thickness of 2 nm to 200 nm is formed on the gate insulating layer 402. Before the oxide semiconductor film 430 is formed by a sputtering method, A reverse sputtering process is performed by introducing an oxygen gas to generate plasma, and a surface of the gate insulating layer 402 is It is preferable to remove any powdery substances (also called particles or dust) adhering to the surface. Putting is a process in which no voltage is applied to the target side, but an RF power source is applied to the substrate side in an argon atmosphere. This method uses a plasma generator to apply a voltage to generate plasma near the substrate and modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, or the like may be used.

[0101] The oxide semiconductor film 430 may be an In-Ga-Zn-O-based, In-Sn-O-based, or In-Sn- Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system In-O-based, Sn-O-based, and Zn-O-based oxide semiconductor films are used. The conductive film 430 is formed by sputtering using an In-Ga-Zn-O metal oxide target. The cross-sectional view at this stage corresponds to FIG. 430 is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically It can be formed by sputtering in a mixed atmosphere of argon and oxygen. In addition, when using a sputtering method, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less is used. The oxide semiconductor film 430 is formed using a SiOx (X>0) that inhibits crystallization. This causes crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is also possible to suppress the above.

[0102] Here, a metal oxide target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol], In:Ga:Zn=1:1:0.5[atom]) The distance between the substrate and the target was 100 mm, the pressure was 0.2 Pa, and the direct current (DC) was Power supply: 0.5 kW, argon and oxygen (argon:oxygen = 30 sccm:20 sccm, oxygen The film is formed in an atmosphere with a nitrogen flow rate of 40%). This is preferable because it reduces the amount of powdery material that is generated during deposition and also makes the film thickness distribution uniform. The thickness of the Zn-O-based film is 2 nm to 200 nm. As a result, a 2000-membrane thin-film was formed by sputtering using an In-Ga-Zn-O metal oxide target. The In-Ga-Zn-O film is deposited to a thickness of 0 nm. As the oxide target, In:Ga:Zn=1:1:1[atom] or In:Ga It is also possible to use a metal oxide target with a composition ratio of Zn=1:1:2 [atom]. can.

[0103] There are two types of sputtering: RF sputtering, which uses a high-frequency power source as the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0104] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The TA equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0105] In addition, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber The plasma generated by microwaves without glow discharge is used for ECR sputtering. There are sputtering devices that use the TA method.

[0106] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and the other is a method of forming thin films by removing the base material during film formation. There is also a bias sputtering method in which a voltage is applied to the plate.

[0107] Next, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. The resist mask used in this process is an inkjet printer. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0108] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or more and 750° C. or less, preferably 400° C. or more so as to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor is The conductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then the oxide semiconductor In order to prevent water and hydrogen from re-entering the oxide semiconductor layer, the oxide semiconductor is cooled without being exposed to the air. A layer 431 is obtained (see FIG. 11(B)).

[0109] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0110] For example, the first heat treatment is performed in an inert gas heated to a high temperature of 650°C to 700°C. The substrate is moved in and heated for a few minutes, then the substrate is moved out and heated to a high temperature inert gas. You can also use GRTA, which is a method of removing the food from inside the container. Using GRTA, high-temperature heat treatment can be performed in a short time. It becomes.

[0111] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0112] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. It is also possible to perform the same on the semiconductor film 430. In that case, after the first heat treatment, The substrate is removed from the apparatus and a second photolithography process is performed.

[0113] The heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer is performed after the formation of the oxide semiconductor layer. After a source electrode layer and a drain electrode layer are stacked on the oxide semiconductor layer, This may be performed either after forming a protective insulating film on the drain electrode layer or after forming a protective insulating film on the drain electrode layer.

[0114] In addition, in the case where an opening is formed in the gate insulating layer 402, the process is performed after the oxide semiconductor film 430 This may be carried out before or after the dehydration or dehydrogenation treatment.

[0115] Note that the etching of the oxide semiconductor film 430 here is not limited to wet etching. Alternatively, dry etching may be used.

[0116] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), Carbon (such as CCl4) is preferred.

[0117] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride ( SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide ( HBr), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas having a gas added thereto, etc. can be used.

[0118] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0119] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0120] In addition, the etching solution after wet etching is washed away together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the material contained therein is The indium contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials such as these, we can make effective use of resources and reduce costs. do.

[0121] In order to etch the desired shape, the etching conditions are adjusted according to the material. Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate.

[0122] Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by sputtering or vacuum deposition. Aluminum (Al), Chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti ), molybdenum (Mo), tungsten (W), or an element selected from the above elements. In addition, manganese (Mn ), magnesium (Mg), zirconium (Zr), beryllium (Be), yttrium The metal conductive film may be made of one or more materials selected from (Y). The insulating film may have a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon A single layer of titanium film, a single layer of copper or copper-based film, a titanium film on an aluminum film, Two-layer structure with copper film laminated on tantalum nitride film or copper nitride film, two-layer structure with copper film laminated on titanium film A three-layer structure in which an aluminum film is laminated on top and a titanium film is laminated on top of the aluminum film. Aluminum (Al) is also known as titanium (Ti), tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scan A film of a single or multiple combinations of elements selected from Sc, alloy film, or nitride A film containing fluorine may also be used.

[0123] When a heat treatment is performed after the formation of the metal conductive film, the metal conductive film must have heat resistance sufficient to withstand this heat treatment. It is preferable that the conductive film has the conductive layer.

[0124] A resist mask is formed on the metal conductive film by a third photolithography process. After etching the substrate to form a source layer 415a and a drain layer 415b, a resist mask is The mask is removed (see FIG. 11(C)). The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0125] Note that the metal conductive film is etched so as not to remove the oxide semiconductor layer 431. The materials and etching conditions are adjusted accordingly.

[0126] Here, a titanium film is used as the metal conductive film, and an In-Ga -Zn-O oxide was used, and ammonia hydrogen peroxide (ammonia, water, hydrogen peroxide) was used as an etchant. A mixture of hydrogen peroxide and water is used.

[0127] Note that in the third photolithography process, the oxide semiconductor layer 431 is partly etched. In some cases, the oxide semiconductor layer may have a groove (a recess).

[0128] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further deformed by ashing. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also eliminates the need for a corresponding photolithography process, making it possible to simplify the process.

[0129] Then, gases such as nitrous oxide (NO), nitrogen (N2), or argon (Ar) are added to The plasma treatment is performed using a fluorine atom. Water adsorbed on the surface is removed. In addition, a mixture of oxygen and argon gas is used to create a plasma. Processing may be carried out.

[0130] After the plasma treatment, the oxide semiconductor layer is not exposed to the air, and the oxide semiconductor An oxide insulating layer 416 serving as a protective insulating film is formed in contact with part of the layer.

[0131] The oxide insulating layer 416 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The edge layer 416 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the edge layer 416. When hydrogen is contained in the oxide insulating layer 416, the hydrogen enters the oxide semiconductor layer and The back channel of the semiconductor layer 431 becomes low-resistance (N-type), and a parasitic channel is formed. Therefore, the oxide insulating layer 416 should be a film containing as little hydrogen as possible. It is important to avoid using hydrogen in the deposition process.

[0132] Here, a silicon oxide film having a thickness of 200 nm is formed as the oxide insulating layer 416 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. The temperature is set to 00°C. The silicon oxide film is formed by sputtering using a rare gas (typically argon). ) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen atmosphere. The target may be a silicon oxide target or a silicon For example, a silicon target can be used to produce oxygen and nitrogen. The silicon oxide film can be formed by sputtering in an atmosphere of nitrogen.

[0133] Then, a second heat treatment (preferably 200°C to 400°C (e.g., 250°C to 350°C) is performed. For example, The second heat treatment is performed at 250° C. for 1 hour under atmospheric conditions. A part of the conductor layer (channel formation region) is heated while being in contact with the oxide insulating layer 416. As a result, oxygen is supplied to a part (channel formation region) of the oxide semiconductor layer. By the heat treatment, hydrogen can be taken into the oxide insulating layer 416 from the oxide semiconductor layer. Cut.

[0134] Through the above steps, the oxide semiconductor layer is dehydrated or dehydrogenated. After the heat treatment, a part of the oxide semiconductor layer (a channel formation region) is selectively treated with an oxygen excess. As a result, the channel forming region 413 overlapping with the gate layer 411 becomes an I-type. , a source region 414a overlapping the source layer 415a, and a drain region 414b overlapping the drain layer 415b. Through the above steps, the transistor 410 is formed. can be.

[0135] For example, a gate bias thermal stress test (BT test) is performed under high temperature and high electric field for a long period of time. Under the conditions of exposure (e.g., 85°C, 2×10 6 V / cm, 12 hours) When impurities (such as hydrogen) are present in the oxide semiconductor, the impurities bond with the main components of the oxide semiconductor. The bonds are broken by a strong electric field (B: bias) and high temperature (T: temperature), creating dangling bonds. This induces a drift in the threshold voltage (Vth). The impurities in the body, especially hydrogen and water, are removed as much as possible, and the above-mentioned high-density plasma CVD device is used to refine the It forms a high-quality insulating film that is dense and has high dielectric strength, and improves the interface characteristics with the oxide semiconductor. This makes it possible to obtain a transistor that is stable even in a harsh external environment.

[0136] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. Here, the heat treatment is performed at 150°C for 10 hours. The temperature may be maintained at the same temperature, or the temperature may be increased from room temperature to 100°C or higher and 200°C or lower. The heating and cooling from the heating temperature to room temperature may be repeated several times. The treatment may be performed under reduced pressure before the formation of the oxide insulating layer 416. This can shorten the heating time.

[0137] Note that the drain region 414b is formed in the oxide semiconductor layer overlapping with the drain layer 415b. By forming the gate insulating film, the reliability of the transistor can be improved. By forming the drain region 414b, the drain region 414b is formed from the drain layer 415b. To form a structure in which the conductivity can be changed stepwise toward the channel forming region 413. can be done.

[0138] In addition, the source region or the drain region of the oxide semiconductor layer is formed by the film thickness of the oxide semiconductor layer. When the thickness is as thin as 15 nm or less, the oxide semiconductor layer is formed over the entire thickness direction. When the thickness is greater than 30 nm and is less than 50 nm, a part of the oxide semiconductor layer, the source layer, or The resistance of the region in contact with the drain layer and its vicinity is reduced, forming a source region or a drain region. In addition, a region of the oxide semiconductor layer close to the gate insulating layer can be made to be an i-type.

[0139] A protective insulating layer may be further formed on the oxide insulating layer 416. For example, the protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. The protective insulating layer is preferably formed by the above-mentioned method. - Impurities such as The silicon nitride film is made of an inorganic insulating film that does not contain any of these elements and blocks their intrusion from the outside. A silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, etc. are used. Here, the protective insulating layer 403 is formed using a silicon nitride film as the protective insulating layer. See Figure 11(D).

[0140] (Regarding various electronic devices equipped with liquid crystal displays) An example of an electronic device incorporating the liquid crystal display device disclosed in this specification will be described below with reference to FIG. This will be described with reference to the following.

[0141] FIG. 12A shows a notebook personal computer. It is composed of a housing 2202, a display unit 2203, a keyboard 2204, and the like.

[0142] FIG. 12B is a diagram showing a personal digital assistant (PDA), and the main body 2211 has a display unit 2 213, an external interface 2215, and an operation button 2214. There is also a stylus 2212 as an accessory for operation.

[0143] FIG. 12C is a diagram showing an electronic book 2220 as an example of electronic paper. The book 2220 is composed of two cases, a case 2221 and a case 2223. Case 2221 and the housing 2223 are integrated by a shaft portion 2237. With this configuration, the electronic book 2220 can be opened and closed with the opening and closing action being performed around the axis. It can be used like a paper book.

[0144] A display unit 2225 is incorporated in the housing 2221, and a display unit 2227 is incorporated in the housing 2223. The display unit 2225 and the display unit 2227 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2225 in FIG. 12C) and An image can be displayed on the display portion (the display portion 2227 in FIG. 12C).

[0145] FIG. 12C shows an example in which an operating unit and the like are provided in the housing 2221. For example, The housing 2221 includes a power switch 2231, operation keys 2233, a speaker 2235, etc. The operation key 2233 can be used to turn pages. A keyboard, a pointing device, etc. may be provided on the same surface. Do not install any external connection terminals (earphone terminal, USB terminal, AC adapter, etc.) on the back or side of the body. and a connector for connecting various cables such as USB cables), a recording medium insertion section, etc. Furthermore, the electronic book 2220 may have a function as an electronic dictionary. The above configuration may also be used.

[0146] The electronic book 2220 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0147] Electronic paper can be applied to any field as long as it displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards.

[0148] FIG. 12D is a diagram showing a mobile phone. The mobile phone includes a housing 2240 and The housing 2241 is made up of two housings, a display panel 2242 and a screen. Speaker 2243, microphone 2244, pointing device 2246, camera The housing 2240 is provided with a lens 2247 for receiving the image, an external connection terminal 2248, and the like. The mobile phone is equipped with a solar cell 2249 for charging the mobile phone, an external memory slot 2250, etc. In addition, the antenna is built into the housing 2241.

[0149] The display panel 2242 has a touch panel function, and in FIG. The multiple operation keys 2245 are shown by dotted lines. A boost circuit is implemented to boost the voltage output from module 2249 to the voltage required for each circuit. In addition to the above configuration, a non-contact IC chip, a small recording device, etc. are also included. It can also be done like this.

[0150] The display direction of the display panel 2242 changes appropriately depending on the usage mode. Since it has a camera lens 2247 on the same surface as the lens 2242, video calls are possible. The speaker 2243 and the microphone 2244 are not limited to voice calls, The housing 2240 and the housing 2241 can be slid together. As shown in Figure 12(D), the device can be folded from the unfolded state to the folded state, making it easy to carry. Suitable miniaturization is possible.

[0151] The external connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. The external memory slot 2250 can store data and other information. By inserting a recording medium, it is possible to store and transfer a larger amount of data. In addition, it may be equipped with an infrared communication function, a television receiving function, etc.

[0152] FIG. 12E is a diagram showing a digital camera. The digital camera has a main body 226. 1, display unit (A) 2267, eyepiece unit 2263, operation switch 2264, display unit (B) 22 It is composed of 65, battery 2266, etc.

[0153] FIG. 12(F) is a diagram showing a television device. In the television device 2270, A display unit 2273 is built into the housing 2271. The display unit 2273 displays images. In this case, the housing 2271 is supported by a stand 2275. The figure shows a configuration in which

[0154] The television device 2270 can be operated using an operation switch provided on the housing 2271 or a separate remote. This can be done by using a remote control operation device 2280. The channel and volume can be controlled by the 2279, and the display 2273 shows In addition, the remote control unit 2280 can be used to control the video. A display unit 2277 for displaying information output from the device 2280 may be provided.

[0155] The television device 2270 is preferably configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting the device to a wired or wireless communication network, It is used to communicate information either directly (i.e., between a sender and a receiver, or between receivers themselves) or in a two-way manner (i.e., between a sender and a receiver, or between receivers themselves). It is possible to do so. [Explanation of symbols]

[0156] 100 pixels 101 scan lines 102 scan lines 103 Signal Line 104 Signal Line 105 Transistor 107 Pixel electrode layer 110 Substrate 111 Gate layer 112 Gate insulating layer 113 Oxide semiconductor layer 114a One of the source layer and the drain layer 114b the other of the source layer and the drain layer 115 Insulating Layer 116 Contact Hole 117a area 117b area 117c area 201 Oxide semiconductor layer 202a Oxide semiconductor layer 202b Oxide semiconductor layer 210 Transistor 211 Insulating layer 212 Insulating layer 220 Transistor 230 Transistor 231 Undercoat insulation layer 232 Insulating layer 233a Contact Hole 233b Contact Hole 234 Insulating layer 235 Contact Hole 400 Substrates 402 Gate insulating layer 403 Protective insulation layer 410 Transistor 411 Gate Layer 413 Channel formation region 414a Source Region 414b Drain region 415a Source layer 415b Drain layer 416 Oxide insulating layer 430 Oxide Semiconductor Film 431 Oxide Semiconductor Layer 800 Measurement System 802 Capacitive element 804 Transistor 805 Transistor 806 Transistor 808 Transistor 1000 pixels 1001 scan lines 1002 scan lines 1003 Signal Line 1004 Signal line 1005 Transistor 1006 Capacitive element 1007 Pixel electrode layer 1008 Capacitance wiring 1010 Board 1011 Gate Layer 1012 Gate insulation layer 1013 Semiconductor layer 1014a One of the source layer and the drain layer 1014b The other of the source layer and the drain layer 1015 Insulation layer 1016 Contact Hole 1017a area 1017b area 1017c area 2201 Main unit 2202 Case 2203 Display section 2204 Keyboard 2211 Main unit 2212 Stylus 2213 Display section 2214 Operation button 2215 External Interface 2220 E-books 2221 Case 2223 Case 2225 Display section 2227 Display section 2231 Power supply 2233 Operation key 2235 Speaker 2237 Shaft 2240 Case 2241 Case 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lenses 2248 External connection terminal 2249 Solar Cell 2250 external memory slot 2261 Main unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television Equipment 2271 Case 2273 Display section 2275 Stand 2277 Display section 2279 Operation Key 2280 Remote Controlled Device

Claims

[Claim 1] A first scanning line and a second scanning line arranged in parallel or approximately parallel; a first signal line and a second signal line arranged perpendicular or substantially perpendicular to the first scanning line and the second scanning line; a transistor including an oxide semiconductor layer, the gate of which is electrically connected to the first scan line, one of a source and a drain of which is electrically connected to the first signal line, and the other of the source and the drain of which is electrically connected to a pixel electrode layer; the first signal line and the second signal line cross the first scanning line and the second scanning line through an insulating layer provided on the first scanning line and the second scanning line, the first signal line has a convex upper surface in a first region where the first signal line crosses the first scanning line and a second region where the first signal line crosses the second scanning line, and has a planar or substantially planar upper surface in a region between the first region and the second region; the pixel electrode layer is provided in a region surrounded by the first scanning line, the second scanning line, the first signal line, and the second signal line.

Images