Light-emitting device

Abstract

To reduce the size of a semiconductor device including a test circuit.SOLUTION: A semiconductor device includes r (r is an integer of 2 or more) first input terminals, one second input terminal, r functional circuits, a demultiplexer, and a switch circuit. The demultiplexer is a pass transistor logic circuit. In the demultiplexer, r output terminals are electrically connected to input terminals of the different functional circuits and the input terminals are electrically connected to the second input terminal. The input terminals of the r circuits are electrically connected to the different first input terminals through the switch circuit. For example, in the testing of the functional circuit, a testing signal is input to the first input terminal and the demultiplexer is operated. By the demultiplexer, one testing signal is input to the r functional circuits.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is, for example, a circuit using a semiconductor, a processing circuit, a memory circuit, a display device, a light emitting device, or the like. The present invention relates to a semiconductor device such as an optical device, a driving method thereof, and a manufacturing method thereof. [Background technology]

[0002] There are various circuit configurations for the pixels of active matrix display devices that use light-emitting elements. Generally, a pixel includes a light emitting element, a pixel control circuit for controlling input of a data signal to the pixel, and a pixel control circuit for controlling input of a data signal to the pixel. A transistor and a transistor that controls the current supplied to the light-emitting element (a driving transistor The drain current flowing through the driving transistor is supplied to the light emitting element. By supplying the drain current, the light emitting element emits light at a brightness according to the value of the drain current. The drain current of the transistor is controlled by the voltage of the data signal.

[0003] Therefore, the electrical characteristics (threshold voltage) of the driving transistors between the multiple pixels that make up the screen of the display device If there is variation in the capacitance (value voltage, field effect mobility, etc.), even if the same voltage data signal is supplied, The luminance of the light-emitting element varies. Variation in display properties is one of the causes of deterioration in the display quality of a display device.

[0004] On the other hand, active matrix display devices are being promoted to have more pixels in order to achieve higher resolution. A single display device has hundreds of thousands to tens of millions of pixels. For example, the number of pixels is If the resolution is Full-HD, then 1366 x 768 x 3 (RGB) = 1,049,08 8, and for 8K4K (Super Hi-Vision), it is 7,680 x 4,320 x 3 ( RGB) = 33,177,600. The electrical characteristics of the driving transistors It is very difficult to perfectly match the electrical characteristics of the driving transistor. In addition, it has been proposed to correct the luminance of the light-emitting element (for example, Patent Document 1).

[0005] In order to accommodate the increasing number of gradations and high definition of the display unit, the driver circuit of the display device, especially the image The source driver circuit that generates the data signal from the image signal uses a dedicated IC (driver IC) is adopted (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2009-265459 A [Patent Document 2] JP 2007-286525 A Summary of the Invention [Problem to be solved by the invention]

[0007] As the resolution increases, the number of driver circuits increases as well as the pixel section. For example, When a test circuit is built into an IC to verify its operation, the size of this test circuit also increases. It's a big deal.

[0008] In addition, the circuit for acquiring the electrical characteristics of the pixel's driving transistor is It handles very small current signals, ranging from a few hundred nA to several hundred nA. In such a case, it is desirable to verify the signal using such a minute current signal.

[0009] In view of the above, one embodiment of the present invention provides a novel semiconductor device or a method for operating the novel semiconductor device. One embodiment of the present invention is to miniaturize a semiconductor device. It is an object of the present invention to provide a semiconductor device capable of performing highly accurate operation verification.

[0010] In addition, the description of a plurality of problems does not preclude the existence of each problem. The embodiment does not necessarily have to solve all of these problems. Also, problems other than those listed may not be solved by the specification. These problems will become apparent from the description of the present invention, drawings, claims, etc. This could be a form of challenge for the Ming. [Means for solving the problem]

[0011] One aspect of the present invention is a demultiplexer having r circuits (r is an integer of 2 or more) and r output terminals. and a demultiplexer, the demultiplexer being a pass transistor logic circuit (Pass Transistor Logic Circuit). The demultiplexer is a digital logic device, and the r output terminals of the demultiplexer are connected to different circuits and electrical It is a semiconductor device that is electrically connected to the

[0012] According to one aspect of the present invention, there is provided a multi-input device having r first input terminals (r is an integer of 2 or more) and one second input terminal. , r circuits, a demultiplexer having r output terminals, and a switch circuit, The demultiplexer is a pass transistor logic circuit, and the r outputs of the demultiplexer are The input terminals are electrically connected to the input terminals of different circuits, and the input terminals of the demultiplexer is electrically connected to the second input terminal, and the input terminals of the r circuits are mutually different first input terminals and a switch circuit electrically connects the first input terminal to the corresponding first input terminal. The semiconductor device to be controlled.

[0013] For example, the semiconductor device of the above embodiment can be applied to a driver IC of a display device.

[0014] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of elements. In some cases, the word "number" is added to indicate the order of the items. It is not something that can be done.

[0015] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics and is a semiconductor element ( A semiconductor is a circuit that contains a semiconductor element (such as a transistor or diode) or a device that has such a circuit. This refers to any device that can function by utilizing the characteristics of the device. For example, an integrated circuit, The chip is an example of a semiconductor device. In some cases, electronic devices and the like are themselves semiconductor devices or include semiconductor devices.

[0016] A transistor has three terminals called the gate, source, and drain. The source terminal is a terminal that functions as a control terminal for controlling the conductive state of a transistor. The two input / output terminals functioning as the drain and the transistor conductivity type are Depending on the level of the applied potential, one side becomes the source and the other side becomes the drain. In the specification, the terms source and drain may be used interchangeably. In addition, in this specification and the like, the two terminals other than the gate may be referred to as the first terminal and the second terminal. There is.

[0017] A node can be a terminal, a wiring, an electrode, a conductor, or an impurity region depending on the circuit configuration, device structure, etc. In addition, the terminals and the like can be referred to as nodes. .

[0018] A voltage is the voltage between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). In many cases, it refers to the potential difference. Therefore, it is possible to say "voltage" as "electric potential." Therefore, even if it is described as ground potential, it does not necessarily mean 0 It may not mean V.

[0019] In this specification, the words "film" and "layer" may be used interchangeably. can be used interchangeably depending on the context. For example, the term "conductive layer" In some cases, it may be possible to change the term "insulating film" to "conductive film". In some cases, the terminology may be changed to the term "insulating layer." Effect of the Invention

[0020] According to one embodiment of the present invention, a novel semiconductor device or a method for operating the novel semiconductor device is provided. According to one embodiment of the present invention, a semiconductor device can be miniaturized. This makes it possible to perform highly accurate operation verification.

[0021] The description of a plurality of effects does not preclude the existence of other effects. It is not necessary to have all of the effects exemplified above. Problems, advantages, and novel features other than those described above will become apparent from the description and drawings of this specification. It becomes clear that: [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are diagrams illustrating examples of the configuration of a semiconductor device. [Diagram 2] FIG. 1 is a circuit diagram showing a configuration example of a pass transistor logic circuit (PTL). [Diagram 3] FIG. 1 is a circuit diagram showing an example of the configuration of a PTL. [Figure 4] FIG. 1 is a circuit diagram showing an example of the configuration of a PTL. [Diagram 5] FIG. 1 illustrates an example of the configuration of a display device. [Figure 6] FIG. 1 is an exploded perspective view showing a configuration example of a display device. [Figure 7] FIG. 2 is a plan view showing a configuration example of a display panel. [Figure 8] A: Circuit diagram showing an example of the configuration of a pixel. B: Timing chart showing an example of the operation of the same. [Figure 9] A and B are circuit diagrams showing examples of monitor circuit configurations. [Figure 10] FIG. 2 shows an example of the configuration of a driver IC. [Figure 11] FIG. 2 is a diagram showing a configuration example of a logic circuit (LGC) and a PTL. [Figure 12] FIG. 1 is a circuit diagram showing a configuration example of a demultiplexer (DEMUX). [Figure 13] FIG. 2 is a diagram showing a configuration example of an analog-to-digital conversion circuit and a readout circuit. [Figure 14] FIG. 2 is a diagram showing a configuration example of a circuit ADC_CM and a readout circuit. [Figure 15] 4 is a timing chart showing an example of the operation of the circuit ADC_CM. [Figure 16] FIG. 2 is a cross-sectional view showing a configuration example of a display panel. [Figure 17] 4A to 4D are diagrams showing examples of transistor configurations. [Figure 18] 4A to 4D are diagrams showing examples of transistor configurations. [Figure 19] 1A to 1C illustrate examples of the structure of a transistor. [Figure 20] AF: A diagram showing an example of the configuration of an electronic device. [Figure 21] AI: A diagram showing an example of the configuration of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, an embodiment of the present invention will be described. However, one embodiment of the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that modifications may be made thereto. Accordingly, one aspect of the present invention is The present invention is not to be construed as being limited to the description of the following embodiment.

[0024] In the drawings, elements that are the same or have similar functions, elements of the same material, or Elements formed at the same time may be given the same reference numerals, and repeated explanations thereof will be omitted. There may be cases where this occurs.

[0025] In addition, when the same symbols are used, especially when it is necessary to distinguish among them, the symbols are marked with " When adding identification symbols such as "_1", "_2", "[n]", "[m, n]", etc. For example, when multiple wirings SL of a pixel section are to be individually distinguished, the column numbers of the pixel sections are used. For this reason, the wiring SL in the second column may be referred to as wiring SL[2].

[0026] In this specification, for example, the clock signal CLK will be abbreviated to signal CLK, CLK, etc. This may include other components (e.g., signals, voltages, potentials, circuits, elements, The same applies to the electrical components (electrodes, wiring, etc.).

[0027] The arrangement of each circuit block in the drawings is for the purpose of explanation only and may differ from the actual arrangement. Even if a diagram shows that different circuit blocks realize different functions, in the actual circuit or area, In some cases, the same circuit block may be provided to realize different functions. The function of each circuit block in the figure is specified for the purpose of explanation, and is not a single circuit. Even if shown as a block, in the actual circuit or area, the process is performed by one circuit block. In some cases, the processing is performed by a plurality of circuit blocks.

[0028] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be described in the drawings or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). (etc.).

[0029] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The above is a formula, and is not limited to the shapes or values ​​shown in the drawings. For example, Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Or, it is possible to include current variation.

[0030] Although the embodiments of the present invention will be described below, the embodiments can be combined as appropriate. In addition, when a plurality of configuration examples are shown in one embodiment, the configuration examples may be combined as appropriate. It is possible to combine

[0031] (Embodiment 1) A semiconductor device having a pass transistor logic circuit will be described. An example of applying a transistor circuit to a test circuit for verifying the operation of a circuit will be shown.

[0032] The semiconductor device 100 shown in FIG. 1 includes a circuit 110, a wiring 112, an output terminal 113, a logic circuit, and A logic circuit (LGC) 120, a logic circuit (LGC) 121, a switch circuit 123, a read circuit READ 124, and a pass transistor logic circuit (PTL) 130. The circuit 110 has K stages of circuits 111 (K is an integer of 2 or more). 00 has K input terminals and an output terminal that outputs a signal CMOUT. The input terminals receive signals MI[1]-MI[K], respectively.

[0033] The switch circuit 123 has a function of controlling the input of the signals MI[1]-MI[K] to the circuit 110. The switch circuit 123 has K switches. Each switch is a semiconductor device. The conductive state of the switch 100 is controlled between one of the input terminals and the circuit 110. The state is controlled by signal TCM.

[0034] The LGC 120 has a function of generating signals for controlling the circuit 110 and the READ 124. Each circuit 111 in the circuit 110 receives an input signal according to a signal generated by the LGC 120. The READ124 is a circuit for driving the circuit 110. 4 is a circuit 111[1]-1 that outputs a signal according to the signal generated by the LGC 120. 11[K]. The signal required for the operation of the circuit 111 and the READ 124 is The signal may be input from an external circuit to the semiconductor device 100.

[0035] The PTL 130 and the LGC 121 are circuits for verifying the operation of the circuit 110. The GC 121 has a function of controlling the PTL 130. The LGC 121 outputs a signal S[h-1: 0] and signal SB[h-1:0]. Signal SB[h-1:0] is -1:0] is an inverted signal. PTL130 outputs the 1 input signal TIREF through K output wirings. (K output terminals). In other words, the PTL130 is a The PTL 130 has a multiplexer (DEMUX) function. ] and signal SB[h-1:0], the wiring for outputting the signal TIREF is selected. The data consisting of signals S[h-1:0] and SB[h-1:0] is input by the signal TIREF. 111[1]-111[K].

[0036] (normal operation) During normal operation of the semiconductor device 100, K switches of the switch circuit 123 are turned on. The signals MI[1]-MI[K] are processed by the circuit 110. Then, one of the circuits 111[1]-111[K] is selected, and the selected circuit 111 The processed signal or signals are output to a wiring 112. The wiring 112 is connected to an output terminal 113. The signal CMOUT output from the output terminal 113 is The signal CMOUT is processed by a circuit external to the device 100. In this case, a plurality of wirings 112 and output terminals 113 are provided according to the number of signals of the signal CMOUT. can be done.

[0037] (Verification operation) In the verification operation of the circuit 110, the K switches of the switch circuit 123 are made non-conductive. The PTL 130 specifies the signal S[h-1:0] and the signal SB[h-1:0]. The signal TIREF is input to any one of the circuits 111. For example, when verifying all the circuits 111, the signal TIREF is sequentially input from the circuit 111[1] to the circuit 111 [K] by the PTL130. The processed signals are sequentially output to the wiring 112 from the circuit 111[1] to the circuit 111 [K] by the READ124. Since the same signal T IREF is processed by the K circuits 111, by analyzing the signal CMOUT, it is possible to determine defects of each circuit 111, verify performance, etc.

[0038] FIG. 1 shows an example in which the output terminals of the circuits 111[1]-111[K] are connected to a common wiring 112. The configuration of the semiconductor device 100 is not limited to this. For example, other circuits may be electrically connected to the subsequent stages of the circuits 111[1] -111[K], respectively.

[0039] <<Example configuration of PTL>> A semiconductor device applicable to the PTL130 shown in FIG. 1 will be described. The PTL1 31 shown in FIG. 2 is a circuit in which the signal path forms a tree structure, and a plurality of transistors are connected in series in a binary tree structure. Here, the transistors are of the n-type. The PTL131 forms an output DEMUX, and h transistors are electrically connected in series between the input terminal and each output terminal. When the output terminal side is used as a reference, in the q-th stage (q is an integer of 1 or more and h or less), there are 2 h transistors, and there are 2 transistor pairs in which the sources are connected to the same node. In the transistor pair, SB[q-1] is input to the gate of one transistor, and to the gate of the other transistor (h+1-q) (h-q) ​​​​​​​S[q-1] is input.

[0040] The operation of PTL131 will be explained using the example where h is 4. In this case, PTL131 has 16 outputs. For ease of understanding, the signal S[3:0] is a digital signal. If the data value is “1”, the signal S[q-1] and the signal SB[q-1] are at high level. A signal (H level) is a voltage that can turn on a transistor and the data value is "0". In this case, the signal S[q-1] and the signal SB[q-1] are at a low level (L level). For example, when the signal S[3:0] is “0000 If the signal S[3:0] is "0111", a signal is output from the terminal OUT[1]. If so, a signal is output from terminal OUT[8].

[0041] The number of output terminals of PTL131 can be changed as appropriate depending on the configuration of the circuit after PTL131. In this case, the number of transistors connected to each output terminal should be equal. For example, a circuit configuration like PTL132 shown in FIG. The PTL 132 shown in FIG. 3 constitutes a 28-output DEMUX. [4:0] and signal SB[4:0] are input. Figure 4 shows the PTL13 represented by logic symbols. 2. PTL132 is a DEMUX141 and DEMUX142 ( 142_1, 142_2), and two DEMUX143 (143_1, 143_2). The DEMUX141 has 4 outputs, the DEMUX142 has 8 outputs, and the DEMUX1 As shown in Figure 3, the DEMUX143 is a 3-port DEMUX from the DEMUX142. This corresponds to a circuit with one transistor removed.

[0042] In the examples of FIGS. 2 and 3, the n-type transistors can be replaced with p-type transistors. do.

[0043] As shown in Figures 2 and 3, a demultiplexer is constructed using pass transistor logic circuits. It is possible to increase the number of outputs relative to the number of stages of pass transistors connected in series. For example, if the number of pass transistor stages is 10, the maximum number of demultiplexer outputs is Large 2 10 = 1024. PTL has a small number of elements and can produce many outputs. The test circuit can be a circuit that does not need to operate during normal operation. Since the test circuit is a small circuit, it is possible to configure the test circuit using the PTL130, This is very effective in reducing the area overhead caused by incorporating a circuit. That is, instead of the 10 stages of pass transistor logic circuits in the semiconductor device 100, 102 This can be understood by assuming a four-stage shift register.

[0044] In addition, when the signal TIREF used for verifying the multiple circuits 111 is an analog signal, In particular, in the case of an analog current signal, the PTL 130 divides the signal TIREF into multiple circuits 111. For example, when the terminal OUT[1 When SB[h-1:0] is selected, the transistor to which the signal SB[h-1:0] is input is on. The other transistors are in the off state. Therefore, the signal output from the terminal OUT[1] is The signal is affected to a certain extent by the leakage current of the transistors in the off state. The number of transistors connected in series should be reduced compared to the number of output terminals. Therefore, the fluctuation of the current value of the analog current is suppressed, and the verification error of the circuit 111 is suppressed. It is possible.

[0045] (Embodiment 2) Here, as an example of a semiconductor device having a pass transistor logic circuit, a display device Here, the semiconductor device according to the first embodiment is provided in a driver circuit. We will explain an example where

[0046] <<Display device>> 5 is a block diagram showing a configuration example of a display device. The display device 200 includes a pixel section 210, a peripheral A side circuit 220, a CPU 230, a control circuit 231, a power supply circuit 232, an image processing circuit 233, and memory 234.

[0047] The CPU 230 is a circuit for executing instructions and controlling the display device 200 in an overall manner. The instructions executed by the CPU 230 are input from the outside and are stored in the internal memory. The CPU 230 outputs signals for controlling the control circuit 231 and the image processing circuit 233. Based on the control signal from the CPU 230, the control circuit 231 controls the operation of the display device 200. The control circuit 231 controls the peripherals so that the processing determined by the CPU 230 is executed. The control circuit 220, the power supply circuit 232, the image processing circuit 233, and the memory 234. The circuit 231 receives, for example, various synchronization signals that determine the timing of rewriting the screen. The synchronous signals include, for example, a horizontal synchronous signal, a vertical synchronous signal, and a reference clock signal. The control circuit 231 generates control signals for the peripheral circuit 220 from these signals. The power supply circuit 232 has a function of supplying a power supply voltage to the pixel section 210 and the peripheral circuit 220. .

[0048] The pixel section 210 includes a plurality of pixels 211, a plurality of wirings GL, a plurality of wirings SL, and a plurality of wirings GL, A plurality of pixels 211 are arranged in an array. A plurality of wirings GL, SL , ML are provided according to the arrangement of the multiple pixels 211. The wiring GL is arranged in the vertical direction. The lines SL and ML are arranged in the horizontal direction. The lines GL are gate lines and scanning lines. The wiring SL may be called a source line, a data line, etc. The wiring ML is a wiring provided for monitoring the pixel 211, and is, for example, This can be called monitor wiring.

[0049] The peripheral circuit 220 includes a gate driver circuit 221, a source driver circuit 222, a monitor The digital signal processing circuit 222 includes a digital signal processing circuit 223 and an analog-to-digital conversion circuit (ADC) 224.

[0050] The gate driver circuit 221 is a circuit for driving the wiring GL and supplies The source driver circuit 222 has a function of generating a signal. The monitor circuit 223 is a line that generates a signal to be supplied to the wiring SL. The ADC 224 detects an analog signal flowing through the monitor circuit 223. This is a circuit for converting the output analog signal into a digital signal. The signal CMOUT is , is the output signal of the ADC 224 and is a digital signal. The signal CMOUT is In this embodiment, the semiconductor device according to the first embodiment is applied to the ADC 224. There are.

[0051] The image processing circuit 233 processes an externally input video signal to generate a data signal VDATA. The data signal VDATA is a digital signal that represents a gray scale. The image processing circuit 233 has a function of correcting the data signal VDATA using the signal CMOUT. The source driver circuit 222 processes the data signal VDATA and supplies the data to each line SL The memory 234 has a function of generating a data signal to be supplied to the image processing circuit 233. The memory 234 is provided to store data necessary for processing. For example, the signal CMOUT, the data signal VDATA, or the externally input video signal is It will be delivered.

[0052] 6 is an exploded perspective view of the display device 200. The display device 200 includes an upper cover 258-1 Between the touch panel unit and the lower cover 258-2, FPC256 is connected. 252, a display panel 250 to which an FPC 255 is connected, a frame 259, a printed circuit board The touch panel unit 251 includes a battery 253. In some cases, the light source 252 and the like may not be provided. A backlight unit may also be provided.

[0053] The upper cover 258-1 and the lower cover 258-2 are The shape and dimensions can be changed as appropriate according to the size of the frame and the display panel 250. The function of the frame 259 is to protect the display panel 250 and also to prevent damage caused by the operation of the printed circuit board 251. The frame 259 also functions as an electromagnetic shield to block electromagnetic waves. , may also have a function as a heat sink.

[0054] The printed circuit board 251 includes a CPU 230, a power supply circuit 232, an image processing circuit 233, a memory 2 34. The power source that supplies power to the power supply circuit 232 may be an external commercial power source. Alternatively, a separately provided battery 253 may be used. When the battery 253 uses a commercial power source, In this case, it can be omitted. In addition, the display device 200 does not include a polarizing plate, a retardation plate, a prism sheet, etc. Additional members such as a bracket may be provided.

[0055] The touch panel unit 252 is a resistive or capacitive touch panel. The display panel 250 may be overlapped with the opposing substrate (sealing substrate). It is also possible to provide a touch panel function to the display panel. It is also possible to provide an optical sensor in each pixel of the 250 to make it an optical touch panel. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 250, and a capacitive touch sensor is provided. It may also be a panel.

[0056] The display panel 250 shown in FIG. 6 has a substrate 260 and a substrate (opposing substrate) 261. The display 60 includes a pixel section 210 and a peripheral circuit 220. The substrate 260 on which the circuit is formed may be called the element substrate (backplane). A part or the whole of the path 220 may be provided on the substrate 260 in the same manufacturing process as the pixel section 210. In the example of FIG. 6, a part of the peripheral circuit 220 is provided in the IC 263. 263 is mounted on the substrate 260 using the COG (Chip on Glass) method.

[0057] <<Display panel>> FIG. 7 is a plan view showing a configuration example of an element substrate of the display panel 250. Here, based on FIG. In the same manner, terms that indicate the positional relationship such as left, right, up, down, etc. will be used.

[0058] The display panel 250 includes a pixel section 210 and a peripheral circuit 220 (circuits 221-224). Among the peripheral circuits, the gate driver circuit 221 and the monitor circuit 223 are This is a circuit formed on the substrate 260 in the same manufacturing process as the element portion 210. 221 is divided into two circuits (GDL, GDR) and is provided on the left and right of the pixel section 210. For example, the odd-numbered wiring GL is electrically connected to the GDR, and the even-numbered wiring GL is electrically connected to the GDL. GL is electrically connected. In this case, GDL and GDR alternately drive the wiring GL. do.

[0059] The area 262 includes a source driver circuit 222 and an ADC 224. In this example, the source driver circuit 222 and the ADC 224 are six driver ICs 10. The number of driver ICs 10 is not limited to this. A plurality of terminals (not shown) are formed on the driver IC 10, which are electrically connected to the driver IC 10. It has been done.

[0060] Hereinafter, the horizontal (H) resolution of the pixel unit 210 is n×RGB, and the vertical (V) resolution is The display device 200 will be described assuming that the image resolution is m. n and m are integers of 2 or more. RGB (Red, Green, Blue) represents the color that the pixel 211 displays. ) constitute one unit pixel.

[0061] The configuration of the unit pixel is not limited to this. The number of sub-pixels, the emission color of the sub-pixels, and The arrangement of the sub-pixels in the unit pixel and the like can be set appropriately. When a unit pixel is made up of four sub-pixels, the combination of colors to be displayed is [red (R), green (G), (G), blue (B), yellow (Y)], or [red (R), green (G), blue (B), white (W)], etc. In this specification, the components are distinguished by the color displayed by the pixel. In this case, identification symbols such as _R, [R], R[1], etc. are added. For example, pixel 211_R represents the red pixel 211. The wiring SL_G[2] is electrically connected to the pixel 211_G. 4 represents the second row of wiring SL.

[0062] <<Pixels>> FIG. 8A is a circuit diagram showing an example of a pixel 211, and FIG. 8B is a circuit diagram showing the operation of the pixel 211 shown in FIG. 10 is a timing chart showing an example.

[0063] FIG. 8A shows the layout in the kth row and jth column (k is an integer between 2 and m, and j is an integer between 2 and n). The pixel 211 is connected to the lines GL, SL, ML, and ANL. The pixel 211 includes transistors M1 to M3, a capacitance element C1, and and a light-emitting element EL1.

[0064] The light-emitting element EL1 has a pair of terminals (anode and cathode). For this purpose, an element capable of controlling the luminance by a current or a voltage can be used. The light-emitting element EL1 is an LED (light-emitting diode) or an OLED (organic light-emitting diode). For example, in the case of an OLED, the light-emitting element EL1 is an EL (electroluminescence) The EL layer is provided between the anode and the cathode, and may be a single layer or multiple layers. The EL layer includes at least a layer containing a light-emitting substance (light-emitting layer). Light-emitting elements that use EL elements to emit light are sometimes called EL elements. In particular, a light-emitting device having an organic EL layer is called an organic EL device. A display device that uses an organic EL element is called an organic light-emitting diode (OLED). Of course, the light-emitting element EL1 can be an organic EL element.

[0065] In FIG. 8A, transistors M1-M3 are n-type transistors, but some or all of them may be The transistors M1-M3 may be p-type transistors. By using such a device structure, the transistor M The current driving capability of the transistors M1-M3 can be improved. may all be transistors without a back gate.

[0066] The transistor M1 connects the gate (node ​​N2) of the transistor M2 and the line SL. The transistor M3 is a pass transistor that connects the wiring ML and the anode of the light-emitting element EL1. Transistor M2 is a pass transistor that connects the drive transistor (node ​​N1) to the The transistor functions as a current source for the current supplied to the light-emitting element EL1. The luminance of the light-emitting element EL1 is adjusted by the magnitude of the drain current of the capacitor M2. The capacitor C1 is a storage capacitor that holds the voltage between the node N1 and the node N2.

[0067] <Example of operation> A data signal Vda is input to the line SL. The voltage of the data signal Vda corresponds to the grayscale of the video signal. In FIG. 8B, Vda[k] and Vda[k+1] correspond to the kth row and This indicates that the data signal Vda is input to the pixel 211 in the (k+1)th row.

[0068] The period P1 is a writing operation period, during which the light-emitting element EL1 does not emit light. A voltage Vano is applied to the cathode of the light-emitting element EL1, and a voltage Vcat is applied to the cathode of the light-emitting element EL1. The line ML is electrically connected to a power supply line that supplies a voltage V0. When the line GL is set to a high level, The transistors M1 and M3 are turned on. The voltage of the wiring SL is applied to the node N2. Therefore, a drain current corresponding to this voltage flows through the transistor M2.

[0069] The voltages Vano, V0, and Vcat satisfy the following formulas (b1) to (b3). In the following formula, the voltage V thE is the light-emitting element EL1 is the threshold voltage, and the voltage V th2 is the threshold voltage of transistor M2. V0 <Vcat+V thE (b1) Vano>V0+V thE (b2) Vano>Vcat+V thE +V th2 (b3)

[0070] Since the formula (b1) and the formula (b2) hold, during the period P1 (writing period), the transistor M By turning on 3, the drain current of the transistor M2 is diverted to the wiring instead of the light-emitting element EL1. By satisfying formula (b3), the light can be preferentially sent to ML during period P2 (light emission period). Since a potential difference occurs between the wiring ANL and the cathode of the light-emitting element EL1, the transistor M The drain current of the second transistor is supplied to the light emitting element EL1, so that the light emitting element EL1 can emit light. In a period P2, the transistor M1 and the transistor M3 are turned off.

[0071] The period P3 is a monitor period for acquiring the drain current of the transistor M2. The power supply that supplies the line ML and the voltage V0 is turned on. The electrical connection between the line and the node N2 is cut off. th2 twist A voltage Vano is applied to the wiring ANL, and the A voltage Vcat is applied to the cathode. By driving the wiring SL in this way, This allows the drain current of the photodiode M2 ​​to flow preferentially to the wiring ML rather than to the light-emitting element EL1. Cut.

[0072] In the period P3, the current I MON During the light emission period, the transistor This corresponds to the drain current flowing through the transistor M2. MON Based on the analysis results, By correcting the voltage of the data signal Vda, the luminance deviation of the pixel 211 can be corrected. do.

[0073] The monitor operation does not always have to be performed after the light emission operation. For example, in pixel 211, After repeating the cycle of writing and emitting the data several times, the monitor operation is performed. After the monitor operation, the data signal corresponding to the minimum gray level 0 can be By writing to pixel 211, light emitting element EL1 may be put into a non-emitting state.

[0074] Here, an example in which a light-emitting element is used as a display element is shown, but the embodiment of the present invention is not limited to this. For example, in this specification, a display device that is a device having a display element A light-emitting element and a light-emitting device having a light-emitting element can be used in various forms. A display element, a display device, a light-emitting element, or a light-emitting device can have various elements. For example, EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), L ED (white LED, red LED, green LED, blue LED, etc.), transistor (current transistors that emit light in response to light emitted from a light source), electron emission elements, liquid crystal elements, electronic ink, electrophoretic elements, Grating light valve (GLV), plasma display (PDP), MEMS ( Display elements using microelectromechanical systems, digital microcomputers Digital Micro Shutter (DMD), Digital Micro Shutter (DMS), MIRASOL (registered trademark), IMOD (Interference Modulation) element, shutter MEMS display element using the optical interference method, MEMS display element using the optical interference method, electrowetting element display elements using carbon nanotubes, piezoelectric ceramic displays, etc. Both have one. Electrical or magnetic effects can affect contrast, brightness, reflectance, The display medium may have a variable transmittance. Examples of display devices using electron-emitting devices include EL displays. Field Emission Display (FED) or SED type flat panel display (S ED:Surface-conduction Electron-emitter D An example of a display device using liquid crystal elements is a liquid crystal display. (Transmissive LCD, Semi-transmissive LCD, Reflective LCD, Direct LCD LCDs (for viewing, projection, etc.) Electronic ink, electronic liquid powder (registered trademark) or an example of a display device using an electrophoretic element is electronic paper. In addition, when realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, A part or the whole of the pixel electrode may function as a reflective electrode. For example, if a part or the whole of the pixel electrode is made of aluminum, silver, etc. In this case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This further reduces power consumption. In this case, graphene or graphite may be placed under the LED electrodes or nitride semiconductor. Graphene or graphite may be formed into a multilayer film by stacking multiple layers. By providing graphene or graphite, a nitride semiconductor, e.g., a crystalline It is possible to easily form an n-type GaN semiconductor layer having a crystalline structure. An LED can be constructed by providing a p-type GaN semiconductor layer having a GaN crystal. An AlN layer is provided between lathane or graphite and a crystalline n-type GaN semiconductor layer. The GaN semiconductor layer of the LED may be formed by MOCVD (metal organic chemical vapor deposition). However, by providing graphene, the GaN of the LED can be formed by the GaN method. The semiconductor layer can also be formed by sputtering.

[0075] <<Monitor circuit>> current I MON is input to the monitor circuit 223. The monitor circuit 223 detects the current I MON A The monitor circuit 223 has a function of controlling the output to the DC 224. FIG. 9A shows an example of the configuration of the monitor circuit 223. The monitor circuit 223 is controlled by the signal V0_SW and the signal MSEL[3:1]. FIG. 9B is a circuit diagram showing an example of the configuration of the circuit MONI[j]. For example, the resolution of the display panel 250 is 8K4K (4320 x RGB (H) x 7680 (V)). Then, the monitor circuit 223 has 4320 circuits MONI.

[0076] The MONI circuit has three inputs and one output. The MONI circuit has three input terminals (ML _R, ML_G, ML_B) are electrically connected, the output terminal is terminal MOUT, and A The MONI circuit includes six transistors (Msw1-Ms The transistors Msw1-Msw3 and MS1-MS3 are The transistor Msw1 functions as a switch. The transistor Msw2 controls the conduction state between the power supply line 215 and the wiring ML_G. The transistor Msw3 controls the conduction state between the power supply line 215 and the wiring ML_B. The transistor MS1 controls the conduction state between the terminal MOUT and the wiring ML_R, and the transistor MS 2 controls the conduction state between the terminal MOUT and the wiring ML_G, and the transistor MS3 controls the conduction state between the terminal MO The power supply line 215 is a line for supplying a voltage V0. do.

[0077] A signal V0_SW is input to the gates of the transistors Msw1 to Msw3. The gates of the data buses MS1, MS2, and MS3 are connected to the signals MSEL[1], MSEL[2], and MSEL [3] is input. The writing period (period P1 in FIG. 8B) and the light emission period (period P2 in FIG. 8B) are In the interval P2), the transistors Msw1-Msw3 are turned on, and the transistors MS1-MS During the monitor period (period P3 in FIG. 8B), the transistors Msw1-Msw3 are turned off. 3 is turned off. Transistors MS1-MS3 are controlled so that only one is turned on. During the monitoring period, the current signals flowing through ML_R[j], ML_G[j], and ML_B[j] I MON _R[j], I MON _G[j], I MON _B[j] sequentially to the terminal MOUT Output from [j].

[0078] Here, the transistors Msw1-Msw3 and MS1-MS3 are n-type transistors. However, some or all of these may be p-type transistors. Msw1-Msw3 and MS1-MS3 have back gates, but some of them may all be transistors without a back gate.

[0079] <<Gate driver circuit (GDR, GDL)>> The circuit GDR and the circuit GDL may each be a shift register with m / 2 stages. The pixel 211 shown in FIG. 8A and the circuit MONI shown in FIG. 9B are each a transistor of a single conductivity type. Therefore, in order to reduce the cost of the display panel 250, It is preferable to fabricate the GDR and the circuit GDL using only n-type transistors. It is nice.

[0080] <<Driver IC>> FIG. 10 shows an example of the configuration of a driver IC. The driver IC 10 shown in FIG. 10 includes a circuit (SD) 20, test circuit 21, analog-to-digital conversion circuit (ADC) 30, logic circuit (L GC) 31, a read circuit 32, a switch circuit 33, a pass transistor logic circuit (P TL) 34, logic circuit (LGC) 35, multiple terminals 50, 3r (r is 2 or more and n or less (integer) terminals 51, a plurality of terminals 52, a terminal 60, r terminals 61, and a plurality of terminals 6 2. Terminal 50 is an input terminal, and terminals 51 and 52 are output terminals. Reference numeral 61 denotes an input terminal, and terminal 62 denotes an output terminal. In addition, some terminals such as terminal 50 are shown as terminals 1 in the drawings. Even if it is a terminal group consisting of multiple terminals according to the number of input signals or output signals, This also applies to other drawings.

[0081] <Source driver section> SD20 is a circuit corresponding to the source driver circuit 222, and is electrically connected to 3r terminals 51. FIG. 10 shows an example in which the unit pixel is made up of three (RGB) pixels 211. In the case where the unit pixel is a pixel 211 having 4 (RGBY), the number of terminals 51 is 4r. .

[0082] The terminals 51[1]-51[3r] are electrically connected to different wirings SL. 50 is n A This is the input terminal for the data signal VDATA of 128 bits. The data signal VDATA is This is a video signal processed by the image processing circuit 233. SD20 processes the data signal VDATA. This generates 3r data signals (analog voltage signals) Vda[1]-Vda[3r]. In addition, SD20 outputs data signals Vda[1]- Vda[3r] is output to terminals 51[1]-51[3r]. The process performed by SD20 is, for example, For example, parallel-serial conversion, digital-analog conversion, signal amplification, etc. The SD 20 is provided with a plurality of types of functional circuits corresponding to the logic.

[0083] A test circuit 21 is provided to verify the operation of the SD 20. The test circuit 21 is A switch circuit is included to control the electrical continuity between D20 and terminal 51. When verifying SD20, The test circuit 21 creates a non-conductive state between SD20 and terminals 51[1]-51[3r]. Under the control of the test circuit 21, the SD 20 outputs one or more data signals Vda from terminal 52. Here, the output signal of the terminal 52 is called a signal TSD. By analyzing the signal TSD, it is possible to determine malfunctions in the SD20 and verify its performance. do.

[0084] <Current detection section> The driver IC 10 receives the output signal (I MON ) to obtain the current value The semiconductor device 100 shown in FIG. 1 is applied to the current detection section. The output section includes an ADC 30, an LGC 31, a read circuit 32, a switch circuit 33, a PTL 34, The LGC 35 has a terminal 60, r terminals 61, and a plurality of terminals 62. Terminal 1 is an input terminal and terminal 62 is an output terminal.

[0085] Terminals 61[1]-61[r] are connected to terminals MOUT (Figure 9) of different circuits MONI. The ADC 30 receives signals from the terminals 61[1]-61[r] and converts them into Each of these circuits is a circuit for converting the signal into a digital signal, and has r circuits ADC_CM. Route ADC_CM receives the input signal B Convert analog to digital signal with 16-bit digital The LGC 31 generates a control signal that controls the ADC 30 and the readout circuit 32. This is a circuit to achieve this.

[0086] The switch circuit 33 is connected to the terminals 61[1]-61[r] and ADC_CM[1]-ADC_CM[r]. The switch circuit 33 has a function of controlling the conduction state between the switch SW3 and the The switch SW3[j] is a conductor between the terminal 61[j] and the input terminal of the ADC 30. (j is an integer between 1 and r). The switch SW3 is, for example, a transistor. When verifying ADC30, configure it with ADC_CM[1]-ADC_CM Input the analog current signal TIREF to [r]. During normal operation, that is, the display panel 250 During the monitor period of pixel 211, ADC_CM[1]-ADC_ CM[r] is the current signal I MON [1]-I MON Enter [r].

[0087] The read circuit 32 is a circuit for reading out the signal of the ADC 30. For example, A shift register is provided in the read-out circuit 32, and ADC_CM[1]-AD A control signal is sequentially output to C_CM[r] to read out the signal. This is a terminal for the output signal CMOUT of the read-out circuit 32.

[0088] PTL34 is a circuit for verifying the operation of ADC30. LGC35 is PTL34. This is a circuit for generating the control signal for the PTL34. The PTL 34 divides the signal TIREF input from the terminal PIN 1 into r Terminal 60 is the signal TIRE. This is the terminal for input of F.

[0089] For example, when six driver ICs 10 are used in the display panel 250, the resolution is 4K2K ( In the case of Quad Full HD, 3840 x RGB(H) x 2160), the number of terminals is 61 The number of terminals 51 is 1920 (3 x 640). In the case of a 320×RGB(H)×7680(V) display, the number of terminals 61 is 720, and the number of terminals 5 The number of 1s is 2160 (3 x 720).

[0090] <ptl> FIG. 11 shows an example of the configuration of the PTL 34 and the LGC 35. The LGC 35 is The pixel section has a function of generating a signal that controls the conductive state of the pixel transistor. An example of a monitor with a resolution of 8K4K (4320 x RGB (H) x 7680 (V)) is shown below.

[0091] The LGC 35 shown in FIG. 11 includes a counter circuit 301, two level shift circuits (LS) 30 Terminals 66-69 are terminals of the driver IC 10. Terminal 66 is a clock signal. Terminal 67 is an input terminal for the signal TCM. Terminal 68 is an input terminal for the signal TMCLK. A terminal 69 is an input terminal for a power supply voltage VDDS, and a terminal 69 is an input terminal for a power supply voltage VSS.

[0092] The counter circuit 301 has a function of obtaining a 10-digit count value in binary notation. The number of digits of the count value of 301 may be determined by the configuration of the PTL 34. 301 is a counter circuit that counts the rising (or falling) edges of the signal TMCLK. 301 denotes a signal TC_CNT[9:0] representing a count value, and its inverted signal TC_CNT B[9:0] is output. The signal TCM is a signal for resetting the count value. For example, When the TCM signal is set to high level, the count value becomes 1023 (2 10 -1), and the signal T C_CNT[9:0] goes high.

[0093] Here, the reset operation of the counter circuit 301 and the switch SW3 of the switch circuit 33 The signal TCM is connected directly or through a level shifter. The signal TCM is input to the switch circuit 33 via the switch (LS). On / off is controlled.

[0094] LS302-1 level-shifts the signal TC_CNT[9:0] and outputs the signal CNT[9:0 LS302-2 level-shifts the signal TC_CNTB[9:0] and generates the signal Generates the signal CNTB[9:0]. Signal CNT[9:0] and signal CNTB[9:0] is input to the PTL 34. The pass transistor of PTL34 is controlled to be on or off.

[0095] PTL34 can be configured in the same circuit configuration as PTL132 (Fig. 3, Fig. 4), and To achieve this structure, multiple n-type or p-type pass transistors can be connected together. The PTL34 shown in Figure 1 supports one DEMUX311, two DEMUX312, and two DEMUX313 is connected to the DEMUX311. Two bits are input, and the DEMUX312 and 313 receive the signals CNT and CNTB, respectively. The lower 7 bits are input.

[0096] DEMUX311 is a 4-output circuit. DEMUX312 is a 256-output circuit. DEMUX313 is a 104 output circuit. DEMUX312_1 is a terminal POUT[1 ]-POUT

[0256] , and DEMUX312_2 is electrically connected to terminals POUT

[0257] -POUT

[0512] . DEMUX313_1 is electrically connected to terminals P OUT

[0513] -POUT

[0616] are electrically connected, and DEMUX313_2 is It is electrically connected to the child POUT

[0617] -POUT

[0720] .

[0097] FIG. 12 shows an example of the configuration of the DEMUX 312. In FIG. 12, the pass transistor is an n-type. shows an example. The circuit excluding the pass transistor surrounded by the dotted line in FIG. 12 corresponds to DEM UX313.

[0098] The counter circuit 301 generates a count value according to the configuration of PTL34. In the example of FIG. 11 the counter circuit 301 counts from 0 to 615 and then counts from 768 to 871 . When the count value is 615, the terminal POUT

[0616] is selected. When the count value is 768, the terminal POUT

[0617] is selected, and when the count value is 871 the terminal POUT

[0720] is selected. Also, when the counter circuit 301 is reset and the count value is 1023, no signal path is formed in PTL34, so none of the terminal POUTs are electrically connected to the terminal PIN. Signal I MON is input from the pixel section 21 to ADC30, the count value of the counter circuit 301 is reset .

[0099] <ADC, Readout Circuit> FIG. 13 shows a configuration example of ADC30 and the readout circuit 32. ADC_CM is an integrating circuit 321, a comparator 322, and a counter circuit 323. To control ADC30 signals are input from outside the driver IC10, LGC31, and the shift register (SR) 332 . For example, the signal CMSROUT at the last stage of SR332 is input to ADC30 .

[0100] The readout circuit 32 has r circuits 331 and SR332. The circuit 331[j] has the function of controlling the output of the signal from ADC_CM[j] to terminal 62. The circuit 331 For example, it can be composed of one or more tri-state buffer circuits (TRIBUF). The SR332 has a function of generating a control signal for the circuit 331. SR332 generates the enable signal for TRIBUF. SR332 is used to generate multiple TRI Select one of the BUFs and connect it to terminal 62, and connect the output of the other TRIBUF to high impedance. Set the device to a impedance state.

[0101] <ADC_CM> 14 shows a configuration example of the ADC_CM and the readout circuit 32. The CM includes an integrator circuit 321, a comparator 322, a counter circuit 323, and a circuit 324. The ADC_CM has a function to detect the value of the signal Ia and displays the value of the signal Ia. In other words, the ADC_CM has the function of generating a digital signal that It is DC and has the function of converting an analog current signal into a digital signal. During verification, it is the analog current signal TIREF, and during normal operation, it is the output signal of the circuit MONI. No. I MON It is.

[0102] The integrating circuit 321 includes an operational amplifier 350, a capacitance element 351, and a switch SW50. The signal Ia is input to the inverting input terminal (terminal (-)) of the operational amplifier 350, and the non-inverting input A reference voltage VREF1 is input to the terminal (terminal (+)). The switch SW50 is connected to a signal C The signal CMSET is a set signal and is controlled by the operational amplifier 350. It has the function of resetting the voltage of the output terminal to the initial value. In this example, the set operation resets the op-amp The voltage at the output terminal of amplifier 350 becomes VREF1. Input is made from terminal 63.

[0103] The comparator 322 receives the output signal VAMP of the operational amplifier 350 and a reference voltage VREF2. In the example of FIG. 14, the comparator 322 has a hysteresis comparator. A resistor is used. The voltage of the input signal at the terminal (+) is equal to the voltage of the input signal at the terminal (-). When the voltage VREF1 and the voltage VREF2 exceed the threshold voltage VREF1, the signal VCMP goes high. It is generated by the power supply generation circuit inside the driver IC10. Here, VREF1>VREF2. be.

[0104] The circuit 324 includes switches SW51-SW54 and an inverter 352. Switches SW51 and SW52 are controlled by a signal CMPOL, and switches SW53 and SW54 are The circuit 324 controls the terminal ( The input to the terminals (+) and (-) is switched between the signal VAMP and the voltage VREF2. The circuit 324 switches the operation mode of the ADC_CM between a current sink mode and a current source mode. The signal CMPOL is a signal for setting the mode. The signal CMPOL is input from a terminal 64 of the driver IC 10. An inverted signal CMPOLB of the signal CMPOL is generated.

[0105] The counter circuit 323 has a function of generating digital data representing the current value of the signal Ia. The counter circuit 323 includes a latch circuit (LAT) 353. The clock signal CMCLK, the signal VCMP, the signal SRESET, and the signal CMSROUT are The clock signal CMCLK is input to the terminal 65 of the driver IC 10. SRESET is a signal generated by LGC35 and is also input to SR332. The cou nter circuit 323 has the function of counting the number of rising (or falling) edges of the signal CMCLK. LAT353 is a circuit for holding the count value. The signal VCM P has the function of stopping the counting operation of the counter circuit 323. For example, when the signal VCM P changes from low level to high level, the counter circuit 323 stops rewriting LAT353. As a result, the count value stored in LAT353 is determined. The signal SR ESET is a signal for resetting the count value of LAT353. The signal CMSRO UT is a signal for outputting the count value from LAT353. LAT353 outputs a digital signal CNTA representing the count value. In FIG. 14, an example is shown in which the counter circuit 323 has the function of obtaining a 12-bit count value in binary.

[0106] <Operation example of ADC_CM> FIG. 15 is a timing chart showing an operation example of ADC_CM. FIG. 15 shows an operation example when a voltage VREF2 is input to the terminal (+) of the comparator 322 and a signal VAMP is input to the terminal (-).

[0107] ADC_CM is reset by the signals CMSET and SRESET. Also, SR332 is reset by the signal SRE SET. The voltage of the signal VAMP becomes the voltage VREF1, and the count value held by LAT353 becomes 0. The counter circuit 323 counts the number of rising edges of the signal C MCLK, and the count value of LAT353 increases by 1. When the signal CMSET becomes low level and the switch SW50 turns off, by the signal Ia The voltage of the signal VAMP drops from VREF1. Eventually, the voltage of the signal VAMP drops to the voltage VR When the voltage VCMP falls below EF2, the signal VCMP goes high. The input of the signal VCMP stops updating the count value of the LAT353 and confirms the count value. The determined count value represents the magnitude of the current of the signal Ia. The counter value is fixed at 218. The counter circuit 323 outputs a high level signal CMSROUT With this input, it outputs a signal CNTA with a count value of "218".

[0108] <Circuit 331> Depending on the number of TRIBUFs in the circuit 331, the signal CNTA is distributed to one or more bits. In the example of FIG. 14, circuit 331 has a TRIBUF of 3. Therefore, the signal CNTA[11:0] is divided into 4 bits and input to the circuit 331. TRIBUF_1 receives the signal CNTA[3:0], and TRIBUF_2 receives the signal CNTA[7:4] is input, and signal CNTA[11:8] is input to TRIBUF_3. will be done.

[0109] SR332 operates according to the signals (SRESET, SRSP, MCLK, etc.) of TRIBUF. Generates an enable signal. SRESET is a signal for resetting the SR332. SRS P is the start pulse signal. MCLK is the clock signal.

[0110] In the circuit 331, TRIBUF_1, TRIBUF_2, and TRIBUF_3 are sequentially input. The enable signal is input, and signals CNTA[3:0], CNTA[7:4], and CN The signals are output from ADC_CM to terminal 62 in the order of TA[11:8]. In the example of 4, the signal CNTA[11:0] is read by the circuit 331 every four bits. The read signal is output from terminal 62. The 4-bit signal CMOUT[3:0] is This is the output signal from terminal 62.

[0111] The signal CMOUT is input to the image processing circuit 233. The image processing circuit 233 outputs the signal CM Analyze OUT and correct the data signal VDATA. The current signal I MON is a weak signal, for example, 110 pA to 10 nA Therefore, the current signal TIREF used to verify the ADC 30 is also the signal I MON and It is required that the current values ​​are approximately the same.

[0112] In this embodiment, the number of stages is very small compared to the number of circuits (ADC_CM) to be verified. The PTL34 can be configured with transistors. This allows the circuit scale of the test circuit to be reduced. This allows the driver IC 10 to be made smaller. This makes it possible to suppress fluctuations in the signal TIREF caused by leakage current from the pass transistor 4. For example, in the example in Figure 11, 780 ADC_CMs are verified using 10 pass-transistor stages. In this way, the PTL 34 is applied to the test circuit. This allows a large number of circuits to be verified using a small test circuit, and also reduces the error. In particular, functional circuits that process current signals of about 1 nA to 10 nA To verify this, adding a PTL to the test circuit is effective in suppressing verification errors. The more circuits are tested, the more pronounced the leakage current reduction effect of PTL34 becomes. The number of circuits to be verified is, for example, 2 k or more (for example, k is 8 to 19). For example, the upper limit of the number of circuits is 2. k Larger, 1×10 4 , or 1 × 10 6 、 or 1×10 7 It can be about that.

[0113] <<Display panel>> FIG. 16 shows an example of a device structure of the display panel 250. FIG. 16 shows a stacked structure of the pixel section 210 and the The device structure of the peripheral circuit 220a (GDR, GDL, and monitor circuit 223 in the example of FIG. 7) 16 is a diagram for explaining the configuration of the display panel 250, and is not a cross-sectional view of a specific portion of the display panel 250. The display panel 250 reflects light 555 extracted from the light emitting element EL1 from the substrate 261 side. 1 shows an example of a top emission structure for extracting

[0114] There are no particular restrictions on the device structures such as transistors and capacitors provided on the substrate 260. Select a device structure suitable for each function of the pixel section 210 and the peripheral circuit 220a. For example, the device structure of a transistor can be a top gate type, a bottom gate type, or front gate and dual gate type with both gate (front gate) and bottom gate A typical example is a multi-gate type having multiple gate electrodes for one semiconductor layer. There are no particular restrictions on the semiconductor layer in which the transistor channel is formed. In terms of structure, semiconductors can be broadly classified into single crystal and non-single crystal semiconductors. Semiconductor materials include conductors, microcrystalline semiconductors, and amorphous semiconductors. Semiconductor materials include Si, Ge, C Group 14 semiconductors containing one or more Group 14 elements such as silicon, silicon germanium, silicon carbide, etc.), oxide semiconductors (e.g., In-Ga-Zn oxide, I n-Sn-Zn oxide, etc.), compound semiconductors, etc.

[0115] Here, as an example of the display panel 250, an element substrate is configured with transistors of the same conductivity type. An example in which a transistor on an element substrate has a channel formed in an oxide semiconductor layer will be described. FIG. 1 shows an example of a transistor that can be used in a semiconductor device according to the present invention. 16 includes a transistor M3, a capacitance element C1, a light-emitting element EL1, and a peripheral circuit 220a The transistors M3 and M10 have a dual gate structure. It has a gate electrode on the substrate 260 side.

[0116] <Element substrate> The element substrate of the display panel 250 is a substrate 260 having an oxide semiconductor (OS) layer, a plurality of insulating layers, The electrode is formed by laminating a plurality of conductive layers.

[0117] The conductive layer of the display panel 250 may be formed of a single layer conductive film or two or more layers of conductive films. Such conductive films include aluminum, chromium, copper, silver, gold, platinum, and titanium. Ta, Nickel, Titanium, Molybdenum, Tungsten, Hafnium, Vanadium, Niobium Metal films of manganese, magnesium, zirconium, beryllium, etc. can be used. In addition, alloy films and compound films containing these metals, and films containing impurity elements such as phosphorus, A polycrystalline silicon film, a silicide film, etc. can be used. The conductive film may be a light-transmitting conductive film. Tungsten-containing indium oxide, tungsten oxide-containing indium zinc oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide (called ITO), indium zinc oxide, and indium with silicon oxide Examples of the film include a film containing a metal oxide such as aluminum tin oxide.

[0118] The insulating layer of the display panel 250 may be formed of a single insulating layer or two or more insulating layers. Inorganic insulating films include aluminum oxide, magnesium oxide, silicon oxide, Silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide , yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide Examples of the resin film include acrylic resin, polycarbonate, and tantalum oxide. imide resin, benzocyclobutene resin, siloxane resin, polyamide resin, epoxy resin In this specification, oxynitride refers to a film that contains more oxygen than nitrogen. Nitrogen oxide refers to a compound that contains more nitrogen than oxygen. cormorant.

[0119] The element substrate of the display panel shown in FIG. 16 includes oxide semiconductor (OS) layers 501 and 502, a first conductive layer, and a Conductive layers 511-513 provided on the first conductive layer, and conductive layers 521-524 provided on the second conductive layer. , conductive layers 531-533 provided in the third conductive layer, conductive layer 541 provided in the fourth conductive layer -544, a conductive layer 550 provided on the fifth conductive layer, and a conductive layer 551 provided on the sixth conductive layer , a conductive layer 552 provided on the seventh conductive layer, an EL layer 553, and insulating layers 571-576. The insulating layer 571 is a gate insulating layer for the transistor M3 and the transistor M10, and a capacitor The insulating layer 572 constitutes the dielectric of the capacitive element C1. Layer 576 acts as a spacer to maintain the space between substrate 260 and substrate 261. do.

[0120] <GDR、GDL> The transistor M10 includes an OS layer 501 and conductive layers 511, 521, 522, and 531. The conductive layer 531 constitutes a back gate and is electrically connected to the conductive layer 511. The conductive layer 541 is an electrode or wiring for wiring elements provided on the GDR and GDL. be.

[0121] <Pixel section> The transistor M3 includes an OS layer 502 and conductive layers 512, 523, 524, and 532. The conductive layer 532 constitutes a back gate and is electrically connected to the conductive layer 512. The conductive layer 512 constitutes the wiring GL, and the conductive layer 523 constitutes the wiring ML. In the example of FIG. 16, the conductive layer 512 is shared with the capacitance element C1. The entire lower surface of the OS layer 502 is electrically conductive via the insulating layer 571. The capacitance element C1 is an MIM type, and includes a conductive layer 513, an insulating layer 57, and a 1, a conductive layer 524, an insulating layer 572, and a conductive layer 533 are laminated. The conductive layer 543 is a wiring SL, and the conductive layer 544 is a transistor for the light-emitting element EL1. This is an electrode for electrically connecting to the transistor M3 and the capacitance element C1.

[0122] Light-emitting element EL1 is provided on insulating layer 574. Conductive layers 550-552 and EL layer The portion where the conductive layers 550 and 551 are laminated functions as the light-emitting element EL1. The conductive layers 550 and 551 are the anode and cathode electrodes of the light element EL1. The conductive layer 552 and the EL layer 553 are provided for each pixel portion 210. There are a few provided.

[0123] The EL layer 553 contains a light-emitting material capable of emitting light by recombining holes and electrons. The EL layer 553 includes a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. Any functional layer may be formed as necessary. In this example, an EL layer 553 that emits white light is provided. The conductive layer 551 is provided to make the light-emitting element EL1 have a microcavity structure. For example, the conductive layer 551 is formed of an indium tin oxide film containing silicon oxide. The conductive layer 551 can reduce the optical path length between the conductive layer 550 and the conductive layer 552. The thickness of the conductive layer 551 is adjusted according to the wavelength of the light to be extracted from the pixel 211. For example, the thickness of the conductive layer 551 is adjusted in the range of 5 nm to 100 nm. The conductive layer 551 is made thicker as the wavelength of the light 555 becomes longer. The thickness is as follows: pixel 211_R>pixel 211_G>pixel 211_B.

[0124] <Example of the configuration of the opposing substrate> The opposing substrate is fixed to face the substrate 260 by a sealing member (not shown). The counter substrate of the display panel 250 shown in FIG. 16 includes a substrate 261, a light-shielding layer 580, a color filter The color filter layer 581 corresponds to the pixel 211. The color filter layer 581 may be provided on the element substrate or may be provided on a The peripheral circuit 220a is shielded from light by a light shielding layer 580. A light-shielding layer 580 is provided on the overcoat 510 so as to shield areas that do not contribute to display. The overcoat layer 582 serves to flatten the surface of the opposing substrate and to remove impurities (typically water and / or oxygen). The overcoat layer 582 is made of, for example, polyimide resin, ethylene glycol, It can be formed from epoxy resin, acrylic resin, or the like.

[0125] (substrate) Substrates applicable to the substrates 260 and 261 include, for example, glass substrates, quartz substrates, and plastic substrates. Includes tungsten substrate, metal substrate, stainless steel substrate, stainless steel foil Substrate, tungsten substrate, substrate with tungsten foil, flexible substrate, lamination Examples of the substrate include a film, a paper containing a fibrous material, and a base film. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. An example of a flexible substrate is polyethylene terephthalate (PET). , polyethylene naphthalate (PEN), and polyethersulfone (PES). Plastics that can be used for bonding, or synthetic resins that have flexibility, such as acrylic. The film is made of polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, etc. Alternatively, a film made of a material such as a cellulose acylate film or an inorganic vapor deposition film may be used. Examples include polyester, polyamide, polyimide, aramid, epoxy, and inorganic deposition film. In the example of FIG. 16, the substrate 261 is transparent to light 555 (visible light). Pass.

[0126] The substrate 260 is a support substrate (glass) used for fabricating the pixel section 210 and the peripheral circuit 220a. After the pixel section 210 and the peripheral circuit 220a are completed, or during the manufacturing process, In the middle of the process, the support substrate may be peeled off and a flexible substrate may be attached by an adhesive layer. The substrate 261 is also a support substrate (such as a glass substrate) used to manufacture the color filter layer 581, etc. After the overcoat layer 582 is formed, the support substrate is peeled off and the adhesive layer is applied to the overcoat layer 582. A flexible substrate may be attached.

[0127] By using flexible substrates for the substrates 260 and 261, a flexible display device can be obtained. In addition, by incorporating a flexible display device, a flexible semiconductor device can be provided. be.

[0128] (Embodiment 3) In this embodiment, a transistor applied to a semiconductor device will be described.

[0129] <<Transistor configuration example 1>> FIG. 17 shows an example of the configuration of an OS transistor. FIG. 17C is a top view (layout diagram) of the transistors TA1 and TA2. FIG. 17D shows a cross-sectional view of the transistors TA1 and TA2 taken along line y1-y2. That is, FIG. 17C shows a cross-sectional view of the transistors TA1 and TA2 in the channel length direction. 17D shows a cross-sectional view of the transistors TA1 and TA2 in the channel width direction.

[0130] In FIG. 17, in order to clarify the device structure, the gate and source of each transistor are The wiring for supplying signals and potentials to the drain is omitted. The channel length is the distance between the source electrode and the drain electrode, and the channel width is the oxide semiconductor layer. The width of the source or drain electrode in the region where the gate electrode overlaps the source or drain electrode. The channel lengths of TA1 and TA2 are La1 and La2, and the channel widths are Wa1 and Wa2. do.

[0131] The transistors TA1 and TA2 are provided on the same insulating surface (substrate 600). The transistors TA1 and TA2 can be manufactured in the same process. , TA2 are transistors having a gate and a back gate. In the transistors TA1, TA2, the back gate is connected to the gate. It is also possible to have no backgate at A2.

[0132] <Transistor TA1> The transistor TA1 is formed on a substrate 600, and has an electrode GE1, an electrode SE1, and an electrode D E1, an electrode BGE1, and a layer OS1. The electrode GE1 is a gate electrode, and the electrode S E1 is the source electrode, DE1 is the drain electrode, and BGE1 is the backgate electrode. The layer OS1 is an oxide semiconductor layer.

[0133] The layer OS1 overlaps with the electrode GE1 via an insulating layer 621. A pair of electrodes (SE1, DE1) are formed in contact with the surface. OS1 has a portion that does not overlap with the electrode GE1 and the pair of electrodes (SE1, DE1). The layer OS1 has a length in the channel length direction longer than the channel length La1 and a channel width The length in the direction is longer than the channel width Wa1.

[0134] An insulating layer 622 and an insulating A layer 623 is formed on the insulating layer 623. An electrode BGE1 is formed on the insulating layer 623. E1 is provided so as to overlap the layer OS1 and the electrode GE1. The electrode BGE1 is provided so as to have the same shape and be located in the same position as the electrode BGE1. contacts the electrode GE1 at an opening CG1 penetrating the insulating layers 621-623.

[0135] As shown in FIG. 17D, the channel region of the transistor TA1 is connected to the electrodes GE1 and B The device structure is surrounded by GE1. Therefore, the channel of the transistor TA1 The region is affected by the electric field formed by not only the electrode GE1 but also the electrode BGE1. Therefore, by connecting the electrode BGE1 to the electrode GE1, The on-current can be increased. Also, the field effect mobility of the transistor TA1 can be improved. In addition, the variation of the electrical characteristics such as the threshold voltage of the transistor TA1 can be suppressed. In addition, by providing the electrode BGE1, the strength of the transistor TA1 can be reduced. The electrode BGE1 acts as a reinforcing member against deformation such as bending of the substrate 600. This makes it possible to make the transistor TA1 less likely to break down.

[0136] The layer OS1 including the channel region has a multi-layer structure. Here, as an example, three oxide semiconductors are used. The oxide film constituting the layer OS1 is a three-layer structure (631, 632, 633). The semiconductor is preferably a metal oxide containing at least one of the same metal elements, and preferably In. It is particularly preferable that the semiconductor layer of a transistor is made of In-containing gold. Metal oxides include In-Ga oxide and In-M-Zn oxide (where M is Al, Ga, Y, or Z). The most typical are r, la, cerium, or neodymium. or materials with added materials can be used.

[0137] The oxide semiconductor film 632 is a film in which a channel region of the transistor TA1 is formed. The oxide semiconductor film 633 forms a channel region in a transistor TA2 to be described later. Therefore, in the transistor TA1, the oxide semiconductor film 632 is In TA2, the oxide semiconductor film 631 is formed so that a channel is formed in the oxide semiconductor film 633. It is preferable to adjust the atomic ratio of the metal elements that are the main components of -633.

[0138] In the transistor TA1, a channel is formed in the oxide semiconductor film 632. This prevents the channel region from coming into contact with the insulating layers 621 and 622. In addition, the oxide semiconductor films 631 to 633 are made of a metal oxide film containing at least one of the same metal elements. By forming the oxide semiconductor film 632 as a thin film, the interface between the oxide semiconductor film 631 and the oxide semiconductor film 632 and the oxide semiconductor film 633 can be easily formed. The interface between the conductive film 632 and the oxide semiconductor film 633 is prevented from causing interfacial scattering. This makes it possible to make the field effect mobility of the transistor TA1 higher than that of the transistor TA2. Also, the on-current can be increased.

[0139] <Transistor TA2> The transistor TA2 is a modification of the transistor TA1, and the layer OS2 is an oxide semiconductor film. It differs from transistor TA1 in that it is a single-layer structure made of 633, but the rest is similar. Here, the channel length La2 of the transistor TA2 is the same as that of the transistor TA1. The channel length La1 is equal to the channel width Wa2, and the channel width Wa1 is equal to the channel width Wa2. The transistor TA2 has an electrode GE2, an electrode SE2, an electrode DE2, an electrode BGE2, and The electrode BGE2 is formed at an opening GC2 penetrating the insulating layers 621-623. The electrode GE2 is a gate electrode, and the electrode SE2 is a source electrode. The electrode DE2 is a drain electrode, and the electrode BGE2 is a back gate electrode. S2 is an oxide semiconductor layer.

[0140] [Insulation layer] The insulating layers 621-623 are formed over the entire area in which the transistors TA1 and TA2 are to be formed. The insulating layers 621-623 are formed of a single layer or multiple layers of insulating film. The layer 621 is a film that constitutes the gate insulating layer of the transistors TA1 and TA2. 22 and 623 form the gate insulating layer on the back channel side of the transistors TA1 and TA2. The uppermost insulating layer 623 is a film that is formed on the substrate 600. It is preferable to form the insulating layer 623 from a material that functions as a protective film. In order to insulate the third layer electrode BGE1 from the second layer electrodes SE1 and DE1, At least one insulating film may be present between them.

[0141] [Oxide semiconductor film] When the semiconductor layer has a multi-layer structure like the layer OS1, the oxide semiconductor films constituting the semiconductor layer are It is preferable that they contain at least one of the same metal elements, and it is preferable that they contain In.

[0142] For example, when the oxide semiconductor film 631 is an In-Ga oxide film, the atomic ratio of In is set to the atomic ratio of Ga. The ratio of the number of atoms is smaller than that of the number of atoms in the In-M-Zn oxide film (where M is Al, Ga, Y, Zr, La, In the case of Ce or Nd), the atomic ratio of In is made smaller than the atomic ratio of M. In this case, In this case, the atomic ratio of Zn can be made the largest.

[0143] For example, when the oxide semiconductor film 632 is an In-Ga oxide film, the atomic ratio of In is set to the atomic ratio of Ga. In the case of an In-M-Zn oxide film, the atomic ratio of In is set to be larger than the atomic ratio of M. In the In-M-Zn oxide film, the atomic ratio of In is larger than the atomic ratio of M and Zn. It is preferable to set the ratio larger than the number of atoms.

[0144] For example, when the oxide semiconductor film 633 is an In-Ga oxide film, the atomic ratio of In is set to the atomic ratio of Ga. In the case of In-M-Zn oxide film, the atomic ratio of In is set to be equal to or smaller than the atomic ratio of In. The atomic ratio of Zn is set to the same as that of M. In this case, the atomic ratio of Zn is larger than that of In and M. Here, the oxide semiconductor film 633 serves as a channel region of the transistor TA2. It is also a film that constitutes the holographic region.

[0145] The atomic ratio of the oxide semiconductor films 631-633 is 1 / 1000 when the films are formed by a sputtering method. This is possible by adjusting the atomic ratio of the constituent materials of the get. In this case, it is possible to adjust the flow rate ratio of the source gases. As an example, in the case of forming an In-M-Zn oxide film by sputtering, The target used for film formation will be described.

[0146] The atomic ratio of the metal elements in the target of the oxide semiconductor film 631 is In:M:Zn=x1:y1 If z1, then x1 / y1 is preferably 1 / 6 or more and less than 1. It is preferable that y1 is ⅓ or more and 6 or less, and more preferably 1 or more and 6 or less.

[0147] Representative examples of the atomic ratio of the target metal elements are In:M:Zn=1:3:2, In :M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4: 6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1: 5:5, In:M:Zn=1:5:6, In:M:Zn=1:5:7, In:M:Zn= 1:5:8, In:M:Zn=1:6:8, etc.

[0148] The atomic ratio of the metal elements in the target of the oxide semiconductor film 632 is In:M:Zn=x2:y2 : z2, x2 / y2 is preferably greater than 1 and equal to or less than 6. It is preferable that / y2 is greater than 1 and not greater than 6. Representative examples are In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=3:1: 3. In:M:Zn=3:1:4, etc.

[0149] The atomic ratio of the metal elements in the target of the oxide semiconductor film 633 is In:M:Zn=x3:y3 If z3, then x3 / y3 is preferably 1 / 6 or more and 1 or less. It is preferable that y3 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Representative examples of atomic ratios of metal elements are In:M:Zn=1:1:1, In:M:Zn= 1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M :Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In :M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1:5:5, In:M:Zn=1:5: 6, In:M:Zn=1:5:7, In:M:Zn=1:5:8, In:M:Zn=1: Examples include 6:8.

[0150] As the oxide semiconductor films 631 to 633, oxide semiconductor films with low carrier density are used. For example, the oxide semiconductor films 631 to 633 may have a carrier density of 1×10 17 pieces / cm 3 Less than or equal to 1×10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following oxide semiconductor film is used.

[0151] The oxide semiconductor films 631 to 633 are formed of oxide semiconductor films having low impurity concentrations and low density of defect states. By using a conductive film, it is possible to fabricate a transistor with even better electrical characteristics. Here, the low impurity concentration and low defect level density (low oxygen vacancies) are the main factors. It is called pure or substantially high purity. Pure or substantially high purity Since oxide semiconductors have few carrier generation sources, the carrier density can be reduced in some cases. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may have a problem. The threshold voltage rarely becomes negative (also called normally-on). In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a low density of defect states. Since the concentration is low, the trap density may also be low. The intrinsic oxide semiconductor film has a significantly small off-state current and a channel width of 1×10 6 μ Even if the device has a channel length of 10 μm and a The off-state current was measured by the semiconductor parameter analyzer when the drain voltage was in the range of 1V to 10V. Below the measurement limit of the -13 A characteristic of less than A can be obtained. In addition, a transistor in which a channel region is formed in the oxide semiconductor film has low fluctuation in electrical characteristics. This results in a small and highly reliable transistor. Impurities include hydrogen, nitrogen, and alkali metals. , or alkaline earth metals, etc.

[0152] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water and an acid. Oxygen vacancies are formed in the lattice from which the atoms are desorbed (or in the part from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. When it bonds with oxygen, which bonds with a metal atom, it may generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. It's easy to become.

[0153] For this reason, in the oxide semiconductor films 631 to 633, oxygen vacancies and hydrogen are reduced as much as possible. Specifically, in the oxide semiconductor films 631 to 633, secondary ions are preferably Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration obtained by the above test is 5×10 19 atoms / cm 3 The following is more preferred: 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than, preferred Or 1×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 The following applies.

[0154] When the oxide semiconductor films 631 to 633 contain silicon or carbon, which is one of the group 14 elements, As a result, oxygen vacancies in the film increase, and the film becomes n-type. The concentration of silicon and carbon in 631-633 (concentrations obtained by secondary ion mass spectrometry) degrees), 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / c m 3 The following applies.

[0155] In addition, in the oxide semiconductor films 631 to 633, The concentration of alkaline metals or alkaline earth metals is 1×10 18 atoms / cm 3 Below is good Preferably 2 x 10 16 atoms / cm 3 The following are alkali metals and alkaline earth metals: When a metal combines with an oxide semiconductor, carriers may be generated, causing the transistor to turn off. The current may increase. It is preferred to reduce the concentration of metals or alkaline earth metals.

[0156] When nitrogen is contained in the oxide semiconductor films 631 to 633, electrons that serve as carriers are generated, and The carrier density increases and it is easy to make it n-type. Therefore, it is recommended to use an oxide semiconductor that contains nitrogen. Since the transistor tends to be normally on, the oxide semiconductor film 631-633 It is preferable that the nitrogen content of is as low as possible. For example, it is preferable that the nitrogen content of is as low as possible. The nitrogen concentration obtained by the method is 5 x 10 18 atoms / cm 3 It is preferable to do the following: .

[0157] Although the oxide semiconductor films 631 to 633 have been described above, the present invention is not limited thereto. An oxide semiconductor film with an appropriate composition is used according to the electrical characteristics (field effect mobility, threshold voltage, etc.). In order to obtain necessary electrical characteristics, the oxide semiconductor films 631 to 633 Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable to make the following appropriate.

[0158] Although the transistors TA1 and TA2 have been described above, the present invention is not limited to these, and any other transistors may be used as required. The transistor configuration can be changed according to the semiconductor and electrical characteristics of the transistor. For example, the presence or absence of a back gate electrode, the stacked structure of the oxide semiconductor layer, the oxide semiconductor layer, the gate The shapes and arrangements of the inlet electrode, source electrode and drain electrode can be appropriately changed.

[0159] <<Transistor configuration example 2>> FIG. 18 shows an example of the structure of a top-gate OS transistor. FIG. 18C shows a top view (layout diagram) of the transistors TA3 and TA4. TA3 and TA4 are cross-sectional views taken along line x5-x6, showing the cross-sectional structure in the channel length direction. FIG. 18D is a cross-sectional view of the transistors TA3 and TA4 taken along line y5-y6. The cross-sectional structure in the width direction is shown.

[0160] The transistors TA3 and TA4 are formed on a substrate 650. The transistor TA3 , electrode BGE3, layer OS3 on insulating layer 651, electrode SE3, electrode DE3, insulating layer 652, and an electrode GE3. The transistor TA4 has a layer OS4, an electrode SE4, and an electrode DE4. , an insulating layer 653, and an electrode GE4. The insulating layer 653 and the insulating layer 652 function as a gate insulating film. The electrodes GE3 and GE4 are gate electrodes, and the electrodes SE3 and SE4 are source electrodes. The electrodes DE3 and DE4 are drain electrodes, and the electrode BGE3 is a back gate electrode. The layers OS3 and OS4 are oxide semiconductor layers. It is formed of a stack of semiconductor films.

[0161] The electrode GE3 is in contact with the electrode BGE3 at the opening CG3. By applying the same potential to both the GBT and the on-state current, the initial characteristic variation is reduced, and the -GBT switch is Suppression of degradation during stress testing and on-current rise voltage at different drain voltages Alternatively, the electrode GE3 and the electrode BGE3 are not connected, and the fluctuation of By applying different potentials, the threshold voltage of the transistor TA3 can be controlled. do.

[0162] In the transistor TA4 and the transistor TA3, the electrodes GE4 and SE4 and Since the electrodes GE4 and SE4 and DE4 do not overlap, the distance between the electrodes GE4 and SE4 and DE4 is In addition, the parasitic capacitance of the electrode GE3, the electrode SE3, and the electrode D Since the electrodes GE3 and E3 do not overlap, the parasitic volume between the electrodes SE3 and DE3 is As a result, when a large-area substrate is used as the substrate 650, To reduce signal delays at electrodes SE4, DE4, GE4, SE3, DE3, and GE3 is possible.

[0163] In the transistor TA3, the electrodes SE3, DE3, and GE3 are used as a mask to perform doping. By adding an element to the layer OS3, a region having oxygen vacancies is formed. In A4, the electrodes SE4, DE4 and GE4 are used as masks to deposit a rare gas element into layer OS4 By adding hydrogen to the insulating layer 65, a region having oxygen vacancies is formed. When forming the transistor TA3, the region having oxygen vacancies in the transistor TA4 is Since the insulating layer 654 containing hydrogen is in contact with the insulating layer 654, the hydrogen contained in the insulating layer 654 has oxygen vacancies. By diffusing the GaN layer into the region, a low resistance region is formed. A region can be formed.

[0164] <<The structure of oxide semiconductors>> Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include a conductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0165] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0166] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. In the case where the crystal is trigonal or rhombohedral, it is referred to as a hexagonal crystal system.

[0167] <caac-os> CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. CAAC-OS is one of the conductors. Alternatively, the oxide semiconductor may be referred to as an oxide semiconductor having no crystals.

[0168] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0169] In the out-of-plane structural analysis of CAAC-OS, 2θ is approximately 31°. In addition to the peak, a peak may appear around 2θ of 36°. This indicates that some of the CAAC-OS crystals do not have the c-axis orientation. The more preferable CAAC-OS is for structural analysis using the out-of-plane method. , shows a peak at 2θ of around 31°, and does not show a peak at 2θ of around 36°. The structure is solved by the in-plane method, in which X-rays are incident on the OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed using XRD, a peak appears at 2θ of approximately 56°. From this, it can be seen that the orientation of the a-axis and b-axis of CAAC-OS is irregular.

[0170] In addition, electron diffraction revealed that the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is It can be seen that the direction is approximately perpendicular to the formation surface or upper surface.

[0171] CAAC-OS is an oxide semiconductor with a low density of defect states. For example, defects due to impurities and oxygen vacancies are included. S can be regarded as an oxide semiconductor with a low concentration of impurities. It can also be said that the oxide semiconductor has few element vacancies.

[0172] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or may cause hydrogen By capturing atoms, they can become a carrier generation source.

[0173] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0174] In addition, an oxide semiconductor with a low density of defect states (few oxygen vacancies) can reduce the carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. A transistor using C-OS has electrical characteristics in which the threshold voltage is negative (normal In addition, the acid is highly pure or substantially pure. The oxide semiconductor has fewer carrier traps. The charge takes a long time to be discharged and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are In contrast, transistors using CAAC-OS can have unstable electrical characteristics. The transistor has small fluctuations in electrical characteristics and is highly reliable. Since the defect level density of AC-OS is low, carriers generated by light irradiation, etc. Therefore, transistors using CAAC-OS have In addition, the change in electrical characteristics due to irradiation with visible light or ultraviolet light is small.

[0175] <Microcrystalline oxide semiconductor> Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often present. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- The nc-OS is called the "High Resolution Oxide Semiconductor." In some cases, the grain boundaries cannot be clearly seen in the TEM images. Therefore, in the following, we will refer to the pellets in the nc-OS. The crystalline part of S is sometimes called a pellet.

[0176] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks were detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy region.

[0177] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0178] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0179] <<Transistor configuration example 3>> Here, an example is shown in which the semiconductor layer is formed of a silicon film.

[0180] FIG. 19 shows an example of a top-gate transistor. A5 is an n-type transistor, and transistor TA6 is a p-type transistor. Transistors TA5 and TA6 are formed on a substrate 671 having an insulating surface.

[0181] Transistor TA5 includes conductive layers 660, 662, 664, 666, and 668. The conductive layer 667, the insulating layer 672, the insulating layer 673, the insulating layer 674, the insulating layer 675, and the semiconductor The transistor TA6 includes a conductive layer 661, a conductive layer 663, a conductive layer 665, and a conductive layer 680. , conductive layer 668, conductive layer 669, insulating layer 672, insulating layer 673, insulating layer 674, insulating layer 6 75, and a semiconductor layer 681.

[0182] The semiconductor layers 680 and 681 are formed of a silicon film. For example, the semiconductor layers 680 and 681 are Amorphous silicon film formed by vapor phase growth method such as plasma CVD method or sputtering method In addition, such amorphous silicon can be formed by laser annealing, etc. It can be made of polycrystalline silicon that has been crystallized by processing. It can also be made of single crystal silicon. It can be formed by injecting hydrogen ions into the wafer and peeling off the surface layer of the single crystal silicon layer. Cut.

[0183] The semiconductor layers 680 and 681 may be crystallized using, for example, a laser crystallization method. Alternatively, there is a crystallization method using a catalytic element and a laser crystallization method. The substrate 671 may be made of heat-resistant material such as quartz. When using a substrate with excellent properties, the thermal crystallization method using an electric furnace and the lamp annealing method using infrared light are This method combines the ball crystallization method, the crystallization method using catalytic elements, and high-temperature annealing at around 950°C. Crystallization methods may also be used.

[0184] The insulating layer 672 serves as an insulating layer for the transistors TA5 and TA6. The semiconductor layer 680 includes a channel region 682, a pair of LDDs (Light Doped MOSFETs), and a pair of MOSFETs. The channel region has a pair of impurity regions 683 and a pair of impurity regions 684. The region 682 is a region that overlaps with the conductive layer 664 of the semiconductor layer 680. 84 functions as a source region and a drain region. To provide n-type conductivity, The LDD region 683 and the impurity region 684 are doped with boron (B), aluminum (Al), and gallium (Ga). The semiconductor layer 681 is doped with an impurity element such as gallium (Ga). The channel region 685 is a conductive region of the semiconductor layer 681, and a pair of impurity regions 686. The pair of impurity regions 686 are a source region and a drain region. To impart p-type conductivity, the impurity region 686 is doped with phosphorus (P), Impurity elements such as As (As) are added.

[0185] The conductive layer 660 and the conductive layer 661 are the first conductive layers. The conductive layer 661 includes a region that functions as a back gate electrode of the transistor T The conductive layer 662 and the conductive layer 663 include a region that functions as a back gate electrode of the first gate electrode A6. There are two conductive layers, conductive layer 664 and conductive layer 665 are the third conductive layer. 4 has a width in the channel length direction shorter than that of the conductive layer 662, and the conductive layer 665 is The width in the longitudinal direction is shorter than that of the conductive layer 663. The region overlapping with the semiconductor layer 680 via the insulating layer 673 is the gate voltage of the transistor TA5. It functions as a pole.

[0186] Conductive layers 666-669 are the fourth conductive layer. Conductive layers 666 and 667 are A region that functions as the source electrode and the drain electrode of the transistor TA5 is provided. The semiconductor layer 680 is in contact with the insulating layer 673 and the opening formed in the insulating layer 674. Layer 668 and conductive layer 669 form the source and drain electrodes of transistor TA6. The insulating layer 673 and the insulating layer 674 are provided with an opening, and the insulating layer 673 and the insulating layer 674 are provided with an opening. It is in contact with the conductor layer 681 .

[0187] (Embodiment 4) In this embodiment mode, a display device and a semiconductor device including the display device will be described.

[0188] As shown in the second embodiment, the flexible display device can be used in electronic devices and lighting devices having flexibility. By incorporating a flexible display device in a display portion, a semiconductor device such as a display panel can be provided. This makes it possible to provide electronic devices and lighting devices that are highly reliable and resistant to repeated bending. can.

[0189] Examples of electronic devices include television sets (also known as televisions or television receivers). (hereinafter referred to as "computer monitors"), digital cameras, digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, Examples include portable information terminals, audio playback devices, and large game machines such as pachinko machines. The electronic equipment may be mounted on the interior or exterior walls of a house or building, or on the curved surfaces of the interior or exterior of a vehicle. It is also possible to incorporate the electronic device in accordance with the above. The display device of the child device may incorporate, for example, the display device of the second embodiment.

[0190] A mobile phone 7400 shown in FIG. 20A includes a display portion 7402 incorporated in a housing 7401. , an operation button 7403, an external connection port 7404, a speaker 7405, a microphone Note that the mobile phone 7400 is an input / output device according to one embodiment of the present invention. The display portion 7402 is manufactured by using the curved display according to one embodiment of the present invention. The present invention provides a highly reliable mobile phone with a high yield. By touching the display portion 7402 with a finger or the like, information can be input. Any operation such as placing a call or inputting characters is performed by touching the display portion 7402 with a finger or the like. Also, by operating the operation button 7403, the power can be turned on, It is possible to switch off the image or change the type of image displayed on the display portion 7402. For example, You can switch from the email creation screen to the main menu screen.

[0191] Fig. 20B shows an example of a wristwatch-type mobile information terminal. The reference numeral 7100 denotes a housing 7101, a display unit 7102, a band 7103, a buckle 7104, and an operation The mobile information terminal 7100 is equipped with a button 7105, an input / output terminal 7106, etc. , e-mail, viewing and writing text, playing music, internet communication, computer games The display unit 7102 can execute various applications such as the following. The display unit 71 is curved and can display information along the curved display surface. The 02 is equipped with a touch sensor, so you can operate it by touching the screen with your finger or a stylus. For example, by touching an icon 7107 displayed on the display unit 7102, the application You can start the application.

[0192] The operation button 7105 is used to set the time, turn the power on and off, and turn wireless communication on and off. It has various functions such as operation, silent mode activation and deactivation, power saving mode activation and deactivation, etc. For example, an operating system installed in the portable information terminal 7100 can The functions of the operation buttons 7105 can be freely set by the system. The 7100 is capable of performing short-range wireless communication according to a communication standard. You can also talk hands-free by connecting to a compatible headset. The portable information terminal 7100 also includes an input / output terminal 7106, and is connected to other information terminals via a connector. Data can be exchanged directly through the input / output terminal 7106. It is also possible to charge the battery. Note that the charging operation is performed by wireless power supply without going through the input / output terminal 7106. It is also acceptable to

[0193] The display panel of the second embodiment can function as a flat light source. The display panel is appropriately called a light-emitting panel or a light source panel. An example of an electronic device equipped with a light source is shown in FIG. 20C. The lighting device 7210 shown in FIG. Each of the devices has a base 7201 equipped with an operation switch 7203 and a light emitting device supported by the base 7201. The display panel is built into the light-emitting part. The light-emitting part is made of a plastic material or a movable frame. The light is fixed with a frame or other material, and the light-emitting surface of the light-emitting part can be freely curved according to the application. FIG. 20C illustrates an example of a lighting device in which a light-emitting unit is supported by a base. The housing including the light-emitting unit can be fixed to the ceiling or hung from the ceiling. The light-emitting surface can be curved, allowing you to brightly illuminate a specific area by curving the light-emitting surface in a concave shape. The light source can also be curved convexly to brightly illuminate an entire room.

[0194] The electronic devices and lighting devices using one aspect of the present invention are not limited to products having flexibility. FIG. 20D shows an example of such an electronic device. The display device 7000 shown in FIG. 20D has the following features: The device includes a housing 7001, a display portion 7002, a support stand 7003, and the like.

[0195] 20E and 20F show an example of a portable touch panel. The touch panel 7300 is , a housing 7301, a display unit 7302, an operation button 7303, a drawer member 7304, and a control unit. The touch panel 7300 is wound in a roll shape in a cylindrical housing 7301. The touch panel 7300 is controlled by a control unit 7305. The video signal can be received by the video input unit 7302, and the received video can be displayed on the display unit 7302. In addition, the control unit 7305 is equipped with a battery. In addition, when a connector is connected to the control unit 7305, The video signal and power may be supplied directly from the outside via a wire. In addition, the operation button 7303 can be used to turn the power on and off, switch the image to be displayed, etc. This can be done.

[0196] FIG. 20F shows a touch panel in a state where the display unit 7302 is pulled out by the pull-out member 7304. In this state, an image can be displayed on the display portion 7302. The operation button 7303 arranged on the surface of the housing 7301 allows easy operation with one hand. Also, as shown in FIG. 20E, the operation button 7303 can be arranged on one side of the housing 7301 instead of in the center. By arranging the display unit 7302 to the side, it can be easily operated with one hand. When the display unit 7302 is removed, the display surface of the display unit 7302 is fixed to a flat surface. A frame for reinforcement may be provided on the side of the housing 7301. The video signal may be received together with the audio signal, and audio may be output based on the audio signal received together with the video signal.

[0197] 21A-21C show an example of the configuration of a foldable mobile information terminal 810. FIG. 21B shows the portable information terminal 810 in an unfolded or folded state. FIG. 21C shows the portable information terminal 810 in a folded state. The portable information terminal 810 is folded. In the folded state, the portable information terminal 810 is It is highly portable, and when unfolded, the seamless, wide display area provides excellent visibility of the display. do.

[0198] The display panel 816 is supported by eight housings 815 connected by hinges 818. The two housings 815 are bent via the hinge 818, so that the portable information terminal 81 The display panel can be reversibly transformed from the unfolded state to the folded state. For example, taps that can be bent with a radius of curvature of 1 mm to 150 mm can be used. A display panel with a touch panel can be provided. The display panel 816 can be folded or unfolded. A sensor may be provided to detect the state in which the sensor is in the closed state and supply detection information. The display panel 816 is folded. The part that is folded up and no longer visible to the user is stopped from operating. Such control may be performed. Specifically, the display may be stopped. In addition, the display panel 816 may be turned off. The information may be acquired and control may be performed to resume display or detection by the touch sensor.

[0199] 21D and 21E show a foldable mobile information terminal 820. FIG. 21E shows the portable information terminal 820 in a folded state with 822 facing outward. The portable information terminal 820 is shown in a folded state with the display unit 822 facing inward. When the information terminal 820 is not in use, the non-display section 825 is folded outward to hide the display section 82. The input / output device of one embodiment of the present invention can be used for the display portion 822. This can be done.

[0200] FIG. 21F is a perspective view illustrating the external shape of the portable information terminal 880. 21H is a perspective view illustrating the external shape of the mobile information terminal 840. .

[0201] The portable information terminals 880 and 840 are, for example, a telephone, a notebook, an information viewing device, or the like. Specifically, each of these devices can be used as a smartphone. The mobile information terminals 880 and 840 can display text and image information on multiple surfaces. For example, three operation buttons 889 can be displayed on one side (FIG. 21F, 21H). Also, information 887 shown in the dashed rectangle can be displayed on another surface (see FIG. 21H). 1G, FIG. 21H). An example of information 887 is SNS (Social Networking Notifications for the mobile phone service, notifications for incoming e-mails and phone calls, notifications for e-mails, etc. Subject of email, sender name, date, time, battery level, antenna reception strength Or, instead of the information 887, the operation Buttons 889, icons, etc. may be displayed.

[0202] 21F and 21G show an example in which information 887 is displayed on the upper side, but the present invention is not limited to this. For example, it may be displayed on the side as in the mobile information terminal 840 shown in FIG 21H. For example, the user of the portable information terminal 880 may store the portable information terminal 880 in a breast pocket of the clothing. In this state, the display (information 887 in this case) can be confirmed. The telephone number or name of the caller can be observed from above the mobile information terminal 880. The user can display the information without taking the mobile information terminal 880 out of his / her pocket. The user can check the status and decide whether to answer the call. In this example, information 855, information 856, and information 857 may be displayed on three or more screens. Here is an example of 857 displayed on different sides. [Explanation of symbols]

[0203] ADC_CM: Circuit, ANL: Wiring, BGE1: Electrode, BGE2: Electrode, BGE3: Electrode , C1: Capacitor element, CG1: Opening, CG3: Opening, DE1: Electrode, DE2: Electrode, DE3 : electrode, DE4: electrode, EL1: light emitting element, GC2: opening, GDL: circuit, GDR: circuit , GE1: electrode, GE2: electrode, GE3: electrode, GE4: electrode, GL: wiring, M1: transistor M10: transistor, M2: transistor, M3: transistor, ML: Line, MONI: circuit, MOUT: terminal, MS1: transistor, MS2: transistor, MS3: transistor, Msw1: transistor, Msw2: transistor, Msw3: Transistor, N1: node, N2: node, OS1: layer, OS2: layer, OS3: layer, O S4: layer, OUT: terminal, PIN: terminal, POUT: terminal, SE1: electrode, SE2: electrode , SE3: electrode, SE4: electrode, SL: wiring, SW3: switch, SW50: switch, SW51: Switch, SW52: Switch, SW53: Switch, SW54: Switch, TA1: transistor, TA2: transistor, TA3: transistor, TA4: transistor TA5: Transistor, TA6: Transistor, 10: Driver IC, 20: Circuit (SD), 21: Test circuit, 30: Analog-digital ADC, 31: logic circuit (LGC), 32: circuit, 33: switch circuit 34: pass transistor logic circuit (PTL), 35: logic circuit (LGC), 50: terminal, 51: terminal, 52: terminal, 60: terminal, 61: terminal, 62: terminal, 63: end child, 64: terminal, 65: terminal, 66: terminal, 67: terminal, 68: terminal, 69: terminal, 100: semiconductor device, 110: circuit, 111: circuit, 112: wiring, 113: output terminal, 120: logic circuit (LGC), 121: logic circuit (LGC), 123: switch circuit, 124: read circuit (READ), 130: pass transistor logic circuit (P TL), 131: pass transistor logic circuit (PTL), 132: pass transistor Logic circuit (PTL), 141: Demultiplexer (DEMUX), 142: Demultiplexer Demultiplexer (DEMUX), 143: Demultiplexer (DEMUX), 200: display device, 210: pixel unit, 211_B: pixel, 211_G: pixel, 211_R : pixel, 211: pixel, 215: power line, 220a: peripheral circuit, 220: peripheral circuit, 22 1: gate driver circuit, 222: source driver circuit, 223: monitor circuit, 224: Analog-to-digital conversion circuit (ADC), 230: CPU, 231: control circuit, 232: Power supply circuit, 233: image processing circuit, 234: memory, 250: display panel, 251: printer 252: Touch panel unit, 253: Battery, 255: FPC, 256 : FPC, 258-1: Upper cover, 258-2: Lower cover, 259: Frame, 26 0: Substrate, 261: Substrate, 262: Area, 263: IC, 301: counter circuit, 302: level shift circuit (LS), 311: DEMUX, 31 2_1:DEMUX, 312_2:DEMUX, 312:DEMUX, 313_1:DE MUX, 313: DEMUX, 321: Integrator, 322: Comparator, 323: Cau counter circuit, 324: circuit, 331: circuit, 350: operational amplifier, 351: capacitance element, 2: inverter, 353: latch circuit (LAT), 501: oxide semiconductor (OS) layer, 502: OS layer, 511: conductive layer, 512: conductive layer, 513: conductive layer, 521: conductive layer, 522: conductive layer, 523: conductive layer, 524: conductive layer, 531: conductive layer, 532: conductive layer, 533: conductive layer, 541: conductive layer, 542: conductive layer, 543: conductive layer, 544: conductive layer, 550: conductive layer, 551: conductive layer, 552: conductive layer, 553: EL layer, 555: light, 571: insulating layer, 572: insulating layer, 573: insulating layer, 57 4: insulating layer, 575: insulating layer, 576: insulating layer, 580: light-shielding layer, 581: color filter layer, 582: overcoat layer, 600: substrate, 621: insulating layer, 622: insulating layer, 6 23: insulating layer, 631: oxide semiconductor film, 632: oxide semiconductor film, 633: oxide semiconductor Body membrane, 650: substrate, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 660: conductive layer, 661: conductive layer, 662: conductive layer, 663: conductive layer, 664: conductive layer, 665: conductive layer, 666: conductive layer, 667: conductive layer, 668: conductive layer, 669: conductive layer, 671: substrate, 672: insulating layer, 673: insulating layer, 674: insulating layer, 675: insulating layer 680: semiconductor layer, 681: semiconductor layer, 682: channel region, 683: LDD region, 684: impurity region, 685: channel region, 686: impurity region, 810: portable information terminal end, 815: housing, 816: display panel, 818: hinge, 820: mobile information terminal, 82 2: display unit, 825: non-display unit, 840: portable information terminal, 845: portable information terminal, 855 : Information, 856: Information, 857: Information, 880: Mobile information terminal, 887: Information, 889: Operation buttons, 7000: display device, 7001: housing, 7002: display unit, 7003: support stand, 7100 : Portable information terminal, 7101: Housing, 7102: Display unit, 7103: Band, 7104: 7105: Operation button, 7106: Input / output terminal, 7107: Icon, 7201 : Stand, 7203: Operation switch, 7210: Lighting device, 7300: Touch panel, 73 01: Housing, 7302: Display unit, 7303: Operation buttons, 7304: Components, 7305: Control Control unit, 7400: mobile phone, 7401: housing, 7402: display unit, 7403: operation button , 7404: External connection port, 7405: Speaker, 7406: Microphone, < / ptl>

Claims

1. a pixel having a first transistor, a second transistor, a third transistor, and a light-emitting element; and first to third wirings electrically connected to the pixel; one of a source and a drain of the first transistor is electrically connected to the first wiring to which a data signal is input; the second transistor has a function of controlling a current flowing between the second wiring and the light-emitting element in accordance with a potential corresponding to the data signal input to a gate of the second transistor via the first transistor; one of a source and a drain of the third transistor is electrically connected to the third wiring; a light-emitting device in which the other of the source and the drain of the third transistor is electrically connected to a pixel electrode of the light-emitting element, a semiconductor film having a channel formation region of the third transistor; a first conductive film having a region in contact with the semiconductor film, a region disposed above the semiconductor film, and having a function as the third wiring; a second conductive film having a region in contact with the semiconductor film and disposed above the semiconductor film; a third conductive film having a region located above the semiconductor film and functioning as a gate of the third transistor; a first insulating film having a region disposed above the first conductive film, a region disposed above the second conductive film, and a region disposed above the third conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the first wiring; a fifth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the second wiring; a sixth conductive film having a region in contact with an upper surface of the first insulating film and electrically connected to the second conductive film; a second insulating film having a region disposed above the fourth conductive film, a region disposed above the fifth conductive film, and a region disposed above the sixth conductive film; the pixel electrode having a region disposed above the second insulating film and electrically connected to the sixth conductive film; a third insulating film having a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the third insulating film, the fourth conductive film overlaps with the third insulating film; the fifth conductive film overlaps with the first conductive film; Light emitting device.

2. a pixel having a first transistor, a second transistor, a third transistor, and a light-emitting element; and first to third wirings electrically connected to the pixel; one of a source and a drain of the first transistor is electrically connected to the first wiring to which a data signal is input; the second transistor has a function of controlling a current flowing between the second wiring and the light-emitting element in accordance with a potential corresponding to the data signal input to a gate of the second transistor via the first transistor; one of a source and a drain of the third transistor is electrically connected to the third wiring; a light-emitting device in which the other of the source and the drain of the third transistor is electrically connected to a pixel electrode of the light-emitting element, a semiconductor film having a channel formation region of the third transistor; a first conductive film having a region in contact with the semiconductor film, a region disposed above the semiconductor film, and having a function as the third wiring; a second conductive film having a region in contact with the semiconductor film and disposed above the semiconductor film; a third conductive film having a region located above the semiconductor film and functioning as a gate of the third transistor; a first insulating film having a region disposed above the first conductive film, a region disposed above the second conductive film, and a region disposed above the third conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the first wiring; a fifth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the second wiring; a sixth conductive film having a region in contact with an upper surface of the first insulating film and electrically connected to the second conductive film; a second insulating film having a region disposed above the fourth conductive film, a region disposed above the fifth conductive film, and a region disposed above the sixth conductive film; the pixel electrode having a region disposed above the second insulating film and electrically connected to the sixth conductive film; a third insulating film having a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the third insulating film, the fourth conductive film overlaps with the third insulating film; the fifth conductive film overlaps with the third conductive film; the fifth conductive film overlaps with the first conductive film; Light emitting device.

3. a pixel having a first transistor, a second transistor, a third transistor, and a light-emitting element; and first to third wirings electrically connected to the pixel; one of a source and a drain of the first transistor is electrically connected to the first wiring to which a data signal is input; the second transistor has a function of controlling a current flowing between the second wiring and the light-emitting element in accordance with a potential corresponding to the data signal input to a gate of the second transistor via the first transistor; one of a source and a drain of the third transistor is electrically connected to the third wiring; a light-emitting device in which the other of the source and the drain of the third transistor is electrically connected to a pixel electrode of the light-emitting element, a semiconductor film having a channel formation region of the third transistor; a first conductive film having a region in contact with the semiconductor film, a region disposed above the semiconductor film, and having a function as the third wiring; a second conductive film having a region in contact with the semiconductor film and disposed above the semiconductor film; a third conductive film having a region located above the semiconductor film and functioning as a gate of the third transistor; a first insulating film having a region disposed above the first conductive film, a region disposed above the second conductive film, and a region disposed above the third conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the first wiring; a fifth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the second wiring; a sixth conductive film having a region in contact with an upper surface of the first insulating film and electrically connected to the second conductive film; a second insulating film having a region disposed above the fourth conductive film, a region disposed above the fifth conductive film, and a region disposed above the sixth conductive film; the pixel electrode having a region disposed above the second insulating film and electrically connected to the sixth conductive film; a third insulating film having a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the third insulating film, the fourth conductive film overlaps with the third insulating film; the fifth conductive film overlaps with the pixel electrode, the fifth conductive film overlaps with the first conductive film; Light emitting device.

4. a pixel having a first transistor, a second transistor, a third transistor, and a light-emitting element; and first to third wirings electrically connected to the pixel; one of a source and a drain of the first transistor is electrically connected to the first wiring to which a data signal is input; the second transistor has a function of controlling a current flowing between the second wiring and the light-emitting element in accordance with a potential corresponding to the data signal input to a gate of the second transistor via the first transistor; one of a source and a drain of the third transistor is electrically connected to the third wiring; a light-emitting device in which the other of the source and the drain of the third transistor is electrically connected to a pixel electrode of the light-emitting element, a semiconductor film having a channel formation region of the third transistor; a first conductive film having a region in contact with the semiconductor film, a region disposed above the semiconductor film, and having a function as the third wiring; a second conductive film having a region in contact with the semiconductor film and disposed above the semiconductor film; a third conductive film having a region located above the semiconductor film and functioning as a gate of the third transistor; a first insulating film having a region disposed above the first conductive film, a region disposed above the second conductive film, and a region disposed above the third conductive film; a fourth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the first wiring; a fifth conductive film having a region in contact with an upper surface of the first insulating film and functioning as the second wiring; a sixth conductive film having a region in contact with an upper surface of the first insulating film and electrically connected to the second conductive film; a second insulating film having a region disposed above the fourth conductive film, a region disposed above the fifth conductive film, and a region disposed above the sixth conductive film; the pixel electrode having a region disposed above the second insulating film and electrically connected to the sixth conductive film; a third insulating film having a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the third insulating film, the fourth conductive film overlaps with the third insulating film; the fifth conductive film overlaps with the pixel electrode, the fifth conductive film overlaps with the third conductive film; the fifth conductive film overlaps with the first conductive film; Light emitting device.

Images