Semiconductor device

Abstract

To provide a semiconductor device having a power MOSFET, capable of improving a response characteristic of a detection element.SOLUTION: A semiconductor device according to an embodiment, comprises: a semiconductor chip that contains a first MOSFET that is formed in a first region of a semiconductor substrate, a detection element that is formed in a second region in the first region, a source electrode that is formed onto an upper side in the first region, and is electrically connected to the source of the first MOSFET; and a source electrode material that is arranged so as to cover the detection element, and is stitch-bonded to the source electrode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] There is known a detection element that protects a power MOSFET when an abnormal current (overcurrent) flows through the power MOSFET. Examples of the detection element include a current detection element including a sense MOSFET and a temperature detection element including a diode.

[0003] Patent Document 1 discloses a technique for arranging a detection element in a power MOSFET. In Patent Document 1, a metal plate overlapping a source electrode includes a source connection part connected to the source electrode and an extension part extending from the source connection part toward a source terminal arranged on a short side. The detection element is arranged so as to overlap with the extension part in a plan view. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-145219 A Summary of the Invention [Problem to be solved by the invention]

[0005] A power MOSFET is composed of multiple unit transistor cells arranged in a matrix, and a source electrode formed on the main surface of a semiconductor substrate and a drain electrode formed on the back surface are common to the multiple unit transistor cells. It is known that when an abnormal current (overcurrent) flows through a power MOSFET, the center of the semiconductor chip on which the power MOSFET is formed becomes hotter than the edges, that is, a temperature difference occurs between the center and edges of the semiconductor chip.

[0006] In Patent Document 1, the detection element is disposed on the edge of the semiconductor chip so as to overlap with an extension extending from the source electrode toward the source terminal. When the detection element is disposed on the edge in this manner, due to the above-mentioned temperature difference, it takes several hundred μs for the detection element to react to the heat caused by the overcurrent and perform a cutoff operation. In semiconductor devices equipped with power MOSFETs, it is desirable to improve the responsiveness of the detection element.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] The semiconductor device according to the present disclosure includes a semiconductor chip including a first MOSFET formed in a first region of a semiconductor substrate, a detection element formed in a second region within the first region, and a source electrode formed above the first region and electrically connected to a source of the first MOSFET, and a source electrode material arranged to cover the detection element and stitch-bonded to the source electrode. Effect of the Invention

[0009] The present disclosure can improve the responsiveness of a detection element of a semiconductor device including a power MOSFET. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view perspective view showing a configuration example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a main part of FIG. [Diagram 3] FIG. 3 is a photograph showing a cross section taken along line II-II in FIG. [Figure 4] FIG. 4 is a photograph showing a cross section taken along line II-II in FIG. [Diagram 5] FIG. 5 is a plan view perspective view showing a configuration example of the semiconductor device according to the second embodiment. [Figure 6]FIG. 6 is a diagram illustrating the temperature difference-Ids (Vds=constant) characteristics of the semiconductor device of FIG. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device in which a high-side configuration is adopted. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device in which a low-side configuration is adopted. [Figure 9] FIG. 9 is a plan perspective view of a semiconductor device of a comparative example. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the present disclosure should not be interpreted narrowly based on the description in the drawings. In addition, in each drawing, the same elements are given the same reference numerals, and duplicated explanations are omitted. Note that, for convenience of explanation, each drawing is not drawn to actual scale.

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. In addition, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more than or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0013] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, amounts, ranges, etc.).

[0014] In this disclosure, a field effect transistor is referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or simply as a MOS, which includes not only a case where an oxide film is used as a gate insulating film, but also a case where an insulating film other than an oxide film is used as a gate insulating film.

[0015] The embodiments relate to a semiconductor device applied to, for example, a power semiconductor device for driving loads such as a motor, a heater, and a lamp mounted on an automobile, and an industrial programmable logic controller, etc. Such semiconductor devices use power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors).

[0016] The semiconductor device of the embodiment is applied to, for example, a driving circuit having a high side configuration or a low side configuration. FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device 1 adopting a high side configuration. As shown in FIG. 7, the semiconductor device 1 includes an output transistor 3 and a body diode 4. The body diode 4 is provided between the source and drain of the output transistor 3. The output transistor 3 and a load 2 are connected in series in this order between a power supply terminal VBAT to which a power supply voltage is supplied and a ground terminal GND to which a ground voltage is supplied. The output transistor 3 is provided between the power supply terminal VBAT and the load 2. That is, the output transistor 3 is used as a high side switch.

[0017] Fig. 8 is a circuit diagram showing a configuration example of a semiconductor device 1 in which a low-side configuration is adopted. As shown in Fig. 8, the semiconductor device 1 includes an output transistor 3 and a body diode 4. The body diode 4 is provided between the source and drain of the output transistor 3. A load 2 and the output transistor 3 are connected in series in this order between a power supply terminal VBAT and a ground terminal GND. The output transistor 3 is provided between the load 2 and the ground terminal GND. That is, the output transistor 3 is used as a low-side switch.

[0018] These semiconductor devices are provided with a detection element that protects the power MOSFET when an abnormal current (overcurrent) flows through the power MOSFET. First, a comparative example of a semiconductor device having a power MOSFET in which a temperature detection element is provided as the detection element will be described.

[0019] Fig. 9 is a planar perspective view of a semiconductor device of a comparative example. Fig. 10 is a cross-sectional view taken along the line XX in Fig. 9. As shown in Figs. 9 and 10, the semiconductor device 1 of the comparative example mainly includes a semiconductor chip 10, a temperature detection element 11, and a metal plate 12. The semiconductor chip 10 is mounted on the main surface of a die pad 13 via an adhesive layer 14. A main MOS region (not shown) is provided in the center of the main surface of the semiconductor chip 10, and a temperature measuring diode region serving as the temperature detection element 11 is provided on the edge.

[0020] A metal plate 12 is connected to a source pad (first source electrode) (not shown) provided on the main MOS region via an adhesive layer 15. That is, in the example shown in FIG. 9, the clip-shaped metal plate 12 serves as a source electrode material connected to the source electrode of the power MOSFET. For example, solder or silver paste is used as the adhesive layers 14 and 15. When the metal plate 12 is used in this way, a bonding process is required to bond the metal plate 12 and the semiconductor chip 10 with the adhesive layer 15.

[0021] The metal plate 12 has a source connection portion 12a and an extension portion 12b, and the extension portion includes an overhang portion and a lead connection portion. The metal plate 12 and a source pad are connected at the source connection portion, and the metal plate 12 and a source terminal are connected at the lead connection portion. The overhang portion between the source connection portion and the lead connection portion is located on the temperature detection element 11 and covers the metal plate 12.

[0022] The semiconductor chip 10, the metal plate 12, and the die pad 13 are covered with a sealing body 18. The sealing body 18 is made of an insulating resin such as epoxy resin. The sealing body 18 is filled between the temperature detection element 11 on the semiconductor chip 10 and the overhanging portion of the metal plate 12, and the two are electrically isolated from each other by the insulating resin.

[0023] As shown in Figs. 9 and 10, the temperature detection element 11 is provided at the edge of the semiconductor chip 10. A temperature difference occurs between point A (the center of the semiconductor chip 10) and point B (the edge of the semiconductor chip 10) shown in Fig. 10, so it takes several hundred microseconds for the detection element to react to the heat caused by the overcurrent and perform a cutoff operation. In a semiconductor device equipped with a power MOSFET, it is desired to improve the responsiveness of the detection element. In addition, when the temperature detection element 11 is provided at the center of the semiconductor chip 10, an insulating material needs to be provided between the metal plate 12 and the temperature detection element 11 to prevent a short circuit between them, which increases the manufacturing process. Therefore, the present inventor has devised the following configuration to solve these problems.

[0024] Embodiment 1. Fig. 1 is a plan view perspective view showing a configuration example of a semiconductor device 1 according to embodiment 1. As shown in Fig. 1, the semiconductor device 1 is a small outline package (SOP) type semiconductor package. As shown in Fig. 1, the semiconductor device 1 mainly includes a semiconductor chip 10, a temperature detection element 11, and a ribbon wire 20.

[0025] The semiconductor chip 10 includes a main MOS region in which a power MOSFET is formed, and a temperature measuring diode region in which a temperature detection element 11 is formed. The power MOSFET is a transistor for switching. As described in FIGS. 7 and 8, when an on-voltage is applied to the gate of the power MOSFET to turn the power MOSFET on, a current flows through the power MOSFET and the load 2 connected in series between the power supply terminal VBAT and the ground potential GND. On the other hand, when an off-voltage is applied to the gate of the power MOSFET to turn the power MOSFET off, it is possible to prevent a current from flowing through the power MOSFET and the load 2 connected in series.

[0026] The semiconductor chip 10 also includes a source pad SP and a gate pad GP. The semiconductor device 1 is provided with a plurality of terminals that serve as external terminals. The plurality of terminals are electrically connected to the semiconductor chip 10. The plurality of terminals include a gate terminal GT, a source terminal ST, and a drain terminal DT. The plurality of terminals are formed of leads made of, for example, a copper plate or a 42 alloy plate with a film thickness of about 250 μm, processed into a desired shape. The source terminal ST is a terminal for supplying a current to the load 2, as shown in FIGS. 7 and 8.

[0027] 1, a plurality of drain terminals DT connected to the drains of the power MOSFETs are arranged on the upper side of the semiconductor device 1. A plurality of source terminals ST connected to the sources of the power MOSFETs are arranged on the left side of the lower side of the semiconductor device 1, which faces the upper side on which the drain terminals DT are provided. A gate terminal GT connected to the gates of the power MOSFETs is arranged on the right side of the lower side on which the source terminals ST are formed.

[0028] The die pad DP and the plurality of drain terminals DT are integrally formed. The semiconductor chip 10 is mounted on the die pad DP via an adhesive layer 14. The gate terminal GT and the gate pad GP are connected by a wire 16. The wire 16 is made of, for example, a copper wire or a gold wire having a diameter of 30 to 50 μm. Note that, instead of the wire 16, it is also possible to use a metallic ribbon wire or the like that is wider than the wire 16. The gate terminal GT is electrically connected to a drive circuit (not shown). The drive circuit controls the potential of the gate of the power MOSFET to control the operation of the power MOSFET.

[0029] A ribbon wire 20 is used as the source electrode material. The ribbon wire 20 is, for example, a strip-shaped electrode material made of flexible aluminum foil with a thickness of about 150 to 250 μm. The ribbon wire 20 is located on the source pad SP of the semiconductor chip 10. The ribbon wire 20 electrically connects the source pad SP and the source terminal ST.

[0030] The ribbon wire 20 is connected to the source terminal ST and the source pad SP by wire bonding. In wire bonding, the tip of the ribbon wire 20 held by a bonding tool (not shown) is connected to the center (first bonding point) of the source pad SP of the semiconductor device 1. The ribbon wire 20 is then routed and its middle part is connected to the end (second bonding point) of the source pad SP. The ribbon wire 20 is further routed and its middle part is connected to the source terminal ST (third bonding point). The ribbon wire 20 is cut near the connection part of the source terminal ST, thereby completing one strand of wire bonding.

[0031] The ribbon wire 20 is connected to the source pad SP or the source terminal ST by stitch bonding. Specifically, while pressing the ribbon wire 20 against the source pad SP, ultrasonic vibration is applied. As a result, the ribbon wire 20 is bonded to the source pad SP, and a stitch bond is formed. In this manner, in the embodiment, the ribbon wire 20 is bonded to the source pad SP and the source terminal ST by the ultrasonic bonding method, and a bonding process using solder or the like is not required. The stitch bond formed at the first bonding point is called the first stitch bond 21a, the stitch bond formed at the second bonding point is called the second stitch bond 21b, and the stitch bond formed at the first bonding point is called the third stitch bond 21c.

[0032] The ribbon wire 20 between the first stitch junction 21a and the second stitch junction 21b is not joined to the source pad SP, and a space exists between the ribbon wire 20 and the source pad SP. The ribbon wire 20 in this space is called a first overhang portion 22a. The ribbon wire 20 between the second stitch junction 21b and the third stitch junction 21c is not joined to the die pad DP, etc., and a space exists between the ribbon wire 20 and the die pad DP, etc. The ribbon wire 20 in this space is called a second overhang portion 22b. That is, the ribbon wire 20 includes the first stitch junction 21a, the second stitch junction 21b, the third stitch junction 21c, the first overhang portion 22a, and the second overhang portion 22b.

[0033] The region facing the first overhang portion 22a of the semiconductor chip 10 is a temperature detection diode region in which the temperature detection element 11 is provided. The temperature detection element 11 is a temperature detection diode in which a plurality of diodes are connected in series. Here, the temperature detection element 11 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view of a main part in which the temperature detection element 11 of Fig. 1 is formed.

[0034] In the example shown in Fig. 2, a so-called epitaxial wafer is used as the semiconductor substrate. The semiconductor substrate is, for example, an n-type semiconductor substrate having n-type impurities such as arsenic (As) introduced therein.+ A substrate body 30 made of, for example, n-type single crystal silicon, and a semiconductor layer formed on the main surface of the substrate body 30. - The semiconductor substrate SB is constituted by an epitaxial semiconductor layer 31 made of n-type single crystal silicon. Note that the semiconductor substrate SB may be n-type single crystal silicon doped with an n-type impurity such as arsenic (As).

[0035] The power MOSFET (not shown) and the temperature detection element 11 are formed on a semiconductor substrate. A main MOS region, which is a region in which the power MOSFET is formed, is disposed in the center of the main surface of the semiconductor substrate. Furthermore, in the main MOS region, a temperature measuring diode region, which is a region in which the temperature detection element 11 is formed, is disposed in a position facing the first overhang portion 22a.

[0036] Although not shown here, in the main MOS region, a plurality of unit transistor cells constituting a power MOSFET are formed on the semiconductor substrate. The power MOSFET is formed by connecting a plurality of unit transistor cells provided in the main MOS region in parallel. The semiconductor substrate functions as a drain region of the unit transistor cells in the main MOS region. A back electrode 32 for drain is formed on the back surface of the substrate body 30 (i.e., the back surface of the semiconductor chip 10). The back electrode 32 is formed, for example, by stacking a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer in this order from the back surface of the substrate body 30. The back electrode 32 is connected to the die pad DP and the drain terminal DT in FIG. 1.

[0037] As shown in Fig. 2, a temperature detection element 11 is formed in the temperature detection diode region, in which a plurality of diodes 110 are connected in series. The diodes 110 are, for example, formed of a polysilicon layer having a PN junction. An anode 111 containing p-type impurities and a cathode 112 containing n-type impurities are formed in the polysilicon layer. The plurality of diodes 110 are connected to each other by diode connection wiring 113.

[0038] The plurality of diodes 110 connected in series are connected to an anode electrode and a cathode electrode via anode wiring and cathode wiring (not shown), respectively. The plurality of diodes 110, diode connection wiring 113, etc. are covered with a protective film 17 made of polyimide resin. Note that the protective film 17 has openings that expose parts of the anode electrode and the cathode electrode, respectively, and an anode pad and a cathode pad are formed therein.

[0039] Thus, in the first embodiment, the temperature detection element 11 is formed in the main MOS region in which the power MOSFET is formed at the center of the semiconductor chip 10. The temperature detection element 11 is covered with the ribbon wire 20 that is stitch-bonded. The ribbon wire 20 is stitch-bonded at least at the first stitch junction 21a and the second stitch junction 21b. The temperature detection element 11 is disposed under the first overhang portion 22a between the first stitch junction 21a and the second stitch junction 21b. That is, the temperature detection element 11 is inserted in the space between the first overhang portion 22a between the first stitch junction 21a and the second stitch junction 21b and the source pad SP.

[0040] Fig. 3 is a photograph showing a cross section taken along the II-II cutting line in Fig. 1. Fig. 3 is a photograph of the cross section of the semiconductor device 1 taken along the II-II cutting line from the right side in Fig. 1. As shown in Fig. 3, a space 23 exists between the first overhang portion 22a and the semiconductor chip 10.

[0041] 3, heat generated in the semiconductor chip 10 is conducted directly to the temperature detection element 11 and also through the ribbon wire 20. This allows the heat generated in the semiconductor chip 10 to be transferred to the temperature detection element 11 more quickly, improving thermal response. By improving thermal response in this way, a cutoff operation can be initiated quickly when an overpower state occurs due to a load short circuit or the like, protecting the element and improving the destruction resistance of the product.

[0042] Although not shown in FIG. 1, the semiconductor device 1 further includes a sealing body that seals the semiconductor chip 10, the die pad DP, the multiple terminals, the ribbon wire 20, and the wire 16. The sealing body is made of an insulating resin such as epoxy resin. FIG. 4 is a photograph showing a cross section taken along the II-II cutting line in FIG. 1. FIG. 4 is a photograph of the cross section of the semiconductor device 1 taken along the II-II cutting line from the left side in FIG. 1. As shown in FIG. 4, the space 23 between the first overhang portion 22a and the semiconductor chip 10 is filled with the sealing body 18. As a result, the two are electrically isolated by the sealing body 18.

[0043] In order to supply heat from first overhang portion 22a to temperature detection element 11, it is sufficient that first overhang portion 22a overlaps at least a part of temperature detection element 11 in a plan view. It is preferable that first overhang portion 22a overlaps with the entire area of ​​temperature detection element 11.

[0044] Embodiment 2. Fig. 5 is a planar perspective view showing a configuration example of a semiconductor device 1 according to embodiment 2. Note that the source terminal ST, the gate terminal GT, the drain terminal DT, etc. are omitted in Fig. 2. In Fig. 5, the same components as those in Fig. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0045] In the second embodiment, a sense MOS 19 is formed instead of the temperature detection element 11. That is, the semiconductor chip 10 includes a main MOS region in which a power MOSFET is formed, and a sense MOS region in which a sense MOSFET, which is a current detection element for detecting a current flowing through the power MOSFET, is formed. The sense MOS 19 is formed in the main MOS region in the center of the semiconductor chip 10 in which the power MOSFET is formed.

[0046] In the sense MOS region, a semiconductor substrate is formed with a plurality of unit transistor cells constituting a sense MOSFET, which is a current detection element. The sense MOSFET is formed by connecting the plurality of unit transistor cells provided in the sense MOS region in parallel.

[0047] Each unit transistor cell formed in the main MOS region and each unit transistor cell formed in the sense MOS region basically have the same structure (configuration), however, the main MOS region and the sense MOS region have different areas, the main MOS region being larger than the sense MOS region.

[0048] For this reason, the number of connected unit transistor cells differs between the power MOSFET and the sense MOSFET. The number of unit transistor cells connected in parallel that make up the sense MOSFET is smaller than the number of unit transistor cells connected in parallel that make up the power MOSFET. For this reason, if the source potentials of the sense MOSFET and the power MOSFET are the same, a smaller current flows through the sense MOSFET than through the power MOSFET.

[0049] Each unit transistor cell in the main MOS region and the sense MOS region is formed of, for example, an n-channel MOSFET with a trench gate structure. In the second embodiment, the power MOSFET and the sense MOSFET are controlled to be turned on and off by supplying a gate voltage to the gate terminal GT.

[0050] The sense MOSFET is a field effect transistor for detecting the current flowing through the power MOSFET. The current flowing through the power MOSFET can be indirectly detected by the sense MOSFET. The sense MOSFET is formed in the semiconductor chip 10 so as to form a current mirror circuit together with the power MOSFET.

[0051] The sense MOSFET has a size that is, for example, 1 / n (n is any integer) of that of the power MOSFET. This size ratio can be changed as necessary. When the source voltage of the sense MOSFET and the source voltage of the power MOSFET are equal, a current that is 1 / n of the current flowing through the power MOSFET flows through the sense MOSFET due to the current mirror configuration described above. In other words, if the size ratio between the power MOSFET and the sense MOSFET is known, the current flowing through the power MOSFET can be found by monitoring the current flowing through the sense MOSFET.

[0052] The sense MOSFET shares its drain and gate with the power MOSFET. That is, the drains of the sense MOSFET and the power MOSFET are electrically connected to each other. This common drain is connected to the drain terminal DT, and the same potential is supplied to the drain of the sense MOSFET and the drain of the power MOSFET. In addition, the gates of the sense MOSFET and the power MOSFET are electrically connected to each other and shared. This common gate is connected to the gate terminal GT, and the same gate voltage is input to the gate of the sense MOSFET and the gate of the power MOSFET.

[0053] On the other hand, the source of the sense MOSFET is not common to the source of the power MOSFET. The source pad SP (first source electrode) of the power MOSFET is connected to a source terminal ST, and the load 2 is connected to the source terminal ST. In contrast, the source electrode (second source electrode) of the sense MOSFET is connected to a source terminal different from the source terminal ST.

[0054] Fig. 6 is a diagram for explaining the temperature difference-Ids (Vds=constant) characteristics of the semiconductor device in Fig. 5. In Fig. 6, the horizontal axis indicates the temperature difference between the power MOSFET and the sense MOSFET, and the vertical axis indicates Ids. Ids (power MOSFET) indicates the current flowing in the power MOSFET. Ids (sense MOSFET) indicates the current flowing in the sense MOSFET. Vds indicates the drain-source potential of the sense MOSFET and power MOSFET.

[0055] Theoretically, the current Ids (power MOSFET) flowing through the power MOSFET is equal to n×the current Ids (sense MOSFET) flowing through the sense MOSFET.

[0056] For example, if the sense MOSFET 19 is provided at the edge of the semiconductor chip 10 where the temperature detection element 11 is arranged in Figures 9 and 10, the temperature of the sense MOSFET will be lower than that of the power MOSFET. As shown in Figure 6, the temperature difference between the power MOSFET and the sense MOSFET becomes large, so that ΔIds, which is Ids (power MOSFET) and n × Ids (sense MOSFET), becomes large, making it impossible to detect current accurately (see temperature difference (large) in Figure 6).

[0057] In contrast, in the second embodiment, the sense MOS 19 is covered with a ribbon wire 20 that is stitch-bonded. The ribbon wire 20 is stitch-bonded at least at the first stitch junction 21a and the second stitch junction 21b. The sense MOS 19 is disposed under the first overhang portion 22a between the first stitch junction 21a and the second stitch junction 21b. In other words, the sense MOS 19 is embedded in the space between the first overhang portion 22a between the first stitch junction 21a and the second stitch junction 21b and the source pad SP.

[0058] With the above configuration, the heat generated in the semiconductor chip 10 is directly conducted to the sense MOSFET 19, and is also conducted from the ribbon wire 20. This makes it possible to reduce the difference in temperature between the sense MOSFET and the power MOSFET, thereby reducing ΔIds and enabling accurate current detection (see temperature difference (small) in FIG. 6).

[0059] Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications are possible without departing from the gist of the invention. For example, instead of the above-mentioned SOP-type package, it is also possible to use an LGA (Land Grid Array) package in which a semiconductor chip is mounted on the main surface side of a glass epoxy board or a build-up board, and lands are arranged in a matrix on the back side of the board. [Explanation of symbols]

[0060] 1 Semiconductor device 2. Load 3 Output transistor 4 Body Diode 10. Semiconductor Chips 11 Temperature detection element 12 metal plate 13 Die pad 14 Adhesive layer 15 Adhesive layer 16 Wire 17 Protective film 18 Sealing body 19 Sense MOS 20 Ribbon Wire 21a First stitch joint 21b Second stitch joint 21c 3rd stitch joint 22a First Overhang 22b 2nd overhang section 23 Space 30 Board body 31 Epitaxial semiconductor layer 32 Back electrode 110 Diode 111 Anode 112 Cathode 113 Diode connection wiring VBAT power supply terminal GND Ground terminal ST Source terminal SP Source Pad GT Gate terminal GP Gate Pad DT Drain terminal DP die pad

Claims

1. a semiconductor chip including: a first MOSFET formed in a first region of a semiconductor substrate; a detection element formed in a second region within the first region; and a source electrode formed above the first region and electrically connected to a source of the first MOSFET; a source electrode material disposed to cover the detection element and stitch-bonded to the source electrode; Equipped with Semiconductor device.

2. the source electrode material is stitch bonded at least at a first joint and a second joint; The detection element is disposed below the source electrode material between a first joint and a second joint. The semiconductor device according to claim 1 .

3. The source electrode material is a ribbon wire made of aluminum. The semiconductor device according to claim 1 .

4. the detection element is a temperature detection element, The temperature detection element includes a plurality of diodes connected in series. The semiconductor device according to claim 1 .

5. the detection element is a current detection element, 2. The semiconductor device according to claim 1, wherein said current detection element includes a second MOSFET and a second source electrode electrically connected to a source of said second MOSFET.

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