Wiring board, semiconductor device, and manufacturing method of wiring board

Abstract

To improve the connection reliability and the transmission characteristic in wiring of a wiring board internal part.SOLUTION: A wiring board 100 includes: a core substrate 110; a first wiring structure body 120; a second wiring structure body 130; and a penetration hole 171. The core substrate 110 comprises a wiring layer 112 formed on an upper surface and a lower surface of a base material 111. The first wiring structure body 120 comprises a wiring layer 122 and an insulation layer 121 that are laminated on the upper surface of the core substrate 110. The second wiring structure body 130 comprises a wiring layer 132 and an insulation layer 131 that are laminated on a lower surface of the core substrate 110. The penetration hole 171 penetrates an insulation layer 131 of the second wiring structure body 130 and the base material 111 of the core substrate 110 to a pad 114 contained in the wiring layer 112 of the core substrate 110, or penetrates the insulation layer 131 of the second wiring structure body 130, the base material 111 of the core substrate 110, and the insulation layer 121 of the first wiring structure body 120 to a pad 124 contained in the wiring layer 122 of the first wiring structure body 120.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, for example, a wiring board on which a semiconductor chip is mounted has a multilayer wiring structure formed by using a semi-additive method. Specifically, a wiring layer is formed on an insulating layer by electroless plating and electrolytic plating, and an insulating layer is further formed to cover the wiring layer. In this way, a wiring board having a multilayer wiring structure is formed by repeatedly stacking insulating layers and wiring layers.

[0003] In such a wiring board, vias are provided through the insulating layers as necessary to electrically connect pads included in adjacent wiring layers, thereby forming wiring within the wiring board having a multilayer wiring structure by the pads and vias of each wiring layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-165329 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned wiring board, as the number of insulating layers and wiring layers increases, the number of points where the pads included in adjacent wiring layers are connected by vias increases, which causes a problem that the connection reliability of the wiring formed inside the wiring board decreases. Specifically, since stress due to, for example, thermal shock is likely to occur at the interface between the pads and vias of each wiring layer, peeling is likely to occur at the interface between the pads and vias of each wiring layer as the number of connection points between pads by vias increases. As a result, the connection reliability of the wiring formed inside the wiring board by the pads and vias of each wiring layer decreases.

[0006] In addition, as the number of insulating layers and wiring layers increases, the number of pads and vias also increases, which causes a problem of degraded transmission characteristics. Specifically, the connection between the pads and vias has a discontinuous conductor structure, and impedance mismatch increases at the discontinuous parts. In addition, the parasitic capacitance between the pads and the ground pattern also increases. This degrades the transmission characteristics of the wiring formed inside the wiring board.

[0007] The disclosed technology has been made in consideration of the above, and aims to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can improve the connection reliability and transmission characteristics of wiring inside the wiring board. [Means for solving the problem]

[0008] In one embodiment, the wiring board disclosed in the present application has a core substrate, a first wiring structure, a second wiring structure, and a through hole. The core substrate includes a wiring layer formed on an upper surface and a lower surface of a substrate. The first wiring structure includes a wiring layer and an insulating layer laminated on an upper surface of the core substrate. The second wiring structure includes a wiring layer and an insulating layer laminated on a lower surface of the core substrate. The through hole penetrates the insulating layer of the second wiring structure and the substrate of the core substrate to a pad included in the wiring layer of the core substrate, or penetrates the insulating layer of the second wiring structure, the substrate of the core substrate, and the insulating layer of the first wiring structure to a pad included in the wiring layer of the first wiring structure. Effect of the Invention

[0009] According to one aspect of the wiring board disclosed in the present application, it is possible to improve the connection reliability and transmission characteristics of the wiring inside the wiring board. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a configuration of a wiring board according to an embodiment. [Diagram 2] FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a diagram showing a specific example of a core substrate forming step. [Figure 4] FIG. 4 is a diagram showing a specific example of the build-up process. [Diagram 5] FIG. 5 is a diagram showing a specific example of the solder resist layer forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of a terminal forming step. [Figure 7] FIG. 7 is a diagram showing a specific example of the through-hole forming step. [Figure 8] FIG. 8 is a diagram showing a specific example of a semiconductor chip mounting process. [Figure 9] FIG. 9 is a diagram showing a specific example of the mounting process. [Figure 10] FIG. 10 is a diagram showing a configuration of a wiring board according to a first modified example of the embodiment. [Figure 11] FIG. 11 is a diagram showing a configuration example of a semiconductor device having the wiring board of FIG. [Figure 12] FIG. 12 is a diagram showing a configuration of a wiring board according to a second modification of the embodiment. [Figure 13] FIG. 13 is a diagram showing a configuration example of a semiconductor device having the wiring board of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of a wiring board, a semiconductor device, and a method for manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited to the embodiments.

[0012] (Embodiment) Fig. 1 is a diagram showing a configuration of a wiring board 100 according to an embodiment. Fig. 1 shows a schematic cross section of the wiring board 100. The wiring board 100 shown in Fig. 1 can be used, for example, as a substrate for a semiconductor device on which a semiconductor chip is mounted.

[0013] Wiring board 100 has a layered structure, and includes core substrate 110, wiring structures 120 and 130, and solder resist layers 140 and 150. In the following description, solder resist layer 150 is the bottom layer and solder resist layer 140 is the top layer as shown in Fig. 1, but wiring board 100 may be used, for example, upside down, or in any position.

[0014] Core substrate 110 has wiring layers 112 formed by plating on the upper and lower surfaces of base material 111, which is a plate-like insulator. The upper and lower wiring layers 112 are connected by vias 113 as necessary.

[0015] The wiring layer 112 on the upper surface is formed with pads 114 which serve as contact terminals that come into contact with electrode pins on a mounting board when the wiring board 100 is mounted on the mounting board, such as a motherboard.

[0016] The wiring structure 120 is formed on the upper surface of the core substrate 110, and is formed by laminating layers including an insulating layer 121 and a conductive wiring layer 122. In FIG. 1, two layers are laminated in the wiring structure 120, but the number of laminated layers may be one layer or three or more layers. The insulating layer 121 is formed using an insulating resin such as an epoxy resin or a polyimide resin. The wiring layer 122 is formed using a metal such as copper. The wiring layers 122 are connected by vias 123.

[0017] In the wiring layer 122 of a predetermined layer, pads 124 are formed which serve as contact terminals that come into contact with electrode pins on a mounting board when the wiring board 100 is mounted on the mounting board, such as a motherboard.

[0018] The wiring structure 130 is formed on the lower surface of the core substrate 110, and is formed by laminating layers including an insulating layer 131 and a conductive wiring layer 132. In FIG. 1, two layers are laminated in the wiring structure 130, but the number of laminated layers may be one layer or three or more layers. The insulating layer 131 is formed using an insulating resin such as an epoxy resin or a polyimide resin. The wiring layer 132 is formed using a metal such as copper. The wiring layers 132 are connected by vias 133.

[0019] The bottom wiring layer 132 has pads 134 formed thereon, which serve as contact terminals that come into contact with electrode pins on a mounting board, such as a motherboard, when the wiring board 100 is mounted on the mounting board.

[0020] Solder resist layer 140 is a layer that covers wiring layer 122 on the surface of wiring structure 120 and protects the wiring. Solder resist layer 140 is a layer made of an insulating photosensitive resin such as an acrylic resin or a polyimide resin, and is one of the insulating layers. Solder resist layer 140 may be formed using an insulating non-photosensitive resin such as an epoxy resin. Solder resist layer 140 and wiring structure 120 are an example of a first wiring structure.

[0021] The solder resist layer 140 side of the wiring board 100 is the surface on which electronic components such as semiconductor chips are mounted. At the positions where the semiconductor chips are to be mounted, openings 141 are formed in the solder resist layer 140. When the solder resist layer 140 is made of a photosensitive resin, the openings 141 can be formed by exposure and development. When the solder resist layer 140 is made of a non-photosensitive resin, the openings 141 can be formed by laser processing. Then, in the openings 141, connection terminals 160 are formed for connecting the wiring layer 122 of the wiring structure 120 and the electrodes of the semiconductor chip.

[0022] Solder resist layer 150 is a layer that covers wiring layer 132 on the surface of wiring structure 130 and protects the wiring. Solder resist layer 150 is a layer made of an insulating photosensitive resin such as an acrylic resin or a polyimide resin, and is one of the insulating layers. Solder resist layer 150 may be formed using an insulating non-photosensitive resin such as an epoxy resin. Solder resist layer 150 and wiring structure 130 are an example of a second wiring structure.

[0023] The solder resist layer 150 side of the wiring board 100 is the surface to be mounted on the mounting board. At the position to be mounted on the mounting board, an opening 151 is formed in the solder resist layer 150, and a pad 134 serving as a contact terminal to come into contact with an electrode pin on the mounting board is exposed from the opening 151.

[0024] Through holes 171 are formed in the solder resist layer 150, the insulating layer 131 of the wiring structure 130, and the base material 111 of the core substrate 110. The through holes 171 penetrate to pads 114 included in the wiring layer 112 on the upper surface of the core substrate 110, and the pads 114 are exposed at the bottom surface of the through holes 171. Further, through holes 172 are formed in the solder resist layer 150, the insulating layer 131 of the wiring structure 130, the base material 111 of the core substrate 110, and the insulating layer 121 of the wiring structure 120. The through holes 172 penetrate to pads 124 included in the wiring layer 122 of a predetermined layer of the wiring structure 120, and the pads 124 are exposed at the bottom surface of the through holes 172.

[0025] In this manner, in the embodiment, the through-hole 171 exposing the pad 114 that serves as a contact terminal with the electrode pin on the mounting substrate is formed in the solder resist layer 150, the wiring structure 130, and the core substrate 110, so that other pads and vias are not arranged below the pad 114. Also, the through-hole 172 exposing the pad 124 that serves as a contact terminal with the electrode pin on the mounting substrate is formed in the solder resist layer 150, the wiring structure 130, the core substrate 110, and the wiring structure 120, so that other pads and vias are not arranged below the pad 124. This makes it possible to reduce the number of connections between pads by vias inside the wiring substrate 100. As a result, it is possible to suppress the occurrence of peeling at the interface between the pad and the via that form the wiring inside the wiring substrate 100, and to reduce discontinuous conductor structures, so that it is possible to improve the connection reliability and transmission characteristics of the wiring inside the wiring substrate 100.

[0026] In the embodiment, pads 114 and 124 are signal pads that transmit signals having a transmission speed faster than that of a signal transmitted to pad 134 included in the lowest wiring layer 132 of wiring structure 130. This makes it possible to increase the speed of signals transmitted using pads 114 and 124.

[0027] Next, a method for manufacturing a semiconductor device having the wiring substrate 100 configured as described above will be described with a specific example with reference to Fig. 2. Fig. 2 is a flow chart showing the method for manufacturing a semiconductor device according to an embodiment.

[0028] First, a core substrate 110 that serves as a support member for wiring substrate 100 is formed (step S101). Specifically, as shown in Fig. 3, vias 113 that penetrate substrate 111, which is a plate-shaped insulator, are formed, and wiring layers 112 made of metal such as copper are formed on the upper and lower surfaces of substrate 111 by, for example, copper foil or copper plating. Fig. 3 is a diagram showing a specific example of the core substrate formation step.

[0029] The wiring layers 112 on the upper and lower surfaces of the substrate 111 are connected by vias 113 formed by plating with a metal such as copper, as necessary. As the substrate 111, for example, a reinforcing material such as a woven glass fabric impregnated with an insulating resin such as an epoxy resin can be used. As the reinforcing material, in addition to the woven glass fabric, a nonwoven glass fabric, an aramid woven fabric, or an aramid nonwoven fabric can be used. As the insulating resin, in addition to the epoxy resin, a polyimide resin, a cyanate resin, or the like can be used. In the wiring layer 112 on the upper surface of the substrate 111, a pad 114 is formed at a position where a through hole 171 is to be formed. Note that, on the lower surface of the substrate 111, the wiring layer 112 is not disposed at a position where the through hole 171 is to be formed. Also, on the upper and lower surfaces of the substrate 111, the wiring layer 112 is not disposed at a position where the through hole 172 is to be formed.

[0030] Then, wiring structures 120, 130 are formed on the upper and lower surfaces of core substrate 110 by a build-up method (step S102). Specifically, as shown in FIG. 4, for example, a layer having insulating layer 121 and wiring layer 122 is laminated on the upper surface of core substrate 110 to form wiring structure 120. Also, a layer having insulating layer 131 and wiring layer 132 is laminated on the lower surface of core substrate 110 to form wiring structure 130. FIG. 4 is a diagram showing a specific example of the build-up process. Insulating layers 121, 131 are formed using insulating resin such as epoxy resin or polyimide resin. Also, wiring layers 122, 132 are formed by plating a metal such as copper.

[0031] Between the wiring layer 112 and the wiring layer 122 on the upper surface of the core substrate 110, or between the wiring layers 122 of adjacent layers, a via 123 formed by plating with a metal such as copper is connected as necessary. Between the wiring layer 112 and the wiring layer 132 on the lower surface of the core substrate 110, or between the wiring layers 132 of adjacent layers, a via 133 formed by plating with a metal such as copper is connected as necessary. The insulating layer 121 and the wiring layer 122 may be laminated in multiple layers on the upper surface of the core substrate 110, and the insulating layer 131 and the wiring layer 132 may be laminated in multiple layers on the lower surface of the core substrate 110. In the wiring layer 122 of a predetermined layer, a pad 124 is formed at a position where the through hole 172 is to be formed. In the wiring layer 132 of the lowest layer, a pad 134 is formed. In the wiring structure 130, the wiring layer 132 is not disposed at a position where the through hole 171 is to be formed. Furthermore, in wiring structures 120, 130, wiring layers 122, 132 are not disposed at positions where through holes 172 are to be formed.

[0032] When wiring structures 120, 130 are formed, outermost wiring layers 122, 132 of wiring structures 120, 130 are covered with solder resist layers 140, 150 (step S103). For example, the topmost wiring layer 122 of wiring structure 120 is covered with solder resist layer 140, and the bottommost wiring layer 132 of wiring structure 130 is covered with solder resist layer 150.

[0033] 5, for example, openings 141 are formed in solder resist layer 140 on the side on which the semiconductor chip is to be mounted, at positions where connection terminals to the semiconductor chip are to be provided. The uppermost wiring layer 122 of wiring structure 120 is exposed at the bottom surface of openings 141. Meanwhile, openings 151 are formed in solder resist layer 150 on the side to be mounted on a mounting board. Pads 134 included in the lowermost wiring layer 132 of wiring structure 130 are exposed at the bottom surface of openings 151. FIG. 5 is a diagram showing a specific example of the solder resist layer formation step.

[0034] When a photosensitive resin is used as the solder resist layers 140, 150, the openings 141, 151 can be formed by exposure and development. When a non-photosensitive resin is used as the solder resist layers 140, 150, the openings 141, 151 can be formed by laser processing.

[0035] Then, connection terminals for connecting a semiconductor chip are formed in the openings 141 of the solder resist layer 140 (step S104). That is, as shown in Fig. 6, for example, connection terminals 160 are formed in the openings 141 by, for example, copper plating. Fig. 6 is a diagram showing a specific example of the terminal formation step.

[0036] Next, through holes 171 are formed in the solder resist layer 150, the wiring structure 130, and the core substrate 110, and through holes 172 are formed in the solder resist layer 150, the wiring structure 130, the core substrate 110, and the wiring structure 120 (step S105). Specifically, as shown in FIG. 7, the solder resist layer 150, the insulating layer 131 of the wiring structure 130, and the base material 111 of the core substrate 110 are cut out to the pads 114 included in the wiring layer 112 on the upper surface of the core substrate 110, to form the through holes 171. Also, the solder resist layer 150, the insulating layer 131 of the wiring structure 130, the base material 111 of the core substrate 110, and the insulating layer 121 of the wiring structure 120 are cut out to the pads 124 included in the wiring layer 122 of a predetermined layer of the wiring structure 120, to form the through holes 172. FIG. 7 is a diagram showing a specific example of the through hole forming step. The through holes 171 and 172 are formed by, for example, drilling. A contact sensor capable of detecting electrical contact with metal is used for drilling, and the timing at which the tip of the drill comes into contact with the pads 114, 124 is detected to stop the drilling.

[0037] The formation of through holes 171 and 172 completes wiring board 100. Then, a semiconductor chip is mounted on the solder resist layer 140 side of wiring board 100 (step S106), and connection terminals 160 and electrodes of the semiconductor chip are connected.

[0038] Specifically, for example, as shown in Fig. 8, the semiconductor chip 210 is mounted above the connection terminals 160. Fig. 8 is a diagram showing a specific example of the semiconductor chip mounting process. The semiconductor chip 210 is mounted on the wiring substrate 100 by bonding the electrodes 211 to the connection terminals 160 with, for example, solder 212, and sealing the bonding portions between the electrodes 211 and the connection terminals 160 with underfill resin 213.

[0039] The wiring board 100 on which the semiconductor chip 210 is mounted is mounted on a mounting board 220 such as a motherboard (step S107) as shown in Fig. 9, for example, to complete a semiconductor device. Fig. 9 is a diagram showing a specific example of the mounting process. Electrode pads 221-223 are formed on the upper surface of the mounting board 220, and electrode pins 224-226 are connected to the electrode pads 221-223 by, for example, solders 224a-226a so as to stand upright relative to the upper surface of the mounting board 220. The electrode pins 224-226 become connection terminals when the wiring board 100 is mounted on the mounting board 220. The electrode pins 224-226 are held by a holder 230 made of, for example, insulating resin.

[0040] The electrode pins 224 are inserted into the openings 151 of the solder resist layer 150 and come into contact with the pads 134 exposed from the openings 151 .

[0041] The electrode pin 225 is inserted into the through hole 171 of the wiring board 100 and comes into contact with the pad 114 exposed from the through hole 171. This electrically connects the pad 114 and the electrode pin 225 at a position closer to the semiconductor chip 210 than the pad 134, thereby reducing the number of connections between the pads by vias between the semiconductor chip 210 and the mounting board 220 and reducing discontinuous conductor structures. As a result, the connection reliability and transmission characteristics of the wiring inside the wiring board 100 can be improved.

[0042] The electrode pin 226 is inserted into the through hole 172 of the wiring board 100 and comes into contact with the pad 124 exposed from the through hole 172. This electrically connects the pad 124 and the electrode pin 226 at a position closer to the semiconductor chip 210 than the pad 134, thereby reducing the number of connections between the pads by vias between the semiconductor chip 210 and the mounting board 220 and reducing discontinuous conductor structures. As a result, the connection reliability and transmission characteristics of the wiring inside the wiring board 100 can be improved.

[0043] Next, various modified examples of the embodiment will be described with reference to Figures 10 to 13. In the various modified examples described below, the same parts as those in the embodiment will be denoted by the same reference numerals, and duplicated explanations may be omitted.

[0044] Fig. 10 is a diagram showing a configuration of a wiring board 100 according to a first modified example of the embodiment. Fig. 11 is a diagram showing a configuration example of a semiconductor device having the wiring board 100 of Fig. 10. The wiring board 100 according to the first modified example is different from the embodiment in that recesses are provided in the pads 114 and 124.

[0045] Specifically, in the first modification, pad 114 of wiring board 100 has recess 114a on the surface exposed at the bottom of through hole 171. Then, electrode pin 225 of mounting board 220 is fitted into recess 114a of pad 114. This suppresses misalignment between pad 114 and electrode pin 225, thereby improving the connection reliability between wiring board 100 and mounting board 220.

[0046] Moreover, in the first modification, the recess 114a has a tapered shape whose width decreases with increasing distance from the plane on which the pad 114 is exposed. This further suppresses misalignment between the pad 114 and the electrode pin 225, thereby further improving the connection reliability between the wiring board 100 and the mounting board 220.

[0047] Moreover, in the first modification, pad 124 of wiring board 100 has recess 124a on the surface exposed at the bottom of through hole 172. Electrode pin 226 of mounting board 220 is fitted into recess 124a of pad 124. This suppresses misalignment between pad 124 and electrode pin 226, thereby improving the connection reliability between wiring board 100 and mounting board 220.

[0048] Moreover, in the first modification, the recess 124a has a tapered shape whose width decreases with increasing distance from the plane on which the pad 124 is exposed. This further suppresses misalignment between the pad 124 and the electrode pin 226, thereby further improving the connection reliability between the wiring board 100 and the mounting board 220.

[0049] Fig. 12 is a diagram showing a configuration of a wiring board 100 according to a second modification of the embodiment. Fig. 13 is a diagram showing a configuration example of a semiconductor device having the wiring board 100 of Fig. 12. In the wiring board 100 according to the second modification, the structures of pads 114 and 124 are different from those of the embodiment. Also, in the semiconductor device according to the second modification, the structures of electrode pins 225 and 226 of a mounting board 220 are different from those of the embodiment.

[0050] Specifically, in the second modification, the pad 114 of the wiring board 100 has a signal pad 115 for signals and a ground pad 116 for grounding arranged around the signal pad 115. The ground pad 116 is set to a ground potential. Meanwhile, the electrode pin 225 of the mounting board 220 has an internal conductor 241 for signals and an external conductor 242 arranged around the outer periphery of the internal conductor 241. The external conductor 242 is set to a ground potential. An insulating resin is filled in the space between the internal conductor 241 and the external conductor 242. Then, with the electrode pin 225 inserted into the through hole 171, the internal conductor 241 contacts the signal pad 115 and the external conductor 242 contacts the ground pad 116. As a result, the intrusion of noise into the transmission signal of the signal pad 115 and the internal conductor 241 is blocked by the ground pad 116 and the external conductor 242, so that the transmission characteristics between the wiring board 100 and the mounting board 220 can be improved.

[0051] In the second modification, the pad 124 of the wiring board 100 has a signal pad 125 for signals and a ground pad 126 for grounding arranged around the signal pad 125. The ground pad 126 is set to a ground potential. On the other hand, the electrode pin 226 of the mounting board 220 has an internal conductor 243 for signals and an external conductor 244 arranged around the outer periphery of the internal conductor 243. The external conductor 244 is set to a ground potential. An insulating resin is filled in the space between the internal conductor 243 and the external conductor 244. Then, with the electrode pin 226 inserted into the through hole 172, the internal conductor 243 contacts the signal pad 125 and the external conductor 244 contacts the ground pad 126. As a result, the intrusion of noise into the transmission signal of the signal pad 125 and the internal conductor 243 is blocked by the ground pad 126 and the external conductor 244, so that the transmission characteristics between the wiring board 100 and the mounting board 220 can be improved.

[0052] As described above, the wiring board (for example, wiring board 100) according to the embodiment includes a core board (for example, core board 110), a first wiring structure (for example, wiring structure 120 and solder resist layer 140), a second wiring structure (for example, wiring structure 130 and solder resist layer 150), and through holes (for example, through holes 171 and 172). The core board includes a wiring layer (for example, wiring layer 112) formed on the upper and lower surfaces of a base material (for example, base material 111). The first wiring structure includes a wiring layer (for example, wiring layer 122) and an insulating layer (for example, insulating layer 121 and solder resist layer 140) stacked on the upper surface of the core board. The second wiring structure includes a wiring layer (for example, wiring layer 132) and an insulating layer (for example, insulating layer 131 and solder resist layer 150) stacked on the lower surface of the core board. The through hole penetrates the insulating layer of the second wiring structure and the base material of the core substrate to a pad (for example, pad 114) included in the wiring layer of the core substrate, or penetrates the insulating layer of the second wiring structure, the base material of the core substrate, and the insulating layer of the first wiring structure to a pad (for example, pad 124) included in the wiring layer of the first wiring structure, thereby improving the connection reliability and transmission characteristics of the wiring inside the wiring substrate. [Explanation of symbols]

[0053] 100 Wiring board 110 Core Board 111 Base material 112,122,132 wiring layer 113,123,133 Via 114,124,134 Pad 114a, 124a Recess 115,125 Signal Pad 116,126 Grounding Pad 120,130 Wiring structure 121,131 Insulating layer 140,150 Solder resist layer 141,151 Opening 160 Connection terminal 171,172 Through holes 210 Semiconductor Chip 211 Electrode 213 Underfill Resin 220 Mounting Board 221,222,223 Electrode pads 224,225,226 Electrode pin 230 Holder 241,243 Inner conductor 242,244 Outer conductor

Claims

1. A core substrate having wiring layers formed on the upper and lower surfaces of a base material; a first wiring structure including a wiring layer and an insulating layer laminated on an upper surface of the core substrate; a second wiring structure including a wiring layer and an insulating layer laminated on a lower surface of the core substrate; a through hole that penetrates the insulating layer of the second wiring structure and the base material of the core substrate to a pad included in the wiring layer of the core substrate, or that penetrates the insulating layer of the second wiring structure, the base material of the core substrate, and the insulating layer of the first wiring structure to a pad included in the wiring layer of the first wiring structure; A wiring board comprising:

2. The pad is The through hole has a recess on the surface exposed at the bottom thereof.

2. The wiring board according to claim 1.

3. The recessed portion is The pad has a tapered shape that decreases in width as it moves away from the exposed surface of the pad.

3. The wiring board according to claim 2.

4. The second wiring structure includes: a second wiring structure including a lowermost wiring layer exposed on a surface of the second wiring structure and a second pad; The pad is A pad for transmitting a signal having a transmission speed faster than that of the signal transmitted to the other pads.

2. The wiring board according to claim 1.

5. The pad is a signal pad for a signal; a ground pad for grounding arranged around the outer periphery of the signal pad; 2. The wiring board according to claim 1, further comprising:

6. A wiring board; A semiconductor chip mounted on the wiring substrate; a mounting substrate on which the wiring substrate carrying the semiconductor chip is mounted; having The wiring board includes: A core substrate having wiring layers formed on the upper and lower surfaces of a base material; a first wiring structure including a wiring layer and an insulating layer laminated on an upper surface of the core substrate; a second wiring structure including a wiring layer and an insulating layer laminated on a lower surface of the core substrate; a through hole that penetrates the insulating layer of the second wiring structure and the base material of the core substrate to a pad included in the wiring layer of the core substrate, or that penetrates the insulating layer of the second wiring structure, the base material of the core substrate, and the insulating layer of the first wiring structure to a pad included in the wiring layer of the first wiring structure; having The mounting board is An electrode pad formed on an upper surface of the mounting substrate; an electrode pin connected to the electrode pad and standing on the upper surface of the mounting substrate; having The electrode pin is The pad is inserted into the through hole of the wiring board mounted on the mounting board and comes into contact with the pad exposed from the through hole. A semiconductor device comprising:

7. The pad is The through hole has a recess on a surface exposed at a bottom thereof, The electrode pin is The recess of the pad is fitted into the recess.

7. The semiconductor device according to claim 6.

8. The pad is a signal pad for a signal; a ground pad for grounding arranged around the signal pad; having The electrode pin is An inner conductor for signals; an outer conductor disposed around the outer periphery of the inner conductor; having When the electrode pin is inserted into the through hole, the inner conductor contacts the signal pad and the outer conductor contacts the ground pad.

7. The semiconductor device according to claim 6.

9. forming a wiring layer on the upper and lower surfaces of a base material to form a core substrate; forming a first wiring structure by laminating a wiring layer and an insulating layer on the upper surface of the core substrate; forming a second wiring structure by laminating a wiring layer and an insulating layer on the lower surface of the core substrate; forming a through hole penetrating through an insulating layer of the second wiring structure and a base material of the core substrate to a pad included in a wiring layer of the core substrate, or forming a through hole penetrating through an insulating layer of the second wiring structure, a base material of the core substrate, and an insulating layer of the first wiring structure to a pad included in a wiring layer of the first wiring structure; 2. A method for manufacturing a wiring board comprising the steps of:

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