Method of enhancing etching selectivity using pulsed plasma

Abstract

To provide a method of enhancing etching selectivity using pulsed plasma.SOLUTION: A method of processing a substrate 103 includes etching a first dielectric material formed on a substrate that is disposed on a substrate-supporting surface of a substrate support assembly 136 disposed within a processing region of a plasma processing chamber 100. The etching process includes: delivering a process gas to the processing region, where the process gas comprises a first fluorocarbon-containing gas and a first process gas; delivering, by use of a radio frequency generator, a radio frequency signal to a first electrode so as to form a plasma in the processing region; and establishing, by use of a first pulsed-voltage waveform generator, a first pulsed voltage waveform at a biasing electrode 104 disposed within the substrate support assembly.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD The embodiments described herein relate generally to semiconductor device manufacturing hardware and processes, and more particularly to an apparatus and method for processing a substrate in a plasma processing chamber. [Background technology]

[0002] Reliable fabrication of high aspect ratio features is one of the key technological challenges for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process, such as a reactive ion etch (RIE) plasma process, to form high aspect ratio openings in a material layer, such as a dielectric layer, of a substrate. In a typical RIE plasma process, a plasma is formed in a RIE processing chamber and ions from the plasma are accelerated towards the substrate surface to form openings in a material layer disposed under a mask layer formed on the substrate surface.

[0003] A typical reactive ion etch (RIE) plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to a "power electrode" (e.g., bias electrode), e.g., a metal plate located adjacent to an "electrostatic chuck" (ESC) assembly (more commonly called a "cathode"). The power electrode can be capacitively coupled to the plasma of the processing system through a thick layer of dielectric material (e.g., ceramic material) that is part of the ESC assembly. In a capacitively coupled gas discharge, the plasma is generated using a radio frequency (RF) generator that is coupled to the RF electrode through an RF matching circuit ("RF match") that adjusts the apparent load to 50 Ω to minimize reflected power and maximize power delivery efficiency. Application of RF voltage to the powered electrodes creates an electron-repelling plasma sheath (also called a "cathode sheath") over the processing surface of a substrate disposed on the substrate support surface of the ESC assembly. The nonlinear, diode-like nature of the plasma sheath rectifies the applied RF electric field, which creates a direct current (DC) voltage drop, or "self-bias," between the substrate and the plasma, making the substrate potential negative with respect to the plasma potential. This voltage drop determines the average energy of the plasma ions accelerating toward the substrate, and thus the etch anisotropy. In particular, the ion directionality, feature profile, and etch selectivity relative to mask and stop layers are controlled by the Ion Energy Distribution Function (IEDF). In a plasma with RF bias, the IEDF typically has two distinct peaks, a low-energy peak and a high-energy peak, and a population of ions with a range of energies extending between the two peaks.The presence of ion populations between the two peaks of the IEDF reflects the fact that the voltage drop between the substrate and the plasma oscillates at the RF bias frequency. When a lower frequency RF bias generator is used to obtain a higher self-bias voltage, the energy difference between these two peaks can be significant. That is, the etch profile is more isotropic due to the ions at the low energy peak, which can lead to bending of the walls of the etched feature. Compared to high energy ions, low energy ions are less effective at reaching the bottom corners of the etched feature (e.g., due to charging effects), but they are less likely to cause sputtering of the mask material. This is important in high aspect ratio etch applications, such as hard mask openings or dielectric mold etch. As feature sizes continue to shrink and aspect ratios increase, the requirement for control of the feature profile becomes more stringent, while a well-controlled IEDF at the substrate surface during processing becomes more desirable.

[0004] It has also been found that in other conventional plasma processes and processing chamber designs, delivery of multiple different RF frequencies to one or more electrodes in a plasma processing chamber can be used to control various plasma characteristics, such as plasma density, ion energy, and / or plasma chemistry. However, it has been found that delivery of multiple conventional sinusoidal waveforms from two or more RF sources, each configured to provide different RF frequencies, does not adequately or desirably control sheath characteristics and can lead to undesired arcing problems. Furthermore, due to direct or capacitive coupling between RF sources during processing, each RF source may induce RF currents (e.g., often referred to as "cross-talk") provided to the output of other connected RF sources, which may result in power being diverted from the intended load (plasma) and further damage each of the RF sources.

[0005] In recent years, high density storage devices including three-dimensional (3D) stacked memory structures have been developed. For example, a 3D NAND stacked memory device may be formed from an array of alternating vertical stacks of dielectric materials and conductive layers (e.g., tungsten-containing layers). Memory openings are formed and extend vertically through the dielectric material-containing layers in the alternating stacks to expose portions of the conductive layers, thus varying in depth within the alternating stack structure. The memory openings are eventually filled with conductive materials to form connections with the exposed portions of each conductive layer in each layer of the alternating stack. The conductive layers in the alternating stacks may function as word lines for the 3D NAND stacked memory device, and bit lines above the array of memory stack structures may be connected to the drain end of the semiconductor channel. However, when forming memory openings extending to different depths within the alternating stacks in a single etching step, it is desirable not to overetch the portions of the layers at the shallowest depths of the alternating stacks relative to the layers formed at the deepest depths. Therefore, what is needed is an etch process that can selectively etch the dielectric portions of the alternating stack and stop on the conductive layers so that all memory openings can be formed down to all layers in the alternating stack, without overetching exposed portions of the various conductive features during the etch process.

[0006] Therefore, there is a need in the art for new, robust and reliable plasma processing and biasing methods that allow for maintaining a nearly constant sheath voltage, thus forming a desired, repeatable IEDF at the surface of the substrate, and allowing precise control over the shape of the IEDF, and potentially the etch profile of features formed at the surface of the substrate. There is also a need for systems, apparatus and methods that solve the problems set forth above. Summary of the Invention

[0007] Embodiments of the present disclosure generally include a method of processing a substrate in a plasma processing chamber, the method including etching a first dielectric material formed on a substrate disposed on a substrate support surface of a substrate support assembly disposed in a processing region of the plasma processing chamber. The process of etching the first dielectric material includes: The method includes delivering a process gas to a processing region of a plasma processing chamber, the process gas including a first fluorocarbon-containing gas and a first process gas, delivering a radio frequency signal to a first electrode disposed within the plasma processing chamber using a radio frequency generator to generate a plasma in the processing region, and establishing a first pulsed voltage waveform at a bias electrode disposed within a substrate support assembly using a first pulsed voltage waveform generator, the first pulsed voltage waveform including a series of repeating pulsed voltage cycles, each pulsed waveform cycle including a first portion occurring during a first time period and a second portion occurring during a second time period greater than the first time period, the pulsed voltage waveform being substantially constant for at least a portion of the second time period.

[0008] An embodiment of the present disclosure may further provide a method of processing a substrate in a plasma processing chamber, the method including etching a first dielectric material formed on a substrate disposed on a substrate support surface of a substrate support assembly disposed in a processing region of the plasma processing chamber. The process of etching the first dielectric material includes delivering a process gas including a first fluorocarbon-containing gas and a first process gas to a processing region of the plasma processing chamber. The first fluorocarbon-containing gas includes at least one of C4F6 or C3F6, and the first process gas includes at least one of N2, Kr, and O2. The process of etching the first dielectric material also includes utilizing a radio frequency generator to deliver a radio frequency signal to a first electrode disposed in the plasma processing chamber to generate a plasma in the processing region, and utilizing a first pulse voltage waveform generator to establish a first pulse voltage waveform at a bias electrode disposed in the substrate support assembly, the first pulse voltage waveform including a series of repeating pulse waveform cycles. Each pulse waveform cycle includes a first portion occurring during a first period and a second portion occurring during a second period greater than the first period. The first period may be between about 200 ns and about 400 ns, and the first period may be less than about 20% of one cycle of the series of repeating cycles. The pulse voltage waveform within each pulse waveform cycle may have a peak-to-peak voltage between about 5 kV and about 20 kV. The pulse voltage waveform is substantially constant during at least a portion of the second period.

[0009] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure, briefly summarized above, may be obtained by referring to the embodiments. Some embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate exemplary embodiments, and therefore should not be considered as limiting the scope of the present disclosure, and other equally effective embodiments may be allowed. [Brief description of the drawings]

[0010] [Figure 1]1 is a schematic cross-sectional view of a processing chamber configured to perform a method according to the present disclosure, according to one embodiment. [Diagram 2] FIG. 2 is a simplified schematic diagram of a biasing scheme that can be used with the processing chamber shown in FIG. 1, according to one embodiment. [Figure 3A] FIG. 2 is a functionally equivalent circuit diagram of a negative pulse bias scheme that can be implemented in the processing chamber shown in FIG. 1 according to one embodiment. [Figure 3B] FIG. 2 is a functionally equivalent circuit diagram of a positive pulse bias scheme that can be implemented in the processing chamber shown in FIG. 1 according to one embodiment. [Figure 4A] 1 illustrates an example of a negative pulse voltage (PV) waveform established at a bias electrode, according to one embodiment. [Figure 4B] 1 illustrates an example of a shaped pulse voltage (PV) waveform established at a bias electrode, according to one embodiment. [Figure 4C] 1 illustrates an example of a positive pulsed voltage (PV) waveform established at a bias electrode, according to one embodiment. [Figure 4D] 1 illustrates a comparison of negative and positive pulse voltage (PV) waveforms established at a substrate during processing, according to one embodiment. [Diagram 5] FIG. 2 illustrates a substrate with etched trenches reaching into various conductive layers of the substrate, according to one embodiment. [Figure 6A] 1 illustrates a diagram of a plasma etching process for a substrate, according to one embodiment. [Figure 6B] 1 illustrates a diagram of a plasma etching process for a substrate, according to one embodiment. [Figure 6C] 1 illustrates a diagram of a plasma etching process for a substrate, according to one embodiment. [Figure 7] 1 illustrates a diagram of a plasma etching process for a substrate, according to one embodiment. [Figure 8] 1 illustrates an exemplary sheath thickness during a plasma etching process, according to one embodiment. [Figure 9]1 illustrates exemplary steps of a plasma etching process, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] For ease of understanding, wherever possible, identical reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0012] Embodiments of the disclosure provided herein include apparatus and methods for plasma processing of a substrate in a processing chamber. More specifically, embodiments of the disclosure describe a process for improving the selectivity of etching of a dielectric layer relative to one or more inorganic materials using a pulsed plasma ion etching process. Embodiments of the disclosure include an apparatus configured to provide a radio frequency (RF) generated RF waveform from an RF generator to one or more electrodes in the processing chamber, and a pulsed-voltage (PV) waveform is delivered from one or more pulsed-voltage (PV) generators to one or more electrodes in the processing chamber.

[0013] Generally, the generated RF waveform is configured to establish and maintain a plasma in the processing chamber, and the delivered PV waveform is configured to control a sheath voltage at the surface of the substrate during a portion of the plasma process, and thus to create a desired ion energy distribution function (IEDF) at the surface of the substrate during one or more plasma processing steps performed in the processing chamber. The plasma processes disclosed herein can be used to control the interaction of the plasma with the substrate surface during processing. In some configurations, the plasma processes disclosed herein are used to control the profile of features formed at the substrate surface during processing. In some embodiments, the pulsed voltage waveform is established by a PV generator electrically coupled to a bias electrode disposed in a substrate support assembly disposed in the plasma processing chamber.

[0014] In general, the fabrication of semiconductor devices can include logic and memory manufacturing processes, such as the fabrication of flash memory. As devices become smaller, structures for efficiently fabricating multiple memory cells are used to maximize the density of memory cells in memory devices. Three-dimensional (3D) NAND technology addresses the challenges associated with two-dimensional (2D) NAND technology and stacking memory cells vertically.

[0015] The plasma etching processes involved in the fabrication of 3D NAND devices are becoming increasingly challenging. In particular, etching stepped contacts in 3D NAND technology provides access to cells at the bottom of the NAND stack, allowing deposition of conductive material (e.g., tungsten) to form word lines that allow access to the cell control gates from external peripheral circuitry. Etching stepped contacts creates etching challenges, especially for high aspect ratio features with aspect ratios of 20:1 to 40:1. Etching through high aspect ratio conductive layers places increased demands on the etch process, which must be able to form openings in the layers that are free of striations, distortion, line bending, faceting, and feature clogging. Besides these demands, a priority for stepped contact etching applications is simultaneous etching on multiple levels with aspect ratios from 20:1 to 40:1 or more, combined with high selectivity to ensure negligible loss of the underlying conductive contact material.

[0016] Correspondingly, pulse voltage technology may provide a method for precisely controlling plasma ion density and ion energy during plasma processing. It is believed that precise control of plasma ion density and ion energy can be used to enhance etch selectivity and improve the results of the etch process while using a desired dry etch chemistry. Furthermore, improved etch selectivity and etch process results can be further achieved by controlling the formation of a fluorocarbon-based polymer layer on the exposed conductive material surface during the etch process using one or more methods described herein.

[0017] FIG. 1 is a schematic cross-sectional view of a processing chamber configured to perform the methods described herein. During some semiconductor plasma processes, ions are intentionally accelerated toward a substrate by a voltage drop in an electron repulsive sheath formed above a substrate placed on a substrate support assembly 136 (FIG. 1). Without intending to be limiting with respect to the scope of the disclosure provided herein, the substrate support assembly 136 is sometimes referred to herein as a "cathode assembly" or "cathode." In some embodiments, the substrate support assembly 136 includes a substrate support 105 and a support base 107. The substrate support 105 may include an electrostatic chuck (ESC) assembly configured to chuck (e.g., hold) a substrate on a substrate receiving surface 105a.

[0018] In some embodiments of the disclosure provided herein, the processing chamber is configured to provide a capacitively coupled gas discharge whereby the plasma is generated by using an RF generation assembly, which includes an RF generator coupled to an RF electrode via an RF matching circuit ("RF matcher"). The RF matching circuit is configured to adjust the apparent load to 50 Ohms to minimize reflected power and maximize power delivery efficiency. In some embodiments, the RF electrode includes a metal plate positioned parallel to the substrate surface facing the plasma.

[0019] Additionally, during plasma processing methods disclosed herein, the ion acceleration cathode sheath is generally formed during plasma processing using a pulsed-voltage (PV) waveform generator configured to establish a pulsed voltage waveform at one or more bias electrodes 104 ( FIG. 1 ) disposed within the substrate support assembly 136. In some embodiments, the one or more bias electrodes 104 include a chuck electrode separated from the substrate by a thin layer of dielectric material formed within the substrate support assembly 136 (e.g., an electrostatic chuck (ESC) assembly) and, optionally, an edge control electrode disposed within or below an edge ring 114 that surrounds the substrate 103 when the substrate 103 is disposed on the substrate support surface 105A of the substrate support assembly 136. As described further below, the PV waveform can be configured to produce a nearly constant sheath voltage (e.g., the difference between the plasma potential and the substrate potential) for a significant portion of the PV waveform's pulse period, which corresponds to a single (narrow) peak comprising the ion energy distribution function (IEDF) of ions reaching the substrate during this portion of the pulse period, also referred to herein as the "ion-current phase."

[0020] Plasma Processing Chamber Hardware Example FIG. 1 is a schematic cross-sectional view of a process chamber 100 in which a composite load 130 (FIGS. 3A-3B) is formed during plasma processing. FIGS. 3A-3B are simplified examples of electrical circuits 140 of pulsed voltage and RF biasing schemes that can be implemented using components found in the process chamber 100, respectively. The process chamber 100 is configured to perform one or more biasing schemes proposed herein, according to one or more embodiments. In one embodiment, the process chamber is a plasma processing chamber, such as a reactive ion etching (RIE) plasma chamber. In some other embodiments, the process chamber is a plasma-enhanced deposition chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber, a plasma-enhanced physical vapor deposition (PEPVD) chamber, or a plasma-enhanced atomic layer deposition (PEALD) chamber. In some other embodiments, the process chamber is a plasma processing chamber, or a plasma-based ion implantation chamber, such as a plasma doping (PLAD) chamber. In some embodiments, the plasma source is a capacitively coupled plasma (CCP) source, which includes an electrode (e.g., chamber lid 123) disposed within the process space facing the substrate support assembly 136. As shown in FIG. 1, the opposing electrode, such as the chamber lid 123 disposed opposite the substrate support assembly 136, is electrically connected to ground. However, in other alternative embodiments, the opposing electrode is electrically connected to an RF generator. In yet another embodiment, the process chamber may alternatively or additionally include an inductively coupled plasma (ICP) source electrically connected to a radio frequency (RF) power source.

[0021] The processing chamber 100 also includes a chamber body 113, which includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which together define a processing space 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material sized and shaped to provide structural support for the components of the processing chamber 100 and are configured to withstand pressure and additional energy applied to the components while a plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or stainless steel. A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases to the processing space 129 from a process gas source 119 in fluid communication therewith. The substrate 103 is loaded into and removed from the processing space 129 through an opening (not shown) in one of the one or more side walls 122, which is sealed with a slit valve (not shown) during plasma processing of the substrate 103. Here, the substrate 103 is transferred to and from the substrate receiving surface 105a of the ESC substrate support 105 using a lift pin system (not shown).

[0022] In some embodiments, the RF generating assembly 160 is configured to provide RF power to a support base 107 disposed in the substrate support assembly 136 proximate the ESC substrate support 105. The RF power delivered to the support base 107 is configured to ignite and sustain a processing plasma 101 formed using a process gas disposed in the processing space 129. In some embodiments, the support base 107 is an RF electrode electrically connected to an RF generator 118 via an RF matching circuit 161 and a first filter assembly 162 disposed in the RF generating assembly 160. In some embodiments, the plasma generating assembly 160 and the RF generator 118 are used to ignite and sustain the processing plasma 101 using the process gas disposed in the processing space 129 and an electric field generated by the RF power provided to the support base 107 by the RF generator 118. The processing space 129 is fluidly connected via a vacuum outlet 120 to one or more dedicated vacuum pumps that maintain the processing space 129 at sub-atmospheric pressure and evacuate process and other gases therefrom. A substrate support assembly 136 disposed within the processing space 129 is disposed on a support shaft 138 that is grounded and extends through the chamber base 124. However, in some embodiments, the RF generation assembly 160 is configured to provide RF power to a bias electrode 104 disposed within the substrate support 105 relative to the support base 107.

[0023] The substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107, as briefly described above. In some embodiments, the substrate support assembly 136 may additionally include an insulating plate 111 and a ground plate 112, as further described below. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed thereon during substrate processing. In some embodiments, one or more cooling channels (not shown) are disposed within the support base 107, and the one or more cooling channels are in fluid communication with a cooling source, such as a refrigerant source or a cooling water source, having a relatively high electrical resistance. In some embodiments, the substrate support 105 includes a heater, for example a resistive heating element embedded within a dielectric material of the substrate support. Here, the support base 107 is formed from a corrosion-resistant, heat-conductive material, such as a corrosion-resistant metal, for example aluminum, an aluminum alloy, or stainless steel, and is bonded to the substrate support using an adhesive or by mechanical means.

[0024] The support base 107 is electrically insulated from the chamber base 124 by an insulating plate 111, and a ground plate 112 is interposed between the insulating plate 111 and the chamber base 124. In some embodiments, the processing chamber 100 further includes a quartz tube 110, or collar, that at least partially circumnavigates a portion of the substrate support assembly 136 to prevent corrosion of the ESC substrate support 105 and / or the support base 107 from contact with corrosive process gases or plasmas, cleaning gases or plasmas, or by-products thereof. Typically, the quartz tube 110, the insulating plate 111, and the ground plate 112 are surrounded by a liner 108. Here, a plasma screen 109, which is substantially flush with the substrate receiving surface of the ESC substrate support 105, prevents plasma from forming in the space between the liner 108 and one or more sidewalls 122.

[0025] The substrate support 105 is typically formed of a dielectric material, such as a corrosion-resistant metal oxide or metal nitride material, such as a bulk sintered ceramic material, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material. In one configuration, the bias electrode 104 is a chucking pole used to chuck the substrate 103 to the substrate receiving surface 105a of the substrate support 105, also referred to herein as the ESC substrate support, against the processing plasma 101 using one or more pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metal meshes, metal foils, metal plates, or combinations thereof. In some embodiments, the bias electrode 104 is electrically coupled to a bias compensation module 116, which provides a chucking voltage, such as a static DC voltage between about −5000V and about 5000V, to the bias electrode 104 using an electrical conductor, such as a coaxial transmission line 106 (e.g., a coaxial cable). As described further below, the high voltage module 116 includes a bias compensation circuit element 116A (FIGS. 3A-3B), a DC power supply 155, and a blocking capacitor 153. The bias compensation module blocking capacitor, also referred to herein as blocking capacitor 153, is disposed between the output of a pulsed-voltage waveform generator (PVWG) 150 and the bias electrode 104.

[0026] The bias electrode 104 is spaced from the substrate receiving surface 105A of the substrate support 105, and thus from the substrate 103, by a layer of dielectric material of the substrate support 105. Depending on the type of electrostatic chucking method utilized in the substrate support 105 to hold the substrate 103 during processing, such as Coulomb force ESC or Johnsen-Rahbek force ESC, different effective circuit elements are used to model the electrical coupling of the bias electrode 104 to the plasma 101. Generally, a parallel plate-like structure is formed by the bias electrode 104 and the layer of dielectric material, which may have an effective capacitance CE, typically between about 5 nF and about 50 nF. Typically, the layer of dielectric material (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) has a thickness between about 0.1 mm and about 1 mm, such as between about 0.1 mm and about 0.5 mm, e.g., about 0.3 mm. Here, the bias electrode 104 is electrically connected to the output of the PVWG 150 using an external conductor, such as a transmission line 106 disposed within the support shaft 138. In some embodiments, the dielectric material and layer thickness may be selected such that the chuck capacitance C of the layer of dielectric material is between about 5 nF and about 50 nF, such as between about 7 nF and about 10 nF.

[0027] In a more complex model of the Johnsen-Rahbek force ESC, the circuit model is as shown, ESC and the ESC dielectric resistance R CER and the gap capacitance C abt and the board capacitance C sub and the substrate resistance R sub The gap capacitance C abt generally considers the gas-containing space above and below a substrate disposed on the substrate support 105. abt is the chuck capacity C ESC is expected to have a capacity in the same range as

[0028] In some applications, the substrate 103 is typically made from a thin layer of semiconductor and / or dielectric material, so that the substrate 103 can be considered electrically to be part of the ESC dielectric layer disposed between the bias electrode 104 and the substrate receiving surface 105a. Thus, in some applications, the chuck capacitance C ESC is the combined series capacitance of the ESC and the substrate (i.e., the substrate capacitance C sub However, in the case of a Coulomb force chuck, the substrate capacitance C sub is typically very large (>10 nF) or the substrate may be conductive (infinite capacitance), so the series capacitance is mainly the capacitance C ESC In this case, the effective capacitance C E is effectively the chuck capacity C ESC In the case of a Johnsen-Rahbek ESC, the dielectric material can be, for example, doped aluminum nitride (AlN) with a dielectric constant (ε) of about 9, so that the ESC dielectric layer is "leaky" in the sense that it is not a perfect insulator and has some conductivity. However, the effective capacitance of the Johnsen-Rahbek ESC should be close to that of the Coulomb chuck. In one example, the volume resistivity of the dielectric layer in the Johnsen-Rahbek ESC is about 10 12 Ω-cm (Ω-cm) or less than about 10 10 or less than 10 8 Ω-cm and 10 12 It is even in the range between Ω-cm.

[0029] The substrate support assembly 136 further includes an edge control electrode 115 disposed below the edge ring 114 and surrounding the bias electrode 104 such that the edge control electrode 115, when biased, can affect or modify a portion of the generated plasma 101 at or outside the edge of the substrate 103 due to its position relative to the substrate 103. The edge control electrode 115 can be biased using a PVWG 150 different from the PVWG 150 used to bias the bias electrode 104. In one configuration, a first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the bias electrode 104 and a second PV waveform generator 150 of the second PV source assembly 197 is configured to bias the edge control electrode 115. In one embodiment, the edge control electrode 115 is disposed within the region of the substrate support 105 as shown in FIG. 1. In general, for a process chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104, as shown in FIG. 1. In some embodiments, the edge control electrode 115 includes a conductive mesh, foil, or plate disposed a similar distance from the surface 105A of the substrate support 105 (i.e., in the Z direction) as the bias electrode 104, as shown in FIG. 1. Alternatively, in some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, or plate disposed on or within a region of the quartz tube 110 (not shown) that surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. In some other embodiments, the edge control electrode 115 is disposed within or coupled to an edge ring 114 disposed adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed of a semiconductor material or a dielectric material (e.g., AlN, Al2O3, etc.).

[0030] 1, the support base 107 is spaced from the bias electrode 104 by a portion of dielectric material. The portion of dielectric material in some configurations is the dielectric material used to form the substrate support 105 and extends from the backside of the substrate support 105 to the bias electrode 104. The portion of dielectric material of the substrate support 105 has a support base capacitance CCL connected in series with the ESC capacitance CE, as shown diagrammatically in FIG. 3A and FIG. 3B. In some embodiments, the thickness of the portion of dielectric material disposed between the support base 107 and the bias electrode 104 is greater than the thickness of the dielectric material disposed between the bias electrode 104 and the substrate 103, where the dielectric materials are the same material and / or form part of the substrate support 105. In one example, the portion of dielectric material (e.g., Al2O3 or AlN) of the substrate support 105 disposed between the support base 107 and the bias electrode 104 is greater than 1 mm thick, e.g., between about 1.5 mm and about 20 mm thick.

[0031] Generally, a low pressure formed in the process space 129 of the process chamber 100 results in poor thermal conduction between the surfaces of the hardware components disposed therein, for example, between the dielectric material of the substrate support 105 and the substrate 103 disposed on the substrate receiving surface of the substrate support 105, reducing the effectiveness of the substrate support in heating or cooling the substrate 103. Therefore, in some processes, a thermally conductive inert heat transfer gas, typically helium, is introduced into a space (not shown) disposed between the non-device surface of the substrate 103 and the substrate receiving surface 105A of the substrate support 105 to improve heat transfer therebetween. A heat transfer gas supplied from a heat transfer gas source (not shown) flows into the backside space through a gas communication passage (not shown) disposed through the support base 107 and further through the substrate support 105.

[0032] The processing chamber 100 further includes a controller 126, also referred to herein as a processing chamber controller. The controller 126 herein includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The controller 126 is used to control the process sequence used to process the substrate 103, including the substrate bias method described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control the processing chamber and sub-processors associated with the processing chamber. The memory 134 described herein, which is generally a non-volatile memory, includes random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage, local or remote. The support circuits 135 are conventionally connected to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data for instructing the processor in the CPU 133 may be coded and stored in the memory 134. A software program (or computer instructions) readable by the CPU 133 in the controller 126 determines what tasks are performable by the components in the process chamber 100. Preferably, the program readable by the CPU 133 in the controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to monitoring and executing the electrode biasing schemes described herein. The program includes instructions that are used to control various hardware and electrical components in the process chamber 100 to perform various process tasks and various process sequences used to implement the electrode biasing schemes described herein.

[0033] During processing, the PV generators 314 in the PV waveform generators 150 of the first PV source assembly 196 and the second PV source assembly 197 establish a pulsed voltage waveform on a load (e.g., the composite load 130) disposed with the processing chamber 100. To simplify the discussion and without intending to be limiting with respect to the disclosure provided herein, the components in the second PV source assembly 197 used to bias the edge control electrodes 115 are not shown diagrammatically in FIGS. 3A-3B. Overall control of the delivery of the PV waveforms from each of the PV waveform generators 150 is controlled using signals provided from the controller 126. In one embodiment, as shown in FIG. 3A, the PV waveform generator 150A is configured to maintain a predetermined substantially constant positive voltage at its output (i.e., relative to ground) for a regularly repeating period of a predetermined length by repeatedly opening and closing its internal switch S1 at a predetermined rate. Alternatively, in one embodiment, as shown in FIG. 3B, the PV waveform generator 150B maintains a predetermined substantially constant negative voltage at its output (i.e., relative to ground) for a regularly repeating period of a predetermined length by repeatedly opening and closing its internal switch S1 at a predetermined rate. In FIGS. 3A-3B, the PV waveform generators 150A, 150B are reduced to a minimal set of components important for understanding their role in establishing a desired pulsed voltage waveform at the bias electrode 104. Each PV waveform generator 150 includes a PV generator 314 (e.g., a DC power supply) configured to provide a PV waveform at an output 350 as shown generally in FIGS. 3A-3B, and one or more electrical components, such as high repetition rate switches, capacitors (not shown), inductors (not shown), flyback diodes (not shown), power transistors (not shown), and / or resistors (not shown). An actual PV waveform generator 150 configurable as a nanosecond pulse generator can include any number of internal components and can be based on more complex electrical circuits than those shown in FIGS. 3A-3B.Each of the schematic diagrams in Figures 3A-3B provides only a functionally equivalent representation of the components of the PV waveform generator 150 and its electrical circuitry to the extent necessary to explain the basic principles of operation, their interaction with the plasma in the process space, and their role in establishing a pulsed voltage waveform, such as the input pulsed voltage waveform at the bias electrode 104. As can be inferred from the schematic diagrams shown in Figures 3A-3B, when the switch S1 moves from an open (off) position to a closed (on) position, it connects the output of the PV waveform generator 150 to its PV generator 314, which generates a substantially constant output voltage. The PV waveform generator 150 is primarily used as a charge injector (current source) rather than as a constant voltage source, and therefore does not need to impose strict requirements on the stability of the output voltage, since the output voltage may vary over time even when the switch remains in the closed (on) position. Furthermore, in some configurations, the PV generator 314 is essentially a sourcing supply, but not a sinking supply, in that it only passes current in one direction (e.g., the output can charge but not discharge a capacitor). In addition, when switch S1 remains in the open (Off) position, the voltage (V0) at the output of the PV waveform generator 150 is not controlled by the PV generator 314, but instead is determined by its own internal components and interactions with other circuit elements.

[0034] The current feedback output stage 314A has one end connected to ground and the other end connected to the junction of the output of the PV waveform generator 150 (i.e., side one of the generator combining assembly (not shown)). The current feedback output stage 314A may include the following components: a resistor, a resistor and inductor connected in series, a switch S2, and / or a more complex combination of electrical elements including a parallel capacitor that allows positive current flow toward ground.

[0035] The transmission line 131, which forms part of the PV transmission line 157 (FIG. 1), electrically connects the output 350 of the PV waveform generator 150 to the second filter assembly 151. The following discussion will primarily refer to the PV transmission line 157 of the first PV source assembly 196 used to couple the PV waveform generator 150 to the bias electrode 104, but the PV transmission line 158 of the second PV source assembly 197, which couples the PV waveform generator 150 to the edge control electrode 115, will include the same or similar components. Thus, generally, the output 350 of the PV waveform generator 150 terminates, where the output of the PV pulse generator 314 is connected to the output 350 and to the current feedback output stage 314A via internal electrical conductors. The transmission line 131 connects the generator coupling assembly 181 located at the output 350 of the PV waveform generator 150 to the second filter assembly 151. The electrical conductors in the various portions of the PV transmission line 157, 158 may include: (a) a coaxial transmission line (e.g., coaxial line 106), which may include a flexible coaxial cable connected in series with a rigid coaxial transmission line; (b) an insulated high voltage corona resistant hook-up wire; (c) a bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements (a)-(e) above. The outer conductor portion (e.g., the first electrical conductor) of the PV transmission line 157, such as the portion of the PV transmission line 157 in the support shaft 138, and the bias electrode 104, may have some coupled stray capacitance C to ground. stray (FIGS. 3A-3B). Although not shown in the figures, the outer conductor portion (e.g., the second electrical conductor) of the PV transmission line 158 and the edge control electrode 115 also have some coupled stray capacitance C strayThe internal electrical conductor of the PV waveform generator 150 may include the same basic elements as the external electrical conductor. In most practical applications, the transmission line 131 will include a line inductance 159 that may include a portion generated by the internal components of the PV waveform generator 150 (i.e., to the left of the generator output coupling assembly 181 (FIGS. 3A-3B)) and / or a portion generated by the external wire / cable connecting the PV waveform generator 150 to the second filter assembly 151 (i.e., to the right of the generator output coupling assembly 181).

[0036] Referring back to FIG. 1, the processing chamber 100 includes a grounded chamber lid 123. In this configuration, which differs substantially from conventional plasma processing chamber designs, RF power is instead delivered through the substrate support. Thus, coupling the RF generator 118 to the support base 107 allows the entire body of the ESC, which is functionally part of the cathode assembly, to have its top electrode grounded, maximizing the current return area. For plasma processes utilizing RF power delivery and PV waveform delivery, maximizing the grounded surface area within the plasma processing chamber, and therefore the current return area, minimizes plasma potential jumps during the ESC charging / sheath collapse phase of the PV waveform cycle generated by the output of the PV waveform generator 150, as described further below. Thus, the apparatus and methods provided herein minimize power loss to the chamber walls and improve plasma processing efficiency. The RF power and PV pulse waveform delivery methods described herein also provide certain process advantages because they affect and allow for improved control of plasma characteristics and radical generation. However, as mentioned above, there is strong capacitive coupling between the support base 107 and the bias electrode 104 through the ESC ceramic layers, and between the RF transmission line 167 and the PV transmission line 157, so when both types of power are transferred through the substrate support assembly 136 (i.e., the cathode assembly), each generator will induce current through the other, resulting in power being diverted away from the intended (plasma) load and possible damage to both generators.

[0037] In another alternative chamber lid 123 configuration that can be used with one or more other embodiments disclosed herein, the chamber lid 123 (i.e., the opposing electrode) is electrically insulated from one or more sidewalls 122 and is electrically coupled to the RF generator 118 via the plasma generating assembly 160. In this configuration, the chamber lid 123 can be driven by the RF generator 118 to ignite and maintain a processing plasma 101 in the process space 129. In one example, the RF generator 118 is configured to provide an RF signal to the chamber lid 123 at a RF frequency greater than about 300 kHz, such as an RF signal at a frequency between about 300 kHz and about 60 MHz, or even an RF signal at a frequency within a range of about 2 MHz to about 40 MHz.

[0038] Plasma processing bias method and process Figure 2 is a simplified schematic diagram of a biasing scheme that may be used with the process chamber shown in Figure 1. As shown in Figure 2, the RF generator 118 and the PV waveform generator 150 are configured to deliver RF and pulsed voltage waveforms, respectively, to one or more electrodes disposed within the chamber body 113 of the process chamber 100. In one embodiment, the RF generator 118 and the PV waveform generator 150 are configured to simultaneously deliver RF and pulsed voltage waveforms to one or more electrodes disposed within the substrate support assembly 136. In one non-limiting example, as previously described, the RF generator 118 and the PV waveform generator 150 are configured to deliver RF and pulsed voltage waveforms, respectively, to the support base 107 and the bias electrode 104, both of which are disposed within the substrate support assembly 136. In another example, the RF generator 118, the first PV waveform generator 150, and the second PV waveform generator 150 are configured to supply an RF waveform, a first pulsed voltage waveform, and a second pulsed voltage waveform, respectively, to the support base 107, the bias electrode 104, and the edge control electrode 115, all of which are disposed within the substrate support assembly 136.

[0039] 2, the RF generator 118 is configured to provide a sinusoidal RF waveform 601 (FIGS. 6A-6G) to one or more electrodes disposed in the chamber body 113 by transmitting an RF signal including the sinusoidal RF waveform 601 (FIGS. 6A-6G) through a plasma generation assembly 160 including an RF matching circuit 161 and a first filter assembly 162. In addition, each of the PV waveform generators 150 is configured to provide a PV waveform, typically including a series of voltage pulses (e.g., nanosecond voltage pulses), to one or more electrodes disposed in the chamber body 113 by establishing a PV waveform 401 (FIGS. 4A, 5A), 441 (FIG. 5B), or 431 (FIG. 5C) at the bias electrode 104 through a second filter assembly 151. Components in the bias compensation module 116 may be optionally disposed between each PV waveform generator 150 and the second filter assembly 151.

[0040] As briefly mentioned above, Figures 3A-3B are each an example of a functionally equivalent simplified electrical circuit 140 of the pulsed voltage and RF bias scheme proposed herein, including a diagram of a plasma in a process space. Figure 3A illustrates a simplified electrical circuit 140 of a pulsed voltage and RF bias scheme utilizing a PV waveform generator 150 in a first PV source assembly 196 configured to provide a positive voltage, such as PV waveform 431 (Figure 4C), during a portion of a process of establishing a PV waveform at the bias electrode 104. Figure 3B illustrates a simplified electrical circuit 140 of a pulsed voltage and RF bias scheme utilizing a PV waveform generator 150 in a first PV source assembly 196 configured to provide a negative voltage, such as PV waveform 401 (Figure 4A), during a portion of a process of establishing a PV waveform at the bias electrode 104. These circuits show a simplified model of the interaction of the pulsed voltage waveform generator 150 and RF generator 118 of the first PV source assembly 196 in the process chamber 100 and generally show the basic elements used during operation of the process chamber 100. The following definitions are used for clarity in this disclosure: (1) all potentials are referenced to ground unless otherwise specified; (2) the voltage at any physical point (such as the substrate or bias electrode) is similarly defined as the potential of said physical point relative to ground (a point of zero potential); (3) the cathode sheath is implied to be an electron-repulsive ion acceleration sheath that corresponds to a negative substrate potential with respect to the plasma; and (4) the sheath voltage (sometimes referred to as the "sheath voltage drop") V sh is defined as the absolute value of the potential difference between the plasma and an adjacent surface (e.g., the substrate or the chamber wall). (5) Substrate potential is the potential of the substrate surface facing the plasma.

[0041] The composite load 130 shown in Figures 3A-3B is illustrated in terms of a standard electrical plasma model that represents the processing plasma 101 as three elements in series. The first element is the electron-repelling cathode sheath (sometimes referred to as the "plasma sheath" or simply the "sheath") adjacent the substrate 103. The cathode sheath is represented in Figures 3A-3B by a conventional three-part circuit element that includes: (a) a diode D that, when open, represents sheath collapse; SH , (b) Current source I, which represents the ion current flowing to the substrate in the presence of a sheath. i , and (c) a capacitor CSH (e.g., ∼100-300 pF) that represents the sheath during the main part of the bias cycle (i.e., the ion flow phase of the PV waveform) where ion acceleration and etching occurs. The second element is the bulk plasma, a single resistor R plasma (e.g. resistor 146 = ∼5-10 ohms). The third element is an electron-repellent wall sheath formed at the chamber wall. The wall sheath is similarly represented in FIG. 3 by three circuit elements. The three circuit elements include: (a) diode D wall , (b) Current source I representing ion flow to the wall iwall , (c) Capacitor C, which primarily represents the wall sheath during the ESC recharge phase of the PV waveform (described later in the text). wall (e.g., ~5-10 nF). The inner surface of the grounded metal wall can be considered to be coated with a thin layer of dielectric material, and in Figure 3, a large capacitor C coat (e.g., ~300-1000nF).

[0042] As shown in FIGS. 3A-3B, the RF generator 118 is configured to provide an RF signal to the support base 107, and thus to the composite load 130, by feeding the generated RF power through the first filter assembly 162, the RF matching circuit 161, the line inductance LLine, the support base capacitance CCL, and the effective capacitance CE. In one embodiment, the RF matching circuit 161 includes a series inductance element LSER, and an adjustable series capacitance element CSER and an adjustable shunt capacitance element CSHunt that may be controlled by an input from the controller 126. In some embodiments, the RF matching circuit 161 may alternatively be formed using other circuit element configurations, such as an L-type circuit, a pi-type circuit, or a transformer match circuit. As previously mentioned, the RF matching circuit 161 is typically configured to adjust the apparent load to 50Ω in order to minimize the reflected power generated by the transmission of the RF signal from the RF generator 118 and maximize its power transmission efficiency. In some embodiments, the RF matching circuit 161 is optional, in which case other RF signal matching techniques (e.g., variable frequency tuning) may be used to avoid inefficiently delivering RF power to the composite load 130 during plasma processing of the substrate.

[0043] The first filter assembly 162 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF transmission line 167 and damaging the RF generator 118. The first filter assembly 162 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator 314 in the PV waveform generator 150, thus preventing current flow to the RF generator 118. In one embodiment, the first filter assembly 162 includes a blocking capacitor CBC disposed between the RF matching circuit 161 and the RF generator 118. In this configuration, the RF matching element 161 is configured to compensate the capacitance of the blocking capacitor CBC to tune the apparent load to the RF generator 118. In one example, the first filter assembly 162 includes a 38-40 pF capacitor to prevent the nanosecond PV waveform (e.g., pulse period 10-100 ns) provided by the PV waveform generator 150 from damaging the RF generator 118. In another example, the first filter assembly 162 includes a blocking capacitor CBC having a capacitance less than 38 pF.

[0044] In some embodiments, as shown in FIGS. 1-3B, each of the PV waveform generators 150 includes a blocking capacitor 153 of the high voltage module 116, and a second filter assembly 151, a high voltage line inductance LHV, and an effective capacitance C E4B. In this case, the system optionally includes a bias compensation module 116 that is used to chuck, e.g., "electrically clamp," the substrate against the substrate receiving surface of the ESC substrate support. Chucking the substrate allows the gap between the substrate receiving surface and the non-device surface of the substrate to be filled with helium gas (He) to provide good thermal contact between the two and to allow temperature control of the substrate by adjusting the temperature of the ESC substrate support. The DC chucking voltage generated by the bias compensation module 116 is combined with the pulsed voltage generated by the PV waveform generator 150 at the bias electrode 104 to provide an additional voltage offset of the pulsed voltage waveform equal to the DC chucking voltage. The additional voltage offset can be added to or subtracted from the offset ΔV shown in FIGS. 4A-4B. The effect of the bias compensation module 116 on the operation of the PV pulse generator 314 of the PV waveform generator 150 can be made negligible by selecting an appropriate size of the blocking capacitor 153 and blocking resistor 154. The blocking resistor 154 is a schematic representation of a resistor located in a component that connects the bias compensation module 116 to a point in the transmission line 131. The value of the blocking capacitor 153 is selected to block only the DC voltage of the bias compensation module, without causing any load on the pulse voltage output of the pulse bias generator. In one example, the capacitance of the blocking capacitor CBC is about 38 pF, and the capacitance of the blocking capacitor 153 is about 40 nF. This blocking resistor 154 is typically set large enough to effectively minimize the current through it. For example, a resistor (≧1 MOhm) is used to make the 400 kHz current flowing from the PV waveform generator 150 into the bias compensation module 116 negligible. In one example, the blocking resistor has a resistance greater than about 500 kOhm.This results in an average induced current of around 0.5-1mA, much smaller than the typical DC current limit of around 5mA for bias compensation module power supplies.

[0045] The second filter assembly 151 includes one or more electrical elements configured to prevent current generated by the output of the RF generator 118 from flowing through the PV transmission line 157 and damaging the PV pulse generator 314 of the PV waveform generator 150. As previously mentioned, the PV transmission line 157 is an assembly including the coaxial transmission line 106 and the transmission line 131. In one embodiment, the second filter assembly 151 includes a filter capacitor 151A having a capacitance CFC and a filter inductor 151B having an inductance LFL, the filter capacitor 151A and the filter inductor 151B being connected in parallel and disposed on the transmission line 157 between the PV pulse generator 314 and the bias electrode 104. In some configurations, the second filter assembly 151 is disposed between the blocking capacitor 153 of the bias compensation module 116 and the bias electrode 104. The second filter assembly 151 acts as a high impedance (e.g., high Z) to the PF signal generated from the PF generator 118, thus preventing current flow to the PV pulse generator 314. In general, the second filter assembly 151 is configured to block the RF signal and any associated harmonics from making a path to the PV pulse generator 314. In some embodiments, the RF signal generated by the RF generator is configured to transmit RF frequencies greater than 400 kHz, such as RF frequencies ≧1 MHz, or ≧2 MHz, or ≧13.56 MHz, or ≧40 MHz, etc. In one example, to prevent RF power provided from the RF generator 118 at a frequency of 40 MHz from damaging the PV pulse generator 314, the second filter assembly 151 includes a filter capacitor 151A having a capacitance of about 51 pF and a filter inductor 151B having an inductance of about 311 nH.

[0046] Pulse Waveform Example As previously discussed, embodiments of the present disclosure provide novel substrate biasing methods that allow for maintaining a nearly constant sheath voltage during processing, thus providing the ability to individually control aspects of the plasma formed within the process space of the plasma processing chamber using one or more RF source assemblies while forming a desired IEDF at the surface of the substrate. In some embodiments, using the novel substrate biasing apparatuses and methods disclosed herein, a single-peak (mono-energetic) IEDF can be formed at the surface of the substrate during processing. In other embodiments, using one or more of the novel substrate biasing apparatuses and methods disclosed herein, a two-peak (bi-energetic) IEDF is formed at the surface of the substrate during processing.

[0047] As described further below in conjunction with FIGS. 4A-4C, a novel substrate biasing method that allows for maintaining a substantially constant sheath voltage during plasma processing includes delivering a series of pulses and / or bursts of pulses during a plasma processing sequence performed on a substrate during a plasma process performed in a plasma processing chamber. The disclosed embodiments provided herein include delivering pulses having a desired PV waveform, each of which includes a number of different phases. As described further below, each PV waveform includes at least one of a number of phases that is controlled by delivery of a voltage signal, or possibly a constant current signal, provided from a PV waveform generator 150. Broadly, for purposes of discussion, each pulse of the PV waveform can be partitioned into two main regions, including a first region 405 and a second region 406, as shown in FIGS. 4A-4C. Broadly, each PV waveform has an amplitude (V out ), offset (e.g., ΔV), pulse period (T P ), pulse repetition frequency (f P =1 / T P ).

[0048] In some embodiments, the PV waveform is established at the bias electrode 104 and the edge control electrode 115 separately using the PV waveform generator 150 of the first PV source assembly 196 and the PV waveform generator 150 of the second PV source assembly 197. FIG. 4A illustrates a negative pulse bias type of pulse voltage waveform, where the PV waveform generator 150 is configured to control the generation of a series 550 of multi-phase negative pulse waveforms 401 to establish a PV waveform at the bias electrode 104 or the edge control electrode 115. In some embodiments, the multi-phase negative pulse waveform 401 includes a series of repeating cycles such that the waveform in each cycle has a first portion that occurs during a first period and a second portion that occurs during a second period. The multi-phase negative pulse waveform 401 also includes a positive voltage that is present only during at least a portion of the first period, and the pulse voltage waveform is substantially constant during at least a portion of the second period. The output of the PV waveform generator 150 is connected to a negative voltage power supply during at least a portion of the second time period.

[0049] 4A and 4D, in one example, substrate PV waveform 425 is a series of PV waveforms established at the substrate due to established PV waveforms formed at bias electrode 104 or edge control electrode 115 by PV waveform generator 150. Substrate PV waveform 425 is established at the surface of the substrate during processing and includes a sheath collapse and ESC recharge phase 450 (or, for ease of discussion, sheath collapse phase 450) extending between points 420 and 421 of the illustrated substrate PV waveform 425, a sheath formation phase 451 extending between points 421 and 422, and an ion flow phase 452 extending between point 422 and the start point 420 of the next successively established pulsed voltage waveform. The plasma potential curves illustrate the local plasma potential during delivery of a negative pulse waveform 401 established at the bias electrode 104 and / or edge control electrode 115 using one or more PV waveform generators 150.

[0050] In this example, a multi-phase negative pulse waveform 401 (FIG. 4A) is formed when the PV waveform generator 150 provides and controls the delivery of negative voltages during two of the phases of an established multi-phase negative pulse waveform 401 during processing in the process chamber 100, such as portions of the PV waveform going negative and / or portions that are maintained at a negative voltage level (e.g., ion flow phases). For example, the portions of the negative pulse waveform 401 that include the negative voltages would, by analogy, relate to the sheath formation phase 451 and ion flow phase 452 of the substrate PV waveform 425. In this case, for the multi-phase negative pulse waveform 401, the delivery of negative voltages from the PV waveform generator 150 occurs during a second phase 406 that extends from point 411 (i.e., the peak of the multi-phase negative pulse waveform 401) or extends between point 411 and the beginning of the sheath collapse phase 450 of the substrate PV waveform, which coincides with point 413. In some embodiments, during the ion flow phase 452 that corresponds to the portion of the established multi-phasic negative pulse waveform 401 between points 412 and 413, the PV waveform generator 150 generates a constant negative voltage (e.g., V OUT For example, during the ion flow phase 452, the ion flow (I i ) deposits a positive charge on the substrate surface, the voltage at the substrate surface increases over time as seen by the positive slope of the line between points 422 and 420. The voltage increase at the substrate surface over time reduces the sheath voltage, resulting in ion energy spreading. Therefore, to minimize the effects of sheath voltage dropping and ion energy spreading, the frequency of the PV waveform (1 / T PD However, it is desirable for the TPD to control and set the PV waveform period (Figure 5A).

[0051] During plasma processing, a PV waveform provided to the bias electrode 104 can be delivered and controlled to create a desired ion energy distribution function (IEDF), such as a nearly monoenergetic IEDF. The generation of the PV waveform and control of the PV waveform characteristics (e.g., peak-to-peak voltage, duty cycle, frequency, etc.) allows for precise control of the plasma ion density and generated ion energy, and further controls the deposition of fluorinated carbon (C) on the conductive material (e.g., W) surface found at the bottom of the etched features. x F y ) based polymer deposition becomes more controllable. Forming a polymer deposition on the surface of the conductive material improves the etch selectivity of the dry etch chemistry to the conductive material versus the intervening dielectric material being etched.

[0052] 4B illustrates a shaped pulse bias type PV waveform, in which a PV waveform generator 150 is configured to control the generation of a series 551 of multi-phase shaped pulse waveforms 441 established at the bias electrode 104 and / or edge control electrode 115. In some embodiments, the multi-phase shaped pulse waveform 441 is generated by the PV waveform generator 150, which is configured to use one or more internal switches and a DC power supply to provide a positive voltage during one or more phases of the voltage pulse (e.g., a first region 405) and a negative voltage during one or more phases of the voltage pulse (e.g., a second region 406).

[0053] In some embodiments, as shown in FIG. 4C, the PV waveform generator 150 is configured to provide a series 552 of multi-phase positive pulse waveforms 431 to the bias electrode 104 and the edge control electrode 115. Each positive pulse in the positive pulse waveform 431 can include multiple phases, such as a sheath collapse phase, an ESC recharge phase, a sheath formation phase, and an ion flow phase. In this example, the first region 405 broadly includes the sheath collapse phase and the ESC recharge phase. The second region 406 broadly includes the sheath formation phase and the ion flow phase. In some embodiments, the multi-phase positive pulse waveform 431 includes a series of repeating cycles, such that the waveform in each cycle has a first portion that occurs during a first period and a second portion that occurs during a second period. The multi-phase positive pulse waveform 431 also includes a positive voltage that is present only during at least a portion of the first period, and the multi-phase positive pulse waveform 431 is substantially constant during at least a portion of the second period. The output of the PV waveform generator 150 is connected to a positive voltage power supply for at least a portion of the first time period.

[0054] Various pulse voltage waveforms 401, 441, and 431 shown in Figures 4A, 4B, and 4C, respectively, represent pulse voltage waveforms provided to the input of bias compensation module 116 and may therefore differ from the pulse voltage waveforms established at bias electrode 104 and edge control electrode 115. The DC offset ΔV seen in each PV waveform depends on various characteristics of the configuration of PV waveform generator 150 used to establish the PV waveform.

[0055] In some embodiments, a series of bursts of at least one or more types of pulse voltage waveforms 401, 441, and / or 431 are established at the bias electrode 104 and / or edge control electrode 115 and at the substrate surface. In one example, multiple pulses within each burst include a series of negative pulse waveforms 401 established at the bias electrode 104 and / or edge control electrode 115. In one example, each of the bursts of pulse voltage waveforms includes a waveform having a consistent pulse voltage shape (e.g., a constant magnitude voltage is provided during a portion of each PV waveform 401) and a burst propagation length T that may vary from one burst to another over time. ON and the burst pause length T off and a pulse having a burst pause length T OFF is the burst transmission length T ON The duty cycle of a burst is the length of time that multiple pulses are delivered in a burst (i.e., the burst delivery length T ON ) by the duration of the burst period (i.e., T BD =T ON +T OFF ), which may be constant or may vary over time. It will be appreciated that in other processing methods, the multiple pulses may include a negative pulse waveform 401, a shaped pulse waveform 441, or a positive pulse waveform 431, or combinations thereof.

[0056] Exemplary selectivity for etching silicon dioxide As previously mentioned, the plasma etching processes involved in the fabrication of 3D NAND devices are becoming increasingly challenging. In particular, etching stepped contacts in 3D NAND technology allows for the formation of a conductive material layer (e.g., a tungsten-containing layer) embedded within the NAND stack to form portions of the wordlines that provide access to the bottom cells of the NAND stack and thus allow access to the cell control gates from external peripheral circuitry.

[0057] FIG. 5 illustrates the results of a stepped contact etch performed on a substrate according to embodiments described herein. According to one embodiment, the substrate 500 includes a mask layer 505 and a multi-layer stack 501, the multi-layer stack 501 including a plurality of conductive layers 520 and a plurality of intervening dielectric material layers disposed between the conductive layers 520. The intervening dielectric material layers and the dielectric material disposed adjacent to a portion of the conductive layers 520 are collectively described herein and collectively referred to as the dielectric material 510. The mask layer 505 includes a pre-etch pattern that is formed based on a customer's specifications using lithography and mask etching processes. The patterned mask layer 505 guides the formation of features, such as trenches 515 formed during a plasma etching process (shown in FIG. 6A). The multi-layer stack 501 includes multiple conductive layers 520 that are formed in a staggered arrangement such that each trench 515 formed during the plasma etching process described herein reaches each conductive layer 520 located at a different depth (Z direction) within the multi-layer stack 501. As shown in Figure 5, each trench 515 formed during the plasma etching process has a different depth and contacts different conductive layers 520 due to the pattern formed in the mask layer 505. Each trench 515 formed during the plasma etching process also does not penetrate through a corresponding conductive layer 520.

[0058] In some embodiments, the conductive layer 520 disposed within the dielectric material 510 of the multi-layer stack 501 may be comprised of tungsten, platinum, titanium, ruthenium, silicon, molybdenum, cobalt, and hafnium.

[0059] 6A-6C each show a portion of a multi-layer stack 501 during various stages of a plasma etching process used to form a trench 515 in a stepped contact structure in a portion of a substrate, according to certain embodiments described herein. FIG 6A shows the substrate with a patterned mask layer 505 formed thereon prior to the plasma etching process used to form the trench 515, referred to herein for discussion as time T0. The pre-etch of the mask layer 505 defines the intended etching location in the dielectric layer 510 during the subsequent plasma etching process.

[0060] FIG. 6B illustrates the substrate 500 during a plasma etching process when the plasma process contacts the conductive layer 520 of the substrate 500. In this example, as shown in FIG. 6B, the plasma etching process forms two trenches in the dielectric layer 510 due to the pattern formed in the mask layer 505. During the plasma etching process, a plasma formed in the plasma processing chamber (e.g., plasma 530 in FIG. 7) interacts with the dielectric material 510 through the patterned mask layer 505 and forms trenches 515 in the dielectric material 510 after a period of time. The composition of the mask layer 505 and the composition of the plasma chemistry used during the etching process are selected such that minimal etching occurs during processing, and the plasma does not etch the mask layer 505, but only etches the dielectric material 510 exposed through the patterned mask layer 505. Each trench 515 has the same depth at this point in the plasma etching process, referred to here as time T1 for discussion purposes. In some embodiments, the plasma etching process functions as described above.

[0061] FIG. 6C shows the substrate 500 at the completion of the plasma etching process, referred to herein for discussion as time T2. The plasma etching process continues to etch the dielectric material 510 in the trench 515 defined by the patterned mask layer 505. Due to the composition of the conductive layer 520 and the need for a specific composition of plasma chemistry to perform the etching process, the conductive layer 520 will undergo some undesired etching as the plasma etching process continues after the conductive layer 520 is initially exposed at time T1 (shown in FIG. 6C). The etch rate of the conductive layer 520 is much less than the etch rate of the dielectric material 510. Correspondingly, the plasma etching process etches the dielectric material 510 to form a trench in the dielectric material 510 until the plasma 530 reaches one or more of the conductive layers 520 in the multi-layer stack 501 or the base layer 525 of the substrate 500. When the plasma 530 reaches one or more of the conductive layers 520 or the base layer 525 of the substrate 500, the etch rate decreases, but the etch rate through the dielectric material 510 remains the same until it reaches another conductive layer or the base layer 525 of the substrate 500.

[0062] As previously described, the plasma etch process etches the dielectric material 510 to form trenches in the dielectric material 510 until the plasma 530 reaches one or more conductive layers 520. Once the plasma 530 etches through the dielectric material 510 and reaches the conductive layers 520, the etch rate slows down due to the preferred dry etch chemistry used during the plasma etch process or due to the selectivity of the etch chemistry composition to the material in the conductive layers 520 relative to the dielectric material 510. As further described below, the dry etch chemistry, i.e., process gas, may be a fluorocarbon-containing gas (e.g., C x F y), and additional non-fluorocarbon-containing process gases. The interface formed at the surface of the conductive layer 520 may be comprised of a polymeric material formed by exposing the dry etching chemistry to the conductive layer material found at the bottom of the etched features. For example, when the one or more conductive layers 520 are made of tungsten (W), the plasma etching process forms a polymeric material on the surface of the tungsten material, thus protecting the otherwise exposed surface. In some examples, the interface formed is a fluorocarbon-based polymer deposited on the surface of the one or more conductive layers 520 for better protection against plasma radical etching. The interface may be formed at each of the one or more conductive layers 520 located at various depths within the substrate as the dry etching plasma process proceeds. The formation of one or more interfaces on the one or more conductive layers aids in the selectivity of the etch. That is, the plasma etching process includes selectively etching the dielectric material 510 and avoiding etching into the one or more conductive layers 520 by forming an interface on the etched surface of the one or more conductive layers 520. In some examples, the formation of an interface on the one or more conductive layers 520 enhances etch selectivity of the substrate such that the plasma 530 (shown in FIG. 7 ) selectively etches the dielectric material 510 of the substrate 500 and does not etch the one or more conductive layers 520 or other underlying material layers.

[0063] FIG. 7 illustrates an improvement in etch selectivity of a plasma etching process according to one embodiment. During the ESC recharge phase of the PV waveform (e.g., the positive jump portion in the PV pulse (FIG. 4D)), the thickness of the sheath of the plasma 530 is reduced and the substrate 500 undergoes plasma radical etching, i.e., etching driven primarily by radicals as opposed to ions, which tend to be more isotropic. During the plasma radical etching, fluorocarbon radicals are deposited in the trenches 515 of the substrate 500, and thus the plasma radicals are advantageously used to form polymer deposits on the surface of the one or more conductive layers 520. Once the ESC recharge phase is terminated, the sheath of the plasma 530 is formed and during the ion flow phase (FIG. 4D), the substrate 500 undergoes plasma ion etching, i.e., etching driven primarily by ions as opposed to radicals, which tend to be more anisotropic.

[0064] FIG. 8 includes a curve 801 illustrating a graph of sheath thickness during a plasma etching process, according to one embodiment. As the PV waveform 401 illustrated in FIG. 4D changes as a function of time, the sheath thickness changes. Specifically, during the ESC recharge phase 450, the sheath thickness decreases and the substrate may undergo plasma radical etching, i.e., etching driven primarily by radicals as opposed to ions, which tend to be more isotropic. Once the ESC recharge phase 450 ends, the sheath is formed during the sheath formation phase 451, and during the ion flow phase 452, the substrate may undergo plasma ion etching, i.e., etching driven primarily by ions as opposed to radicals, which tend to be more anisotropic. During the ion flow phase 452, the sheath thickness may decrease in line with the increase in wafer voltage during the ion flow phase 452.

[0065] 9 is a flow diagram illustrating an exemplary process 900 for processing a substrate in a plasma processing chamber, in accordance with certain embodiments of the present disclosure. The process 900 can be performed, for example, in a plasma processing chamber (such as the plasma processing chamber 100 of FIG. 1).

[0066] Step 900 may begin by placing a substrate having a patterned mask layer and a first dielectric material formed thereon on a substrate support surface of a substrate support assembly disposed within a processing region of a plasma processing chamber, in step 905. Step 905 generally includes steps performed in steps 910-920, which may be performed in any order, but are generally performed simultaneously for the majority of the time that step 905 is performed.

[0067] In step 910, the plasma etching process includes delivering a dry etch chemistry into a processing region of the plasma processing chamber. The dry etch chemistry includes a first fluorocarbon-containing gas (e.g., C4F6, C3F6, etc. x F y) and a first process gas. Delivering the dry etch chemistry into the processing region of the plasma processing chamber includes delivering two or more gases selected from, but not limited to, a first flow rate of N2 gas, a second flow rate of Krypton (Kr) gas, a third flow rate of C4F6 gas, a fourth flow rate of C3F6 gas, and a fifth flow rate of O2 gas. The plasma etch process also includes controlling a chamber pressure, a substrate support temperature, a roof temperature, and a support helium (He) pressure. The first flow rate of N2 can range between 5 sccm and 1000 sccm. The second flow rate of Kr can range between 5 sccm and 1000 sccm. The third flow rate of C4F6 can range between 5 sccm and 1000 sccm. The fourth flow rate of C3F6 can range between 5 sccm and 1000 sccm. The fifth flow rate of O2 can range between 5 sccm and 1000 sccm. The plasma etch process also includes controlling a chamber pressure within a range between 1 mTorr and 500 mTorr. The plasma etch process also includes controlling a substrate support temperature within a range between -80°C and 500°C. The plasma etch process also includes controlling a roof temperature within a range between 10°C and 500°C. The plasma etch process also includes controlling a He pressure within a range between 0-100 Torr. In one example, the plasma etch process includes delivering a process gas having a composition formed by a C4F6 gas flow rate ratio of about 4 to a C3F6 gas flow rate, a C4F6 gas flow rate ratio of about 2 to an O2 gas flow rate, a C4F6 gas flow rate ratio of about 1.1 to an N2 gas flow rate, and a C4F6 gas flow rate ratio of about 0.7 to a Kr gas flow rate at a chamber pressure between about 1 mTorr and about 40 mTorr.

[0068] In step 915, the plasma etching process includes utilizing a radio frequency generator to transmit a radio frequency signal to a first electrode disposed within the plasma processing chamber to form a plasma within the processing region. The transmission of a radio frequency signal to a first electrode disposed within the plasma processing chamber to form a plasma includes parameters including, but not limited to, source power and frequency. The power of the RF source can range between 500W and 5000W at a frequency greater than 400kHz (>400kHz), e.g., 2MHz, or 13.56MHz, or 40MHz, or 60MHz.

[0069] In step 920, the plasma etch process includes establishing a first pulse voltage waveform at a bias electrode in a substrate support assembly using a first pulse voltage waveform generator. The first pulse voltage waveform may include a series of repeating pulse waveform cycles. Each pulse waveform cycle includes a first portion (810 in FIG. 8) occurring during a first time period and a second portion (811 in FIG. 8) occurring during a second time period greater than the first time period. Each pulse waveform cycle also includes a peak-to-peak voltage. The pulse voltage waveform output from the first pulse voltage waveform generator is substantially constant during at least a portion of the second time period. The first time period of each pulse waveform cycle may include a sheath collapse phase, an ESC recharge phase, and a sheath formation phase. The second time period of each pulse waveform cycle may include an ion flow phase. In some examples, the plasma etch process includes a plasma radical etch during the first time period and a plasma ion etch during the second time period. The plasma etches through the dielectric material via plasma ion etching during a second period of each pulse waveform, and the plasma etches the one or more conductive layers via plasma radical etching during a first period of each pulse waveform.

[0070] Delivering a pulsed voltage waveform to a bias electrode 104 disposed within a plasma processing chamber includes delivering a pulsed voltage waveform having parameters including, but not limited to, a PVT bias power, a duty cycle, a pulse frequency, a peak-to-peak voltage, and a flow ratio control (FRC). The bias power can range between 500 W and 500,000 W. The duty cycle can be between 0-100%, such as between about 1 and 99%, or between 5-20%, for a PV waveform generator 150 configured to provide a positive output voltage during a positive pulse waveform 431 is generated, or between 50-98% for a PV waveform generator 150 configured to provide a negative output voltage during a negative pulse waveform 401 is generated. The pulse frequency can be between 1-1000 kHz, such as between about 10 kHz and about 500 kHz, or between about 50 kHz and about 400 kHz, or even between about 50 kHz and about 200 kHz. The FRC can range from 0 to 100% for all FRC channels. The peak-to-peak voltage of each PV waveform generated by the PV waveform generator 150 within the set of PV waveforms is between 0.5 kV and 20 kV, e.g., between about 2 kV and about 20 kV, or between about 5 kV and about 9 kV, or between about 5 kV and about 8 kV. It has been found that a higher peak-to-peak voltage increases the etch rate of the features and, moreover, surprisingly improves the selectivity for etching tungsten using the dry etch chemistry described in step 910 and other process parameters disclosed herein, e.g., steps 915 and 920.

[0071] Operation 900 may be completed for a desired period of time or until a desired endpoint is sensed within the plasma processing chamber such that an etching process may be performed through one or more layers of a multi-layer stack, such as the process described above with respect to Figures 5-6C. In some embodiments, one or more software algorithms within controller 126 are used to monitor, control and / or execute the process performed in operation 900.

[0072] While the above is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is defined by the following claims.

Claims

1. 1. A method for processing a substrate in a plasma processing chamber, comprising: etching a first dielectric material formed on a substrate disposed on a substrate support surface of a substrate support assembly disposed in a processing region of the plasma processing chamber, wherein etching the first dielectric material comprises: delivering a process gas comprising a first fluorocarbon containing gas and a first process gas to the processing region of the plasma processing chamber; transmitting a radio frequency signal to a first electrode disposed within the plasma processing chamber using a radio frequency generator to generate a plasma within the processing region; and utilizing a first pulsed voltage waveform generator to establish a first pulsed voltage waveform at a bias electrode disposed within the substrate support assembly, the first pulsed voltage waveform comprising a series of repeating pulse waveform cycles; Each pulse waveform cycle is a first portion occurring during a first time period and a second portion occurring during a second time period greater than the first time period; and a peak-to-peak voltage, the pulse voltage waveform is substantially constant for at least a portion of the second period. Establishing a first pulsed voltage waveform A method comprising:

2. The method of claim 1 , wherein the first period of time is between about 200 ns and about 400 ns.

3. 2. The method of claim 1, wherein the first period of time is less than about 20% of one of the series of repeating cycles.

4. 4. The method of claim 3, wherein the pulse voltage waveform in each pulse waveform cycle has a peak-to-peak voltage of between about 5 kV and about 20 kV.

5. The method of claim 1 , wherein the process gas comprises a second fluorocarbon-containing gas and a second process gas.

6. The first fluorocarbon-containing gas is ４ F ６ Or C ３ F ６ and the first process gas comprises at least one of N ２ , Kr, and O ２ The method of claim 1 , comprising at least one of:

7. placing a mask over the substrate including one or more conductive layers; providing the substrate including the mask and the one or more conductive layers in the plasma processing chamber; Etching the first dielectric material based on a plurality of parameters; The method of claim 1 further comprising:

8. The method of claim 7 , wherein the one or more conductive layers comprise at least one of tungsten, platinum, titanium, ruthenium, and silicon.

9. The method of claim 7 , wherein the one or more conductive layers comprise at least one of molybdenum, cobalt, and hafnium.

10. Etching the first dielectric material comprises: Etching a first trench through the first dielectric material, the first trench extending to a first conductive layer of the one or more conductive layers; Etching a second trench through the first dielectric material beyond a depth of the first trench, the second trench extending to a second conductive layer of the one or more conductive layers; The method of claim 7, comprising:

11. Etching the first dielectric material comprises:

11. The method of claim 10, comprising etching a third trench through the first dielectric material beyond a depth of the second trench, the third trench eventually reaching a base layer of the substrate.

12. The method of claim 10 , wherein the first trench does not extend through the first conductive layer and the second trench does not extend through the second conductive layer.

13. 11. The method of claim 10, wherein etching the first trench through the dielectric comprises etching the second trench to a depth that matches the depth of the first trench.

14. 2. The method of claim 1 , wherein etching the first dielectric material comprises etching one or more trenches through the first dielectric material, each of the one or more trenches having a different depth and each of the one or more trenches contacting a different conductive layer of the one or more conductive layers.

15. The method of claim 14 , wherein each of the one or more trenches does not penetrate through any of the one or more conductive layers.

16. 15. The method of claim 14, wherein etching the first dielectric material comprises forming an interface between one or more trenches and a conductive layer of the one or more conductive layers.

17. The method of claim 16 , wherein the ends of each of the one or more conductive layers are offset from one another to form a stepped portion.

18. delivering the process gas to the processing region of the plasma processing chamber to form a chamber pressure between 1 mTorr and 500 mTorr; and delivering the process gas includes flowing the first fluorocarbon-containing gas at a first flow rate and flowing the first process gas at a second flow rate; 10. The method of claim 1, wherein the pulsed voltage waveform established with the bias electrodes positioned comprises a duty cycle of between 1% and 99%.

19. The first fluorocarbon-containing gas is ４ F ６ Or C ３ F ６ and the first process gas comprises at least one of N ２ , Kr, and O ２ The method of claim 18, comprising at least one of the following:

20. the series of repeating pulse waveform cycles are provided at a pulse frequency of between about 300 and about 500 kHz; 20. The method of claim 19, wherein etching the first dielectric further comprises maintaining a temperature of the substrate support surface within a range between -80°C and 500°C.

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