Semiconductor device

Abstract

To provide a semiconductor device occupying a smaller area and having a high degree of integration.SOLUTION: A semiconductor device includes a first insulating layer 82, a conductive layer, and a second insulating layer 87. The conductive layer is provided between the first insulating layer 82 and the second insulating layer 87. The first insulating layer 82, the conductive layer, and the second insulating layer 87 include an overlapping region. A contact plug 63 penetrates the first insulating layer 82, the conductive layer, and the second insulating layer 87. The contact plug 63 includes a region where the radius becomes smaller starting from a border between the second insulating layer 87 and the conductive layer in a depth direction from the second insulating layer 87 toward the first insulating layer 82.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). Semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are attracting attention.

[0005] A transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-ripple transistor using an oxide semiconductor. Low power consumption CPUs that utilize peak current characteristics have been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2012-257187 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area. Another object is to provide a semiconductor device with a high degree of integration. Another object of the present invention is to provide a semiconductor device with high speed. One of the objects of the present invention is to provide a semiconductor device having high productivity. Another object of the present invention is to provide a semiconductor device with a high yield. Another object is to provide a novel semiconductor device. It is an object of the present invention to provide a method for fabricating a semiconductor device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor using silicon The present invention relates to a semiconductor device having a transistor formed by the above method.

[0010] One aspect of the present invention is a semiconductor device having a first insulating layer, a conductive layer, a second insulating layer, and a contact plug. The conductive layer is provided between the first insulating layer and the second insulating layer, and the first insulating layer, the conductive layer and the The first insulating layer and the second insulating layer have an overlapping area, and the contact plug is a conductive layer. The contact plug is provided to penetrate the conductive layer and the second insulating layer. In the depth direction from the first insulating layer to the first insulating layer, the diameter is reduced at the interface between the second insulating layer and the conductive layer. The semiconductor device is characterized by having a region where the thickness of the semiconductor substrate is small.

[0011] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a contact plug. a first transistor having an active region in a silicon substrate; The second transistor has an oxide semiconductor in an active layer. The transistors each have an overlapping region, and a third transistor is disposed between the first transistor and the second transistor. a first insulating layer on the first transistor, a second insulating layer on the second transistor, One of the source electrode and the drain electrode is a source electrode or a drain electrode of a second transistor. The contact plug is electrically connected to one of the gate electrodes. a first insulating layer, one of a source electrode or a drain electrode of a second transistor, and a The contact plug extends from the second insulating layer toward the first insulating layer. In the depth direction, the second insulating layer and the source electrode or drain electrode of the second transistor The semiconductor device is characterized by having a region whose diameter decreases at the interface with one of the poles. .

[0012] The first transistor and the second transistor may form a CMOS circuit. .

[0013] The oxide semiconductor is In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, It is preferred that the metal oxide contains at least one of these elements (Ce, Nd or Hf).

[0014] The contact plug penetrates the oxide semiconductor layer of the second transistor. It can also be written as:

[0015] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of forming a first insulating layer, forming a conductive film on the first insulating layer, and The conductive film is selectively etched using the mask to form a conductive layer and the conductive A through hole is formed through the layer in the thickness direction, and a second insulating layer is formed so as to cover the conductive layer and the through hole. and selectively etching the second insulating layer using a second mask, An opening having a diameter larger than the diameter of the through hole is formed to expose the through hole, and the conductive layer is used as a mask to The method for manufacturing a semiconductor device is characterized in that the first insulating layer is selectively etched. Effect of the Invention

[0016] According to one embodiment of the present invention, a semiconductor device that occupies a small area can be provided. It is possible to provide a semiconductor device with a high degree of integration. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device with high productivity can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a method for manufacturing the above semiconductor device can be provided.

[0017] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0018] [Figure 1] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a semiconductor device. [Diagram 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Diagram 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 6] FIG. 1 is a top view illustrating a semiconductor device. [Figure 7] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a semiconductor device. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] FIG. 1 is a top view illustrating a semiconductor device. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 17] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 18] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 25] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 28] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 29] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 30] FIG. 1 is a top view illustrating a transistor. [Diagram 31] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 32] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 33] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 34] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 35] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 36] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 37] FIG. 2 is a diagram for explaining an example of the configuration of a CPU. [Figure 38] FIG. [Figure 39] 1A to 1C are diagrams illustrating electronic devices. [Diagram 40] FIG. [Diagram 41] FIG. [Diagram 42] FIG. 2 is a diagram illustrating an etching apparatus. [Diagram 43] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Diagram 44] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Diagram 45] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 46] Electron diffraction pattern of CAAC-OS. [Figure 47] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 48] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Figure 49] A diagram explaining InGaZnO4 crystals and pellets. [Figure 50] Schematic diagram explaining a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0020] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0021] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0022] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0023] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0024] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0025] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0026] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0027] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0028] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and X is electrically connected to the first connection path, and the first connection path does not have a second connection path; The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third connection path is electrically connected to Y through Z2 by an electrical path of The fourth electrical path does not include the fourth connection path, and the fourth electrical path is a drain of a transistor. (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0029] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0030] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0031] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0032] (Embodiment 1) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. .

[0033] FIG. 1A is a cross-sectional view illustrating a structure of a semiconductor device of one embodiment of the present invention. The semiconductor device is a transistor 51 having an active region on a silicon substrate 40, and an oxide semiconductor The transistor 51 is a p-ch type, and the transistor 52 has a semiconductor layer as an active layer. By making the resistor 52 an n-channel type, a CMOS circuit can be formed. The transistors 51 and 52 shown in FIG. 1B form an inverter circuit 90. (see).

[0034] The transistor 51 includes an active region in which a channel is formed, a source region, a drain region, a gate The basic structure of the transistor 52 is an insulating film and a gate electrode. The basic structure of the device is an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. As shown in FIG. 1A, each of a transistor 51 and a transistor 52 is By overlapping a portion of the above-mentioned components, the area occupied by the circuit can be reduced.

[0035] In the inverter circuit 90, an n-ch type semiconductor device having an active region in the silicon substrate 40 is used. This eliminates the need for the transistor process, and the process of forming p-wells and n-type impurity regions, etc. This can eliminate the need for additional steps, thereby significantly reducing the number of steps.

[0036] An insulating layer 81, an insulating layer 82, an insulating layer 83 and an insulating layer 84 are provided on the transistor 51. Here, for convenience of explanation, the insulating layers 81 to 84 are collectively referred to as a first insulating layer. .

[0037] In addition, a transistor 52 is provided on the first insulating layer, and an insulating layer 85, an insulating layer 86 and an insulating layer 87 are provided. The insulating layer 87 is collectively referred to as the second insulating layer.

[0038] The insulating layers constituting the first insulating layer and the second insulating layer are not limited to the above-mentioned form, and may be any of the above-mentioned insulating layers. Some of the layers may be omitted and other insulating layers may be added.

[0039] One of the source region and the drain region of the transistor 51 is formed by a first insulating layer and a second insulating layer. The contact plug 61 is electrically connected to the insulating layer. 1 is electrically connected to wiring 71 on the second insulating layer.

[0040] The gate electrode of the transistor 51 is a contact that penetrates the first insulating layer and the second insulating layer. The contact plug 62 is electrically connected to the second insulating layer 61. It is electrically connected to the wiring 73 on the top.

[0041] The other of the source region and the drain region of the transistor 51 is a first insulating layer. One of the source electrode or the drain electrode of the transistor 52 and a contact penetrating the second insulating layer The source region of the transistor 51 is electrically connected to the contact plug 63. The other of the drain regions and one of the source electrode or drain electrode of the transistor 52 are Electrical connection is made via contact plug 63 .

[0042] The gate electrode of the transistor 52 is connected to a contact plug 64 that penetrates the second insulating layer. The contact plug 64 is electrically connected to the wiring 73 on the second insulating layer. That is, the gate electrode of the transistor 51 and the gate electrode of the transistor 52 are The electrode is electrically connected via the contact plug 62, the wiring 73, and the contact plug 64. It will be connected.

[0043] In FIG. 1A, the contact plugs 62 and 64 are located at positions in the depth direction. Since it is different from other contact plugs, it is indicated by different hatching.

[0044] The other of the source electrode and the drain electrode of the transistor 52 penetrates the second insulating layer. The contact plug 65 is electrically connected to the second It is electrically connected to the wiring 72 on the insulating layer.

[0045] In the semiconductor device according to one embodiment of the present invention, a plurality of transistors having overlapping regions are provided. After forming the contact plug, a contact plug is formed to electrically connect the plurality of transistors and The contact plug is connected to wiring, etc. By adopting such a configuration, the process is simplified. In addition, wiring can be freely performed after the transistors are formed. By changing a part of the process, semiconductor devices with different functions can be formed. This can reduce costs of production and manufacturing.

[0046] Here, the contact plug is formed by first forming a contact hole and then inserting a Conductive material is embedded using CVD (Chemical Vapor Deposition) method etc. In this process, a large aspect ratio is used to reduce the area occupied. It is preferable to form a large contact hole through multiple layers and with a small aspect ratio. It is very difficult to form a contact hole with a large ratio.

[0047] The contact holes for providing the contact plugs 61 and 62 shown in FIG. Since the first insulating layer and the second insulating layer are formed by etching, the difficulty is relatively low. For example, In the case of oxide insulating layers, nitride insulating layers, and the like, the same etching conditions can be used for processing even if the types are different. This is because in many cases,

[0048] On the other hand, the contact hole for providing the contact plug 63 is formed by etching the insulating layer. In addition, the source or drain electrodes (typically metal layers) of transistor 52 are etched. Since the etching conditions are different for the insulating layer and the metal layer, This requires switching of etching gas and etchant, which effectively increases the number of processes. In addition, during the etching process, deposition, plasma damage, over-etching, etc. This can sometimes lead to defects.

[0049] Therefore, in one embodiment of the present invention, a contact hole for providing the contact plug 63 is In order to form the transistor 52 in advance without increasing the process and without inducing defects, A method of forming a through hole in either the source electrode or the drain electrode is used.

[0050] 2A to 2D are process diagrams for forming the contact plug 63. 1, the transistor 51 and a part of an insulating layer provided on the transistor 51 are not shown. The left side of the figure shows a cross-sectional view, and the right side shows a top view.

[0051] First, two layers of an oxide semiconductor layer having a three-layer structure are formed on the insulating layer 84, and the oxide semiconductor layer and The source electrode layer 32 and the drain electrode layer 33 are formed so as to be in contact with each other (see FIG. 2(A)). Here, a through hole 20 is provided in the source electrode layer 32. The through hole 20 is In addition, it can be formed in the same process as the patterning of the drain electrode layer 33 .

[0052] As shown in FIG. 3(A), the through hole 20 may also be provided in the drain electrode layer 33. When the through hole 20 provided in the main electrode layer 33 is not used, the through hole is not included in the subsequent process. The contact plug or the like may be connected to the drain electrode layer 33 in a region having a large area. The names of the source electrode layer and the drain electrode are interchangeable depending on the transistor operation. The names of the drain electrode layer 33 and the drain electrode layer 2 can be interchanged.

[0053] Next, the remaining layer of the oxide semiconductor layer, the gate insulating film and the gate electrode layer are formed. The basic structure of transistor 52 is then completed. A second insulating layer is then placed on transistor 52. At this time, a part of the second insulating layer is formed in the through hole 20. Further, a resist mask 35 for forming a plurality of contact holes is formed on the second insulating layer. (See FIG. 2(B)).

[0054] Then, an etching process is performed to form contact holes 21 to At this time, the through hole 20 is provided in the source electrode layer 32. Therefore, there is no need to change the etching conditions for the insulating layer to those for the metal layer. This makes it possible to easily carry out the etching process.

[0055] In the etching process, the contact hole 23 and the through hole 20 must not be misaligned. In order to achieve this, the diameter of the contact hole 23 in the second insulating layer region is set to be larger than the diameter of the through hole 20. Therefore, the contact hole 23 is preferably larger than the first insulating layer. In the depth direction from the first insulating layer to the source electrode layer 32 of the transistor 52 and the second insulating layer The diameter of the insulating layer becomes smaller at the boundary between the insulating layer and the conductor.

[0056] FIG. 2B shows an example of a resist mask in which all contact holes are formed at the same time. However, a method for sequentially forming contact holes having different depths may be used. As shown in FIG. 3(B), a relatively deep contact hole is first formed, and then the contact A method of forming a relatively shallow contact hole by temporarily filling the contact hole with an organic resin. Conversely, a relatively shallow contact hole may be formed first, and then a relatively deep contact hole may be formed. A method of forming contact holes may also be used.

[0057] Then, the contact holes are filled with a conductive layer to form contact plugs 61 to A contact plug 65 is formed (see FIG. 2(D)). According to the shape of the contact hole 23, the source electrode layer 32 of the transistor 52 and the The diameter changes at the interface with the insulating layer 2.

[0058] 40A to 40F show the source electrode layer 3 of the transistor 52 shown in FIG. 40(A) is an enlarged view of the vicinity of the interface between the second insulating layer and the second insulating layer. However, one embodiment of the present invention is not limited thereto. The shape of 20 and its surroundings can be varied.

[0059] For example, as shown in FIG. 40B, the corner of the side wall of the contact plug 63 formed in the through hole 20 The angle of the sidewall of the contact plug 63 may be different from the angle of the other portions of the sidewall of the contact plug 63. As shown in FIG. 40C, the diameter of the contact plug 63 changes inside the source electrode layer 32. Alternatively, as shown in FIG. 40(D), a contact plug may be formed inside the source electrode layer 32. The angle of the side wall of the lug 63 may be changed. The diameter of the contact plug 63 changes at the interface between the electrode layer 32 and the first insulating layer. Also, as shown in FIG. 40(F), a contact plug 6 may be formed inside the first insulating layer. The diameter of 3 may be variable.

[0060] Since the sidewall of the contact plug has a slight taper angle, It can be said that the diameter changes at any point in the depth direction. In the embodiment, regardless of these diameter changes, the contact plug does not have a significant diameter change. It is characterized by having a certain region.

[0061] Note that the transistor 52 used in the semiconductor device of one embodiment of the present invention has a structure in which a semiconductor device is formed on an oxide semiconductor layer. A source electrode and a drain electrode are formed on the It may be configured not to be in contact with the insulating layer 84. In such a configuration, The oxygen that is absorbed by the source electrode and the drain electrode is not taken by the metal layer that constitutes the source electrode and the drain electrode. Therefore, the oxygen can be efficiently supplied to the oxide semiconductor layer, and the transistor 52 The electrical characteristics and reliability can be improved.

[0062] In the case of the above-described structure, the semiconductor device according to one embodiment of the present invention is as shown in FIG. However, a through hole is provided in either the source electrode or the drain electrode of the transistor 52. This makes it easier to form a contact hole for providing the contact plug 63 .

[0063] In this case, when forming a contact hole for providing the contact plug 63, The oxide semiconductor layer is also etched. The oxide semiconductor layer is etched under the same etching conditions as the insulating layer. Since the thickness of the oxide semiconductor layer may differ from that of the oxide semiconductor layer, a through hole may also be provided in the oxide semiconductor layer.

[0064] For forming a contact plug 63 in a configuration in which a through hole is also provided in the oxide semiconductor layer The process diagrams are shown in FIG. 5A to FIG. 5D. are the same as the steps in FIG. 2(A) to FIG. 2(D), and the description thereof will be omitted.

[0065] 41(A) to 41(F) show the source electrode layer 32 and the front electrode layer of the transistor 52 shown in FIG. FIG. 41(A) is an enlarged view of FIG. 5(D) showing the vicinity of the interface with the second insulating layer. However, one aspect of the present invention is not limited to this. By adjusting the etching conditions, the through hole 20 and The shape of the periphery can be varied.

[0066] For example, as shown in FIG. 41(B), the contact is formed at the interface between the source electrode layer 32 and the oxide semiconductor layer. The diameter of the cut plug 63 may be changed. The diameter of the contact plug 63 may change inside the semiconductor layer. 1(D), a contact plug 63 formed in the through hole 20 in the oxide semiconductor layer The angle of the sidewall of the contact plug 63 may be different from the angle of the sidewall of the other portion. In addition, as shown in FIG. 41(E), the contact is formed at the interface between the oxide semiconductor layer and the first insulating layer. The diameter of the plug 63 may be changed. The diameter of the contact plug 63 may change inside the edge layer. The contact plug 63 may have a shape that is a combination of the shapes shown.

[0067] 6A and 6B are top views of a semiconductor device according to one embodiment of the present invention. 6A is a top view of the semiconductor device shown in FIG. 6B is a top view of the semiconductor device shown in FIG. Note that FIG. 1(A) and FIG. 4 correspond to the cross section taken along line P1-P2 shown in FIG. 6(A) and (B). In the figure, OS indicates an active layer made of an oxide semiconductor, and Si indicates a silicon active layer. Indicates the sexual area.

[0068] Another embodiment of the present invention is shown in FIG. A transistor 53 having an active region on the silicon substrate 40 and a transistor having an oxide semiconductor layer as an active layer The transistors 53 and 54 shown in FIG. In the connection of the capacitor 55, a circuit 91 shown in the circuit diagram of FIG. The semiconductor device shown in FIG. 7A has a capacitance element 55 and has a connection form of each element. Except for this, the semiconductor device can have the same structure as that shown in FIG.

[0069] Here, the gate electrode layer of the transistor 53 and the source electrode layer of the transistor 54 A contact is provided to electrically connect one of the drain electrode layers to one of the electrode layers of the capacitance element 55. The contact plug 66 is connected to the source electrode layer of the transistor 54. Or a through hole provided in one of the drain electrode layers (shared with one of the electrode layers of the capacitor element 55) Therefore, similar to the contact plug 63 shown in FIG. In the depth direction from the insulating layer toward the first insulating layer, the source electrode layer of the transistor 54 Alternatively, the diameter of the drain electrode layer is reduced at the interface between one of the drain electrode layers and the second insulating layer.

[0070] In FIG. 7A, the contact plugs 66 and 67 are located at positions in the depth direction. Since it is different from other contact plugs, it is indicated by different hatching.

[0071] When the structure of the transistor 52 shown in FIG. 4 is applied to the transistor 54, the transistor 54 shown in FIG. FIG. 9A is an example of a top view of the semiconductor device shown in FIG. FIG. 9B is an example of a top view of the semiconductor device shown in FIG. 8 corresponds to the cross section taken along line Q1-Q2 in FIGS. 9(A) and 9(B).

[0072] The circuit 91 shown in FIG. 7B is capable of retaining memory contents even when power is not supplied, and This is an example of a semiconductor device (memory circuit) that has no limit to the number of times it can be written.

[0073] The transistor 54 including an oxide semiconductor has electrical characteristics of extremely low off-state current. For example, when the voltage between the source and drain is 0.1 V, When the voltage is set to 5 V or 10 V, the off-state current is normalized by the channel width of the transistor. The current density can be reduced from several yA / μm to several zA / μm. Transistors made of other materials, such as crystalline silicon, are easier to operate at high speeds. Therefore, by combining the two, a memory with high data retention capacity and high speed operation can be created. The device can be configured.

[0074] In the semiconductor device shown in FIG. 7B, the potential of the gate electrode of the transistor 53 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows.

[0075] The writing and holding of data will be described. First, the potential of the wiring 77 is applied to the transistor 54. is set to an on-state potential, turning on the transistor 54.

[0076] By the above operation, the potential of the wiring 76 is applied to the gate electrode of the transistor 53 and the capacitor 5 5. That is, a predetermined charge is applied to the node FN (write). Here, charges that give two different potential levels (hereinafter, low level charge and high level charge) are Either the charge or the charge itself is given.

[0077] After that, the potential of the wiring 77 is set to a potential at which the transistor 54 is turned off. By turning off 54, the charge applied to the node FN is held (retained). Since the off-state current of the transistor 54 is extremely small, the charge of the node FN remains constant for a long time. Retained.

[0078] Next, reading of information will be described. With a predetermined potential (constant potential) applied to the wiring 75, When an appropriate potential (read potential) is applied to the wiring 78, the charge held in the node FN is In response, the wiring 79 assumes a different potential.

[0079] In general, if the transistor 53 is an n-channel type, the gate electrode ( The apparent threshold voltage V when a high-level charge is applied to the th_ H In this case, a low-level charge is applied to the gate electrode (node ​​FN) of the transistor 53. The apparent threshold voltage V th_L Lower.

[0080] Here, the apparent threshold voltage is the voltage required to turn on the transistor 53. Therefore, the potential of the wiring 78 is Vth_H and V th _L The potential V between 0 By this, the gate electrode (node ​​FN) of the transistor 53 It can distinguish a given charge.

[0081] For example, when a high level charge is applied in a write operation, the line 78 The potential is V 0 (>V th_H ), transistor 53 is in the "on state." When a level charge is applied, the potential of the wiring 78 becomes V 0 ( <V th_L ) Therefore, the potential of the wiring 79 is not determined. By doing so, the stored information can be read out.

[0082] When memory cells are arranged in an array, only the information in the desired memory cell is read. In this way, in memory cells that do not read information, The transistor 53 is turned "off" regardless of the potential applied to the output electrode. potential, that is, V th_H A smaller potential may be applied to the wiring 78. Regardless of the potential applied to the electrodes, transistor 53 is in the "on" state. Electric potential, i.e., V th_L A larger potential should be applied to the wiring 78 .

[0083] In the semiconductor device illustrated in FIG. 7B, an oxide semiconductor is used in the channel formation region, and the off-state current is By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. This makes it possible to reduce the frequency of the power consumption significantly. In addition, even if there is no power supply (although it is preferable that the potential is fixed), Even if the device is turned off, the contents can be stored for a long period of time. The device may perform an operation of supplying power thereto.

[0084] In addition, in the above-mentioned driving method, a high voltage is required to write information to the node FN. There is no problem of deterioration of the transistor 53. For example, Electrons are injected into the floating gate by applying a voltage, and electrons are released from the floating gate. Since there is no operation to pull out the transistor, problems such as deterioration of the gate insulating film of the transistor 53 are prevented. In other words, the semiconductor device according to the disclosed invention does not have the problem of the conventional nonvolatile memory. There is no limit to the number of times the memory can be rewritten, which has been a problem, and reliability is improved dramatically. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. can also be easily achieved.

[0085] Components of the semiconductor device according to one embodiment of the present invention will be described below. Although the semiconductor device shown in FIG. 1A will be described, other semiconductor devices shown in this embodiment will be described. The same is true for the body apparatus.

[0086] The silicon substrate 40 is not limited to a bulk silicon substrate, but may be an SOI substrate. Instead of the silicon substrate 40, germanium, silicon germanium, silicon carbide, gallium Materials include aluminum arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors. A substrate made of the same material as the material can also be used.

[0087] The transistor 51 is not limited to a planar type transistor, but may be of various types. For example, FIN type, TRI-GATE type, The transistor may be a gate type transistor or the like.

[0088] The insulating layer 81 can function as a protective film, and is typically a silicon nitride film or an aluminum oxide film. The insulating layer 82 and the insulating layer 87 function as a planarizing film. Typically, a silicon oxide film, a silicon oxynitride film, etc., can be used. can be done.

[0089] The insulating layer 83 can function as a hydrogen blocking film. Hydrogen in the insulating layer provided near the region terminates the dangling bonds of silicon, This has the effect of improving the reliability of the transistor 51. Hydrogen in the insulating layer provided near the oxide semiconductor layer, which is the active layer, is absorbed into the oxide semiconductor. This is one of the factors that generates carriers, which reduces the reliability of the transistor 52. Therefore, the upper layer of a transistor using a silicon-based semiconductor material is not When transistors using nitride semiconductors are stacked, hydrogen diffusion between them is prevented. It is preferable to provide an insulating layer 83 having a function of preventing hydrogen from being trapped in the lower layer. The confinement improves the reliability of the transistor 51 and also prevents hydrogen from penetrating from the lower layer to the upper layer. By suppressing the diffusion of the impurities, the reliability of the transistor 52 can be improved at the same time. can.

[0090] The insulating layer 83 may be made of, for example, silicon nitride, aluminum oxide, or aluminum oxynitride. , gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, halide Use hafnium, hafnium oxide nitride, yttria stabilized zirconia (YSZ), etc. The insulating layer 85 can also be made of these materials.

[0091] The insulating layer 84 serves as an oxygen source for the oxide semiconductor layer of the transistor 52 . Therefore, the insulating layer 84 is an insulating layer containing oxygen, and has a composition with more oxygen than the stoichiometric composition. In addition, the insulating layer 84 is preferably a gate electrode on the back gate side of the transistor 52. Since the oxide semiconductor layer can function as a gate insulating film, the defect-free It is preferable that the film is one that is less likely to generate

[0092] The insulating layer 84 can typically be a silicon oxide film or a silicon oxynitride film. In addition, the insulating layer may be a laminate of a silicon nitride film or a silicon oxynitride film and the insulating layer. The insulating layer 86 may also be made of these materials.

[0093] The contact plugs 61 to 65 are typically made of a metal material. Specifically, tungsten can be used. The contact plug can be Alternatively, titanium nitride may be provided on the wall surface, and tungsten may be provided inside the titanium nitride. The periphery layer and the top surface of the contact plug are planarized using CMP (Chemical Mechanical Planarization). A polishing technique can be used.

[0094] In this embodiment, one embodiment of the present invention will be described using a configuration of an inverter circuit and a memory circuit as an example. It is possible to apply this to other circuits. This also applies to cases where three or more transistors or other elements are electrically connected. It is possible.

[0095] In this embodiment, a transistor having a silicon active region and a transistor having an oxide semiconductor active region are In the above example, a transistor having a silicon-containing layer is stacked on a semiconductor device. However, the present invention is not limited to this. The present invention can also be applied to a case where a plurality of transistors are stacked. The present invention can also be applied to a case where a plurality of transistors are stacked.

[0096] Further, one embodiment of the present invention can also be applied to electrical connection of overlapping wirings.

[0097] FIG. 42 shows an example of an etching apparatus for etching a multi-layer film having a plurality of film types. The etching apparatus shown in FIG. C, and to temporarily hold the substrate while it is being moved to each etching chamber. A transfer chamber 820 for transferring etching gas to each etching chamber A gas supply system 830 supplies the gas, etc. It has a supply system, a pump system, and a gas abatement system.

[0098] To form fine openings in a multi-layer film with multiple film types, a parallel plate type etching device is used. In particular, it is preferable to use an etching device having a high-density plasma source. It is preferable to use an appropriate etching gas for etching each layer. It is preferable to have a gas supply system that allows for a selection of gases, especially one that combines multiple gases. It is preferable to have a gas supply system that can

[0099] For example, the formation of a fine opening in a multi-layer film having multiple film types can be achieved in one etching chamber. In this method, the optimum etching gas for each layer can be used. As shown in Figure 42, if the etching equipment has three etching chambers, multiple This allows multiple substrates to be processed simultaneously, improving production efficiency. Cut.

[0100] When etching a multi-layer film having multiple film types in one etching chamber, In the etching chamber, the gas is switched to the optimum gas depending on the type of film to be etched. Various etching products can deposit on the walls of the etching chamber. The particles may peel off from the walls of the chipping chamber and become particles. If it adheres to the surface, it may cause etching defects.

[0101] As a method for preventing the generation of such particles, The following is a method of etching using the etching apparatus shown in Figure 42. Here, an example of etching a multi-layer film having a plurality of film types will be shown. The object of the etching is a first insulating film, a second insulating film, a third insulating film, and an oxide semiconductor film. A conductive film, a fourth insulating film, an organic resin film, and a photoresist are formed on the substrate in this order. The photoresist is a laminated material formed by exposing and developing the photoresist to a desired shape. It has the following shape.

[0102] First, the substrate is placed in the etching chamber 810A, and the organic resin film and the fourth insulating film are Etching is then performed. The substrate is then transferred from the etching chamber 810A to the transfer chamber 810B. The substrate is then moved to an etching chamber 810B via a chamber 820, and the conductive film is etched. The substrate is then transferred from the etching chamber 810B to the transfer chamber 8 20, and then moved to the etching chamber 810A, where the oxide semiconductor film, the third insulating film, The insulating film and the second insulating film are then etched. The substrate is then removed from the etching chamber 810A. Then, the substrate is transferred to the etching chamber 810C via the transfer chamber 820. Then, by ashing, the products of previous etching are removed. The etching chamber 810C is transferred to the transfer chamber 820 via the transfer chamber 820. The substrate is then moved to an etching chamber 810A, where the first insulating film is etched. From the etching chamber 810A, the etching The photoresist and organic The resin film is removed.

[0103] Even if the structure has a multi-layer film, the above steps can be repeated to obtain a multi-layer structure. This makes it possible to form minute openings.

[0104] In the above example, multiple etching steps are used to etch a multilayer film having multiple film types. In this case, the substrate is transferred under vacuum and exposed to the air atmosphere. Since there is no need to use a single etching chamber, etching can be performed with good reproducibility. In this case, the etching gas is not switched for each film type. Therefore, the processing time is shortened. This makes it possible to increase production efficiency.

[0105] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0106] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. Note that, in the drawings in this embodiment, the For ease of illustration, some elements may be enlarged, reduced, or omitted.

[0107] 10A and 10B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 10(A) is a top view, and FIG. 10(A) is a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 10(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 16(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is sometimes called the channel width direction.

[0108] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, an insulating layer 190 (flattening film) that contacts the insulating layer 180 may be formed as necessary. It may have.

[0109] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0110] In addition, a region 231 shown in FIG. 10B is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are conductive regions. The conductive layers 140 and 150 are in contact with each other, for example, the conductive layers 140 and 150. If a conductive material that easily bonds with oxygen is used as 150, the resistance of the regions 231 and 232 can be reduced. It can be resistant.

[0111] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0112] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0113] In addition, the conductive layer 170 is illustrated as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0114] In addition, although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may be applied to other transistors described in this embodiment. can.

[0115] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 11A is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 11(B). Also, the dashed line C3 shown in FIG. The cross section in the -C4 direction corresponds to FIG. 16(B). The direction of the dashed dotted line C3-C4 may be referred to as the channel length direction, and the direction of the dashed dotted line C3-C4 may be referred to as the channel width direction.

[0116] The transistor 102 has an insulating layer 160 acting as a gate insulating film and a gate electrode layer. Similar to transistor 101 except that the end is not aligned with the active conductive layer 170. The structure of the transistor 102 includes a conductive layer 140 and a conductive layer 150 disposed between an insulating layer 16. 0, the resistance between the conductive layer 140 and the conductive layer 150 and the conductive layer 170 is It has the features of high resistance and low gate leakage current.

[0117] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. On the other hand, since no offset region is formed in the oxide semiconductor layer 130, a transistor with a high on-current is formed. It is easy to form a transistor.

[0118] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 12A is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 12(B). Also, the dashed line D3 shown in FIG. The cross section in the -D4 direction corresponds to FIG. 16(A). The direction of the dashed dotted line D3-D4 may be referred to as the channel length direction, and the direction of the dashed dotted line D3-D4 may be referred to as the channel width direction.

[0119] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer 190 (planarizing film) in contact with 150 may also be provided.

[0120] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0121] In addition, a region 231 shown in FIG. 12B is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. If an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0122] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0123] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 13A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 13(B). Also, the dashed line E3 shown in FIG. The cross section in the -E4 direction corresponds to FIG. 16(A). The direction of the dashed dotted line E3-E4 may be referred to as the channel length direction, and the direction of the dashed dotted line E3-E4 may be referred to as the channel width direction.

[0124] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0125] In addition, the regions 331 and 334 shown in FIG. 13B are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. Regions 331 and 332 correspond to regions 231 and 232 in transistor 101. The resistance can be reduced in the same manner as in the case of the transistor 2. The resistance can be reduced in the same manner as in the region 231 and the region 232 in the capacitor 103. The width of the region 334 and the region 335 in the channel length direction is preferably 100 nm or less. When the gate thickness is 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. It is also possible to adopt a configuration in which the above-mentioned resistance reduction is not performed.

[0126] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0127] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 14A is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 14(B). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 16(A). The direction of the dashed dotted line F3-F4 may be referred to as the channel length direction, and the direction of the dashed dotted line F3-F4 may be referred to as the channel width direction.

[0128] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer 190 (planarizing film) may be provided.

[0129] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0130] The transistor 105 includes a conductive layer 141 and a conductive layer 151, and an insulating layer 17. 5 and the insulating layer 180 through an opening formed therein. 1, except that it has conductive layers 142 and 152 electrically connecting them. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 101. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0131] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 15A is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 15(B). Also, the dashed line G3 shown in FIG. The cross section in the -G4 direction corresponds to FIG. 16(A). The direction of the dashed dotted line G3-G4 may be referred to as the channel length direction, and the direction of the dashed dotted line G3-G4 may be referred to as the channel width direction.

[0132] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, the insulating layer 180, the conductive layer 142, and the insulating layer 190 (flat) in contact with the conductive layer 152 are The substrate may have a support film, etc.

[0133] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0134] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0135] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0136] In addition, the region 231 and the region 232 in the transistor 103, the transistor 104, In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed and the conductor is formed. Impurities that cause oxygen vacancies in the oxide semiconductor layer may be added. Examples of the elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, and nitrogen. , helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium One or more selected from the group consisting of titanium, zinc, and carbon can be used. Methods for adding impurities include plasma treatment, ion implantation, ion doping, and plasma A Zumai immersion ion implantation method or the like can be used.

[0137] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0138] When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of an impurity element, Hydrogen enters the oxygen vacancy site and a donor level is formed near the conduction band. Therefore, the oxide conductor has a light-transmitting property. An oxide semiconductor that has been made into a conductor is called an oxide conductor.

[0139] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0140] In addition, the transistor of one embodiment of the present invention can be formed as shown in FIG. 18(A) and (B) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0141] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0142] In addition, in the transistors 101 to 106 in FIG. Although an example in which the oxide semiconductor layer 130 is a single layer is illustrated, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is 20. Alternatively, it can be replaced with the oxide semiconductor layer 130 shown in FIG.

[0143] 19A, 19B, and 19C are top views of an oxide semiconductor layer 130 having a two-layer structure. 19(A) is a top view, and FIG. 19(B) corresponds to the cross section in the direction of the dashed line A3-A4 shown in FIG. The cross section corresponds to FIG.

[0144] 20A, 20B, and 20C are top views of the oxide semiconductor layer 130 having a three-layer structure. 20(A) is a top view, and the dashed line A1- The cross section in the A2 direction corresponds to FIG. 20(B). Also, the dashed line A3-A shown in FIG. The cross sections in four directions correspond to FIG. 20(C).

[0145] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0146] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 21A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 21(B). Also, the dashed line H3 shown in FIG. The cross section in the -H4 direction corresponds to FIG. 27(A). The dashed line H1-H2 direction is the channel The longitudinal direction, the direction of the dashed dotted line H3-H4, may be referred to as the channel width direction.

[0147] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 in contact with the insulating layer 180. (flattening film) or the like.

[0148] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0149] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 22A is a top view of the transistor 108. The cross section in the 1-I2 direction corresponds to FIG. 22(B). Also, the dashed line I3 shown in FIG. The cross section in the -I4 direction corresponds to FIG. 27(B). The longitudinal direction, the direction of the dashed dotted line I3-I4, may be referred to as the channel width direction.

[0150] The transistor 108 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 102 .

[0151] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 23A is a top view of the transistor 109. The cross section in the 1-J2 direction corresponds to FIG. 23(B). The cross section in the -J4 direction corresponds to FIG. 27(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, may be referred to as the channel width direction.

[0152] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer 190 (planarizing film) in contact with the conductive layer 150 may be provided.

[0153] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0154] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 24A is a top view of the transistor 110. The cross section in the 1-K2 direction corresponds to FIG. 24(B). Also, the dashed line K3 shown in FIG. 24(A) The cross section in the -K4 direction corresponds to FIG. 27(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, may be referred to as the channel width direction.

[0155] The transistor 110 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0156] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 25A is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 25(B). Also, the dashed line L3 shown in FIG. The cross section in the -L4 direction corresponds to FIG. 27(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, may be referred to as the channel width direction.

[0157] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. It may also have an insulating layer 190 (planarization film) in contact with 52.

[0158] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide and the conductive layer 141 and the conductive layer 151 and the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 105 .

[0159] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 26A is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 26(B). The cross section in the -M4 direction corresponds to FIG. 27(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, may be referred to as the channel width direction.

[0160] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0161] In addition, the transistor of one embodiment of the present invention can be formed as shown in FIG. 29(A) and (B) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0162] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is a top view (oxide semiconductor layer 1) shown in FIG. As shown in FIG. 30, only the conductive layer 140 and the conductive layer 150 are shown, (W OS) of the conductive layer 140 and the conductive layer 150. SD ) is formed long It may be formed short. OS ≧W SD (W SD W OS (hereinafter) As a result, the gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electric field of the transistor The characteristics can be improved.

[0163] In the transistors of one embodiment of the present invention (transistors 101 to 112), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0164] In addition, a transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By passing a current through the conductor layer 130b, the device is less susceptible to the effects of interface scattering and a high on-current can be obtained. In addition, by increasing the thickness of the oxide semiconductor layer 130b, the on-current can be improved. For example, the thickness of the oxide semiconductor layer 130b can be set to 100 nm to 200 nm. Good too.

[0165] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0166] Note that in this specification, the channel length refers to, for example, the length of a semiconductor device when viewed from above in a top view of a transistor. A conductor (or the part of the semiconductor through which current flows when the transistor is on) and a gate The source (or source region) in the region where the electrode overlaps or the region where the channel is formed This refers to the distance between the source electrode (or drain region) and the drain (drain electrode). In addition, the channel length of a single transistor does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions in which the channel is formed. The value may be a maximum, minimum or average value.

[0167] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on-state). The region where the gate electrode overlaps with the current-carrying part of the gate electrode, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0168] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0169] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0170] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0171] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0172] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0173] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0174] The substrate 115 is a silicon substrate 40, an insulating layer 81, an insulating layer 82, and an insulating film 114 shown in FIG. This corresponds to a structure including an insulating layer 83. Note that only p-ch type transistors are formed on the silicon substrate. To form n - It is preferable to use a silicon substrate having a conductivity type of , n - The substrate may be an SOI substrate having a type or i-type silicon layer. The surface orientation of the silicon substrate on which the transistor is formed is preferably a (110) surface. A p-channel transistor is formed on a silicon substrate having a (110) surface. Thus, the mobility can be increased.

[0175] The insulating layer 120 corresponds to the insulating layer 84 in FIG. In addition, the insulating layer 140 serves to supply oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is an insulating film containing oxygen. It is preferable that the insulating film contains more oxygen than the stoichiometric composition. For example, , Thermal Desorption Spectroscopy (TDS) The amount of oxygen released, calculated as oxygen atoms, was 1.0×10 19 atom s / cm 3 The film surface temperature during the TDS analysis is The range of 100° C. to 700° C., or 100° C. to 500° C. is preferable. As mentioned above, when the substrate 115 is a substrate on which other devices are formed, the insulating layer 120 may be It also functions as an interlayer insulating film. In that case, CMP (chemical mechanical polishing) is used to make the surface flat. The planarization process should be performed using a method such as MIP (Mechanical Mechanical Polishing). is preferred.

[0176] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. It is also possible.

[0177] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are The details will be mainly explained for the case where the layers are stacked in order.

[0178] In addition, when the oxide semiconductor layer 130 is a single layer, the layer corresponding to the oxide semiconductor layer 130b can be used.

[0179] In addition, when the oxide semiconductor layer 130 has two layers, a layer corresponding to the oxide semiconductor layer 130a and In this case, a layer corresponding to the oxide semiconductor layer 130b is stacked in this order from the insulating layer 120 side. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are interchanged. It is also possible.

[0180] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is stacked on the oxide semiconductor layer 130 having a three-layer structure, or the three-layer structure Another oxide semiconductor layer may be inserted at any of the interfaces.

[0181] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). The electron affinity is the energy difference between the vacuum level and the top of the valence band (ionic The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the value of

[0182] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum of the oxide semiconductor layer 13 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be made of a thin oxide semiconductor.

[0183] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0184] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface state may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a can reduce the threshold voltage. As a result, variations in electrical characteristics such as the threshold voltage of the transistors can be reduced. In addition, the reliability of the transistor can be improved.

[0185] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0186] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0187] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c is at least indium (In) or It is preferable that the alloy contains lead (Zn). Alternatively, it is preferable that the alloy contains both In and Zn. In addition, in order to reduce variation in electrical characteristics of transistors using the oxide semiconductor, Both preferably include a stabilizer.

[0188] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, with other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0189] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0190] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0191] In addition, InMO 3 (ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metallic element or elements. Also, In 2 SnO 5 (ZnO) n (n>0, and and n is an integer) may be used.

[0192] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, 30a In:M:Zn=x 1 :y 1 :z 1 [Atomic ratio], the oxide semiconductor layer 130b is I n:M:Zn=x 2 :y 2 :z 2 [Atomic ratio], the oxide semiconductor layer 130c is In:M:Z n=x 3 :y 3 :z 3 [Atomic ratio], y 1 / x 1 and y 3 / x 3 y 2 / x 2 It is preferable that y is larger than y. 1 / x 1 and y 3 / x 3 Yes 2 / x 2 than 1. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, y 2 x 2 If this is the case, the electrical characteristics of the transistor will be stabilized. However, y 2 x 2 When the field effect mobility of the transistor becomes more than three times higher, Because y 2 x 2 It is preferable that the concentration is less than three times the concentration of the stoichiometric amount.

[0193] When Zn and O are excluded from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0194] The oxide semiconductor layer 130b is a semiconductor layer including the oxide semiconductor layer 130a and the oxide semiconductor layer 130. It is preferable to have a higher indium content than c. In oxide semiconductors, the s orbital of heavy metals is the The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are formed. Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the mobility of the oxide semiconductor layer 130b is higher than that of the oxide semiconductor layer 130b. By using oxides with a high content of sodium, a transistor with high field effect mobility can be realized. It is possible.

[0195] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less. More preferably, the thickness of the oxide semiconductor layer 130c is set to 15 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. It is preferable that the thickness of the oxide semiconductor layer 30a is larger than that of the oxide semiconductor layer 130c.

[0196] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic (i-type) or It is effective to make the oxide semiconductor layer substantially intrinsic. Rear density is 1×10 17 / cm 3 Preferably less than 1 x 10 15 / cm 3 Not yet More preferably, it is less than 1×10 13 / cm 3 It means that it is less than.

[0197] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in layer 130c and at each interface.

[0198] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) In the case of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm3 less than , and more preferably 1×10 18 atoms / cm 3 The hydrogen concentration is, for example, For example, at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. , 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Below or less, more preferably 1×10 19 atoms / cm 3 Less than 5×10, more preferably 1 8 atoms / cm 3 The nitrogen concentration is, for example, In the thickness or in a region of the oxide semiconductor layer, 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following do.

[0199] In addition, when the oxide semiconductor layer contains crystals and contains silicon or carbon at a high concentration, the oxide In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, For example, at a certain depth in the oxide semiconductor layer or in a certain region of the oxide semiconductor layer In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm3 less than 1×10 18 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, , the carbon concentration in a certain region of the oxide semiconductor layer is set to 1×10 19 atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It is sufficient that the part is less than

[0200] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or approximately 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0201] In addition, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not contact the gate insulating film like a gate insulating film is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field effect mobility of the transistor. It is preferable that the region of the oxide semiconductor layer that serves as a channel is separated from the gate insulating film. .

[0202] Therefore, the oxide semiconductor layer 130 is divided into an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel is formed in the oxide semiconductor layer 130b. Thus, a transistor having high field effect mobility and stable electrical characteristics can be formed. It is possible to form a

[0203] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers having different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0204] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0205] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: 9:6 (atomic ratio), and in the oxide semiconductor layer 130b, In:Ga:Zn=1:1:1, 2: In-Ga, such as 1:3, 5:5:6, 3:1:2, or 4:2:4.1 (atomic ratio) The oxide semiconductor layer 130a may be formed of an oxide semiconductor The atomic ratios of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c are each calculated based on the above formula as an error. This includes a fluctuation of plus or minus 40% in the child ratio.

[0206] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well. In the transistor using the semiconductor layer 130, the channel is formed in the oxide semiconductor layer 130b. In addition, the oxide semiconductor layer 130 has a conduction band minimum that changes continuously. The channel formed in this way can also be called a U-shaped well. can also be called a buried channel.

[0207] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a method of forming a silicon oxide film or the like. In the vicinity of the interface with the insulating layer, trap levels due to impurities or defects may be formed. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c makes it possible to form the oxide semiconductor layer 13 This makes it possible to keep 0b away from the trap level.

[0208] However, the energy minimum of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the conduction band minimum of the oxide semiconductor layer 130b and the energy of the oxide semiconductor layer 130c is small, Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, causing the transistor to turn off. The threshold voltage of the transistor is shifted in the positive direction.

[0209] Therefore, in order to reduce the variation in the threshold voltage of the transistor, the oxide semiconductor layer 130 a and the conduction band minimum of the oxide semiconductor layer 130c, and the oxide semiconductor layer 130b It is necessary to provide a certain difference between the conduction band minimum energy of The energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0210] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0211] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Representative examples include Ti, which is particularly susceptible to bonding with oxygen, and the fact that the subsequent process temperature can be relatively high. For these reasons, it is more preferable to use W, which has a high melting point. In addition, Cu and Cu-M, which have low resistance, are also preferable. A laminate of an alloy such as n and the above material may be used. In the transistors 106, 111, and 112, for example, the conductive layer 14 The conductive layers 142 and 152 are laminated films of Ti and Al. etc. can be used.

[0212] The above material has a property of extracting oxygen from the oxide semiconductor film. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0213] In addition, when W is used for the conductive layer 140 and the conductive layer 150, it is possible to dope the W with nitrogen. By doping with nitrogen, the oxygen-pulling property can be moderately weakened, resulting in n-type In addition, the conductive layer can be prevented from expanding to the channel region. The n-type semiconductor layer is laminated with the oxide semiconductor layer, and the n-type semiconductor layer is brought into contact with the oxide semiconductor layer. Even if the n-type semiconductor is used, it is possible to prevent the n-type region from expanding into the channel region. The layers are nitrogen-doped In-Ga-Zn oxide, zinc oxide, indium oxide, and oxide. Tin oxide, indium tin oxide, etc. can be used.

[0214] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. ), nitrogen, zirconium (Zr), etc. may be contained as impurities.

[0215] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0216] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. The dielectric constant is high. Therefore, the physical thickness can be made larger than the equivalent oxide thickness. Even if the thickness of the valence oxide film is set to 10 nm or less or 5 nm or less, the leakage current due to the tunnel current is In other words, a transistor with a small off-state current can be realized. Furthermore, hafnium oxide having a crystalline structure can be used in combination with hafnium oxide having an amorphous structure. Therefore, in order to make a transistor with a small off-current, For this purpose, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal system include monoclinic and cubic crystal systems. However, one embodiment of the present invention is not limited to these. I can't.

[0217] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When a conductor is in contact with the oxide semiconductor, the density of the nitrogen oxide levels in the energy gap of the oxide semiconductor increases. The insulating layer 120 and the insulating layer 160 may be resistant to, for example, the emission of nitrogen oxides. An oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film with a low outflow is used. It is possible.

[0218] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, has a low nitrogen oxide emission rate in TDS. This is a membrane that releases more ammonia than the amount of ammonia released. 10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is the result of the TDS analysis. The surface temperature of the film is 50°C to 650°C or 50°C to 550°C. A range is preferred.

[0219] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0220] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine atom.

[0221] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0222] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film improves the electrical properties of the transistor during and after the transistor manufacturing process. Preventing impurities such as hydrogen and moisture, which are factors that cause fluctuations in the oxide semiconductor layer 130, from entering the oxide semiconductor layer 130; Preventing the release of oxygen, which is the main component material constituting the semiconductor layer 130, from the oxide semiconductor layer and insulating it It is suitable for use as a protective film having the effect of preventing unwanted release of oxygen from layer 120. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. can.

[0223] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0224] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0225] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the ON voltage is reduced, the ON current decreases.

[0226] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0227] In addition, in the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side direction in addition to a gate electric field from the vertical direction. In other words, the gate electric field is applied to the entire channel formation layer. Since the effective channel width is increased by adding a second gate, the on-current can be further increased.

[0228] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. First, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. In addition, the oxidation of the oxide film according to one embodiment of the present invention has an effect of making it difficult for an interface state to be formed. In a transistor having a three-layer structure of the oxide semiconductor layer 130, the oxide semiconductor layer 130b is disposed in the middle of the three-layer structure. By placing the layer in the position above the object, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor, the threshold voltage is stabilized. It is possible to reduce the S value (subthreshold value). (current when gate voltage VG is 0V) can be lowered, reducing power consumption. In addition, the threshold voltage of the transistor is stabilized, which improves the long-term reliability of the semiconductor device. In addition, the transistor of one embodiment of the present invention can be miniaturized. Since the deterioration of electrical characteristics can be suppressed, it is suitable for forming highly integrated semiconductor devices. I can say.

[0229] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0230] (Embodiment 4) In this embodiment, the transistor 101 and the transistor 107 described in the second embodiment are A method for manufacturing the transistor 111 will be described.

[0231] First, an example of a method for manufacturing a silicon transistor included in the substrate 115 will be described. As for the n substrate,- A single crystal silicon substrate is used, and an insulating layer (field oxide film) is applied to the surface. The element formation regions are formed by the LOCOS method ( Local Oxidation of Silicon (STI) method and Shall Low Trench Isolation, etc. can be used.

[0232] Here, the substrate is not limited to a single crystal silicon substrate, but may be SOI (Silicon on Insul A substrate such as a photodiode may also be used.

[0233] Next, a gate insulating film is formed so as to cover the element formation region. The surface of the deposition region is oxidized to form a silicon oxide film. After the formation of the silicon oxide film, a nitriding treatment may be performed to nitride the surface of the silicon oxide film.

[0234] Next, a conductive film is formed to cover the gate insulating film. The conductive film is made of tantalum (Ta). , Tungsten (W), Titanium (Ti), Molybdenum (Mo), Aluminum (Al), Elements selected from copper (Cu), chromium (Cr), niobium (Nb), etc. or these elements The material may be an alloy or compound material mainly composed of these elements. It can also be formed of a metal nitride film made by nitriding silicon. Alternatively, the insulating layer 11 may be formed from a semiconductor material such as polycrystalline silicon.

[0235] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film. Form.

[0236] Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the gate electrode layer. Then, etch-back is performed to form sidewalls on the side surfaces of the gate electrode layer.

[0237] Next, a resist mask is selectively formed so as to cover areas other than the element formation area. By introducing impurity elements using the mask and gate electrode layer, p + Type Impurity In this case, to form a p-channel transistor, the impurity element and For this purpose, boron (B) or gallium (Ga), which are impurity elements that impart p-type conductivity, is used. This can be done.

[0238] This completes the fabrication of a p-channel transistor with an active region on the silicon substrate. A passivation film such as a silicon nitride film or an aluminum oxide film is formed on the transistor. It is preferable to form

[0239] Next, an interlayer insulating film is formed on the silicon substrate on which the transistors are formed, and various contact plates are Lugs and various wiring are formed. Also, as explained in the first embodiment, the diffusion of hydrogen is prevented. An insulating layer such as aluminum oxide is formed on the substrate 115. The insulating film includes a silicon substrate on which a semiconductor device is formed, and an interlayer insulating film formed on the silicon substrate.

[0240] Next, a manufacturing method of the transistor 101 will be described with reference to FIGS. The left side of the drawing shows a cross section of the transistor in the channel length direction, and the right side shows a cross section in the channel width direction. The cross section is shown. The drawing in the channel width direction is an enlarged view, so the apparent film thickness of each element is shown on the left. It is different in the drawing on the right.

[0241] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The oxide semiconductor layer 130 has a three-layer structure. In this case, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are formed as two layers. When the conductor layer 130 has a single-layer structure, it is sufficient to form the conductor layer 130 into one layer of the oxide semiconductor layer 130b.

[0242] First, an insulating layer 120 is formed on a substrate 115. The type of substrate 115 and the insulating layer 120 The material can be referred to the description of the third embodiment. The insulating layer 120 is formed by sputtering. , CVD method, MBE (Molecular Beam Epitaxy) method, etc. It can be formed.

[0243] In addition, the insulating layer 120 is subjected to ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by implantation, plasma treatment, or the like. By adding the oxygen, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 is further facilitated. It can be made easier.

[0244] Note that the surface of the substrate 115 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no effect of scattering, the insulating layer 120 may be omitted.

[0245] Next, an oxide semiconductor film 130A that will become the oxide semiconductor layer 130a is formed on the insulating layer 120. The oxide semiconductor film 130B which becomes the semiconductor layer 130b and the oxide semiconductor film 130c which becomes the oxide semiconductor layer 130c are The oxide semiconductor film 130C is formed by sputtering, CVD, MBE, or the like (FIG. 3 1(A)).

[0246] When the oxide semiconductor layer 130 has a stacked structure, the oxide semiconductor film is Using a multi-chamber deposition device (e.g., a sputtering device), each layer is exposed to the atmosphere. It is preferable to laminate the layers continuously without causing any damage to the sputtering device. In order to remove as much water and other impurities as possible from semiconductors, a cryopump is used. High vacuum evacuation (5×10) using a suction type vacuum pump -7 Pa~1×10 -4 Pa degree and the substrate on which the film is to be formed can be heated to 100°C or higher, preferably 500°C or higher. It is preferable to be able to heat the gas. Alternatively, a turbomolecular pump and a cold trap can be combined. It is important to prevent gas containing carbon components and moisture from flowing back into the chamber from the exhaust system. It is also preferable to use an exhaust system that combines a turbo molecular pump and a cryopump. Good too.

[0247] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of the sputtering gas. , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, moisture or the like is prevented from being taken into the oxide semiconductor film as much as possible. This can be prevented.

[0248] The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C are The material described in Embodiment 3 can be used. For example, the oxide semiconductor film 130A In:Ga:Zn=1:3:6, 1:3:4, 1:3:3 or 1:3:2 [atomic ratio In the oxide semiconductor film 130B, the In-Ga-Zn oxide of In:Ga:Zn=1:1:1 In-Ga-Zn oxide with atomic ratios of 3:1:2, 5:5:6 or 4:2:4.1 The oxide semiconductor film 130C has a composition of In:Ga:Zn=1:3:6, 1:3:4, 1:3:3, or the like. Alternatively, In-Ga-Zn oxide with an atomic ratio of 1:3:2 can be used. The nitride semiconductor film 130A and the oxide semiconductor film 130C are formed of an oxide such as gallium oxide. In addition, when the sputtering method is used for the film formation method, the above-mentioned materials are used as a target. The oxide semiconductor film 130A and the oxide semiconductor film 13 The atomic ratios of the oxide semiconductor film 130B and the oxide semiconductor film 130C are each calculated by subtracting the above atomic ratios from the atomic ratios as an error. For example, the material In:Ga:Zn=4:2:4.1 The atomic ratio of the film formed by sputtering using the material as a target was In:Ga:Zn=4: Sometimes it can be 2:3.

[0249] However, as described in detail in the third embodiment, the oxide semiconductor film 130B contains an oxide semiconductor A material having a larger electron affinity than the oxide semiconductor film 130A and the oxide semiconductor film 130C is used.

[0250] Note that the oxide semiconductor film is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0251] After the oxide semiconductor film 130C is formed, a first heat treatment may be performed. , at a temperature of 250°C or more and 650°C or less, preferably 300°C or more and 500°C or less, The reaction may be carried out in a nitrogen atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere of the first heat treatment is an inert gas atmosphere, and then the desorbed oxygen is replenished. In order to prevent this, the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas. The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C The crystallinity of the insulating layer 120, the oxide semiconductor film 130A, and the oxide semiconductor film 130 are increased. Impurities such as hydrogen and water can be removed from B and the oxide semiconductor film 130C. Note that the first heat treatment is performed on the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, This may also be performed after the etching for forming the oxide semiconductor layer 130c.

[0252] Next, a conductive layer is formed on the oxide semiconductor film 130C. The conductive layer is formed, for example, by the following method. It can be formed by

[0253] First, a first conductive film is formed on the oxide semiconductor film 130C. l, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and related metallic materials A single layer or a laminate of materials selected from the alloys above may be used.

[0254] Next, a negative resist film is formed on the first conductive film, and an electron beam is applied to the resist film. The first layer is exposed to light using a method such as immersion exposure, liquid immersion exposure, or EUV exposure, and then developed. A resist mask is formed. An organic layer is placed between the first conductive film and the resist film as an adhesive. It is preferable to form a coating film. Also, the first A resist mask of the above may be formed.

[0255] Next, the first conductive film is selectively etched using the first resist mask to form a first resist. The resist mask is then ashed to form a conductive layer.

[0256] Next, the conductive layer is used as a hard mask to form an oxide semiconductor film 130A. 130B and the oxide semiconductor film 130C are selectively etched to remove the conductive layer. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The oxide semiconductor layer 130 is formed by stacking the above-mentioned conductive layers (see FIG. 31B). The oxide semiconductor layer 130 may be formed using the first resist mask without forming a layer. Here, oxygen ions may be implanted into the oxide semiconductor layer 130.

[0257] Next, a second conductive film is formed so as to cover the oxide semiconductor layer 130. The material that can be used for the conductive layer 140 and the conductive layer 150 described in the third embodiment The second conductive film can be formed by a method such as sputtering, CVD, or MBE. There can be.

[0258] Next, a second resist mask is formed on the portions that will become the source and drain regions. Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150. (See Figure 31(C)).

[0259] Next, an insulating film 160A is formed on the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150. The insulating film 160A can be used for the insulating layer 160 described in the third embodiment. The insulating film 160A can be formed by a method such as sputtering, CVD, or MBE. etc. can be used.

[0260] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. By the second heat treatment, oxygen is removed from the insulating layer 120 to the oxide semiconductor layer 1 The second heat treatment can be omitted and the third heat treatment can be performed. The above effect may be obtained by the above-mentioned theory.

[0261] Next, a third conductive film 171A and a fourth conductive film 172A, which will become the conductive layer 170, are formed on the insulating film 160A. The third conductive film 171A and the fourth conductive film 172A are formed as in the embodiment. The conductive layer 171 and the conductive layer 172 may be formed of a material that can be used for the conductive layer 171 and the conductive layer 172 described in 3. The third conductive film 171A and the fourth conductive film 172A may be formed by a sputtering method, a CVD method, or the like. The deposition method, MBE method, etc. can be used.

[0262] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 32(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed by using the resist mask. 72A and the insulating film 160A are selectively etched to form the conductive layer 171 and the conductive layer 172. The conductive layer 170 and the insulating layer 160 are formed (see FIG. 32(B)). If the insulating film 160A is not etched, the transistor 102 can be fabricated. Cut.

[0263] Next, the oxide semiconductor layer 130, the conductive layer 140, the conductive layer 150, the insulating layer 160 and the conductive layer An insulating layer 175 is formed on the insulating layer 170. For the material of the insulating layer 175, see the description of the third embodiment. In the case of the transistor 101, an aluminum oxide film is preferably used. The insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, or the like. .

[0264] Next, the insulating layer 180 is formed on the insulating layer 175 (see FIG. 32(C)). For the material, the description of the third embodiment can be referred to. In addition, the insulating layer 180 is formed by sputtering. The method may be the CVD method, MBE method, or the like.

[0265] In addition, the insulating layer 175 and / or the insulating layer 180 may be subjected to ion implantation, ion doping, Using plasma immersion ion implantation and plasma treatment methods, etc. By adding oxygen, the insulating layer 175 and / or the insulating layer 1 This makes it easier to supply oxygen from the electrode 80 to the oxide semiconductor layer 130 .

[0266] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed by removing the insulating layer 120, the insulating layer 175, and the insulating layer 18. 0, excess oxygen is easily released, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. can be done.

[0267] Next, a method for manufacturing the transistor 107 will be described. Detailed explanation of the steps overlapping with the manufacturing method of 01 will be omitted.

[0268] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a and a The oxide semiconductor film 13A is an oxide semiconductor film 130b. A film of 0B is formed by using a method such as sputtering, CVD, or MBE (see FIG. 33(A)).

[0269] Next, a first conductive film is formed on the oxide semiconductor film 130B, and the first A conductive layer is formed using a resist mask. Then, the conductive layer is subjected to an acid treatment using the resist mask as a hard mask. The conductive semiconductor film 130A and the oxide semiconductor film 130B are selectively etched to form the conductive layer 130A. The layers are removed to form a stack of oxide semiconductor layers 130a and 130b. (See FIG. 33(B)). Note that a hard mask is not formed, and the first resist mask is used. Here, the stack may be formed using the oxide semiconductor layer 130a and the oxide semiconductor Oxygen ions may be implanted into the layer 130b.

[0270] Next, a second conductive film is formed so as to cover the stacked layer. A second resist mask is formed on the portion to be the gate region, and the second resist mask is used to Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150 ( See Figure 33(C).

[0271] Next, a conductive layer is formed on the stack of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. 140 and the conductive layer 150, an oxide semiconductor film 130C which becomes an oxide semiconductor layer 130c is formed. Further, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0272] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 34(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed by using the resist mask. 72A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form a conductive A conductive layer 170 consisting of a layer 171 and a conductive layer 172, an insulating layer 160, and an oxide semiconductor The insulating film 160A and the oxide semiconductor layer 130c are formed (see FIG. 34B). The film 130C is etched using a fourth resist mask to form the transistor 108. can be produced.

[0273] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 140, conductive layer 150, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed over the conductive layer 170 (see FIG. 34(C)).

[0274] Through the above steps, the transistor 107 can be manufactured.

[0275] Next, a method for manufacturing the transistor 111 will be described. Detailed explanation of the steps overlapping with the manufacturing method of 01 will be omitted.

[0276] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a and a The oxide semiconductor film 13A is an oxide semiconductor film 130b. Then, the first conductive film is formed on the 0B film by using a sputtering method, a CVD method, an MBE method, or the like. A conductive layer 141a is formed over the oxide semiconductor film 130B using a first resist mask. (See FIG. 35(A)).

[0277] Then, the oxide semiconductor film 130A and the oxide semiconductor The oxide semiconductor layer 130a and the oxide semiconductor layer 130b are selectively etched. b and the conductive layer 141a (see FIG. 35B). Oxygen ions may be implanted into the semiconductor layer 130a and the oxide semiconductor layer 130b.

[0278] Next, a second resist mask is formed on the portions that will become the source region and the drain region; Part of the conductive layer 141a is etched using the second resist mask, and the conductive layer 141 Then, a conductive layer 151 is formed (see FIG. 35C).

[0279] Next, a conductive layer is formed on the stack of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. An oxide semiconductor film 130C that becomes an oxide semiconductor layer 130c is formed on the conductive layer 151. Further, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0280] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 36(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed by using the resist mask. 72A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form a conductive A conductive layer 170 consisting of a layer 171 and a conductive layer 172, an insulating layer 160, and an oxide semiconductor A layer 130c is formed (see FIG. 36(B)).

[0281] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 141, conductive layer 151, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed on the conductive layer 170 .

[0282] Next, openings are formed in the insulating layer 175 and the insulating layer 180 reaching the conductive layer 141 and the conductive layer 151. A fifth conductive film is formed so as to cover the opening. A fourth resist mask is provided, and the fifth conductive film is selectively etched using the fourth resist mask. Then, etching is performed to form the conductive layer 142 and the conductive layer 152 (see FIG. 36C).

[0283] Through the above steps, the transistor 111 can be manufactured.

[0284] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are typically The can be formed by sputtering or plasma CVD, but other methods, such as thermal The insulating layer may be formed by a CVD method. An example of a thermal CVD method is MOCVD (Metal O Organic Chemical Vapor Deposition (ALD) method These include the Atomic Layer Deposition (ALD) method.

[0285] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0286] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0287] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially The gas may be introduced into the chamber and the film may be formed by repeating the gas introduction sequence. For example, By switching between the switching valves (also called high-speed valves), two or more types of raw materials can be mixed. The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the multiple source gases. At the same time or after this, an inert gas (argon, nitrogen, etc.) is introduced to If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second raw material gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later, forming a thin film. This process is repeated several times while controlling the gas introduction sequence until the desired thickness is formed. The thickness of the thin film can be adjusted by repeating the gas introduction sequence. The number of repetitions can be adjusted to allow precise film thickness adjustment, and fine F This is suitable for producing ET.

[0288] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a Zn-O film, trimethylindium, trimethylgallium, and Dimethyl zinc can be used. The chemical formula for trimethylindium is In(C H 3 ) 3 The chemical formula for trimethylgallium is Ga(CH 3 ) 3 Also, The chemical formula for dimethylzinc is Zn(CH 3 ) 2 In addition, the combination is limited to these. Instead of trimethylgallium, triethylgallium (chemical formula Ga(C 2 H 5 ) 3 ) Diethyl zinc (chemical formula Zn(C)) can also be used instead of dimethyl zinc. 2 H 5 ) 2 ) can also be used.

[0289] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis The raw material gas was vaporized with trimethylsilyl dimethylamide hafnium (TDMAH) as an oxidizing agent. Zon (O 3 Two types of gases are used: tetrakisdimethylamidohafnium The formula is Hf[N(CH 3 ) 2 ] 4 Other liquid materials include tetrakis(ethoxy) (dimethylamido) hafnium.

[0290] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) The raw gas is oxidized and H 2 Two types of gases are used: trimethylammonia, trimethylphenylacetone, and trimethylphenylacetone. The chemical formula for aluminum is Al(CH 3 ) 3 Other liquid materials include Tris(diisopropyl alcohol, Methylamido)aluminum, triisobutylaluminum, aluminum tris(2, 2,6,6-tetramethyl-3,5-heptanedionate).

[0291] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O 2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0292] For example, when forming a tungsten film using a deposition system that uses ALD, the WF 6 G S and B 2 H 6 The gases are introduced repeatedly in sequence to form an initial tungsten film, and then WF 6 Gas and H 2 Gases are introduced simultaneously to form a tungsten film. 2 H 6 Instead of gas SiH 4 A gas may also be used.

[0293] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH 3 ) 3 Gas and O 3 Gases were introduced repeatedly in sequence to O layer, and then Ga(CH 3 ) 3 Gas and O 3 Gas is introduced simultaneously to form the Ga-O layer. Then Zn(CH 3 ) 2 and O 3 Gases are introduced simultaneously to form a Zn-O layer. The order of these layers is not limited to this example. In addition, by mixing these gases, In-Ga Alternatively, a mixed compound layer such as an In-Zn-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. Oh, O 3 H obtained by bubbling inert gas such as Ar instead of gas 2 O gas However, it is not possible to use 3 It is preferable to use In(CH 3 ) 3 gas Instead, In(C 2 H5 ) 3 Gas may also be used. 3 ) 3 Change to gas Ga(C 2 H 5 ) 3 Gas may also be used. 3 ) 2 Gas may be used. stomach.

[0294] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0295] (Embodiment 5) <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0296] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0297] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0298] Oxide semiconductors are classified into, for example, non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Alternatively, oxide semiconductors can be divided into crystalline oxide semiconductors and amorphous oxide semiconductors, for example. can be.

[0299] As the non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors made of crystalline oxides include semiconductors made of microcrystalline oxides and amorphous oxides. The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0300] First, let me explain about CAAC-OS.

[0301] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0302] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of CAAC-OS were obtained by using a high-resolution microscope. By observing the TEM image, multiple pellets can be confirmed. On the other hand, the high-resolution TEM image also clearly shows the boundaries between pellets, i.e., grain boundaries. Therefore, CAAC-OS cannot check the boundary between the It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0303] For example, as shown in FIG. 43(A), a cross section of the CAAC-OS is taken from a direction approximately parallel to the sample surface. Here, a high-resolution TEM image of the sample is observed. The TEM image is observed using the spherical convergence corrector function. Hereinafter, the high-resolution TEM image using the differential correction function will be referred to as the Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM images were obtained using, for example, an atomic resolution TEM manufactured by JEOL Ltd. This can be done using an analytical electron microscope such as the JEM-ARM200F.

[0304] FIG. 43(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 43(A). From FIG. 43(B), it can be seen that the metal atoms are arranged in layers in the pellet. Each layer of metal atoms is formed on the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed) or on the The shape reflects the unevenness of the surface, and is aligned parallel to the surface on which the CAAC-OS is formed or the top surface. .

[0305] In FIG. 43(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines. From Figure 43(B) and Figure 43(C), The size of each pellet is about 1 nm to 3 nm, and the inclination between pellets is about 1 nm to 3 nm. The size of the gap caused by the crack is about 0.8 nm. The nanocrystal may also be called a nanocrystal (nc).

[0306] Here, from the Cs-corrected high-resolution TEM image, the pellet 5 of CAAC-OS on the substrate 5120 was A schematic diagram of the arrangement of 100 would resemble a pile of bricks or blocks. (See FIG. 43(D).) The inclination between the pellets observed in FIG. 43(C) The location where this occurs corresponds to the area 5161 shown in FIG.

[0307] For example, as shown in FIG. 44(A), the CAAC-OS Observe the Cs-corrected high-resolution TEM images of the planes of regions (1) and (2) in Figure 44(A). The Cs-corrected high-resolution TEM images of the enlarged areas (a) and (b) are shown in Fig. 4(B) and Fig. 4(C), respectively. 44(B), 44(C) and 44(D). The pellets were then inspected to ensure that the metal atoms were arranged in triangular, quadrangular or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0308] For example, InGaZnO 4 X-ray diffraction (XRD) was performed on CAAC-OS with the crystal structure Using the out-of-plane method with a 3D ray diffraction (RF) device, When structural analysis was performed, a peak appeared at a diffraction angle (2θ) of approximately 31°, as shown in Figure 45(A). This peak may occur in InGaZnO 4 It is attributed to the (009) plane of the crystal of Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. You can see that it is pointing in the right direction.

[0309] In addition, InGaZnO 4 The out-of-plane method of CAAC-OS with crystals In the structural analysis by NMR, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° may be due to the c-axis orientation in some CAAC-OS. This indicates that the CAAC-OS contains crystals that do not have a peak at 2θ of around 31°. It is preferable that the compound exhibits a peak at 2θ of about 36° and does not exhibit a peak at 2θ of about 36°.

[0310] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In GaZnO 4In the case of CAAC-OS, the 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. And InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed at around 56° and φ When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0311] Next, the In-Ga-Zn oxide CAAC-OS was subjected to a plasmon resonance in a direction parallel to the sample surface. Diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident (selected area transmission electron diffraction The pattern is shown in FIG. 46(A). O 4 The spots due to the (009) plane of the crystal are confirmed. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the On the other hand, the same sample had a surface perpendicular to the sample surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from the direction is shown in Fig. 46(B ) is shown. From FIG. 46(B), a ring-shaped diffraction pattern is confirmed. Therefore, Diffraction analysis also revealed that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. It can be seen that the first ring in FIG. 46(B) is made of InGaZnO 4 Crystal This is thought to be due to the (010) and (100) planes. The second ring is thought to be due to the (110) plane.

[0312] In this way, the c-axis of each pellet (nanocrystal) is approximately perpendicular to the surface on which the pellet is formed or the top surface. Because of the direction, CAAC-OS is aligned with CANC (C-Axis Aligned The oxide semiconductor may also be referred to as an oxide semiconductor having nanocrystals.

[0313] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are The removal of oxygen from the oxide semiconductor disrupts the atomic arrangement of the oxide semiconductor, which is a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Since the radius of the oxide semiconductor is large, when the oxide semiconductor is contained in the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed. Impurities contained in an oxide semiconductor can cause carrier transport and lead to a decrease in crystallinity. These may be sources of tripping or carrier generation.

[0314] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen deficiencies in the body act as carrier traps or capture hydrogen to reduce the amount of carriers. It can be a source of pollution.

[0315] In addition, transistors using CAAC-OS show changes in their electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0316] Next, a microcrystalline oxide semiconductor will be described.

[0317] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- In addition, nc-OS is a In high-resolution TEM images, the grain boundaries may not be clearly visible. It is possible that the pellets in AAC-OS have the same origin. Therefore, in the following, The crystalline part of c-OS is sometimes called a pellet.

[0318] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks were detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. When nanobeam electron diffraction was performed on the OS, multiple spots were observed within the ring-shaped region. There may be cases where this occurs.

[0319] In this way, the crystal orientation of each pellet (nanocrystal) is not regular. nc-OS has NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0320] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0321] Next, the amorphous oxide semiconductor will be described.

[0322] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystal parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0323] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0324] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. In contrast, when nanobeam electron diffraction is performed, no spots are observed, but a halo pattern is observed. can be.

[0325] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, the distance between the nearest neighbors or the second nearest neighbors is called the A structure that has order but no long-range order is sometimes called an amorphous structure. According to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. In addition, oxides with at least long-range order cannot be called solid oxide semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, the CAAC-OS and nc-OS are It cannot be called a compound semiconductor.

[0326] Note that the oxide semiconductor has a structure that exhibits physical properties between the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. (a-like OS:amorphous-like Oxide Semiconductor It is called a uctor.

[0327] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0328] The following describes how the effect of electron irradiation differs depending on the structure of the oxide semiconductor.

[0329] We prepared a-like OS, nc-OS and CAAC-OS. -Ga-Zn oxide.

[0330] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0331] In addition, the size of the crystal part of each sample is measured. Figure 47 shows the crystal part of each sample (from 22 points). This is an example of investigating the change in the average size of the 45 locations. It can be seen that the crystal part grows larger according to the cumulative dose of electron irradiation. As shown in (1) in 47, the size of the particles was about 1.2 nm in the initial stage of TEM observation. The crystal part (also called the initial nucleus) that was initially exposed to a cumulative irradiation dose of 4.2 × 10 8 e - / nm 2 Smell On the other hand, the size of the nc-OS and C The AAC-OS had a cumulative electron dose of 4.2 × 10 8 e - / nm 2 To It was found that the size of the crystals did not change regardless of the cumulative dose of electron irradiation until the crystals were Specifically, as shown in (2) in Figure 47, regardless of the course of TEM observation, The size of the crystals is about 1.4 nm. As shown above, the size of the crystals is about 2.1 nm regardless of the TEM observation process. You can understand.

[0332] In this way, a-like OS can be observed by irradiating it with a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, good quality nc-OS and In the case of CAAC-OS, crystallization due to minute electron irradiation, which is comparable to that observed with a TEM, is hardly observed. You can see that it cannot be seen.

[0333] The size of the crystalline parts of the a-like OS and nc-OS was measured using high-resolution TEM. For example, InGaZnO 4 The crystal of In has a layered structure. There are two Ga-Zn-O layers between the InGaZnO 4 The unit cell of the crystal is It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is determined by the lattice of the (009) plane. This is approximately the same as the interplanar spacing (also called the d value), and the value was determined to be 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and investigated the In the area where the thickness is between 0.28 nm and 0.30 nm, each lattice fringe is InGaZ nO 4 This corresponds to the ab plane of the crystal.

[0334] In addition, the density of an oxide semiconductor may differ depending on the structure. For example, If the composition of is known, the density of the single crystal of the same composition can be compared to that of the said composition. The structure of the oxide semiconductor can be estimated. For example, the density of a single crystal is e The density of OS is 78.6% or more and less than 92.3%. For example, the density of a single crystal is In contrast, the density of the nc-OS and CAAC-OS was 92.3% or more and less than 100%. Note that an oxide semiconductor having a density of less than 78% of that of a single crystal can be formed by film formation. The body is difficult.

[0335] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor that satisfies the [numerical ratio], single crystal InGaZnO with a rhombohedral crystal structure 4 of Density is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1[ In the case of an oxide semiconductor that satisfies the atomic ratio, the density of the a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1 [ In the oxide semiconductor that satisfies the [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0336] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0337] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a compound semiconductor and a CAAC-OS.

[0338] Oxide semiconductors, which have low impurity concentrations and low defect state densities (few oxygen vacancies), have carrier Therefore, such an oxide semiconductor can be used as a high-purity intrinsic or The a-type oxide semiconductor is essentially a highly pure intrinsic oxide semiconductor. The impurity concentration is lower than that of OS-like and amorphous oxide semiconductors, and the density of defect states is lower. That is, a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor is likely to be obtained. In the case of a transistor using the CAAC-OS or nc-OS, the threshold voltage is negative. In addition, the high purity intrinsic or In reality, high-purity intrinsic oxide semiconductors have few carrier traps. Transistors using C-OS or nc-OS have small fluctuations in electrical characteristics and are highly reliable. The charge trapped in the carrier traps in the oxide semiconductor is It takes a long time for the charge to be released, and it can behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect states has a low current density. The electrical characteristics may become unstable.

[0339] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0340] FIG. 48A shows how a CAAC-OS film is formed by a sputtering method. FIG.

[0341] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition speed. The sputtering method is called magnetron sputtering.

[0342] The target 5130 has a polycrystalline structure, with each grain including a cleavage plane.

[0343] As an example, the cleavage surface of a target 5130 having an In-Ga-Zn oxide is described. FIG. 49(A) shows InGaZnO contained in the target 5130. 4 The crystal structure of In FIG. 49(A), the c-axis is oriented upward, and the InGaZnO 4 This is the structure of the crystal when observed.

[0344] As shown in FIG. 49(A), the oxide in each of the two adjacent Ga-Zn-O layers is It can be seen that the atomic groups are arranged close to each other. And the oxygen atom has a negative charge. As a result, the two adjacent Ga-Zn-O layers repel each other. ZnO 4 The crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0345] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is set to 0.02m or more and 0.5m or less. Most of the deposition gas (e.g., oxygen) is The chamber is filled with a gas mixture containing 5% or more by volume of nitrogen, argon, or oxygen. The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, discharge begins and plasma is generated. It is noted that a high-density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 are generated. The ions 5101 are, for example, positive oxygen ions (O + ) and argon cations (A r + ) etc.

[0346] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually reach the target 5130. At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are peeled off and knocked out. 5100a and pellet 5100b are structured by the impact of the collision of ion 5101. Distortion may occur.

[0347] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example equilateral, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, planar surface. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5 The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may have a shape that is made up of multiple triangles. In some cases, the shape may be two squares (for example, a diamond).

[0348] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferred over thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The diameter of the pellet 5100 is 1.2 nm or more and 2.5 nm or less. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the Ga-Zn-O layer 30, as shown in FIG. A pellet 5100 having three layers, an In-O layer, a Ga-Zn-O layer, and a Ga-Zn-O layer, is ejected. FIG. 49(C) shows the structure of the pellet 5100 when observed from a direction parallel to the c-axis. Therefore, the pellet 5100 is composed of two Ga-Zn-O layers (pans) and an In- It can also be called a nano-sized sandwich structure having a layer (filling) and a layer (filling).

[0349] The pellet 5100 receives an electrical charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 5100 has oxygen atoms on the side, and the oxygen atoms are negatively charged. In this way, the sides can be charged with the same polarity, The repulsion between the particles occurs, allowing the particles to maintain their flat shape. However, in the case of In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. Or, an acid bonded to an indium atom, a gallium atom, or a zinc atom may The elementary atoms may become negatively charged. Also, the pellet 5100 may become charged as it passes through the plasma. It grows by bonding with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. The difference in size between (2) and (1) in Figure 47 above is due to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellet 5100 is Since the film does not grow on the substrate, it becomes nc-OS (see Figure 48(B)). The film can be formed at room temperature. Therefore, even if the substrate 5120 has a large area, the nc-OS can be formed. In order to grow the pellet 5100 in plasma, the sputtering method It is effective to increase the deposition power. By increasing the deposition power, the pellet 5100 The structure can be stabilized.

[0350] As shown in FIG. 48(A) and FIG. 48(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the substrate 5120. Pellet 51 Since the 00 is electrically charged, it approaches an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120. The magnetic field and the electric current act on the object, resulting in a force (Lorentz force). This is what Fleming This can be understood by the left-hand rule.

[0351] The pellet 5100 has a large mass compared to a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of a field and an electric current. In order to increase the size of the substrate 5120, the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably It is preferable to provide an area where the resistance is 50 G or more. The magnetic field parallel to the top surface of the substrate 5120 is 1.5 times that of the magnetic field perpendicular to the top surface of the substrate 5120. fold or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is a good idea to provide an area for this purpose.

[0352] At this time, the magnet and the substrate 5120 move or rotate relatively to each other. Thus, the orientation of the horizontal magnetic field on the top surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces in various directions and is moved in various directions. Can be moved.

[0353] Also, when the substrate 5120 is heated as shown in FIG. The resistance due to friction between the substrate 5120 and the substrate 5120 is small. The pellet 5100 glides over the upper surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches the side of the pellet, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 0 is removed. The removed oxygen atom causes the acid in CAAC-OS to be Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. or 170° C. or more and less than 400° C. That is, when the substrate 5120 has a large area, In this case, it is possible to form a CAAC-OS film.

[0354] In addition, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged and the The structural distortion caused by the collision of the pellet 5101 is relaxed. Pellet 5100 becomes almost a single crystal, so pellet 5 Even if the 100 are heated after bonding, the pellet 5100 itself hardly expands or contracts. This is not possible. Therefore, the gaps between the pellets 5100 may widen, causing defects such as grain boundaries. It does not form depressions or crevasses.

[0355] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The aggregates of Pellet 5100 (nano crystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between them. Even if CAAC-OS is deformed, such as shrinking, by heating or bending, the local stress Therefore, it is possible to reduce the strain or release the distortion. The structure of nc-OS is suitable for biological devices. The arrangement is like something stacked in order.

[0356] When the target is sputtered with ions, not only pellets but also zinc oxide and other substances fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And, 0.1 nm to 10 nm, 0.2 nm to 5 nm, or 0.5 A zinc oxide layer 5102 having a thickness of 2 nm or more is formed. A schematic cross-sectional view is shown in FIG.

[0357] As shown in FIG. 50(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, it slides on pellet 5105b. In another aspect of 5a, a plurality of particles 510 ejected from the target along with zinc oxide. The substrate 5120 is heated to crystallize the region 5105a1. The element 5103 may include oxygen, zinc, indium, gallium, and the like.

[0358] Then, as shown in FIG. 50(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a1 at its side. Place it so that it touches the other side of 05b.

[0359] Next, as shown in FIG. 50(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then pellet 5105a2 and pellet 51 It slides on the pellet 5105b. It also slides towards the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0360] As shown in FIG. 50(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is arranged so that its side surface is in contact with the pellet 5105a. Also, the other side of the pellet 5105d is arranged so as to contact the other side of the pellet 5105c. In the process, a plurality of particles 5103 that fly out of the target together with zinc oxide are deposited on the substrate 512. Heating at 0 causes crystallization, forming region 5105d1.

[0361] As described above, the piled up pellets are arranged so that they come into contact with each other, and the pellets are formed on the side surfaces. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth that occurred after deposition.

[0362] In addition, the gaps between the pellets 5100 become extremely small, so that one large pellet is formed. The large pellets may have a single crystal structure. The size is 10 nm to 200 nm, 15 nm to 100 nm, or In some cases, the thickness of the transistor channel may be between 20 nm and 50 nm. When the formation region is smaller than a large pellet, it has a single crystal structure as the channel formation region. In addition, the pellet size is increased, so that the transistor chip size can be increased. A region having a single crystal structure is used as the channel forming region, the source region, and the drain region. It may be possible.

[0363] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0364] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is to be formed does not have a crystal structure, For example, the CAAC-OS film can be formed on the substrate 5120. Even if the structure of the upper surface (the surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a film of C-OS.

[0365] In addition, the CAAC-OS can be used even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven. For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed with the flat surface, which is parallel to the ab plane, facing down. When the pellet 5100 has a uniform thickness, the pellets 5100 are arranged side by side facing each other. A layer with high crystallinity is formed. The layers are then stacked in n layers (n is a natural number). Thus, CAAC-OS can be obtained.

[0366] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510. The structure is made up of n layers (n is a natural number) of layers with 0s arranged along the unevenness. Since the surface of the CAAC-OS is uneven, gaps may easily occur between the pellets. However, there are cases where intermolecular forces act between the pellets, and even if there are irregularities, the The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is maintained. It can be called CAAC-OS.

[0367] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if there is any, a uniform film can be formed.

[0368] Since the CAAC-OS film is formed by such a model, the sputtered particles have a thin film thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0369] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface with an amorphous structure. It is possible to obtain a CAAC-OS having the formula:

[0370] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0371] (Embodiment 6) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0372] FIG. 37 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 1 is a block diagram showing a configuration of an example.

[0373] The CPU shown in FIG. 37 includes an ALU 1191 (ALU: Arithmetic logic unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, The ROM 1199 and the ROM interface 1189 are Of course, the CPU shown in FIG. 37 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 37 is regarded as one core, and a multi-core processor including multiple cores is used. Alternatively, the CPU may be configured to operate each core in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It may be a bit, etc.

[0374] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0375] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes to register 1196 according to the CPU state.

[0376] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. Supplied to various circuits.

[0377] In the CPU shown in FIG. 37, a register 1196 is provided with a memory cell. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0378] In the CPU shown in FIG. 37, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0379] FIG. 38 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. The semiconductor device may further include other elements such as a capacitor.

[0380] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 120 The first gate of the transistor 1209 is connected to the ground potential (0V) or to a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to a load such as a resistor. The configuration is such that the terminal is grounded via a ground terminal.

[0381] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., truncation) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0382] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection part is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0383] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0384] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0385] In the transistor 1209 in FIG. 38, the second gate (second gate electrode: back The first gate is connected to a control signal WE, and the second gate is connected to a control signal WE. A control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, a ground potential GND or the solenoid potential of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the base potential of the transistor. This is a potential signal for controlling the threshold voltage of the transistor 1209. In addition, the control signal WE2 is the same potential signal as the control signal WE. The transistor 1209 may be a transistor without a second gate. A resistor can also be used.

[0386] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 38, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. The signal is then input to the circuit 1201.

[0387] In FIG. 38, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0388] In addition, in FIG. 38, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. 0. For example, a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may include any other element other than the transistor 1209. The other transistors may include a transistor in which a channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor that is connected to the gate of the transistor.

[0389] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0390] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0391] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 1 Even when the power supply voltage is not supplied to 200, the signal held in the capacitance element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0392] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0393] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal can be read out accurately.

[0394] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0395] In this embodiment, the memory element 1200 is used as a CPU. The 200 is equipped with a DSP (Digital Signal Processor), custom L SI, PLD (Programmable Logic Device) and other LSIs, R Also applied to F-ID (Radio Frequency Identification) It is possible.

[0396] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0397] (Embodiment 7) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used In addition, mobile phones, portable game consoles, portable data terminals, electronic books, video cameras, Digital still cameras and other cameras, goggle-type displays (head-mounted displays) ), navigation systems, audio playback devices (car audio, digital audio players) Years, etc.), copiers, facsimiles, printers, printer-combiners, automated teller machines Examples of such electronic devices include ATMs and vending machines. Specific examples of such electronic devices are shown in Figure 39.

[0398] FIG. 39A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. 39A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0399] FIG. 39B shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input of information. .

[0400] FIG. 39(C) shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0401] FIG. 39(D) shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 may be a touch panel.

[0402] FIG. 39(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0403] FIG. 39(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a rear end. It has 954 etc.

[0404] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can. [Explanation of symbols]

[0405] 20 Through Hole 21 Contact Hole 22 Contact Hole 23 Contact Hole 24 Contact Hole 25 Contact Hole 32 Source electrode layer 33 Drain electrode layer 35 Resist mask 40 Silicon Substrate 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Capacitive element 61 Contact plug 62 Contact plug 63 Contact plug 64 Contact plug 65 Contact plug 66 Contact plug 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 81 Insulating layer 82 Insulating layer 83 Insulating Layer 84 Insulating Layer 85 Insulating Layer 86 Insulating Layer 87 Insulating Layer 90 Inverter circuit 91 Circuit 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130A Oxide semiconductor film 130b Oxide semiconductor layer 130B Oxide semiconductor film 130c Oxide semiconductor layer 130C Oxide semiconductor film 140 Conductive layer 141 Conductive Layer 141a Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 156 Resist Mask 160 Insulating layer 160A Insulating film 170 Conductive Layer 171 Conductive Layer 171A Conductive film 172 Conductive Layer 172A Conductive film 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 190 Insulating Layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Display section 919 Camera 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Display section 933 Wristband 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 5100 pellets 5100a Pellet 5100b Pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellet 5105a1 area 5105a2 Pellet 5105b Pellet 5105c Pellet 5105d Pellet 5105d1 area 5105e Pellet 5120 Circuit Board 5130 Target 5161 area

Claims

[Claim 1] A semiconductor device having a first transistor, a second transistor, and a contact plug, the first transistor has an active region in a silicon substrate; the second transistor has an oxide semiconductor in an active layer; the first transistor and the second transistor each have an overlapping region; a first insulating layer between the first transistor and the second transistor; a second insulating layer on the second transistor; one of a source electrode or a drain electrode of the first transistor is electrically connected to one of a source electrode or a drain electrode of the second transistor via the contact plug; the contact plug penetrates the first insulating layer, one of the source electrode or drain electrode of the second transistor, and the second insulating layer, and the contact plug has, in a depth direction from the second insulating layer toward the first insulating layer, a region whose diameter decreases at an interface between the second insulating layer and one of the source electrode or drain electrode of the second transistor.

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