Systems for high speed transactions with nonvolatile memory on double data rate memory bus

Abstract

To provide a memory device and a system that provide high speed access to a memory in higher temperature applications.SOLUTION: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; and for each received command, determining if the command is an express read (NVR) command, determining if a next consecutive command is a NVR command, in which consecutive NVR commands form a NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock.SELECTED DRAWING: Figure 16

Description

[Technical field]

[0001] Related Applications This application is an international application of U.S. Nonprovisional Application No. 17 / 125,927, filed December 17, 2020, which claims the benefit of priority pursuant to 35 U.S.C. 119(e) to U.S. Provisional Application No. 63 / 088,572, filed October 7, 2020, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates generally to systems requiring high speed access to memory devices, and more particularly to systems that access non-volatile memory devices through a double data rate interface. [Background technology]

[0003] A system-on-chip (SoC) can enable high performance control of a device in a very compact package. SoCs enjoy wide use from very compact devices (e.g., cell phones) to very large devices (e.g., automobiles). SoCs typically include a processor circuit and on-board memory for storing data, including instructions executable by the processor. SoC performance often depends heavily on memory access speed. For ambient temperature and below temperature applications, SoCs can include a combination of non-volatile memory (NVM) and volatile memory, such as dynamic random access memory (DRAM). The NVM can store data in the absence of power. The DRAM can provide acceptable access speeds and consume relatively little power. In this type of system, it is common to load data from the NVM into the DRAM for access by the processor and / or to back up the DRAM data with the NVM.

[0004] For higher temperature applications, e.g., automotive, DRAM is not a desirable memory choice because as temperature increases, DRAM performance can degrade. As a result, higher temperature applications can use static RAM (SRAM) as a volatile memory. SRAM can offer much faster speeds than DRAM, but SRAM can have higher component prices and can draw more power than DRAM.

[0005] 19 is a block diagram of a conventional DRAM read operation compatible with the LPDDR4 standard promulgated by JEDEC. At time t0, a first read command sequence may be received. The read command sequence may include two activate instructions (Activate1, Activate2), a read instruction, and a CAS instruction. The read command sequence may be received over eight clock cycles (of CK_t) (i.e., from time t0 to t2).

[0006] At time t2, a second read sequence having the same type of instructions as the first read sequence can begin.

[0007] The DRAM may have a read latency (RL) of 14 clocks and a skew delay (tDQSCK) of approximately two clocks (at a clock speed of 800 MHz). After such a delay, at time t4, the read data may be output in a minimum burst of 16 (or 32 depending on the burst length setting). For the burst of 16 shown, the total time to receive the burst of 16 may be 31 clocks, or 38.75 ns at 800 MHz.

[0008] In a x32 configuration, 64 bytes may be transferred over eight clock cycles (between times t4 and t5). For a system with 32 bytes of cache memory, this type of read transfer may result in 32 bytes being discarded.

[0009] DRAM (including LPPDR4 compatible DRAM as shown in FIG. 19) can provide fast access speeds to systems such as SoCs, but as mentioned above, DRAM is not suitable for some environments, e.g., higher temperature environments.

[0010] It would be desirable to arrive at some method of providing high speed access to memory in higher temperature applications that does not suffer from the drawbacks of conventional methods. [Brief description of the drawings]

[0011] [Figure 1] 1 illustrates a non-volatile memory (NVM) device and fast access operation according to an embodiment. [Diagram 2] FIG. 2 is a block diagram of an NVM device according to one embodiment. [Diagram 3] FIG. 13 is a block diagram of an NVM device according to another embodiment. [Figure 4] FIG. 13 is a block diagram of an NVM device according to a further embodiment. [Diagram 5] FIG. 2 is a timing diagram of a high-speed access operation to an NVM device according to one embodiment. [Figure 6] A timing diagram of a high-speed access operation to an NVM device according to another embodiment. [Figure 7] FIG. 1 is a block diagram of an NVM device having a double data rate (DDR) parallel interface (I / F) and a serial I / F according to one embodiment. [Figure 8] FIG. 13 is a block diagram of an NVM device having a DDR parallel interface I / F and a serial I / F according to another embodiment. [Figure 9] FIG. 2 is a block diagram illustrating an NVM device address space according to one embodiment. [Figure 10] 10A and 10B show registers of an NVM device that may be included in one embodiment, FIG. 10C shows a conventional LPDDR4 command format, and FIG. 10D shows a high-speed access command format according to one embodiment. [Figure 11] FIG. 2 is a schematic diagram of a memory cell array that may be included in one embodiment. [Figure 12] 1 illustrates a perspective view of an integrated circuit device according to one embodiment. [Figure 13] FIG. 2 is a block diagram of a memory controller according to one embodiment. [Figure 14] FIG. 1 is a block diagram of a system according to one embodiment. [Figure 15] FIG. 1 is a diagram of an automobile system according to one embodiment. [Figure 16] FIG. 2 is a flow diagram of an NVM method according to one embodiment. [Figure 17] FIG. 1 is a flow diagram of a memory controller method according to one embodiment. [Figure 18] FIG. 2 is a flow diagram of a method of a system according to one embodiment. [Figure 19] FIG. 1 is a timing diagram of a conventional LPDDR4 compatible read access according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] According to embodiments, a non-volatile memory (NVM) device can process a decreasing sequence of commands (NVR commands) to read data from NVM cells of one or more arrays. In some embodiments, an NVR command pair can have all the command and address data necessary for a read operation. Read data corresponding to the NVR commands can be output from the NVM device at double data rate (DDR). In some embodiments, the read data can be output in bursts of eight data.

[0013] In some embodiments, the NVM device may have an interface that is compatible with a physical interface that complies with the LPDDR4 standard.

[0014] In some embodiments, an NVR command pair can have a command value that is distributed across both NVR commands of the pair. In some embodiments, an NVR command pair can have an address value that is distributed across both NVR commands of the pair.

[0015] In some embodiments, the NVR command may have a format conforming to commands conforming to the LPDDR4 standard, however, one or more bit positions that provide command data in the LPDDR4 command may provide address data in the NVR command.

[0016] In some embodiments, the NVM device may include a serial interface in addition to the DDR interface.

[0017] In some embodiments, an NVM device can be part of a system that performs cache line reads to a cache memory: fast access operations (read accesses performed by NVR commands) to one or more NVM devices can fill a cache line without having to discard any read data.

[0018] In some embodiments, the NVM device can be part of a system having a memory controller. The memory controller can issue a read command sequence having an NVR command to the NVM device and can issue a read command sequence according to an existing standard (e.g., LPDDR4) to another device (e.g., dynamic random access memory (DRAM)). The read sequence according to the existing standard can have more commands (e.g., four commands) compared to the sequence of NVR commands (e.g., two commands).

[0019] In the various embodiments that follow, similar items are referred to by reference numbers that have the same reference number but whose first digit corresponds to the drawing number.

[0020] FIG. 1A is a block diagram of an NVM device 100 according to one embodiment. The NVM device 100 may include one or more memory cell arrays 102 and a DDR interface 104. In the illustrated embodiment, the memory cell array 102 may be an NVM cell array 102 that may include any suitable type of NVM cell capable of retaining data in the absence of power. In some embodiments, the NVM cell array 102 may include decoder circuitry for accessing the NVM cells in response to address values, and write circuitry (e.g., program and erase circuitry) for storing data values ​​in the NVM cells. In some embodiments, the memory cell array 102 may include volatile memory cells, including but not limited to dynamic random access memory (DRAM) cells and / or static RAM (SRAM) cells, along with appropriate access and support circuitry (e.g., decoder circuitry, refresh circuitry for DRAM, etc.).

[0021] The DDR interface 104 may include a command and address (CA) input, a parallel data connection (DQ), and one or more clock inputs (CLK). The CA inputs may receive command and address data for accessing memory locations in the NVM cell array 102. The CLK inputs may receive one or more clock inputs for timing inputs and output signals for the NVM device 100. The DQ connections may output parallel data values ​​in response to requests received on the CA inputs. The output data values ​​may be provided synchronously with the rising and falling edges of the input clock (i.e., at double data rate). In some embodiments, the DQ may be unidirectional and may provide only output data from the NVM device. However, in other embodiments, the DQ may be bidirectional and may both receive and output data.

[0022] In some embodiments, the DDR interface 104 may have signaling compatible with existing memory standards. In one embodiment, the DDR interface 104 may have signaling compatible with the LPDDR4 standard promulgated by JEDEC. That is, the DDR interface 104 may have a physical interface compatible with the LPDDR4 physical interface standard (i.e., LPDDR4 PHY).

[0023] The DDR interface 104 may have signaling compatible with existing standards, but may handle shorter read command sequences than existing standards of this type. In some embodiments, the DDR interface 104 may be compatible with an LPDDR4 PHY, but may handle a faster read sequence of two commands, as opposed to the four command read sequence dictated by the LPDDR4 standard.

[0024] The DDR interface 104 may include a command decoder 105 for performing the fast accesses described herein. In some embodiments, the command decoder 105 may recognize fast access commands to enable access to the NVM cell array 102. In some embodiments, the command decoder 105 may distinguish the fast access commands from other commands. A continuous sequence of fast access commands may be considered a fast command sequence. A fast command sequence may include all instructions and address data to perform an access to the NVM device 100. In some embodiments, the DDR interface may be compatible with existing standards (e.g., LPDDR4), and a fast command sequence may include fewer commands than an access according to the existing standard.

[0025] In some embodiments, the CA inputs may be less than 7 bits wide and the DQ connections may be less than 20 bits wide.

[0026] In some embodiments, NVM device 100 may be an integrated circuit device that includes one or more integrated circuit (IC) substrates formed within a single IC package.

[0027] Figure 1B is a timing diagram illustrating access operations for an NVM device such as Figure 1A. Figure 1B illustrates a read access compatible with a predetermined standard (Std) and a fast read access (fast) to an NVM device according to one embodiment that can occur in fewer clock cycles than a standard read access.

[0028] FIG. 1B includes waveforms for a timing clock (CK), a CA input for standard access (CA(Std)), a CA input in fast access (CA(fast)), output data in standard access (DQ(Std)), and output data for fast access (DQ(fast)).

[0029] At time t0, a read command sequence can be received by the memory device. The read command sequence can include command and address values ​​for one read operation. FIG. 1B shows the command address values ​​for the standard case as well as the fast case. As shown, the standard read command sequence requires "n" commands (Std0 to Stdn), where n is greater than 2. In contrast, the fast access consists of fewer NVR commands (NVR1, NVR2, and possibly NVR3).

[0030] In response to receiving a first NVR command (NVR1), the command can be evaluated (shown as 147) to determine if it is a fast access command. If the received command is a fast access command, then the next command in the sequence can be examined to determine if it is a fast access command. A set of consecutive fast access commands can form a fast access command sequence. Thus, FIG. 1B shows a fast access command sequence of NVR1 / NVR2 (two sequences) and, optionally, a fast access command sequence of NVR1 / NVR2 / NVR3 (three sequences).

[0031] At time t1, the reception of the fast read command sequence (NVR1 / NVR2) can be completed. After time t1, but before time t2, the reception of the fast read command sequence (NVR1 / NVR2 / NVR3) can be completed.

[0032] At time t2, a standard read command sequence (shown as ACT1, ACT2, READ, CAS2, but not limited to any particular protocol / standard), which requires more clock cycles than the fast case, can be received to completion.

[0033] At time t3, data corresponding to the fast read command sequence can be output.

[0034] At time t4, data output for fast access from the NVM device can be completed. In the illustrated example, data corresponding to a standard read command sequence can also be output at this time.

[0035] At time t5, data output for standard access can be completed.

[0036] In the illustrated embodiment, the fast read operation may include fewer commands (and therefore fewer clock cycles) and may optionally retrieve data in a smaller burst sequence than a standard read access. As a result, the fast read operation may occupy less time on the CA bus and retrieve data in less time than a standard read operation. In some embodiments, the smaller burst sequence may be a selectable feature of the memory device, and larger burst sequences (including those of conventional size) are supported.

[0037] Although Figure 1B shows the NVR command being received over two clock cycles of CK, alternative embodiments may receive the NVR command over a greater number of clock cycles. By way of example only, the command and address data contained in NVR1 / NVR2 of Figure 1B may be contained within one NVR command that occupies four clock cycles.

[0038] In some embodiments, the NVR command can be received over j×2 clock cycles, where j is an integer greater than or equal to 1.

[0039] 1C is a diagram illustrating various examples of fast read (NVR) command sequences according to an embodiment. It should be understood that such sequences occur over time as successive commands issued from a controller device and / or received at an NVR device. Successive commands can be commands received one after the other without an intervening delay or without a sufficiently long period of intervening delay.

[0040] NVR command sequence 149A shows a two command sequence (NVR1 / NVR2) that ends with no further commands being received. From the bit value of NVR1, the command decoder can determine that the command is an NVR command. As a result, the command decoder can treat the next consecutive command as a possible NVR command. Thus, NVR2 is detectable in the next NVR command in the sequence. In the illustrated embodiment, NVR command sequence 149A ends when no consecutive commands are received after NVR2. In some embodiments, commands are received over a predetermined number of timing clock cycles. Any NVR command sequence can be considered to be terminated if no commands are received in such amount of clock cycles.

[0041] When the command sequence is completed, the resulting NVR command (NVR1 / NVR2) of the sequence is used to access the NVM cell, i.e., the command NVR1 / NVR2 is understood to include all command and address data necessary for read access.

[0042] NVR command sequence 149B shows an NVR command sequence like 149A, however, NVR command sequence 149B is terminated by receipt of a command that is not an NVR command. The command decoder detects NVR1 and then examines the next command (NVR2) and can determine that it is also an NVR command and therefore part of the same NVR command sequence. Since NVR2 is an NVR command, the command decoder can look at the next successive command (MRR1) and determine if it is an NVR command. However, in this case, MRR1 is not an NVR command. As a result, the NVR command sequence can end and the NVM cells are accessed by the address values ​​of NVR1 / NVR2.

[0043] NVR command sequence 149C shows an NVR command sequence like 149A, but with more NVR commands. In some embodiments, the address space of the target memory device may require more address bits than can be provided by two NVR commands. Therefore, one or more NVR commands (in this case, one command NVR3) can be added to the NVR command sequence. Longer fast read command sequences can be terminated in the same manner as described above. Additionally, the NVR command sequence can have any number of NVR commands, including more than three NVR commands.

[0044] It should be understood that an NVR command sequence can include one NVR command.

[0045] Although embodiments may take many forms, some embodiments may be a single integrated circuit (IC) device having one or more integrated circuit dies. Figures 2-4 show three of many possible IC devices according to embodiments.

[0046] 2 is a block diagram of an NVM IC device 200 having a single die 207 formed in an IC package 205. The IC package may take any suitable form including, but not limited to, a ball grid array (BGA) including a fine pitch BGA (FBGA), a small outline package, a flat package, a pin grid array, or a chip carrier. The die 207 may include an NVM cell array 202, a DDR I / F 204, and a serial I / F 206. The NVM cell array 202 may take any form described herein or equivalent. In some embodiments, the NVM cell array 202 may include a first bank 202-0 and a second bank 202-1.

[0047] The DDR I / F 204 may include a CS input, a clock input (CLK), a CA input, a DQ, and a data strobe output (DQS). The DDR I / F 204 may also include a command decoder 205 or equivalent that may decode the fast access commands (e.g., NVR1, NVR2...NVRn) described herein. The DDR I / F 204 may enable access to the NVM cell array 202, including read and write operations. In some embodiments, in addition to fast access, the DDR I / F 204 may enable or be configurable to enable standard access. In some embodiments, the command decoder 205 may process a continuous uninterrupted NVR command sequence (e.g., a first NVR1 / NVR2 pair immediately followed by a second NVR1 / NVR2 pair) for each of the banks 202-0 / 1, enabling uninterrupted output of data from the banks 202-0 / 1 on DQ at double data rate.

[0048] Serial I / F 206 may enable access to NVM array 202 via a serial bus. Serial I / F 206 may include a serial chip select input (SERIAL_CS), a serial clock input (SERIAL_CLK), and a serial data I / O (SERIAL_DQ). SERIAL_CS may enable NVM device 200 to be selected for access by other devices (e.g., a host device) via serial I / F 206. SERIAL_CLK may receive timing signals for synchronizing data input to and output from NVM device 200. SERIAL_DQ may receive commands, addresses, and data values ​​for accessing memory locations (including configuration registers) of NVM device 200. SERIAL_DQ may output serial data in response to an access.

[0049] FIG. 3 is a block diagram of an NVM IC device 300 having a first die 307A and a second die 307B formed in the same IC package 305. The IC package can take any suitable form as described herein. The first die 307A can include an NVM cell array 302A, a DDR I / F 304, and a serial I / F 306A, as in FIG. 2. The second die 307B can include an NVM cell array 302B and a serial I / F 306B. The first and second die 307A / B can be connected by an internal bus 309. Access at the DDR I / F 304 can access the NVM cell array 302A on the first die 307A and can access the NVM cell array 302B on the second die 307B via the internal bus 309. A shared serial bus 311 can enable access to one of the dies 307A / B via a common serial input 313.

[0050] DDR I / F 304 can operate like that of Figure 2. However, command decoder 305 can handle consecutive uninterrupted NVR sequences targeted at banks of different dies (e.g., 302-0A / 302-0B) and enable uninterrupted output of data from banks 302-0A / 302-0B on DQ_A / B.

[0051] 4 is a block diagram of an NVM IC device 400 having a first die 407A and a second die 407B formed in the same IC package 405. The NVM IC device 400 can have items like those of FIG. 3. The NVM IC device 400 can differ from FIG. 3 in that each die 407A / B can have a respective DDR I / F 404A / B, each including a chip select input (CS_A / B), a clock input (CLK_As / Bs), a CA input (CA_A / B), DQ (DQ_A / B) and DQS (DQS_A / B). Each DDR I / F 404A / B can also have its own command decoder 405A / B. In some embodiments, command decoder 405A can process continuous, uninterrupted NVR sequences targeted at banks 302-0A / 1A in NVM cell array 402A, and command decoder 405B can process continuous, uninterrupted NVR sequences targeted at banks 302-0B / 1B in NVM cell array 402B.

[0052] In the embodiments of Figures 2-4, the DDR I / F (204, 304, 404A, 404B) may have signaling compatible with the DDR standard promulgated by JEDEC. In some embodiments, this type of DDR I / F may be compatible with the LPDDR4 standard promulgated by JEDEC.

[0053] In the embodiments of Figures 2-4, the serial I / F (206, 306A / B, 406A / B) can be compatible with the Serial Peripheral Interface (SPI) standard, including having one serial data line or having multiple serial data lines (e.g., quad SPI).

[0054] FIG. 5 is a timing diagram illustrating a high-speed read operation for an NVM device according to an embodiment. In FIG. 5, it is assumed that the access may occur through a DDR interface having an input compatible with the LPDDR4 PHY standard. However, the DDR interface can process high-speed access commands that may include a command sequence of fewer commands than conventional LPDDR4 accesses. FIG. 5 illustrates the following waveforms: CS indicates a chip select input (CS), CA[5:0] indicates a command address input (having a bit width of 6 bits), CMD is a write representation of command data received on CA, CK_t is a timing clock, DQS[1:0] indicates a data strobe output, DQ[15:0] indicates a data I / O having a bit width of 16 bits, and DM[1:0] indicates an output configured to provide error correction code (ECC) data corresponding to the data output on DQ.

[0055] At time t0, CS can go high, selecting the NVM device for an access operation. Also at time t0, the NVM device can begin receiving a command sequence on the CA for a first fast read operation. Such a command sequence can take the form of a first NVR command (NVR-1). The first NVR command (NVR-1) is received over one clock cycle (of CK_t), followed by a second NVR command (NVR-2) received over another clock cycle. However, it should be understood that alternative embodiments can include a sequence of more than two NVR commands.

[0056] At time t1, CS can go high again to continue selecting the NVM device for access operations.

[0057] At time t2, the first access may be completed with the first command sequence being completed after about three clock cycles. In response to the command sequence, the NVM device may begin accessing the NVM cells for the requested read data.

[0058] At time t3, CS can go high again to continue selecting the NVM device for the access operation. Also at time t3, a second fast access operation can begin. The second access operation can occur in the same manner as the first access operation.

[0059] At time t4, the second access may be completed with the second command sequence having been received through four clock cycles. In response to the second command sequence, the NVM device may begin accessing the NVM cells for a second set of read data. Times t2 to t4 may be a column-to-column delay time (tCCD), which may be four clocks.

[0060] Time t5 may mark the end of a read latency (RL) time, which may vary according to clock speed and NVM device architecture. In the illustrated embodiment, RL may be 14 clock cycles.

[0061] At time t6, after RL time and an additional clock skew delay (tDQSK), the read data (D0 to D7) for the first access can be output on DQ along with the corresponding data strobe signal DQS. The read data can be output at double data rate with respect to CK_t and can have a burst length (BL) of 8. In addition, at the output of DM, 2 bits of ECC data can be output along with each read data value. In the illustrated embodiment, through each of the two clock cycles after t6, DQ / DM can output 64 bits of read data along with 8 bits of ECC data.

[0062] At time t7, the read data for the second access (D0 through D7) can be output on DQ immediately after the read data for the first access. This second set of read data can have the same general format as the first read data.

[0063] Still referring to FIG. 5, a sequence of read commands NVR1 / NVR2 can take four clock cycles. While FIG. 5 shows a 16-bit (i.e., x16) DQ, it should be understood that other embodiments can include 32-bit (i.e., x32) accesses. As two of many possible examples, the NVR1 / NVR2 command can be targeted at two NVM devices, each of which returns a x16 bit. Alternatively, the NVM devices can have a x32 bit output. Thus, while FIG. 5 shows data output at x16 bits per half clock cycle, in a two device / bank configuration, data can be output at x32 bits over eight half clock cycles. In this type of configuration, two NVM devices (or one NVM device with a x32 DQ) can output 32 bytes of data over four clocks. This type of read operation can be pipelined (i.e., while FIG. 5 shows two pipelined read operations, a greater number of read operations can be pipelined). In many systems, cache memory accesses write data to cache lines that are 32 bytes in size, so each pipelined NVR read access can fill one cache line with no data being wasted.

[0064] As shown in FIG. 5, the time between the start of the fast read command (t0) and the time when all data is output (t7) can include three clock cycles for command address data (NVR1 / 2), 14 clock cycles for RL, two clock cycles for tDQSK, and four clock cycles for data (BL=8). At a clock speed of 800 MHz, the total time can be 28.75 ns. Thus, with a pipelined fast read access, the first cache line can be filled with data from the non-volatile memory in 28.75 ns, and the next cache line is filled every 5 ns (i.e., four clock cycles). This is in stark contrast to the conventional access operation of FIG. 19, which takes 38.75 ns for the first cache line, 10 ns for each subsequent operation, and discards 32 bytes from each read data set.

[0065] 5 shows an embodiment with 8 BLs, embodiments may also support larger BL sizes. In some embodiments, a BL of 8 may be a selectable feature among other BL sizes (e.g., 32). Additionally, other embodiments may provide BLs of sizes greater than 8, e.g., 16 BLs, and do not support the short BL size of 8.

[0066] Figure 6 is a timing diagram illustrating an access operation for an NVM device according to another embodiment. Figure 6 illustrates an access through a DDR interface, like Figure 5, but targeting two different NVM devices. Figure 6 illustrates similar waveforms to Figure 5, except that there may be two chip select waveforms, CS0 and CS1. In addition, there may be two different data strobe signals, DQSA, DQSB.

[0067] The operations may occur in the same general manner as shown in FIG. 5, except that the first NVM device is selectable by signal CS0 between times t0 and t1, and the second NVM device is selectable by signal CS1 between times t2 and t3. In some embodiments, there may be a time tBT separating the NVR sequence for one device (NVR1A / NVR2A) from the NVR sequence for the next device (NVR1B / NVR2B). The time tBT may vary according to the type of device and the clock speed. As some of many possible examples, at a clock speed of 800 MHz, tBT may be two clock cycles (of CK_t), and at a clock speed of 1600 MHz, tBT may be four clock cycles. The data output on DQ between times t4 and t5 may be from the first NVM device, and the data output on DQ after time t5 may be from the second NVM device. In some embodiments, there may be a time tDQBT separating the data sets.

[0068] FIG. 7 is a block diagram of an NVM device 700 according to another embodiment. The NVM device 700 may be one implementation of the devices and dies shown in the other embodiments. The NVM device 700 may include a first interface 704, a second interface 706, and a number of separately addressable banks 702-0 to 702-3. The first I / F 704 may be a parallel DDR I / F and may receive command sequences at the CA input and provide parallel output data on the data output DQ synchronous to the rising and falling edges of the clock CLK. The first interface 704 may be connectable to a parallel data bus 710. The parallel data bus 710 may have command and address values ​​transmitted over a CA bus, which is separate from the data bus DQ on which data may be output (or input). In some embodiments, the signaling on the first I / F 704 may be compatible with the LPDDR4 standard. The first I / F 704 may also include a command decoder 705 and equivalents for handling high speed accesses as described herein.

[0069] The second I / F 706 may be a serial I / F that may enable serial data transactions on one or more serial data I / Os (S_DQ) synchronous to a serial clock S_CK. The second I / F 706 may be connectable to a serial bus 708. In some embodiments, the second I / F 706 may be compatible with the SPI standard.

[0070] The banks (702-0 to 702-3) may each include many NVM cells. Within each bank (702-0 to 702-3), the NVM cells may be arranged in one or more arrays. The NVM cells may take any suitable form, and in some embodiments may be "flash" type NVM cells. The banks (702-0 to 702-3) are separately addressable; that is, the physical addressing of the device 700 may have a separate bank address for each bank (702-0 to 702-3). All the banks (702-0 to 702-3) may be connected to a first bus system 712A and a second bus system 712B. A first bus system 712A can connect the banks (702-0 through 702-3) to the first I / F 704, and a second bus system 712B can connect the banks (702-0 through 702-3) to the second I / F 706. Although Figure 7 shows a device with four banks, embodiments may include a greater or lesser number of banks.

[0071] In some embodiments, bank addressing can enable pipelined access to the NVM device with fast access commands (e.g., command pair NVR1 / NVR2). Command sequences for different banks can be received at the first interface 704 in a pipelined manner (i.e., with no intervening data between command address values ​​and with minimal or no delay between command address values). In response to such pipelined command sequences, data from different banks can be output on DQ in sequential bursts with minimal or no delay between such bursts.

[0072] 8 is a block diagram of an NVM device 800 according to a further embodiment. The NVM device 800 can be any one of the implementations shown herein. The NVM device 800 can include a DDR4 I / F 804, a Quad SPI (QSPI) compatible I / F 806, a LPDDR4 compatible physical layer interface (PHY) 816, a QSPI compatible PHY 818, a number of banks 802-0 to 802-7, a first access path 820-0 to 820-7 for each bank (802-0 to 802-7), a second access path 822-0 to 822-7 for each bank (802-0 to 802-7), and a parameter / configuration register 821.

[0073] The LPDDR4 PHY 816 may include a chip select CS input, a clock input CK_t, a CA input, a first DQ[7:0] with a corresponding data clock output DQS0_t, and a second DQ[15:8] with a corresponding data clock output DQS1_t. Such inputs and outputs may be connected to an LPDDR4 compatible bus 810. The DDR4 I / F 804 processes command and address data and may include a command decoder 805 that may process fast access command address values ​​that may be received in a command sequence (e.g., NVR1...NVRn), with each command in the sequence being received over two or less cycles of CK_t. In some embodiments, the DDR4 I / F 804 may also process LPDDR4 compatible commands (e.g., address data commands received over eight clocks). In some embodiments, the DDR4 I / F 804 may be a read-only interface for user storage space access and may not process write commands to the user storage space. In some embodiments, the DDR4 I / F 804 can handle write operations to configuration and / or other registers of the NVM device 800.

[0074] The DDR4 I / F 804 can be connected to the banks (814-0 to 814-7) via a first bus system 812A. The DDR4 I / F 804 can process pipelined fast access commands every four clock cycles and provide corresponding output data in bursts of eight at double data rate on DQ. In some embodiments, such successive pipelined fast access commands can be to different banks 802-0 to 802-7.

[0075] The QSPI PHY 818 can include a serial chip select SPI_CS, a serial clock input SPI_CK, and four serial data I / Os SPI_DQ. Such I / Os can be connected to an SPI-compatible serial bus 808. The QSPI I / F 806 can process commands received by the QSPI PHY 818, including QSPI-compatible commands. Such commands can include both read and write (e.g., program, erase) commands.

[0076] Parameter / configuration registers 821 may store parameter values ​​accessible by other devices that may indicate the capabilities of NVM device 800. In some embodiments, registers 821 may store parameter values ​​that indicate NVM device 800 is capable of performing fast access operations.

[0077] Each bank (802-0 to 802-7) may include NVM cells arranged in rows and columns. Each bank (802-0 to 802-7) is separately accessible via a unique bank address. In some embodiments, the NVM cells may be erasable (e.g., flash-type cells) groups. The read paths (820-0 to 820-7) may enable read access to their corresponding banks (802-0 to 802-7) from the DDR4 I / F 804 via the first bus system 812A. In some embodiments, the read paths (820-0 to 820-7) may also be write paths that enable write data to be written into the banks (802-0 to 802-7) from the DDR2 I / F 804. The R / W paths (822-0 through 822-7) can enable read or write access to their corresponding banks (802-0 through 802-7) from the QSPI I / F 806 via the second bus system 812B.

[0078] According to embodiments, an NVM device may include an address space of storage locations for user data as well as data specific to the NVM device. Such address space may include locations for parameter data indicative of fast access capabilities and / or configuration data for configuring the NVM device for fast access operations.

[0079] 9 shows an NVM device 900 having an address space 923, an LPDDR I / F 904 connectable to a parallel bus 908, and a serial I / F 906 connectable to a serial bus 910. The LPDDR4 PHY 904 can be compatible with the LPDDR4 standard PHY. The serial I / F 906 can be compatible with the SPI standard.

[0080] The address space 923 may include various memory locations accessible by predefined addresses. In some embodiments, the NVM device 900 may have address reconfiguration capabilities for, by way of example only, logical to physical address translation and / or wear leveling. In the illustrated embodiment, the addressable space 923 may include any of the following: user space 902, LPDDR4 mode register 921-0, device identification (ID) register 921-1, device parameter register 921-2, secure area 921-3, and serial I / F register 921-4. The user space 902 may include an NVM cell array for storing user data in a non-volatile manner and is accessible via the LPDDR4 I / F 904 and the SPI I / F 906.

[0081] The LPDDR4 mode register 921-0 can store values ​​for configuring the LPDDR4 I / F 904. In some embodiments, the LPDDR4 mode register 921-0 can include a register for establishing a BL size, including but not limited to a short BL size, such as 8, and / or a larger BL size, including 16 or 32. In some embodiments, the LPDDR4 mode register 921-0 can include a standard access configuration register 924. According to a value stored in the fast access control register 924, the NVM device 900 can execute a sequence of standard access commands, which may include more commands than fast access. In some embodiments, the NVM device 900 can execute a fast access by determining whether a successive command is an NVR command. The standard access configuration register 924 can enable an LPDDR4 command sequence of four commands in addition to the fast command. The LPDDR4 mode register 921-0 is accessible via the LPDDR4 I / F 904 or the SPI I / F 906.

[0082] The device ID register 921-1 can store a value that can identify the NVM device 900 to other devices in a system. In some embodiments, the value stored in the device ID register 921-1 can indicate that the NVM device is capable of executing fast access commands. The parameter register 921-2 can store a value that can identify the capabilities of the NVM device 900 to other devices in a system. In some embodiments, the parameter register 921-2 can include a fast access parameter register 925 that can indicate that the NVM device is capable of executing fast access commands. Other devices (i.e., the host and / or memory controller) can access the parameter register 921-2 and / or the device ID register 921-1 and determine that the NVM device 900 is capable of executing fast access commands.

[0083] The secure area 921-3 may store data values ​​that are not accessible by devices external to the NVM device or that are accessible only through a secure access procedure, such as an authentication process. Some or all of the DDR I / F register 921-0, the device ID register 921-1, the parameter register 921-2, and the serial I / F register 921-4 may be secure areas.

[0084] The serial I / F register 921-4 can store values ​​for configuring the serial I / F 906. In some embodiments, the device ID register 921-1, the parameter register 921-2 and the serial I / F register 921-4 are accessible via the serial I / F 906 rather than via the DDR I / F 904.

[0085] 10A illustrates an example of a DDR I / F register 1021-1 that may be included in an NVM device according to one embodiment. The DDR I / F register 1021-1 may include various registers for configuring the DDR I / F, including a fast access control register 1024. The fast access control register 1024 may store values ​​that may control various characteristics of a fast access operation, including, but not limited to, the number of clock cycles in a received command, any delay between back-to-back accesses (e.g., tBT), the burst length for data, etc.

[0086] 10B illustrates an example of parameter registers 1021-2 that may be included in an NVM device according to one embodiment. Parameter registers 1021-2 may include various registers for indicating parameters of the NVM device, including standard access compatible registers 1025. Standard access compatible registers 1025 are accessible by other devices (e.g., a host or controller) and indicate that the NVM device is capable of performing standard accesses and equivalents that may require longer command sequences than the fast accesses described herein.

[0087] Of course, the configuration or parameter registers can take any form appropriate to the architecture of the NVM device.

[0088] FIG. 10C illustrates a format of a conventional LPDDR4 read command 1035. The conventional read command 1035 may include a first portion 1035H that is received when CS is high (and for a first clock cycle) and a second portion 1035L that is received when CS is low (and for a second clock). The conventional read command 1035 may include bit positions that store command data (CMD). The bit positions correspond to CA bus bits CA0 and CA1 during the first clock cycle. An LPDDR4 command sequence may include four commands ACT1, ACT2, READ, and CAS having this format.

[0089] FIG. 10D illustrates a format of an NVR command 1039 according to one embodiment. The NVR command 1039 can have the same format as a conventional LPDDR4 command, including 6 bits received in two clock cycles. The NVR command 1039 can differ from a conventional LPDDR4 command in that the bit position that provides the command data in the LPDDR4 command (e.g., 1037 in FIG. 10C) can provide address information 1041 in the NVR command. FIG. 10D shows that CA1 provides the address data, but in other embodiments, CA0 can provide the address data (while CA1 provides the command data). As emphasized herein, a command sequence for a fast access operation can include two or three NVR commands, as opposed to the four commands required by a conventional LPDDR4 read operation.

[0090] Although embodiments may include any suitable NVM array structure or NVM cell type, some embodiments may include a one-transistor (1T) NOR type array. FIG. 11A is a schematic diagram of a 1T NOR array 1102A that may be included in one embodiment. The array 1102A may include many memory cells (one shown as 1126-0) arranged in rows and columns, with memory cells in the same row connected to the same word line (one shown as 1126-2) and memory cells in the same column connected to the same bit line (one shown as 1126-3). In some embodiments, the memory cells (1126-0) have a charge storage structure 1126-1 between the control gate and the channel, which may be formed by a single transistor structure. The charge storage structure 1126-1 may store one or more bits of data as a charge (including a lack of charge). The charge storage structure 1126-1 may take any suitable form, including but not limited to a floating gate, a charge storage dielectric (e.g., a replacement gate), or a combination thereof.

[0091] An embodiment may include any suitable volatile array structure or volatile memory cell type. FIG. 11B is a schematic diagram of a possible volatile memory cell array that may be included in an embodiment. FIG. 11B shows an array 1102B that may include many volatile memory cells (one shown as 1126-0V) arranged in rows and columns and connected to one or more bit lines (e.g., 1126-3) and word lines (e.g., 1126-2). The volatile memory cells (1126-0V) may take any suitable form, including but not limited to DRAM cells 1126-0V1 and / or SRAM cells 1126-0V2. The SRAM cells 1126-0V2 include but are not limited to 4-transistor (4T), 6T and / or 8T variations.

[0092] In some embodiments, the fast read command (NVR1 / NVR2) can be used to access volatile memory cells in the same manner as NVM cells described herein. In some embodiments, a memory device can include both NVM cells and volatile memory cells, both of which are accessible by the fast read command. In other embodiments, a memory device can receive fast access commands that access only volatile memory cells.

[0093] Although embodiments may include a system having a memory device operating in conjunction with a host device, embodiments may also include a standalone NVM device with a parallel I / F formed in one IC package. This type of embodiment is shown in FIG. 12. FIG. 12 shows a packaged NVM device in a perspective top view 1200T and a bottom view 1200B. The NVM device 1200T / B may include many physical connections (e.g., 1127), all or some of which may be connected to a DDR I / F as described herein. This type of DDR I / F may process the high-speed access commands and equivalents as described herein. However, it should be understood that a memory device according to embodiments may include any other suitable package type, including directly bonding a memory device die onto a system circuit board.

[0094] Although embodiments may include an NVM device, embodiments may also include a memory controller that can generate high-speed command and address values ​​through a DDR I / F for the NVM device. Figure 13 illustrates a memory controller 1330 according to one embodiment.

[0095] The memory controller 1330 may include a command queue 1334, a write queue 1336, a read queue 1338, a transaction processing circuit 1340, a PHY interface circuit 1342, an LPDDR4 PHY 1316, and an ECC circuit 1348. The command queue 1334, the write queue 1336, and the read queue 1338 may be connected to a controller I / F 1332, which may be connected to a controller (e.g., a host processor), etc. The command queue 1334 may receive memory requests through the controller I / F 1332 to access an NVM device connected to the LPDDR4 compatible bus 1310. The write queue 1336 may receive write data to be programmed into the NVM device through the LPDDR4 PHY 1316. The read queue 1338 may output read data received from the NVM device through the LPDDR4 PHY 1316.

[0096] The transaction processing circuit 1340 may include a command encoding circuit 1344 and a configuration register 1320. The command encoding circuit 1344 may include a standard encoding 1346-0 and a high-speed encoding 1346-1. The standard encoding 1346-0 may encode the memory request into a format compatible with the LPDDR4 standard (e.g., a sequence of four commands transmitted over eight clocks). The high-speed encoding 1346-1 may encode the memory request into a high-speed access format (e.g., a sequence of one or more consecutive NVR commands). In some embodiments, encoding the command between different formats (e.g., standard / high-speed) may be performed in response to a request received through the command queue 1334. That is, a request from the controller may indicate whether the access should be in standard or high-speed format. Additionally or alternatively, encoding the command may be controllable according to a high-speed encoding register value 1324 stored in the configuration register 1320.

[0097] The PHY I / F circuit 1342 can generate input signals from command and address values ​​for appropriate signaling by the LPDDR4 PHY 1316 and can organize data values ​​from signals received at the LPDDR4 PHY 1316. The LPDDR4 PHY 1316 is connected to the LPDDR4 bus 1310 and can transmit signals and receive data, including transmitting command address values ​​for fast access operations and receiving read data from the fast access. The ECC circuit 1348 can perform error detection and correction operations on data values ​​received at the LPDDR4 PHY 1316. In some embodiments, the ECC circuit 1348 can use ECC values ​​received on the DM input of the LPDDR4 bus 1310.

[0098] Embodiments may also include systems that can use fast access operations to an NVM device to fill cache memory lines of a controller device (e.g., a system or host CPU). Figure 14 illustrates a system 1450 according to one such embodiment.

[0099] System 1450 may include one or more NVM devices (two shown as 1400-0, 1400-1), a host system 1443, and, optionally, a dynamic random access memory (DRAM) device 1458. NVM device 1400-0 / 1 may include an NVM array 1402, a DDR I / F 1404, and a serial I / F 1406. NVM device 1400-0 / 1 may be connected to a DDR bus 1410 via DDR I / F 1404 and to a serial bus 1432 via serial I / F 1406. NVM device 1400-0 / 1 may perform high speed access operations or equivalents as described herein.

[0100] The host system 1443 may include a DDR memory controller 1430, a CPU subsystem 1452, and a serial bus memory controller 1445. The DDR memory controller 1430 may be connected to the DDR bus 1410 and the CPU subsystem 1452. In response to a request from the CPU subsystem 1452, the DDR memory controller 1430 may generate command sequences including NVR commands and equivalents described herein over the CA portion of the DDR bus 1410. The CPU subsystem 1452 may include one or more processing circuits 1429, instructions 1431 executable by the processing circuits 1429, and a cache memory 1454. The serial bus memory controller 1445 may be connected to the serial bus 1432. In response to a request from the CPU subsystem 1452, the serial bus memory controller 1445 may generate serial commands and data to access devices on the serial bus 1432, including the NVM devices 1400-0 / 1.

[0101] Having described the various portions of the system 1450, the cache fill operation for the system is now described.

[0102] The cache memory 1454 can be organized into cache lines (one shown as 1454-0) accessible by the processing circuitry 1429. According to an embodiment, the DDR memory controller 1430 can access one or more NVM devices 1400-0 / 1 with two fast read operations to retrieve data to fill a cache line (two shown as 1454-0) without having to discard any data. In some embodiments, a fast read command sequence to one or two NVM devices 1400-0 / 1 can retrieve an amount of read data equal to a cache line. In some embodiments, each fast read command sequence consists of a command sequence of only two commands. However, as will be appreciated from the embodiments herein, a fast command sequence can include a fewer or greater number of fast read (i.e., NVR) commands.

[0103] In some embodiments, this type of cache line fill operation is possible for a single NVM device. For example, via data path 1433-0, DDR memory controller 1430 can issue a fast read sequence to NVM device 1400-0 to access data 1455a. Data 1455a can be output in a burst sequence and can equal a cache line. In some embodiments, this type of data burst can be x32 (32 bits wide), have a burst length of 8, and can fill a cache line of 32 bytes.

[0104] In some embodiments, the fast read sequence can be pipelined (e.g., issued with no delay between or with no other intervening commands or operations). By way of example only, in a pipelined forwarding operation, data 1455a and 1455b can be output one after the other to fill two cache lines 1454-0 without having to discard any data. In some embodiments, data 1455a can be stored in one bank of NVM device 1400-0 and data 1455b can be stored in another bank of NVM device 1400-0.

[0105] In some embodiments, cache line fill operations are possible to different NVM devices. For example, DDR memory controller 1430 can issue a fast read sequence to both NVM device 1400-0 and NVM device 1400-1. The fast read sequence can access data 1455a and data 1455b'. Data 1455a and data 1455b' can be equal to the size of a cache line. In some embodiments, NVM devices 1400-0 and 1400-1 can each provide eight x16 data bursts in parallel to fill a 32-byte cache line. Fast read operations to multiple devices can be pipelined and output sequential data sets that each fill a cache line.

[0106] In some embodiments, cache fill operations are possible for the DRAM device 1458. The DRAM device 1458 may include a DDR interface 1404' that is compatible (or programmable to be compatible) with executing fast read commands.

[0107] 14, in some embodiments, the CPU subsystem 1452 may include either a parameter request procedure 1431-0 or a fast access configuration procedure 1431-1. The parameter request procedure 1431-0 may request parameter data from the NVM device 1400-0 / 1 that may identify whether such a device is compatible with fast access operations. The fast access configuration procedure 1431-1 may write data values ​​and configure the DDR memory controller 1430 for fast access operations.

[0108] In some embodiments, the DRAM device 1458 may have a DDR interface 1404' that is compatible with fast access commands, as described above. In other embodiments, the DRAM DDR I / F 1404' may not be compatible with fast access commands.

[0109] Referring to FIG. 15, an automobile 1566 system is illustrated according to one embodiment. The automobile system 1566 can have a number of subsystems (two shown as 1550-0 and 1550-1) operated by a host device (e.g., a CPU subsystem) that communicates with one or more NVM devices. Such subsystems (1550-0, 1550-1) can include an electronic control unit (ECU) and / or an advanced driver assistance system (ADAS). However, in other embodiments, such subsystems can include a dashboard display / control subsystem and / or an infotainment subsystem, as just two of many possible examples. Each subsystem (1550-0, 1550-1) can include a host device that can access the NVM device with fast access commands and equivalents described herein for fast retrieval of data. In some embodiments, such access can be for fast cache line fills. In some embodiments, the host device can be configured to execute code directly from the NVM device (i.e., execute in place). This is in stark contrast to conventional systems in which data (eg, code) can be loaded from a conventional NVM device into volatile memory (eg, SRAM) for access by a host device.

[0110] The described devices and systems disclose various methods according to embodiments, additional methods being described with reference to flow diagrams. Figure 16 is a flow diagram of a method 1670 for executing a fast access command by an NVM device according to one embodiment.

[0111] The method 1670 may include receiving a command (1670-0). Such actions may include receiving a command from a command address (CA) input of the NVM device. The method 1670 may determine if the received command is an NVR command (1670-2). Such actions may include determining if a particular bit position of the command identifies the command as an NVR command. If the command is not an NVR command (N in 1670-2), the method 1670 may process the commands as a set of a predetermined size (1670-14). Such actions may include processing commands as if they were a set of four commands rather than as a variable size NVR sequence.

[0112] If the received command is determined to be an NVR command (Y at 1760-2), the method 1670 may determine if a next command has been received (1670-6). Such actions may include receiving a command with substantially no delay relative to a previously received command. If a next command is not received (N at 1670-6), the NVR sequence may end (1670-12). In this manner, an NVR command sequence of one or more NVR commands may be determined.

[0113] If the next command is received (Y at 1670-6), the method 1670 may determine if the next command is an NVR command (1670-8). If the next command is an NVR command (Y at 1670-8), the method 1670 may return to 1670-4 and the next NVR command may be added to the NVR sequence. If the next command is not an NVR command (N at 1670-8), the NVR sequence may end (1670-10) and the non-NVR commands may be processed as a predefined set (1670-14).

[0114] When the NVR command sequence is completed (1670-10 or 1670-12), the method 1670 can access a memory device location according to the address data of the NVR sequence (1670-16).

[0115] FIG. 17 is a flow diagram of another method 1770 according to one embodiment. The method 1770 may be performed by a memory controller or the like to access data stored within an NVM device. The method 1770 may include requesting (1770-0) a parameter value from the NVM device. Such an action may include reading the parameter value from a memory location (e.g., a parameter register) of the NVM device. In some embodiments, such a request may occur through a DDR I / F of the NVM device. However, in other embodiments, such a request may occur through a serial I / F of the NVM device.

[0116] The method 1770 may determine (1770-2) whether the received parameter data indicates that the NVM device is capable of performing fast access operations. Such actions may include determining that one or more bits of a configuration value read from the NVM device have a predetermined value.

[0117] If the parameter value indicates that the NVM device can perform fast access (Y at 1770-2), the method 1770 may configure the NVR sequence size according to the size of the NVM device to be accessed (1770-4). For example, for some NVM devices, two NVR commands may have enough address bits to access all address locations. However, for larger devices, additional NVR commands may be included to provide more address bits. The method 1770 may further include receiving a request to access the NVM device (1770-6). Such a request may be received by the memory controller from a CPU subsystem (e.g., a host), or the like. In response to the request, the method 1770 may output an NVR sequence of the configured size (1770-8). Such an action may include outputting a sequence of NVR commands on a DDR bus, e.g., a CA portion of a LPDDR4 compatible bus. The method 1770 may include receiving data corresponding to the NVR sequence in a DDR burst of read data values ​​(1770-10). Such actions may include receiving data with ECC data. Additionally, in some embodiments, data received in bursts of 8 may correspond to the size of a cache line for the system or an integer fraction (e.g., 1 / 2, 1 / 4) of the cache line size. In some embodiments, DDR bursts of read data values ​​may be 8 or less. However, other embodiments may include larger sized bursts.

[0118] If the parameter value indicates that the NVM device cannot perform high speed access (N at 1770-2), the method 1770 may include receiving a request to access the NVM device (1770-12). However, in response to such a request, the method 1770 may output a read sequence of four or more commands (1770-14). Additionally, the data may be received in DDR bursts of data values ​​(1770-16). In some embodiments, such data values ​​may be in bursts of greater than eight, for example, bursts of 16 or 32.

[0119] FIG. 18 is a flow diagram of another method 1870 according to another embodiment. The method 1870 is executable by a system to fill cache lines of a cache memory with data read directly from one or more NVM devices. The method 1870 may include a host device or memory controller 1830 receiving a cache fill request for a cache having cache lines having a size of X bytes (1870-2). Such an action may include the host device issuing a read request to the memory controller. The value X is understood to be a number greater than 1. In some embodiments, X may be an even number greater than 4. The method 1870 may include issuing an NVR command sequence for each cache line of the cache fill request (1870-4). Such an action may include issuing such a command sequence on a command address bus that is separate from the data bus. In some embodiments, such a command address bus may have a width of 6 bits or less.

[0120] The method 1870 may include outputting X bytes of data in a DDR burst for each NVR sequence (1870-6). Such actions may include outputting data from more than one NVM device on the DDR bus. In some embodiments, such actions may include outputting data from two different NVM devices in response to the same command address value. In some embodiments, such DDR bursts may have a burst length of 8. However, in other embodiments, the DDR bursts may be of a larger size, e.g., 16 or 32.

[0121] The method 1870 may fill the cache line with X bytes of data received from one or more NVM devices (1870-8). Such actions may include filling the cache line without discarding any read data received from the NVM devices.

[0122] According to embodiments, the NVM device can provide high speed access for higher temperature systems. Such NVM devices can eliminate the need for volatile memory, e.g., SRAM or DRAM. This can enable more compact systems and / or reduced system costs.

[0123] According to an embodiment, the NVM device can provide more efficient use of the CA bus for smaller data transfers by enabling fast access requests over four clock cycles as opposed to eight clock cycles. Furthermore, smaller data transfers can enable more efficient cache fills. As one of many possible examples, as shown in FIG. 5 and FIG. 19, in a x32 configuration, the NVM device can have a cache line fill latency of 28.75 ns (at an 800 MHz clock) as opposed to a DRAM device latency of 38.75 ns. Furthermore, DRAM accesses can end up discarding data. This type of capability can enable a new cache line fill every 5 ns (at an 800 MHz clock) as opposed to every 10 ns (with data discard).

[0124] It should be understood that throughout this specification, a reference to "one embodiment" or "an embodiment" means that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the invention. It should therefore be emphasized and recognized that two or more references to "an embodiment" or "one embodiment" or "alternative embodiments" in various parts of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined as appropriate in one or more embodiments of the invention.

[0125] Similarly, in the exemplary embodiments of the invention described above, it should be understood that various features of the invention are sometimes grouped together in a single embodiment, drawing or description in order to streamline the disclosure to aid in understanding one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as expressly expressing an intention that the claims require more features than are expressly recited in each claim. Rather, inventive aspects may be less than all features of a single above-described disclosed embodiment. Thus, the claims following the detailed description are expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

Claims

1. receiving a plurality of successive commands on a unidirectional command address (CA) bus input of a discrete non-volatile memory (NVM) device, said commands being synchronous to a timing clock; for each received command, determining whether the command is a non-volatile read (NVR) command; if the command is determined to be an NVR command, determining whether a next consecutive command is an NVR command, the consecutive NVR commands forming an NVR command sequence; accessing read data stored in NVM cells of the NVM device in response only to the NVR command sequences; driving the read data onto a parallel data input / output (I / O) of the NVM device in bursts of data values, the data values ​​of the bursts being output synchronously with rising and falling edges of the timing clock; Including, the CA bus input includes a plurality of parallel CA signal inputs; method.

2. the NVR commands on the CA bus inputs and the data values ​​on the data I / O are generated by signaling compatible with the LPDDR4 standard. The method of claim 1.

3. the NVR command includes bit value positions that correspond to bit value positions of a command compatible with the LPDDR4 standard; At least one NVR command includes address data at bit positions where the LPDDR4 compatible command includes command data; The method of claim 1.

4. The method further includes receiving each NVR command over an integer multiple of two cycles of the timing clock, the integer being equal to or greater than 1. The method of claim 1.

5. the NVR command sequence includes all command and address values ​​necessary to access the read data; The method of claim 1.

6. each NVR command has a format compatible with commands in the LPDDR4 standard, including a command bit position that identifies said command; determining whether the command is an NVR command includes determining whether a command bit position of the NVR command matches a predetermined value; The method of claim 1.

7. The method comprises: receiving a serial command and serial address value on a serial port of the NVM device, the serial port being distinct from the CA input and data I / O; accessing an NVM cell of the NVM device in response to the serial command and an address value; Further comprising: The method of claim 1.

8. the burst of data values ​​has a burst length (BL) that is configurable to one of a plurality of BL values, at least one BL value being less than or equal to 8; The method of claim 1.

9. 1. An integrated circuit (IC) device, comprising: a command address (CA) input including a plurality of parallel CA inputs; a data bus input / output (I / O) including a plurality of parallel data I / Os configured to receive at least the burst data values ​​synchronously with rising and falling edges of a timing clock; at least one non-volatile memory (NVM) cell array; a command decoder configured to detect commands received at the CA input, including a fast read (NVR) command sequence; An access circuit; Equipped with each NVR command sequence includes a number of consecutive NVR commands that are distinguishable from other commands by bit values ​​of the NVR commands; Each NVR command sequence is terminated by receipt of a non-NVR command or by the end of successive command reception; the access circuitry is configured to access the at least one NVM cell array and output read data in response only to the NVR command sequence received on the CA bus input. Integrated circuit (IC) devices.

10. The CA bus includes six CA inputs; The CA bus and data bus I / O are compatible with the LPDDR4 physical interface standard; 10. The IC device of claim 9.

11. All address data for accessing the read data is included in the NVR command sequence.

10. The IC device of claim 9.

12. the NVR command includes bit value positions that correspond to bit value positions of a command compatible with the LPDDR4 standard; At least one NVR command includes address data at bit positions where the LPDDR4 compatible command includes command data; 10. The IC device of claim 9.

13. each NVR command is received at the CA input over an integer multiple of two cycles of the timing clock, the integer being greater than or equal to 1; 10. The IC device of claim 9.

14. the IC device further includes a serial bus input including at least one serial I / O line configured to receive serial command and serial address data; the access circuitry is configured to access the at least one NVM cell array in response to a serial command and serial address data; 10. The IC device of claim 9.

15. the burst of data values ​​has a burst length (BL) that is configurable to one of a plurality of BL values, at least one BL value being less than or equal to 8; 10. The IC device of claim 9.

16. a unidirectional command address (CA) bus; A bidirectional data bus; a host system having a memory controller; A memory system; A system comprising: the memory controller is configured to issue a sequence of consecutive fast memory read (NVR) commands on the CA bus, each NVR command being issued synchronously with a timing clock and including a bit value that distinguishes the NVR command from other commands; the memory controller is configured to receive on the data bus read data corresponding to the sequence of NVR commands; The memory system includes at least one NVM cell array, a command decoder circuit, and an access circuit; The command decoder circuit includes: For each received command, determining whether the command is a non-volatile read (NVR) command; If the command is determined to be an NVR command, determining whether the next consecutive command is an NVR command; It is configured as follows: Consecutive NVR commands form an NVR command sequence, The access circuitry responds only to the NVR command sequence by: accessing the at least one NVM cell array and accessing read data stored in the NVM cell array; outputting said read data on said data bus in bursts of data values; wherein the data values ​​of the burst are output in synchronization with rising and falling edges of the timing clock. system.

17. The memory controller includes a controller interface (I / F) connected to the CA bus and a data bus, the memory system includes a memory device I / F connected to the CA bus and the data bus; The controller I / F and the memory device I / F are compatible with the LPDDR4 physical I / F standard; 17. The system of claim 16.

18. the NVR command includes bit value positions that correspond to bit value positions of a command compatible with the LPDDR4 standard; At least one NVR command includes address data at bit positions where the LPDDR4 compatible command includes command data; 17. The system of claim 16.

19. the host system includes at least one cache memory having cache lines of a predetermined size; a size of the read data output by the NVM system in the burst of data values ​​that corresponds to the predetermined size; 17. The system of claim 16.

20. the memory controller issues each NVR command over an integer multiple of two cycles of the timing clock, the integer being greater than or equal to 1; 17. The system of claim 16.

21. the host system is configured to request parameter data from the NVM system; encoding a read request to the NVM system into an NVR command sequence in response to the parameter data having a predetermined value; 17. The system of claim 16.

22. The memory system further includes at least one volatile memory cell array and a volatile memory access circuit; The volatile memory access circuit responds only to an NVR command sequence by: accessing the at least one volatile memory cell array and accessing volatile read data stored in the memory cell array; outputting the volatile read data on the data bus in a volatile memory burst of volatile data values; wherein the volatile data values ​​of the volatile memory bursts are output synchronously with rising and falling edges of the timing clock.

17. The system of claim 16.

23. the burst of data values ​​has a burst length (BL) that is configurable to one of a plurality of BL values, at least one BL value being less than or equal to 8; 17. The system of claim 16.

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