Semiconductor device

Abstract

To provide a semiconductor device suitable for miniaturization.SOLUTION: A semiconductor device comprises: a first element; a first insulator on the first element; a first barrier film on the first insulator; a first conductor on the first barrier film; a second barrier film on the first conductor; a second insulator on the second barrier film; and a semiconductor on the second insulator. The first conductor is surrounded by the first barrier film and the second barrier film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The present invention relates to a method, manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. The present invention relates to a driving method thereof or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Devices, storage devices, imaging devices, electro-optical devices, power generation devices (thin-film solar cells, organic thin-film solar cells etc.), and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials that can be used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0004] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating a transistor using this method have been disclosed (see Patent Documents 1 and 2).

[0005] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. 2. Description of the Related Art There is an increasing demand for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a highly integrated semiconductor device.

[0008] Another object of another embodiment of the present invention is to provide a highly reliable semiconductor device. do.

[0009] Another object is to provide a semiconductor device with good electrical characteristics. Another object of the present invention is to provide a semiconductor device having a novel structure. One of the objectives is to provide the following.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising a first element, a first insulator on the first element, and a first insulating layer on the first element. A first barrier film on an insulator, a first conductor on the first barrier film, and a second barrier film on the conductor; a second insulator on the second barrier film; and a semiconductor on an insulator, the first conductor being interposed between the first barrier film and the second The semiconductor device is surrounded by a barrier film.

[0012] Another aspect of the present invention is a semiconductor device including a first element, a first insulator on the first element, and a first barrier film on the first insulator, and a first conductor on the first barrier film; a second barrier film on the first conductor and a second insulator on the second barrier film; a semiconductor over the second insulator, the first insulator having a groove or opening, At least a portion of the first conductor is disposed in the groove or the opening, and the first conductor is The semiconductor device is surrounded by the first barrier film and the second barrier film.

[0013] Another embodiment of the present invention is a semiconductor device including a first conductor in contact with the semiconductor, a second conductor provided in an opening provided in the semiconductor and the first conductor; It is a semiconductor device.

[0014] Another aspect of the present invention is a semiconductor device including a first element, a first insulator on the first element, and a first barrier film on the first insulator, and a first conductor on the first barrier film; a second barrier film on the first conductor and a second insulator on the second barrier film; a semiconductor on the second insulator, a second conductor in contact with the semiconductor, and and electrically connecting the first element provided in an opening provided in the second conductor. and a third conductor.

[0015] Another aspect of the present invention is a semiconductor device including a first element, a first insulator on the first element, and a first barrier film on the first insulator, and a first conductor on the first barrier film; a second barrier film on the first conductor and a second insulator on the second barrier film; a semiconductor on the second insulator, a second conductor in contact with the semiconductor, and and a third insulator on the second conductor, and a semiconductor and a third insulator overlapping each other. and a third conductor comprising the first insulator having a groove or opening, and the first conductor At least a portion of the first conductor is provided in the groove or the opening, and the first conductor is an opening formed in the semiconductor and the second conductor and surrounded by the barrier film and the second barrier film; and a fourth conductor electrically connected to the first element provided on the first substrate. be.

[0016] Another aspect of the present invention is a semiconductor device including a first element, a first insulator on the first element, and a first barrier film on the first insulator, and a first conductor on the first barrier film; a second barrier film on the first conductor and a second insulator on the second barrier film; a semiconductor on the second insulator, a second conductor in contact with the semiconductor, and and a third insulator on the second conductor, and a semiconductor and a third insulator overlapping each other. a third conductor, a third barrier film on the third conductor, and a third barrier film and a second element on the first conductor, the first conductor being connected to the first barrier film and the second barrier film. The first conductive film is surrounded by an insulating film and is provided in an opening in the semiconductor and the second conductive film. and a fourth conductor electrically connected to the second element. do.

[0017] Another aspect of the present invention is a semiconductor device including a first element, a first insulator on the first element, and a first barrier film on the first insulator, and a first conductor on the first barrier film; a second barrier film on the first conductor and a second insulator on the second barrier film; a semiconductor on the second insulator, a second conductor in contact with the semiconductor, and and a third insulator on the second conductor, and a semiconductor and a third insulator overlapping each other. a third conductor, a third barrier film on the third conductor, and a third barrier film and a second element on the first insulator, the first insulator having a groove or an opening, the first conductor At least a portion of the first conductor is provided in the groove or the opening, and the first conductor is an opening formed in the semiconductor and the second conductor and surrounded by the barrier film and the second barrier film; a fourth conductor electrically connected to the first element and the second element provided on the The semiconductor device has the following features.

[0018] The first, second and third barrier films are made of silicon nitride, silicon oxynitride, and silicon oxynitride, respectively. Aluminum oxide, aluminum oxide nitride, gallium oxide, gallium oxide nitride, oxide Of yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride, It is preferred to include at least one.

[0019] The second barrier film may be an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based Oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride semiconductor film, S n-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN, ZnN, etc.), etc. It is possible to use at least one of these materials, or a laminate of a plurality of materials. It is also possible.

[0020] In addition, an insulating film containing an oxide is provided between the first barrier film and the semiconductor, and the insulating The film preferably has regions containing more than stoichiometric oxygen. .

[0021] The oxide-containing insulating film has a hydrogen concentration of 5×10 18 atoms / cm 3 It is preferred to have an area of ​​less than 100 nm.

[0022] In addition, the semiconductor contains hydrogen at a concentration of 5×10 18 atoms / cm 3 Less than It is preferred to have a region.

[0023] The second element is a transistor, and the third insulator is a gate of the transistor. The gate insulating film has a hydrogen concentration of 5×10 18 atoms / cm 3 It is preferred to have an area of ​​less than 100 nm.

[0024] In addition, the above transistors have a subthreshold swing value of 60mV / dec. or more. , preferably 100 mV / dec. or less. Effect of the Invention

[0025] According to one embodiment of the present invention, a semiconductor device suitable for miniaturization can be provided.

[0026] Alternatively, it is possible to impart good electrical characteristics to the semiconductor device. It is possible to provide a semiconductor device. Or, it is possible to provide a semiconductor device having a novel configuration. The description of these effects does not preclude the existence of other effects. An embodiment of the present invention does not necessarily have all of these effects. Other effects are obvious from the description, drawings, claims, etc. Other effects can be extracted from the detailed description, drawings, claims, etc. [Brief description of the drawings]

[0027] [Figure 1] 1 shows a configuration example of a semiconductor device according to an embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a stacked structure included in a semiconductor device according to an embodiment; [Diagram 3] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 4] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 5] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 6] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are circuit diagrams and configuration examples of a semiconductor device according to an embodiment. [Figure 8] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 9] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 10] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 11] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 12] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 13] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 14]Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 15] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 16] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 17] Electron diffraction pattern of CAAC-OS. [Figure 18] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 19] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Figure 20] A diagram explaining InGaZnO4 crystals and pellets. [Figure 21] Schematic diagram explaining a film formation model of CAAC-OS. [Figure 22] FIG. [Diagram 23] 3 shows a configuration example of an RF device according to an embodiment. [Figure 24] 3 shows an example of the configuration of a CPU according to the embodiment. [Diagram 25] 1 is a circuit diagram of a memory element according to an embodiment. [Figure 26] 1 is a circuit diagram of a display device according to an embodiment. [Figure 27] 1 is an electronic device according to an embodiment. [Figure 28] 1 shows an example of use of an RF device according to an embodiment. [Figure 29] 1A to 1C are diagrams illustrating a band structure according to an embodiment. [Diagram 30] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 31] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 32] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 33] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 34] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 35] 1 shows a configuration example of a semiconductor device according to an embodiment. [Diagram 36] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 37] 1 shows a configuration example of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and the repeated explanations are omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be used.

[0030] In each figure described in this specification, the size, layer thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0031] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are added for the purpose of convenience and are not intended to be limiting.

[0032] In this specification, the electrodes and the wiring electrically connected to the electrodes are integrated. That is, a part of the wiring may function as an electrode, or a part of the electrode may function as a wiring. In some cases, it may be possible.

[0033] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0034] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0035] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0036] (Embodiment 1) [Example of laminated structure] A transistor 100 that can be used in a semiconductor device of one embodiment of the present invention will be described below. An example of a laminate 10 including the following will be described. FIG. 1 is a schematic cross-sectional view of the laminate 10 shown below. be.

[0037] In addition, various elements can be formed and stacked on the upper or lower layers of the laminate 10. 1 shows an example in which the laminate 10 is laminated on the laminate 20, and the laminate 30 is laminated on the laminate 10. In FIG. For example, a single crystal silicon semiconductor is formed as the laminate 20, and then the laminate 10 is formed thereon. It is also possible to further form elements such as capacitors on top as a laminate 30 .

[0038] The laminate 10 includes an insulator 102 in contact with the upper surface of the insulator 101 and a dielectric film formed on the insulator 102. The groove or opening and the burr that contacts the inside of the groove or opening and the upper surface of the insulator 102. The insulating film 103 is a conductive film provided in the groove or opening of the insulator 102 via the barrier film 103. The conductor 104a, the barrier film 105a in contact with the upper surface of the conductor 104a, and the barrier film 103 An insulator 106 contacting the upper surface and the upper surface of the barrier film 105a, and a A semiconductor 107a, a semiconductor 108a in contact with the upper surface of the semiconductor 107a, and a semiconductor 108a The conductor 109b and the conductor 109c are in contact with the upper surface and are spaced apart from each other in a region overlapping with the semiconductor 108a. At least the conductor 109b, the conductor 109c, the semiconductor 108a, and the semiconductor 107a A plurality of plugs 120a, 120b are provided in openings in the semiconductor 108a. A semiconductor 113 in contact with the upper surface, an insulator 114 in contact with the upper surface of the semiconductor 113, and an insulator 11 4, and at least a semiconductor 107a, a semiconductor 108a, and a semiconductor A barrier film 116 is provided to cover the insulating film 113 .

[0039] The conductor 104a and the barrier film 105a are provided to overlap the semiconductor 108a. The gate electrode 104a functions as a second gate electrode.

[0040] In addition, since the conductor 104a is surrounded by the barrier film 103 and the barrier film 105a, The conductor 104a can be prevented from being oxidized.

[0041] One of the conductors 109b and 109c functions as a source electrode and the other functions as a drain electrode. The plugs 120a and 120b have at least a side surface that is in contact with the semiconductor 108. a, one of the plugs 120a and 120b functions as a source electrode, and the other functions as a drain electrode. The plug 120a functions as a drain electrode. The plug 120b is made up of conductors 111c and 112b.

[0042] In addition, the plugs 120a and 120b are connected to the conductors 109b and 109c and the semiconductors 108a and Since the semiconductor device is formed in an opening in the semiconductor 107a, the semiconductor device can be miniaturized. do.

[0043] The insulator 114 is provided between the semiconductor 108a and the conductor 115 and serves as a gate insulating film. It works like this.

[0044] The conductor 115 is provided to overlap the semiconductor 108a and functions as a first gate electrode. has.

[0045] The transistor 100 includes at least a semiconductor 108a, an insulator 114, and a conductor 115. 15 and others.

[0046] The insulator 101 is preferably made of silicon nitride having a thickness of about 50 nm. The insulator 102 is made of TEOS (Tetra-Ethylene Oxide) having a thickness of about 150 nm. It is preferable to use silicon oxide formed using ethyl-ortho-silicate. stomach.

[0047] The insulator 102 may be made of a material that has an etching selectivity with respect to the insulator 101. Each of the insulators 101 and 102 is made of, for example, silicon oxide, silicon oxynitride, Silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, oxynitride Aluminum, aluminum nitride, or the like may also be used, and may be a laminate or a single layer.

[0048] The insulator 102 is a planarizing layer that flattens steps caused by structures provided in the lower layer. The upper surface of the insulator 102 is subjected to CMP (chemical mechanical polishing) to improve the flatness of the upper surface. Flattening process using chemical mechanical polishing method etc. The surface may be planarized by a method such as the above-mentioned.

[0049] The barrier film 103 and the barrier film 116 can be made of a material such as silicon nitride. , silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, nitrile Gallium oxide, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Aluminum oxide, in particular, has excellent barrier properties against water and hydrogen. This is preferable because

[0050] The barrier film 103 and the barrier film 116 are layers of materials that are difficult to permeate water and hydrogen, as well as other Layers containing an insulating material may be stacked. For example, silicon oxide or silicon oxynitride may be used. A layer containing carbon and a layer containing a metal oxide may be laminated.

[0051] Here, in the layer below the barrier film 103, hydrogen, water, etc. are reduced or removed as much as possible. It is preferable to suppress the gas. Hydrogen and water cause fluctuations in the electrical properties of oxide semiconductors. In addition, hydrogen may diffuse from the lower layer to the upper layer through the barrier film 103. The barrier film 103 can suppress the moisture.

[0052] The hydrogen and water contained in each layer below the barrier film 103 are reduced as much as possible. In order to suppress outgassing, a plasma is applied before forming the barrier film 103 or on the barrier film 103. Immediately after the openings for forming the lugs 120a and 120b are formed, the barrier film 103 is It is preferable to carry out a heat treatment to remove hydrogen and water contained in the lower layer. As long as the heat resistance of the conductive film and the electrical characteristics of the transistor are not deteriorated, The higher the temperature of the heat treatment, the more preferable. Specifically, for example, 450° C. or higher, preferably 490° C. or higher. The temperature should be 530° C. or higher, preferably 530° C. or higher, but may be 650° C. or higher. The mixture is stirred in an inert gas atmosphere or a reduced pressure atmosphere for at least 1 hour, preferably at least 5 hours. It is preferable to carry out the heat treatment for 10 hours or more. The temperature can be determined by taking into consideration the heat resistance of the wiring, electrodes, or plug materials included in the device. For example, if the material has low heat resistance, the temperature should be 550°C or less, 600°C or less, or 65 The heat treatment may be performed at a temperature of 0°C or less or 800°C or less. Both may be performed at least once, but it is more preferable to perform them multiple times.

[0053] In addition, the barrier film 103 and the barrier film 116 may be made of a material that is difficult for oxygen to permeate. The above-mentioned materials are excellent barrier materials against oxygen as well as hydrogen and water. By using such a material, oxygen released when the insulator 106 is heated can be prevented from entering the insulating layer 106. Diffusion into layers below the film 103 and above the barrier film 116 is suppressed. As a result, the semiconductor 107a, the semiconductor 108a, and the semiconductor 109 are released from the insulator 106. The amount of oxygen that can be supplied to the conductor 113 can be increased.

[0054] In this way, the concentration of hydrogen and water contained in each layer located below the barrier film 103 is reduced. The barrier film 103 prevents hydrogen and water from entering the semiconductor 107. a, semiconductor 108a, and semiconductor 113. The hydrogen and water contents in the semiconductor layers 108a and 113 are extremely low. For example, the semiconductor 107a, the semiconductor 108a, the semiconductor 113, and is the hydrogen concentration in the insulator 114, which is 5×10 18 atoms / cm 3 Less than, preferably 1×10 18 atoms / cm 3 less than 3×10 17 atoms / cm 3 It is possible to reduce the

[0055] The conductor 104a may be made of tantalum, tungsten, titanium, molybdenum, chromium, or nickel. Metals selected from the group consisting of carbide, etc., or alloy materials or compounds mainly composed of these metals It is preferable to use polycrystalline silicon doped with impurities such as phosphorus. A laminated structure of a metal nitride film and the above-mentioned metal film may also be used. Examples of the material that can be used include tungsten nitride, molybdenum nitride, and titanium nitride. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented. It is possible.

[0056] The conductor 104a is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal may also be used.

[0057] For example, the conductor 104a may have a three-layered structure. The first layer is titanium, the second layer is titanium, and the third layer is titanium. The second layer on the first layer is titanium nitride, and the third layer on the second layer is tungsten. A laminated structure such as the above may also be used.

[0058] The barrier film 105a is an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, or the like. Semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride semiconductor film, Sn-based oxynitride semiconductor film Providing a nitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.), etc. These films have a work function of 5 eV or more, preferably 5.5 eV or more, Since the electron affinity is larger than that of oxide semiconductors, transistors using oxide semiconductors The threshold voltage of the transistor can be shifted to the positive side, making it possible to switch the transistor with normally-off characteristics. For example, when an In-Ga-Zn-based oxynitride semiconductor film is used, At least, the In- A Ga-Zn-based oxynitride semiconductor film is used.

[0059] It is preferable that the barrier film 105a is made of a material that does not easily diffuse oxygen. The conductor 104a can be prevented from being oxidized, and the resistance value of the conductor 104a can be prevented from increasing. come.

[0060] The insulator 106 is preferably made of an oxide material from which oxygen is partially released by heating. .

[0061] As an oxide material that releases oxygen by heating, It is preferable to use an oxide containing more oxygen than the stoichiometric composition. When an oxide film containing oxygen is heated, some of the oxygen is released. The oxide film containing more oxygen than the The oxygen in terms of oxygen atoms was analyzed by Esorption Spectroscopy. The amount of desorption is 1.0×10 18 atoms / cm 3 More than 3.0×10 20 at oms / cm 3 The oxide film is as above. Note that the surface temperature of the film during the TDS analysis was The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. stomach.

[0062] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can be used. , aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, iridium oxide Examples include yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride. In this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen as its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. When an oxide semiconductor is used as the semiconductor material, the The oxygen thus obtained is supplied to the oxide semiconductor, and oxygen vacancies in the oxide semiconductor can be reduced. As a result, the fluctuation of the electrical characteristics of the transistor can be suppressed, and the reliability can be improved. .

[0063] Before the formation of the insulator 106, the upper surface of the barrier film 103 and the upper surface of the barrier film 105a are If the structure has no steps, the insulator 106 can be formed thin.

[0064] The semiconductor 108a is a semiconductor such as a silicon-based semiconductor in a region where a channel is formed. In particular, the semiconductor 108a may include a material having a band gap larger than that of silicon. It is preferable that the semiconductor 108a includes an oxide semiconductor. A semiconductor material with a wider band gap and lower carrier density than silicon is called The use of such a compound is preferable because it can reduce the current in the off state of the transistor.

[0065] For example, the oxide semiconductor may contain at least indium (In) or zinc (Zn It is preferable that the oxide contains In-M-Zn (wherein M is Al, Ti, Metals such as Ga, Ge, Y, Zr, Sn, La, Ce or Hf) are included. nothing.

[0066] In particular, the semiconductor has a plurality of crystal parts, and the c-axis of the crystal parts is aligned with the surface on which the semiconductor is formed, or or an oxide that is oriented perpendicular to the upper surface of the semiconductor and has no grain boundaries between adjacent crystal portions. It is preferable to use a semiconductor film.

[0067] By using such materials as semiconductors, fluctuations in electrical properties are suppressed, leading to high reliability. This makes it possible to realize a high-speed transistor.

[0068] Note that a preferred embodiment of an oxide semiconductor that can be used as a semiconductor and a method for forming the same will be described later. This will be described in detail in the following embodiment.

[0069] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor and an insulator overlapping the oxide semiconductor. At least one metal element among the metal elements constituting the oxide semiconductor is used as a constituent element between the oxide semiconductor and the metal element. It is preferable that the oxide semiconductor and the oxide semiconductor are included. It is possible to suppress the formation of trap levels at the interface with the overlapping insulator.

[0070] That is, one embodiment of the present invention is a method for forming an oxide semiconductor layer on at least a channel formation region of the oxide semiconductor. The top and bottom surfaces of the oxide semiconductor function as barrier films to prevent the formation of interface states in the oxide semiconductor. It is preferable that the oxide semiconductor layer is in contact with the object. Suppresses the generation of oxygen vacancies and the inclusion of impurities, which are factors that cause carrier generation in the semiconductor and at the interface. Since it is possible to control the amount of the oxide semiconductor, the oxide semiconductor can be made highly purified and intrinsic. The term "inertization" refers to making an oxide semiconductor intrinsic or substantially intrinsic. This suppresses fluctuations in the electrical characteristics of transistors, including compound semiconductors, to provide highly reliable semiconductor devices. It becomes possible to do so.

[0071] Note that in this specification and the like, when an oxide semiconductor is referred to as being substantially intrinsic, the carrier density of the oxide semiconductor is 1×10 17 / cm 3 Less than 1×10 15 / cm3 Less than or equal to 1 × 10 13 / cm 3 Not yet By making the oxide semiconductor highly purified and intrinsic, it is possible to provide stable electrical characteristics to the transistor. It can be granted.

[0072] The semiconductor 107a is disposed between the insulator 106 and the semiconductor 108a.

[0073] The semiconductor 113 is provided between the semiconductor 108a and the insulator 114 which functions as a gate insulating film. It is being done.

[0074] The semiconductor 107a and the semiconductor 113 each contain one of the same metal elements as the semiconductor 108a. It is preferable that the oxide contains at least one of these.

[0075] Note that the boundary between the semiconductor 108a and the semiconductor 107a and the boundary between the semiconductor 108a and the semiconductor 113 The border may be unclear.

[0076] For example, the semiconductor 107a and the semiconductor 113 include In or Ga, and are typically , In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Al, Ti , Ga, Y, Zr, La, Ce, Nd or Hf) and is more conductive than the semiconductor 108a. A material whose conduction band lower edge energy is close to the vacuum level is used. or the energy of the lower end of the conduction band of the semiconductor 113 and the energy of the lower end of the conduction band of the semiconductor 108a. The difference in energy between the 5 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less It is preferable that the semiconductor 113 be made of gallium oxide or the like. In some cases, the semiconductor 113 may function as a part of the gate insulating film.

[0077] The semiconductor 108a is sandwiched between the semiconductor 107a and the semiconductor 113. By using an oxide with a higher Ga content that functions as a stabilizer compared to 108a, This makes it possible to suppress release of oxygen from the semiconductor 108a.

[0078] The semiconductor 108a may be, for example, In:Ga:Zn=1:1:1 or 3:1:2. When an In-Ga-Zn oxide having a certain ratio is used, the semiconductor 107a or the semiconductor 113 is For example, In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4, 1: In-Ga-Zn oxide with atomic ratios of 6:8, 1:6:10, or 1:9:6 The atoms of the semiconductor 108a, the semiconductor 107a, and the semiconductor 113 can be used. The atomic ratios are subject to a margin of error of ±20%. The semiconductor 107a and the semiconductor 113 may be made of materials having the same composition or materials having different compositions. Fees may also be used.

[0079] In addition, when an In-M-Zn oxide is used as the semiconductor 108a, the semiconductor 108a and The target used for forming the semiconductor film is a metal element contained in the target. When the atomic ratio is In:M:Zn=x1:y1:z1, the value of x1 / y1 is 1 / 3 or less. z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, It is preferable to use an oxide having an atomic ratio of 1 to 6. In addition, when z1 / y1 is 6 or less, This makes it easier to form the CAAC-OS film described later. Typical examples of the atomic ratio include In:M:Zn = 1:1:1, 3:1:2, etc.

[0080] Further, when an In-M-Zn-based oxide is used as the semiconductor 107a and the semiconductor 113, for forming the oxide films that become the semiconductor 107a and the semiconductor 113, the target used is such that when the atomic ratio of the metal elements contained in the target is In:M:Zn = x2:y2:z2, x2 / y2 < x1 / y1, and it is preferable to use an oxide having an atomic ratio where the value of z2 / y2 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. By setting z2 / y2 to 6 or less, it becomes easier to form the CAAC-OS film described later. Typical examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:4, 1:3:6, 1:3:8, etc.

[0081] Further, by using a material for the semiconductor 107a and the semiconductor 113 whose conduction band bottom energy is closer to the vacuum level than that of the semiconductor 108a, a channel is mainly formed in the semiconductor 108a, and the semiconductor 108a becomes the main current path. In this way, by sandwiching the semiconductor 108a in which the channel is formed with the semiconductor 107a and the semiconductor 113 containing the same metal element, the generation of these interface levels is suppressed, and the reliability in the electrical characteristics of the transistor is improved.

[0082] Note that this is not limited thereto, and those having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic ratio of metal elements and oxygen, interatomic distance, and density of the semiconductor 108a, the semiconductor 107a, and the semiconductor 11 3 It is preferable to set the degree, etc., appropriately.

[0083] Here, between the semiconductor 107a and the semiconductor 108a, In addition, between the semiconductor 108a and the semiconductor 113, There may be a mixed region of the semiconductor 108a and the semiconductor 113. The mixed region may be an interface state. Therefore, the density of the semiconductor 107a, the semiconductor 108a, and the semiconductor 113 is reduced. The body has a continuous change in energy near each interface (also called a continuous junction). .) band structure.

[0084] Here, the band structure will be explained (FIGS. 29(A) and (B)). Insulator 106, semiconductor 107a, semiconductor 108a, semiconductor 113, and The energy (Ec) of the conduction band minimum of the insulator 114 functioning as a gate insulating film is shown.

[0085] As shown in FIG. 29(A) and FIG. 29(B), a semiconductor 107a, a semiconductor 108a, a semiconductor In the semiconductor 107a, the energy of the conduction band minimum changes continuously. Since the semiconductor 108a and the semiconductor 113 are made of the same elements, oxygen diffuses between them. This can also be understood from the fact that the semiconductor 107a, the semiconductor 108a, and the semiconductor Although 113 is a laminate of layers with different compositions, it can also be said to be physically continuous.

[0086] The oxide semiconductors that are stacked with the same main component are not simply stacked, but are joined together in a continuous manner. In the case of a U-shaped well structure (here, in particular, the energy of the conduction band edge changes continuously between layers), In other words, trap centers and recombination centers are formed at the interfaces of each layer. The layered structure is formed so that there are no impurities that would create such defect levels. When impurities are present between the layers of a laminated multilayer film, the continuity of the energy band is lost. At the interface, carriers are trapped or disappear due to recombination.

[0087] In FIG. 29A, the semiconductor 107a and the semiconductor 113 have the same Ec. For example, the semiconductor 107a is semiconductor 107b. When Ec of 13 has high energy, part of the band structure is as shown in Figure 29(B). As shown.

[0088] As shown in FIG. 29(A) and FIG. 29(B), the semiconductor 108a serves as a well, and a channel It can be seen that the semiconductor 107a, the semiconductor 108a, The energy of the conduction band edge of the semiconductor 113 changes continuously, so it is called a U-shaped well (U The chuck formed in this way can also be called a "shape well." The channel can also be called a buried channel.

[0089] In addition, near the interface between the semiconductor 107a and the semiconductor 113 and an insulating film such as a silicon oxide film, A trap level due to impurities or defects may be formed near the semiconductor 107a. The conductor 113 can separate the semiconductor 108a from the trap level. However, the Ec of the semiconductor 107a or the semiconductor 113 and the Ec of the semiconductor 108a When the energy difference is small, electrons in the semiconductor 108a exceed the energy difference and enter the trap level. When electrons are captured in the trap level, negative charges are generated at the interface of the insulating film. This generates a fixed charge, and the threshold voltage of the transistor shifts in the positive direction.

[0090] Therefore, in order to reduce the variation in the threshold voltage of the transistor, the semiconductor 107a and It is necessary to provide an energy difference between Ec of the semiconductor 113 and the semiconductor 108a. The respective energy differences are preferably 0.1 eV or more, more preferably 0.15 eV or more. This is more preferable.

[0091] The semiconductor 107a, the semiconductor 108a, and the semiconductor 113 may include a crystalline portion. It is particularly preferable to use crystals oriented along the c-axis to provide stable electrical characteristics to transistors. It can be given.

[0092] In the band structure shown in FIG. 29B, the semiconductor 113 is not provided. Between 108a and the insulator 114 functioning as a gate insulating film, an In-Ga oxide (e.g. For example, an atomic ratio of In:Ga=7:93 may be used.

[0093] The semiconductor 108a is an oxide having a larger electron affinity than the semiconductor 107a and the semiconductor 113. For example, the semiconductor 108a is made of a material other than the semiconductor 107a and the semiconductor 113. Electron affinity: 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less Preferably, the oxide has an electron transport potential of 0.15 eV or more and 0.4 eV or less. The sum energy is the difference between the vacuum level and the energy at the bottom of the conduction band.

[0094] Here, the thickness of the semiconductor 108a is at least thicker than that of the semiconductor 107a. It is preferable that the semiconductor 108a is thicker than the semiconductor 108a. In addition, the semiconductor 107a does not lose the effect of suppressing the generation of interface states in the semiconductor 108a. For example, the thickness of the semiconductor 108a is set to be approximately the same as that of the semiconductor 107a. It is more than 1 time, preferably 2 times or more, more preferably 4 times or more, and more preferably If it is not necessary to increase the on-state current of the transistor, However, the thickness of the semiconductor 107a may be equal to or greater than the thickness of the semiconductor 108a.

[0095] In addition, the semiconductor 113, like the semiconductor 107a, suppresses the generation of interface states in the semiconductor 108a. For example, the thickness may be equal to or greater than that of the semiconductor 107a. If the semiconductor 113 is thick, the semiconductor 113 may function as a gate electrode. Since there is a risk that the electric field from 115 may not reach the semiconductor 108a easily, the semiconductor 113 is thin. For example, it is preferable that the thickness of the semiconductor 108a is thinner than that of the semiconductor 108a. However, the thickness of the semiconductor 113 is not limited to this, and may be determined based on the withstand voltage of the insulator 114 that functions as a gate insulating film. Taking this into consideration, the value may be appropriately set according to the voltage at which the transistor is driven.

[0096] Here, for example, the semiconductor 108a is an insulator having a different constituent element (for example, a silicon oxide film). When a semiconductor comes into contact with a material (such as an insulator containing a metal oxide), an interface state is formed at the interface between the semiconductor and the material. In such a case, transistors with different threshold voltages appear. However, this structure can cause the apparent threshold voltage of the transistor to fluctuate. In the transistor, the semiconductor 108a contains one or more metal elements. Since the semiconductor 107a has the structure, an interface state is formed at the interface between the semiconductor 107a and the semiconductor 108a. Therefore, by providing the semiconductor 107a, the threshold voltage of the transistor is This can reduce variations and fluctuations in electrical characteristics such as voltage.

[0097] In addition, a channel is formed at the interface between the insulator 114, which functions as a gate insulating film, and the semiconductor 108a. When such a layer is formed, interfacial scattering occurs at the interface, and the field effect mobility of the transistor decreases. However, in the transistor of this configuration, the semiconductor 108a is Since the semiconductor 113 contains one or more metal elements, the semiconductor 108a and the semiconductor At the interface with 113, carrier scattering is unlikely to occur, which increases the field-effect mobility of the transistor. It can be made easier.

[0098] The conductor 109b and the conductor 109c are made of aluminum, titanium, chromium, nickel, or copper. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten. The metal or alloy containing the metal as the main component is used in a single layer or multilayer structure. For example, a single layer structure of an aluminum film containing silicon, a titanium film on which an aluminum film is laminated, A two-layer structure with an aluminum film laminated on a tungsten film, a two-layer structure with a copper-magnesium film laminated on a tungsten film, - Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film A two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or titanium nitride film and its An aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and then the aluminum film or the copper film is laminated on the titanium film or the titanium nitride film. A three-layer structure in which a titanium film or titanium nitride film is formed on top, a molybdenum film or molybdenum nitride film A molybdenum film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film. A three-layer structure is formed by laminating a layer of a molybdenum film or a molybdenum nitride film on top of the layer of a silicon nitride film. A transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used. .

[0099] The insulator 114 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or alumina oxide. Aluminum, hafnium oxide, gallium oxide or Ga-Zn metal oxide, silicon nitride The insulating film may be formed as a laminate or a single layer.

[0100] The insulator 114 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), high-k materials such as yttrium oxide may also be used. .

[0101] The insulator 114 may be aluminum oxide, magnesium oxide, silicon oxide, or oxide. Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Oxide insulation such as titanium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide Films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride. A nitride insulating film or a mixture of these materials may be used.

[0102] In addition, the insulator 114 is made of oxygen having a stoichiometric composition similar to the insulator 106. It is preferable to use an oxide insulating film containing as much oxygen as possible.

[0103] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. For example, hafnium oxide, aluminum oxide, and oxide are mixed in the gate insulating film. By using a material with many electron capture levels, such as tantalum, and by using a material that can withstand higher temperatures (the operating temperature of semiconductor devices), Or higher than the storage temperature, or 125°C to 450°C, typically 1 At a temperature of 50°C or higher and 300°C or lower, the potential of the gate electrode is set to the potential of the source electrode or drain electrode. By maintaining the higher temperature for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move toward the pole, some of which are captured by the electron capture level.

[0104] In this way, a transistor that has captured the necessary number of electrons at the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The treatment for adding the conductive layer may be performed during the manufacturing process of a transistor.

[0105] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After, or after the completion of the pre-process (wafer processing), or after the wafer dicing process It is advisable to carry out the inspection at any stage before shipment from the factory, after packaging, etc. It is preferred that the subsequent exposure to temperatures above 125° C. is not to be allowed for more than 1 hour.

[0106] The conductor 115 may be, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum, A metal selected from tungsten, or an alloy containing the above-mentioned metals, or the above-mentioned metals It can be formed by using an alloy of manganese, zirconium, etc. One or more of the metals may be used. Also, impurity elements such as phosphorus may be used. Semiconductors such as doped polycrystalline silicon, and silicides such as nickel silicide The conductor 115 may have a single-layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, A two-layer structure in which a titanium film is laminated on a titanium nitride film; a two-layer structure in which a titanium film is laminated on a titanium nitride film; A two-layer structure in which a tantalum nitride film is laminated on a tungsten nitride film, or a tungsten nitride film is laminated on a tantalum nitride film or a tungsten nitride film A two-layer structure with a stainless steel film, a titanium film, and an aluminum film laminated on top of the titanium film. There is also a three-layer structure in which a titanium film is formed on top of the aluminum. One selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film made of a combination of a plurality of metals may be used.

[0107] The conductor 115 may be made of indium tin oxide or indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide Add indium tin oxide, indium zinc oxide, and silicon oxide containing titanium oxide. A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the light-transmitting conductive material and the above metal may also be used.

[0108] The conductor 115 is made of a material for adjusting the work function, such as titanium nitride, titanium Ta nitride, tungsten, tungsten nitride, ruthenium, N-type polycrystalline silicon Alternatively, P-type polycrystalline silicon or the like may be used. To achieve this, it is advisable to use a material with a high work function. Examples include tungsten, tungsten nitride, and ruthenium.

[0109] In addition, an In-Ga-Zn-based oxynitride semiconductor film is provided between the conductor 115 and the insulator 114. In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride Semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN, Z These films may have a work energy of 5 eV or more, preferably 5.5 eV or more. function, which is larger than the electron affinity of an oxide semiconductor. The threshold voltage of the transistor can be shifted to the positive side, and the so-called normally-off characteristic can be improved. For example, a switching element with high conductivity can be realized by using an In-Ga-Zn-based oxynitride semiconductor film. In the case where the semiconductor 108a is used, the nitrogen concentration is at least higher than that of the semiconductor 108a, specifically, 7 atomic % or more of In -Ga-Zn-based oxynitride semiconductor film is used.

[0110] The above is a description of the configuration example.

[0111] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The above-mentioned embodiments may be combined, adapted, or substituted as desired.

[0112] (Embodiment 2) [Example of manufacturing method] An example of a method for manufacturing the semiconductor device shown in the above configuration example will be described below with reference to FIGS. I will use this to explain.

[0113] An insulator 102 is formed on an insulator 101. The insulator 101 has a thickness of about 50 nm. It is preferable to use silicon nitride having a thickness of 150 n. TEOS (Tetra-Ethyl-Ortho-Silica) with a thickness of about 100 μm It is preferable to use silicon oxide formed using a silicon oxynitride film.

[0114] Each of the insulators 101 and 102 is made of, for example, silicon oxide or silicon oxynitride. , silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, nitride oxide Alternatively, aluminum oxide, aluminum nitride, etc. may be used, and the layer may be a multilayer or a single layer.

[0115] The insulators 101 and 102 are formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like. al Vapor Deposition) method (thermal CVD method, PECVD (Plasma Enhanced CVD method, etc.), MOCVD (Metal Organic CVD) method, MBE (Molecular Beam Epitaxy) method, ALD( Atomic Layer Deposition) method, PLD (Pulsed Las) er Deposition) method, HDP (High density plasma) -CVD method, low pressure CVD method (LP-CVD: low pressure CVD), normal pressure CVD method (AP-CVD: atmospheric pressure CVD), By forming a film using the mate sputtering method or the long throw sputtering method, It may be formed.

[0116] In particular, when the insulator is formed by a CVD method, preferably a plasma CVD method, the filling This is also preferable because it can improve the incorporation of the plasma. The deposition method is preferably a thermal CVD method, an MOCVD method or an ALD method.

[0117] Next, a heat treatment is performed. This heat treatment is performed under an inert gas atmosphere such as a rare gas or nitrogen gas. Alternatively, it can be performed in a reduced pressure atmosphere at a temperature of, for example, 490° C. or higher and lower than the distortion point of the substrate.

[0118] This heat treatment removes water from the stack that is formed below and includes the insulator 102. The material that adversely affects the semiconductor formed above the insulator 102, such as silicon, is desorbed or removed. It is preferable to carry out the heat treatment, but if it is not necessary, It is also possible to omit this step. You can do this after you finish.

[0119] Next, an opening or a groove is formed in the insulator 102. When providing the insulator 102, the insulator 102 is made of a material having a large etching selectivity with respect to the insulator 101. It is preferable to select a combination of

[0120] When forming an opening or a groove in the insulator 102, a photolithography method or the like is used. A resist mask is formed on the insulator 102, and unnecessary portions of the insulator 102 are removed. Then, the resist mask is removed to leave the insulator 102. An opening or a groove can be formed. (Figure 3(a))

[0121] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, Various microfabrication techniques can be used. For example, A method of slimming the resist mask may be used. A dummy pattern was formed by a raffin method or the like, and a sidewall was formed on the dummy pattern. After that, the dummy pattern is removed, and the remaining sidewall is used as a mask to etch the processed film. In addition, in order to achieve a high aspect ratio when etching the film to be processed, In order to achieve this, it is preferable to use anisotropic dry etching. A hard mask made of a film may also be used.

[0122] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6 nm), H-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Also, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Instead of light for exposure, electron beams can be used. Extreme ultraviolet light, X-rays, or The use of an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0123] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. The organic resin film may be, for example, By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce the variation in thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is required to have a high resistance to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film. As the resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. Alternatively, it may be removed after removing the resist mask.

[0124] Next, a barrier film 103 is provided on the insulator 102 in which the opening or groove is formed. The aluminum oxide film 103 is preferably made of aluminum oxide having a thickness of about 50 nm. (Figure 3(b))

[0125] The laminated body provided under the barrier film 103 is analyzed by thermal desorption spectroscopy (TDS analysis). The amount of hydrogen molecules desorbed at a substrate surface temperature of 400°C, as measured by the At 0° C., the amount of hydrogen molecules released is preferably 130% or less, more preferably 110% or less. Alternatively, TDS analysis showed that the amount of desorbed hydrogen molecules at a substrate surface temperature of 450°C was 350 It is preferable that the amount of desorption is 130% or less, and preferably 110% or less, of the amount of desorption at .degree.

[0126] The barrier film 103 has a function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer. The barrier film 103 is a layer having a function of forming a barrier between an electrode or wiring provided above it and It has an opening or a plug for electrically connecting to an electrode or wiring provided below. Good too.

[0127] Materials that can be used for the barrier film 103 include silicon nitride and silicon oxynitride. , aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, iridium oxide Examples include yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride. In particular, aluminum oxide is preferred because it has excellent barrier properties against water, hydrogen, and oxygen. It is nice.

[0128] The barrier film 103 is made of a layer of a material that is difficult for water and hydrogen to permeate, and also of a layer containing other insulating materials. For example, a layer containing silicon oxide or silicon oxynitride, a metal Layers containing oxides may be laminated.

[0129] Moreover, it is preferable that the barrier film 103 is made of a material that is difficult for oxygen to permeate. The material has excellent barrier properties against oxygen as well as hydrogen and water. By using the barrier film 1, oxygen released when the insulator 106 to be provided later is heated is prevented from entering the barrier film 1. As a result, the diffusion of the ions from the insulator 106 to the layer below 03 can be suppressed. This can increase the amount of oxygen that can be released and supplied to the semiconductors 107, 108, and 113. do.

[0130] In addition, it is preferable that the water and hydrogen contained in the barrier film 103 itself is reduced. For example, the barrier film 103 is a barrier film having a substrate surface temperature in the range of 20° C. to 600° C. as determined by TDS analysis. The amount of hydrogen molecules (M / z=2) desorbed at this point is 2×10 15 pieces / cm 2 Less than, preferably 1×10 15 pieces / cm 2 less than 5×10 14 pieces / cm 2 Materials that are less than It is preferable to use it for the barrier film 103. Alternatively, the TDS analysis shows that the substrate surface temperature is 2 The amount of water molecules (M / z=18) desorbed in the range of 0°C to 600°C is 1×10 16 pieces / cm 2 Less than 5 x 10 15 pieces / cm 2 less than 2×10 12 pieces / cm 2 It is preferable to use a material for the barrier film 103 that has a viscosity of less than 100 .mu.m.

[0131] Next, a conductor 104 is provided on the barrier film 103. (FIG. 3(c))

[0132] The conductor 104 may be made of tantalum, tungsten, titanium, molybdenum, chromium, or nickel. Metals selected from the group consisting of carbides, etc., or alloy materials or compound materials mainly composed of these metals It is preferable to use polycrystalline silicon containing impurities such as phosphorus. A laminated structure of a metal nitride film and the above-mentioned metal film may also be used. Examples of the metal that can be used include tungsten nitride, molybdenum nitride, and titanium nitride. By providing the nitride film, the adhesion of the metal film can be improved and peeling can be prevented. It is possible.

[0133] The conductor 104 may be made of indium tin oxide or indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide Add indium tin oxide, indium zinc oxide, and silicon oxide containing titanium oxide. A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the light-transmitting conductive material and the above metal may also be used.

[0134] The conductor 104 is formed by a sputtering method, a vapor deposition method, a CVD method (thermal CVD method, MOCVD method, The film can be formed by a method such as PECVD. Also, damage caused by plasma is not possible. To reduce this, the thermal CVD method, the MOCVD method or the ALD method is preferred.

[0135] Next, the conductor 104 is CMP (Chemical Mechanical Polishing) The surface may be planarized by a planarization process using a planarization method such as a shaping method.

[0136] At this time, the conductor 104 is removed by removing the burrs on the areas of the insulator 102 where there are no openings or grooves. The upper surface of the conductive film 103 may be polished by the CMP method until the upper surface of the conductive film 104 is flush with the upper surface of the conductive film 103. Well, you can stop halfway.

[0137] Next, the conductor 104 is etched to obtain the conductor 104a. The upper surface of a is the upper surface of the barrier film 103 on the area where the opening or groove of the insulator 102 is not provided. It is preferable that the thickness is lower than that of the surface, and it is particularly preferable that the thickness is lower by about 50 nm (FIG. 3( d))

[0138] Next, a barrier film 105 is provided on the barrier film 103 and the conductor 104a. (FIG. 4(a) ))

[0139] The barrier film 105 is an In-Ga-Zn-based oxynitride semiconductor film or an In-Sn-based oxynitride semiconductor film. Semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride semiconductor film, Sn-based oxynitride By providing a semiconductor film, such as an In-based nitride semiconductor film, an In-based oxynitride semiconductor film, or a metal nitride film (InN, ZnN, etc.), These films have a work function of 5 eV or more, preferably 5.5 eV or more, and are oxidative. Since the electron affinity of the oxide semiconductor is larger than that of the oxide semiconductor, The threshold voltage of the transistor can be shifted to the positive side, and the switching characteristic of the transistor can be changed to the normally-off characteristic. For example, when an In-Ga-Zn-based oxynitride semiconductor film is used, At least a nitrogen concentration higher than that of the semiconductor 108a, specifically, an In-Ga-Zn system having a nitrogen concentration of 7 atomic % or more An oxynitride semiconductor film is used.

[0140] It is preferable that the barrier film 105 is made of a material that does not easily diffuse oxygen. The conductor 104a can be prevented from being oxidized, and the resistance value of the conductor 104a can be prevented from increasing. The barrier film 105 is formed using the same material and film-forming method as the barrier film 103. is possible.

[0141] Next, the barrier film 105 is applied to the insulator 102 in the burr region on the area where no opening or groove is provided. The upper surface of the film 103 is polished by the CMP method until the upper surface of the film 103 and the upper surface of the barrier film 105 are flush with each other. A barrier film 105a is obtained (FIG. 4(b)). In FIG. 4(b), the barrier film 105a is polished by the CMP method. Although an example in which a barrier film 105a is obtained will be shown, it is not necessary to remove the barrier film 105.

[0142] Next, an insulator 106 having a thickness of about 100 nm is provided (FIG. 4(c)).

[0143] The insulator 106 is preferably an insulator that releases oxygen by a subsequent heat treatment or the like. The released oxygen is used to reduce oxygen vacancies in the oxide semiconductor, and the transistor On the other hand, the single crystal silicon on the lower side of the laminate 10 can improve the electrical characteristics and reliability. When semiconductor devices using silicon are formed, the oxygen released reaches the single crystal silicon. The above-mentioned aluminum oxide may deteriorate the electrical characteristics and reliability of the semiconductor element. The film has a function of preventing oxygen from entering the elements located below the laminate 10. Even if a silicon oxynitride film containing excess oxygen is provided, it is possible to obtain an element having high electrical characteristics and reliability (e.g. It is possible to fabricate transistors using single crystal silicon.

[0144] The insulator 106 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, PECVD method, etc.), etc. It can be formed by using a method such as MOCVD, MBE, ALD or PLD. In particular, the insulator is formed by a CVD method, preferably a plasma CVD method. This is preferable because it can improve the coverage and reduce damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferred.

[0145] In order to make the insulator 106 contain excess oxygen, for example, the insulator 106 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulator 106 after the deposition to make it contain excess oxygen. Alternatively, a region having either of these may be formed, or both approaches may be combined.

[0146] For example, oxygen (at least oxygen radicals, oxygen atoms, oxygen ions) may be added to the insulator 106 after the film formation. A region containing excess oxygen is formed by introducing oxygen into the film. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0147] In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. In the oxygen introduction process, the oxygen-containing gas may contain a rare gas and / or hydrogen. For example, a mixture of carbon dioxide, hydrogen and argon gases can be used.

[0148] After the insulator 106 is formed, the CMP method or the like is used to improve the flatness of the upper surface. A flattening process may also be performed.

[0149] In addition, the upper surfaces of the barrier films 103 and 105a are processed by the CMP method. In other words, it is preferable to prevent the occurrence of a step by forming the insulator 106 on the substrate. By preventing steps from occurring on the surface, the thickness of the insulator 106 can be made thin. Here, the thickness was set to 100 nm, but it can also be made thinner.

[0150] Next, the semiconductor 107 and the semiconductor 108 are formed. For example, the semiconductor 107 has a thickness of 15 mm. The semiconductor 108 is an oxide semiconductor having a thickness of 20 nm to 40 nm. It is preferable to use a sputtering method for forming these semiconductor films. The oxide semiconductor film of the semiconductor 107 was formed with an atomic ratio of In:Ga:Zn=1:3:4. In addition, a target of In:Ga is used for depositing an oxide semiconductor of the semiconductor 108. A target having an atomic ratio of Zn=1:1:1 is used.

[0151] The semiconductor 107 and the semiconductor 108 are successively formed without being exposed to the air. is preferred.

[0152] After the semiconductor 107 and the semiconductor 108 are formed, heat treatment is preferably performed. The treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. This can be done in an active gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. In addition, the heat treatment is performed in an inert gas atmosphere, and then the desorbed oxygen is replenished. In order to prevent this, the heat treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. This may be done immediately after film formation, or after processing the semiconductor to form island-shaped semiconductors. By the heat treatment, oxygen is supplied from the insulator 106 to the semiconductors 107 and 108. In this way, oxygen vacancies in the semiconductor film can be reduced.

[0153] Next, a conductor 109 is provided. The conductor 109 is a tongue having a thickness of about 100 nm. It is preferable to use stainless steel. The film of the conductor 109 is formed by a sputtering method. It is possible to do so.

[0154] The conductor 109 can be formed by sputtering or by other methods such as CVD (thermal CVD, (including MOCVD, PECVD, etc.), MBE, ALD, or PLD methods, etc. In particular, the conductor can be formed by a CVD method, preferably a plasma CVD method. Therefore, it is preferable to form a film by using plasma, since the covering property can be improved. To reduce damage, the thermal CVD method, the MOCVD method, or the ALD method is preferable.

[0155] Conductor 109, semiconductor 108, semiconductor 107, insulator 106, barrier film 103, insulator An opening is formed in the insulating material 102 and the insulating material 101. At this time, a photolithography method or the like is used. A resist mask is formed on the conductor 109 to remove unnecessary portions of the conductor 109. After that, the resist mask is removed, and the semiconductor 10 is formed using the conductor 109 as a mask. 8. Openings are formed in the semiconductor 107, the insulator 106, and the barrier film 103. In this manner, An opening 110 is formed. (FIG. 4(d))

[0156] Next, the conductor 111 and the conductor 112 are formed inside the opening 110 and on the conductor 109. The conductor 111 and the conductor 112 are formed by, for example, a sputtering method or a CVD method (thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or PLD method It can be formed using the above. (Figure 5(a))

[0157] The conductor 111 and the conductor 112 may be made of tantalum, tungsten, titanium, molybdenum, or the like. Metals selected from the group consisting of tin, chromium, niobium, etc., or alloys containing these metals as the main components. It is preferable to use a polycrystalline material or a compound material to which impurities such as phosphorus are added. Silicon can be used. A laminated structure of a metal nitride film and the above metal film can also be used. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride is used. By providing a metal nitride film, the adhesion of the metal film can be improved. This makes it possible to prevent peeling.

[0158] Next, the conductor 112 may be planarized by a planarization process such as a CMP method. The conductor 112 is CMP-processed until the upper surface of the conductor 112 is flush with the upper surface of the conductor 111. Alternatively, the etching may be stopped midway. The conductor 112 may be etched. In this manner, the conductors 112a and 112b are (Fig. 5(b))

[0159] Next, the conductors 111, 112a, and 112b are subjected to photolithography. A resist mask is formed by a method or the like. The unnecessary portions are removed to obtain the conductor 111a. Then, the resist mask is removed, and the conductor Using 111a as a mask, the conductor 109, the semiconductor 108, and the semiconductor 107 are etched. In this manner, the conductor 109a, the semiconductor 108a, and the semiconductor 107a are obtained. When etching the conductor 109a, the semiconductor 108a, and the semiconductor 107a, the insulator 106 Therefore, the depth of etching may be considered in advance. It is preferable to form the insulator 106 as thick as possible. (FIG. 5(c))

[0160] Next, the conductor 111a located on the conductor 109a is removed, and the conductor 111b and the conductor Here, plugs 120a and 120b are formed. Then, the conductor A part of 109a is etched to obtain conductors 109b and 109c. Photolithography or the like can be used. Here, the conductor 109a is etched, When the conductor 109b and the conductor 109c are obtained, a part of the semiconductor 108a is etched. As a result, the portions that do not overlap with the conductor 109b and the conductor 109c may become thin. Therefore, the thickness of the semiconductor that will become the semiconductor 108 is made thick in advance, taking into account the depth to be etched. It is preferable to have the above structure in place (Figure 6(a)).

[0161] The plugs 120a and 120b are formed by conductors 109b and 109b overlapping the semiconductor 108a. Since the element is provided in an opening formed in c, the element can be miniaturized.

[0162] In addition, the conductors 109b and 109c are arranged in the same layer as the semiconductor 108a and the semiconductor 107a. A line may be formed.

[0163] Next, a semiconductor, an insulator, and a conductor are laminated in this order. A resist mask is then formed on the conductor, and unnecessary portions of the conductor are removed. By removing the resist, the conductor 115 can be formed. The unnecessary portions of the insulator and the semiconductor are removed without removing the mask, and the insulator 114 and the semiconductor are removed. A conductor 113 may be formed. After removing the resist mask, a conductor 115 may be formed. Using the mask, unnecessary portions of the insulator and the semiconductor are removed to form the insulator 114 and the semiconductor. A body 113 may be formed.

[0164] The semiconductor 113 is an oxide semiconductor having a thickness of 5 nm. In this case, a sputtering method is preferably used for forming the oxide semiconductor film. A target having an atomic ratio of Ga:Zn=1:3:2 is used.

[0165] The semiconductor 113, the insulator 114, and the conductor 115 are not exposed to the air. It is preferable to deposit the films in succession (Fig. 6(b)).

[0166] Next, a barrier film 116 is provided. As the barrier film 116, the same material as the barrier film 103 is used. It is possible to use different materials and deposition methods. (Figure 6(c))

[0167] After the barrier film 116 is formed, it is preferable to perform heat treatment. Oxygen is supplied to the semiconductors 107a, 108a, and 113 from the semiconductor 107a In addition, oxygen vacancies in the insulators 106, 108a, and 113 can be reduced. The oxygen desorbed from the barrier film 103 and the barrier film 116 is blocked by the barrier film 103 and the barrier film 116. Since the oxygen does not diffuse to the layer below the film 103 or to the layer above the barrier film 116, the oxygen is effectively Therefore, the semiconductors 107a, 108a, and 113 can be supplied with the The amount of oxygen can be supplied without being lost, and the semiconductors 107a, 108a, and 113 can be This can effectively reduce oxygen deficiencies.

[0168] In this manner, the stack 10 including the transistor 100 is formed.

[0169] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The above-mentioned embodiments may be combined, adapted, or substituted as desired.

[0170] (Embodiment 3) Other examples of transistor configurations that can be applied to the transistor 100 included in the laminate 10 are as follows: Shown below.

[0171] FIG. 9(A) is a schematic top view of a transistor, and FIGS. 9(B) and 9(C) are schematic top views of a transistor. 9(A) is a schematic cross-sectional view taken along the cutting lines A1-A2 and B1-B2 of FIG. 9(B) corresponds to a cross section of the transistor in the channel length direction, and FIG. 9(C) corresponds to a cross section of the transistor in the channel length direction. It corresponds to a cross section in the channel width direction.

[0172] In FIG. 9, the semiconductor 113 is a conductor 109, as compared to the transistor 100 shown in FIG. b. Between the conductor 109c and the semiconductor 108a, the semiconductor 113 is a semiconductor An example is shown in which the same photomask is used to process the upper surface of the semiconductor substrate 108a so that the upper surface of the semiconductor substrate 108a roughly matches the upper surface of the semiconductor substrate 108a. is doing.

[0173] FIG. 10(A) is a schematic top view of a transistor, and FIGS. 10(B) and 10(C) are 10(A) and 10(B) are schematic cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in FIG. FIG. 10(B) corresponds to a cross section of a transistor in the channel length direction, and FIG. 10(C) corresponds to a cross section of a transistor in the channel length direction. It corresponds to a cross section in the channel width direction of a transistor.

[0174] In FIG. 10, the semiconductor 113 and the insulator 11 are different from the transistor 100 shown in FIG. The semiconductor 14 and the conductor 115 are arranged so as not to overlap with the conductor 109b and the conductor 109c. 13, the insulator 114 and the conductor 115 are arranged in the same photomask so that their top surface shapes are roughly the same. This shows an example of processing using a sk.

[0175] FIG. 11(A) is a schematic top view of a transistor, and FIGS. 11(B) and 11(C) are 11(A) and 11(B) are schematic cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in FIG. FIG. 11(B) corresponds to a cross section in the channel length direction of a transistor, and FIG. 11(C) corresponds to a cross section in the channel length direction of a transistor. This corresponds to a cross section of the transistor in the channel width direction.

[0176] In FIG. 11, conductor 115 is different from conductor 100 in FIG. 109b and the conductor 109c.

[0177] FIG. 12(A) is a schematic top view of a transistor, and FIGS. 12(B) and 12(C) are 12(A) and 12(B) are schematic cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in FIG. FIG. 12(B) corresponds to a cross section of a transistor in the channel length direction, and FIG. 12(C) corresponds to a cross section of a transistor in the channel length direction. It corresponds to a cross section in the channel width direction of a transistor.

[0178] In FIG. 12, the conductor 109b and the conductor When the semiconductor 113, the insulator 114, and the conductor 115 are not provided, the top surface shapes of the semiconductor 113, the insulator 114, and the conductor 115 are 13 shows an example in which the same photomask is used to process the pattern so as to roughly match the pattern shown in FIG.

[0179] FIG. 13(A) is a schematic top view of a transistor, and FIGS. 13(B) and 13(C) are 14 are schematic cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in FIG. 13(B) corresponds to a cross section of the transistor in the channel length direction, and FIG. 13(C) corresponds to a cross section of the transistor in the channel length direction. It corresponds to a cross section of the capacitor in the channel width direction.

[0180] In FIG. 13, the conductor 104a is insulated from the insulator 102, as compared to the transistor 100 shown in FIG. 1, a barrier film 103 is provided on the conductor 104a and on the insulator 102. vinegar.

[0181] In FIG. 13, an oxide semiconductor is preferably used for the conductor 104a. It is preferable to use silicon nitride containing hydrogen for the oxide semiconductor. The contact of the oxide semiconductor layer with the insulating film increases the electrical conductivity of the oxide semiconductor layer.

[0182] In addition, in each of the transistors shown in FIGS. 9 to 12, the conductor 115, the conductor 109b The semiconductor 113, the semiconductor 108a, and the semiconductor 107a that do not overlap with the conductor 109c In the region, it is preferable to add impurities to each semiconductor to reduce its resistance. These include argon, phosphorus, boron, nitrogen, aluminum, hydrogen, tungsten, chromium, Manganese, vanadium, titanium, magnesium, calcium, etc. can be used. The method of adding impurities to semiconductors is by plasma treatment, ion implantation, etc. It is possible to do so.

[0183] In this specification, the term "approximately coincident upper surface shapes" means that there is at least a slight difference between the layers. For example, the upper and lower layers have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where a part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0184] As shown in FIG. 9C, in a cross section in the channel width direction of the transistor, A conductor 115 functioning as a contact electrode is provided on the top and side surfaces of the semiconductor 108a. As a result, a channel is formed not only in the vicinity of the top surface of the semiconductor 108a but also in the vicinity of the side surface. The effective channel width is increased, and the current in the on-state (on-current) can be increased. In addition, the width of the semiconductor 108a is extremely small (for example, 50 nm or less, preferably 30 nm or less). , more preferably 20 nm or less), a channel is formed inside the semiconductor 108a. Since the area covered by the gate is wider, the contribution to the on-current increases as the gate size is reduced.

[0185] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum value, minimum value, and The value is the average value.

[0186] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the gate electrode (where the current flows) or in the region where the channel is formed, This refers to the length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum value, minimum value, and maximum value in the region where the channel is formed. The value is the average value.

[0187] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in a transistor with a fine and three-dimensional structure, The percentage of the channel region formed on the side of the semiconductor compared to the percentage of the channel region formed on the inside of the semiconductor. In that case, the apparent channel width shown in the top view may be In this case, the effective channel width where the channel is actually formed is larger than the actual channel width.

[0188] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0189] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is defined as the "surrounded channel width (SCW)". In this specification, when it is simply referred to as the channel width, In some cases, this refers to the enclosed channel width or apparent channel width. In the detailed description, when the term "channel width" is used simply, it may refer to the effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, enclosure The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. , values ​​can be determined.

[0190] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0191] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The above-mentioned embodiments may be combined, adapted, or substituted as desired.

[0192] (Embodiment 4) [Configuration example] FIG. 7A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device includes a transistor 200, a transistor 100, a capacitor 130, and a wiring BL , a wiring WL, a wiring CL, and a wiring BG.

[0193] In this embodiment, one embodiment of the laminated structure shown in FIG. A single crystal silicon semiconductor is used as the layered body 20, and the layered body 10 is laminated on the layered body 20. An example in which capacitors are stacked as a laminate 30 is shown above.

[0194] One of the source and drain of the transistor 200 is electrically connected to the wiring BL, and the other The first side is electrically connected to the wiring SL, and the gate is the source or drain of the transistor 100. The transistor 100 is electrically connected to one electrode of the capacitor 130. The other of the drains is electrically connected to the wiring BL, and the gate is electrically connected to the wiring WL. The other electrode of the capacitor 130 is electrically connected to the wiring CL. The gate of the transistor 200 is electrically connected to the second gate of the transistor 100. A node between one of the source or drain of the transistor 100 and one electrode of the capacitor 130 The node is called a node FN.

[0195] The semiconductor device shown in FIG. 7A is arranged when the transistor 100 is in a conductive state (on state). A potential corresponding to the potential of the line BL is applied to the node FN. Also, when the transistor 100 is turned off, When the transistor is in the off state, the potential of the node FN is maintained. The semiconductor device shown in FIG. 1A functions as a memory cell of a memory device. The liquid crystal element and organic EL (Electroluminescence) In the case where a display element such as a pixel element is included, the semiconductor device of FIG. It can also be used to

[0196] The conductive or non-conductive state of the transistor 100 is selected by applying a signal to the wiring WL or the wiring BG. It can be controlled by the potential applied to the wiring WL or the wiring BG. The threshold voltage of the transistor 100 can be controlled by the above. In addition, by using a transistor with a small off-state current, the node F Therefore, the potential of N can be maintained for a long period of time. Since the frequency of switching can be reduced, a semiconductor device with low power consumption can be realized. Note that a transistor including an oxide semiconductor is an example of a transistor with low off-state current. Sta. is mentioned.

[0197] A constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 is The apparent threshold voltage fluctuates, causing the transistor 200 to switch between conductive and non-conductive states. By utilizing the change in the non-conducting state, the potential information held at the node FN is converted into data. The data can be read out by

[0198] The potential held at node FN is 3.15×10 8 seconds) In order to hold the capacitance, the off-state current per 1 fF and the channel width of the transistor per 1 μm are The current value is 4.3yA (1yA is 10 -24 A) is preferably less than At this time, it is preferable that the allowable fluctuation in the potential of the node FN is within 0.5 V. Alternatively, the off-state current is preferably less than 1.5 yA at 95° C. In the semiconductor device according to the present invention, the hydrogen concentration in the layer below the barrier film is sufficiently reduced. As a result, the transistor using an oxide semiconductor as the upper layer has such an extremely low onset voltage. A floating current can be realized.

[0199] The subthreshold swing value (S value) of a transistor using an oxide semiconductor is 66mV / dec. or more, preferably 60mV / dec. or more, more preferably 50m V / dec. or more, and 200mV / dec. or less, preferably 150mV / dec. or less, more preferably 100 mV / dec. or less, and even more preferably 80 mV / dec. or less. The smaller the S value, the lower the turn-off voltage at a specific voltage. Therefore, the off-state current can be reduced.

[0200] By arranging the semiconductor device shown in FIG. 7A in a matrix, a memory device (memory cell It is possible to configure a

[0201] FIG. 7B shows an example of a cross-sectional structure of a semiconductor device capable of realizing the circuit shown in FIG. vinegar.

[0202] The semiconductor device includes a transistor 200, a transistor 100, and a capacitor . The transistor 100 is disposed on the transistor 200. A barrier film 103 is provided between the transistors 100 .

[0203] The transistor 200 is provided on a semiconductor substrate 711. A semiconductor 712, a gate insulating film 714, a gate electrode 715, and a source region or drain The low-resistance region 713a and the low-resistance region 713b function as an in-region.

[0204] The transistor 200 may be either a p-channel type or an n-channel type, depending on the circuit configuration and An appropriate transistor may be used depending on the driving method.

[0205] The region in which the channel of the semiconductor 712 is formed and the region in the vicinity thereof, the source region or the drain region In the low resistance region 713a and the low resistance region 713b which become the in-region, a silicon-based semiconductor Preferably, the material comprises a semiconductor such as a silicon dioxide, and more preferably, single crystal silicon. Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide) Alternatively, the crystal may be made of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). It may be made of silicon with a distorted lattice. Or it may be made of GaAs and AlGaAs. By using the above, the transistor 200 can be made into a HEMT (High Electron Mo It may also be referred to as a "capability transistor."

[0206] The low resistance region 713a and the low resistance region 713b are formed of a semiconductor material applied to the semiconductor 712. In addition, elements that impart n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, are added. Contains elements that contribute.

[0207] The gate electrode 715 is made of an element that provides n-type conductivity, such as phosphorus, or a p Semiconductor materials such as silicon that contain elements that impart electrical conductivity of the type, metal materials, alloy materials, For the material, conductive materials such as metal oxide materials can be used. In particular, It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use a ten.

[0208] Here, the configuration including the transistor 200 corresponds to a part of the stack 20 in FIG. do.

[0209] Here, even if a transistor 180 as shown in FIG. 8 is used instead of the transistor 200, 8 shows a cross section of the transistor 180 in the channel length direction on the left side, and a cross section of the transistor 180 in the channel width direction on the right side. The transistor 180 shown in FIG. A part of the semiconductor substrate) has a convex shape, and the gate insulating film 814 and A gate electrode 815 is provided. Such a transistor 180 is formed on a protruding portion of a semiconductor substrate. Since it uses a fin-type transistor, it is also called a fin-type transistor. The insulating film may have an insulating film functioning as a mask for forming the protrusions. The above shows a case where a protrusion is formed by processing a part of a semiconductor substrate. A shaped semiconductor may be formed.

[0210] Covering the transistor 200 are an insulator 721, an insulator 722, an insulator 723, and an insulator The bodies 724 are stacked in order.

[0211] The insulator 721 is formed in the low resistance region 713a and the low resistance region 7 It functions as a protective film during activation of the conductive element added to 13b. 721 does not have to be provided if it is not necessary.

[0212] When the semiconductor 712 is made of a silicon-based semiconductor material, the insulator 722 is made of an insulating material containing hydrogen. A hydrogen-containing insulator 722 is provided on the transistor 200, and the insulator 722 is heated. By performing the treatment, the dangling bonds in the semiconductor 712 are terminated by the hydrogen in the insulator 722. As a result, the reliability of the transistor 200 can be improved.

[0213] The insulator 723 is preferably a silicon nitride film or the like. It also functions as a barrier film to prevent hydrogen desorbed from the layer 722 from diffusing to the upper layer. do.

[0214] The insulator 724 is used to smooth out the steps caused by the transistor 200 and other components disposed below it. The top surface of the insulator 724 is a planarization layer that is used to improve the planarization of the top surface. For this purpose, the CMP (Chemical Mechanical Polishing) method is used. The surface may be planarized by a planarization process performed in advance.

[0215] The insulator 724 is a USG formed by HDP-CVD or atmospheric CVD. (Undoped Silicate Glass) film may also be used. (Borophosphosilicate Glass) membrane and BSG (Borosilicate Glass) membrane. For example, silane gas, TEOS gas, ozone gas, etc. Gas, oxygen gas, phosphine, diborane , Triethyl borate, Trimethyl borate, Triethyl phosphate, Trimethyl phosphate, Phosphorous acid A BSG film or a BPSG film may be formed by a CVD method using trimethyl ester or the like. SG film, BPSG film, BSG film, etc. can be processed by reflowing with heat treatment or by using the CMP method. The flatness may be further improved.

[0216] In addition, the insulators 721, 722, 723, and 724 have low resistance regions 71 3a and the low resistance region 713b, plugs 761 and 763, which are electrically connected to the transistor 2 A plug 762 or the like that is electrically connected to the gate electrode 715 of 00 may be embedded.

[0217] On the upper part of the insulator 724, a wiring 731, a wiring 732, a wiring 733, etc. are provided. do.

[0218] The wiring 731 is electrically connected to the plug 761. The wiring 732 is electrically connected to the plug 762. In addition, the wiring 733 is electrically connected to a plug 763 .

[0219] The material of the wiring 731, the wiring 732, the wiring 733, etc. may be a metal material, an alloy material, or In particular, materials having both heat resistance and electrical conductivity, such as metal oxide materials, can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use stainless steel.

[0220] The wiring 731, the wiring 732, the wiring 733, and the like are embedded in the insulator 725. The upper surfaces of the insulator 725 and the wiring 731, the wiring 732, and the wiring 733 are Planarization is preferred.

[0221] The laminate 10 is laminated on the laminate 20 described above.

[0222] A stacked body 30 is provided on the stacked body 10. An insulating layer covering the stacked body 10 including the transistor 100 is provided. The insulator 726 functions as a planarizing layer that covers the uneven shape of the underlying layer. The insulator 708 may function as a protective film when the insulator 726 is formed. 8 may not be provided if not required.

[0223] The barrier film 116, the insulator 708, and the insulator 726 are electrically connected to the conductor 109b. a plug 764 electrically connecting to the conductor 115; a plug 765 electrically connecting to the gate electrode 715; and a plug 766 electrically connected to the conductor 109c, and a low resistance region of the transistor 200. A plug 767 that electrically connects to 713b is embedded.

[0224] On the insulator 726, a wiring 751 electrically connected to the plug 764, a plug 765, and Wiring 752 for electrical connection, wiring 753 for electrical connection with plug 766, and plug 7 Wiring 754 and the like are provided for electrical connection to 67 .

[0225] The wiring 751, the wiring 752, the wiring 753, the wiring 754, and the like are embedded in the insulator 727. The wiring 751, the wiring 752, the wiring 753, the wiring 754, the insulator 72 The upper surface of each of the plates 7 etc. is preferably flattened.

[0226] An insulator 728 is provided on the insulator 727. The insulator 728 includes a wiring 751. a plug 768 electrically connected to the wiring 753; a plug 769 electrically connected to the wiring 7 A plug 770 and the like are provided for electrical connection to 54 .

[0227] On the insulator 728, a wiring 755 electrically connected to the plug 768, a plug 769 and An electrode 781 for electrical connection, wiring 756 for electrical connection with the plug 770, etc. are provided. Note that a part of the electrode 781 also functions as a wiring.

[0228] The wiring 755, the wiring 756, the electrode 781, and the like are embedded in the insulator 729. The upper surfaces of the wiring 755, the wiring 756, the electrode 781, the insulator 729, etc. are planarized. It is preferable to do so.

[0229] The insulator 782 is provided on and in contact with the electrode 781, and the electrode 783 is provided on the insulator 782. The electrode 781, the insulator 782, and the electrode 783 constitute the capacitor 130. Part of the electrode 783 also functions as wiring.

[0230] An insulator 730 is provided on the insulator 729, and the capacitor 130 is embedded in the insulator 730. The insulator 730 also includes a plug 771 electrically connected to the wiring 755, and a wiring 7 A plug 772 and the like are provided for electrical connection to 56 .

[0231] On the insulator 730, a wire 757 electrically connected to the plug 771 and a wire 758 electrically connected to the plug 772 are provided. Wiring 758 and the like are provided for electrical connection.

[0232] The wiring 757, wiring 758, etc. are embedded in the insulator 741. It is preferable that the upper surfaces of the lines 757, wiring 758, insulators 741, etc. are planarized.

[0233] An insulator 742 is provided on the insulator 741. The insulator 742 includes a wiring 75 8. A plug 773 or the like is provided for electrical connection to the semiconductor device 8.

[0234] A wiring 759 that electrically connects to the plug 773 is provided on the insulator 742 .

[0235] The wiring 759 is embedded in the insulator 743. The upper surface of each of the bodies 743 etc. is preferably planarized.

[0236] An insulator 744 is provided on the insulator 743 .

[0237] Here, in FIG. 7B, the wiring 757 corresponds to the wiring BL shown in FIG. Similarly, the wiring 752 corresponds to the wiring WL, the electrode 783 corresponds to the wiring CL, and the conductors 104a and The barrier film 105a corresponds to the wiring BG. , the electrode 781 of the capacitor 130, and the conductor 109c of the transistor 100. This corresponds to node FN shown in FIG.

[0238] The semiconductor device according to one embodiment of the present invention includes a transistor 200 and a The transistor 100 is located above the capacitor 130. Therefore, by stacking these, the area occupied by the element can be reduced. Furthermore, the barrier film 103 provided between the transistor 200 and the transistor 100 As a result, impurities such as water and hydrogen present in the layers below this region diffuse toward the transistor 100. This can be suppressed.

[0239] In this embodiment, an example in which the capacitor 130 is disposed above the transistor 100 has been shown. The capacitor 130 may be placed in another location. For example, the transistor 200 and the transistor 1 00. The electrodes of the capacitor 130 may be made of metal, but may also be made of semiconductor. As the semiconductor material, polycrystalline silicon with impurities added is used. It is good.

[0240] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The above-mentioned embodiments may be combined, adapted, or substituted as desired.

[0241] (Embodiment 5) In this embodiment, a semiconductor device that can be suitably used as a semiconductor of one embodiment of the present invention will be described. An oxide semiconductor will be described.

[0242] Oxide semiconductors have a large energy gap of 3.0 eV or more, making them suitable for The oxide semiconductor film obtained by processing the oxide semiconductor film under suitable conditions and sufficiently reducing the carrier density is applied. In a transistor with a low resistance, the leakage current between the source and drain in the off state (off current) can be made extremely low compared to conventional silicon-based transistors. .

[0243] The applicable oxide semiconductors include at least indium (In) or zinc (Zn It is particularly preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to gallium (Ga), tin (Sn), hafnium (Hf), and zirconium (Zr) , titanium (Ti), scandium (Sc), yttrium (Y), lanthanides (e.g. , cerium (Ce), neodymium (Nd), gadolinium (Gd), or It is preferable that one or more kinds of the amine compound are contained.

[0244] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg acids oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO (also written as In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxides, In-Zr-Zn-based oxides, In-Ti-Zn-based oxides, In-Sc-Zn In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, I n-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga- Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, I An n-Hf-Al-Zn oxide can be used.

[0245] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. The metal elements may be included.

[0246] In addition, as an oxide semiconductor, 1+α M 1-α O3(ZnO) m (-1≦α≦1, m >0 and m is not an integer) may be used. Note that M is Ga, F One or more metal elements selected from e, Mn and Co, or the above-mentioned The elements shown are used as bilayers. In2SnO5(ZnO) is used as an oxide semiconductor. n A material expressed as (n>0, and n is an integer) may be used.

[0247] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A Or, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=2:1:3 and its composition It is preferable to use an oxide in the vicinity of the above.

[0248] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors and generate electrons, which are carriers. This causes a transistor Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove the impurities to obtain a high purity so that the impurities are not included as much as possible.

[0249] Note that the oxide semiconductor film is dehydrated (dehydrogenated) to At the same time, oxygen may also decrease. A process to add oxygen to an oxide semiconductor to compensate for oxygen vacancies that have increased due to oxidation. In this specification and the like, when oxygen is supplied to an oxide semiconductor film, This may be referred to as oxygen addition treatment, or oxygen contained in the oxide semiconductor film may be added to the oxide semiconductor film to obtain a stoichiometric composition. When the oxygen concentration is increased beyond this range, it is sometimes referred to as hyperoxygenation treatment.

[0250] In this manner, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies with oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is nearly i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that the number of carriers derived from donors in the oxide semiconductor film is extremely small. (close to zero), carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below It says something.

[0251] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 at room temperature (approximately 25°C). -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10 -24 A or below, or 85 1×10 at °C -15 A or less, preferably 1×10 -18 A or less, more preferably 1x 10 -21 A or less. Note that the off state of a transistor is an n-channel In the case of a transistor of this type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. In general, if the gate voltage is 1V, 2V, or 3V less than the threshold voltage, , the transistor is turned off.

[0252] <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0253] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include a conductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0254] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0255] <caac-os> First, let me explain about CAAC-OS. xis aligned nanocrystals) It is also possible.

[0256] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0257] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0258] The following describes the CAAC-OS observed by TEM. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0259] FIG. 14(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 14(A). From FIG. 14(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0260] As shown in Figure 14(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 14(B) and Figure 14(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination of the The zeolites can also be referred to as nanocrystals (nc).

[0261] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 14(D)). The inclination between the pellets observed in FIG. 14(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0262] FIG. 15(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 15(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 15(B), Fig. 15(C), and Fig. 15(D), respectively. 15(D). From Fig. 15(B), Fig. 15(C) and Fig. 15(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0263] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 16(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0264] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0265] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. 16(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is In the case of scanning, as shown in FIG. 16(C), the peaks belonging to the crystal plane equivalent to the (110) plane Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0266] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in FIG. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 17(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 17(B) This is thought to be due to the (110) plane, etc.

[0267] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can also be considered an oxide semiconductor with a low impurity concentration. It can also be said that the oxide semiconductor has few oxygen vacancies.

[0268] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or may cause hydrogen By capturing atoms, they can become a carrier generation source.

[0269] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor and rearrange the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0270] In addition, an oxide semiconductor with a low density of defect states (few oxygen vacancies) can reduce the carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. A transistor using C-OS has electrical characteristics in which the threshold voltage is negative (normal In addition, the acid is highly pure or substantially pure. The oxide semiconductor has fewer carrier traps. The charge takes a long time to be discharged and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are On the other hand, transistors using CAAC-OS may have unstable electrical characteristics. The resulting transistor has small fluctuations in electrical characteristics and is highly reliable.

[0271] In addition, because the density of defect states in CAAC-OS is low, the capacitive coupling generated by light irradiation can be suppressed. Therefore, the transistor using CAAC-OS is less likely to be captured by the defect level. The electrical characteristics of a transistor vary little when exposed to visible or ultraviolet light.

[0272] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0273] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- The nc-OS is called the "High Resolution Oxide Semiconductor." In some cases, the grain boundaries cannot be clearly seen in the TEM images. Therefore, in the following, we will refer to the pellets in nc-OS as the pellets of the same origin. The crystalline part of S is sometimes called a pellet.

[0274] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peak was detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy region.

[0275] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0276] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0277] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0278] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0279] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0280] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction was performed, no spots were observed, and only a halo pattern was observed. It is measured.

[0281] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, the distance between the nearest neighbors or the second nearest neighbors is called the A structure that has order but does not have long-range order is sometimes called an amorphous structure. According to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. In addition, oxides with at least long-range order cannot be called solid oxide semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, the CAAC-OS and nc-OS are It cannot be called a compound semiconductor.

[0282] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0283] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0284] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0285] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (referred to as sample B), and Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). is also an In-Ga-Zn oxide.

[0286] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0287] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0288] Figure 18 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 18, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 18, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0289] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0290] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0291] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0292] In some cases, single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0293] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a semiconductor and a CAAC-OS.

[0294] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0295] FIG. 19A shows how a CAAC-OS film is formed by a sputtering method. FIG.

[0296] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition speed. The sputtering method is called magnetron sputtering.

[0297] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is set to 0.02m or more and 0.5m or less. Most of the deposition gas (e.g., oxygen) is The chamber is filled with a gas mixture containing 5% or more by volume of nitrogen, argon, or oxygen. The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, discharge begins and plasma is generated. It is noted that a high-density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 are generated. The ions 5101 are, for example, positive oxygen ions (O + ) and argon cations (A r + ) etc.

[0298] Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and any of the grains The crystal grains include cleavage planes. FIG. 20(A) shows an example of a cleavage plane included in a target 5130. The crystal structure of InGaZnO4 is shown in Fig. 20(A). This is the structure of an InGaZnO4 crystal. In the Ga-Zn-O layer, the oxygen atoms in each layer are arranged close to each other. It can be seen that the oxygen atom has a negative charge, and the two adjacent G Repulsion occurs between the a-Zn-O layers. As a result, the InGaZnO4 crystals are close to each other. The cleavage plane is between the two Ga-Zn-O layers.

[0299] Ions 5101 generated in the high-density plasma region are applied to the target 5130 side by the electric field. The cleavage plane is accelerated and eventually collides with the target 5130. At this time, flat or pellet-like particles are generated from the cleavage plane. Pellet 5100a and pellet 5100b, which are pellet-shaped sputtered particles, are peeled off and struck. The pellets 5100a and 5100b are the same as the pellets 5101. The impact of a collision can cause distortion of the structure.

[0300] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example equilateral, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, planar surface. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5 The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may have a shape that is made up of multiple triangles. In some cases, the shape may be two squares (for example, a diamond).

[0301] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferred over thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is (1) in FIG. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the surface of the semiconductor substrate 30, the Ga-Zn-O layer, A pellet 5100 having three layers, an In-O layer and a Ga-Zn-O layer, is exfoliated. (C) shows the structure of the exfoliated pellet 5100 observed from a direction parallel to the c-axis. The plate 5100 is a nanotube having two Ga-Zn-O layers (panels) and an In-O layer (tool). It can also be called a no-size sandwich structure.

[0302] The pellet 5100 may become negatively or positively charged on its sides as it passes through the plasma. The pellet 5100 may, for example, be negatively charged due to the oxygen atoms located on its sides. The sides of the particles have the same polarity, causing repulsion between the charges, forming a flat or pellet-like shape. It is possible to maintain the shape of the In-Ga-Zn In the case of oxides, the oxygen atoms bonded to the indium atoms may be negatively charged. Or, an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom is negatively charged. In addition, when the pellet 5100 passes through the plasma, it may be possible that the pellet 5100 may be oxidized by the impurities in the plasma. When it grows by combining with other atoms such as tungsten, gallium, zinc, and oxygen, The difference in size between (2) and (1) in Figure 18 above corresponds to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellets on the substrate 5120 Since the growth of 5100 is difficult to occur, it becomes nc-OS (see Figure 19(B)). Since the film can be formed in a short time, it is possible to form a film of nc-OS even on a large-area substrate (5120). In order to grow the pellet 5100 in plasma, the sputtering method is used. It is effective to increase the film formation power in the pellet 51. The structure of 00 can be stabilized.

[0303] As shown in FIG. 19(A) and FIG. 19(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the substrate 5120. Pellet 51 Since the 00 is electrically charged, it approaches an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120 in a magnetic The force (Lorentz force) is exerted by the action of the electric field and the electric current. This is explained by Fleming's This can be understood using the left-hand rule.

[0304] The pellet 5100 has a large mass compared to a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of a magnetic field and a current. In order to provide sufficient force to move the top surface of the substrate 5120, The magnetic field parallel to the upper surface of the plate 5120 is 10 G or more, preferably 20 G or more, and more preferably It is preferable to provide an area where the resistance is 30 G or more, and more preferably 50 G or more. On the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 is applied to the upper surface of the substrate 5120. At least 1.5 times, preferably at least 2 times, more preferably at least 3 times the magnetic field perpendicular to the surface More preferably, a region in which the difference is 5 times or more is provided.

[0305] At this time, the magnet and the substrate 5120 move or rotate relatively to each other. Thus, the orientation of the horizontal magnetic field on the top surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces from various directions and is moved in various directions. Can be moved.

[0306] Also, when the substrate 5120 is heated as shown in FIG. 19(A), the pellet 5100 The resistance due to friction between the substrate 5120 and the substrate 5120 is small. The pellet 5100 glides over the upper surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches the side of the pellet, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 0 is removed. The removed oxygen atom causes the acid in CAAC-OS to be Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. 170° C. or more and less than 400° C. Therefore, Even in this case, it is possible to form a CAAC-OS film.

[0307] In addition, the pellet 5100 is heated on the substrate 5120, whereby the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relieved. The pellet 51 with the distortion relieved is shown in FIG. 00 is almost a single crystal. Pellet 5100 is almost a single crystal, Even if the pellets 5100 are heated after being bonded to each other, the pellets 5100 themselves do not expand or contract. Therefore, the gaps between the pellets 5100 widen, causing the grains to It does not form defects such as boundaries or crevasse formation.

[0308] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The aggregates of Pellet 5100 (nano crystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between the pellets 5100. The CAAC-OS was deformed, such as shrinking, due to heating during film formation, heating after film formation, or bending. Even in cases where the material is not fully deformed, it is possible to relieve local stress or release strain. This structure is suitable for use in flexible semiconductor devices. The resulting arrangement resembles randomly stacked nanocrystals.

[0309] When the target 5130 is sputtered by ions 5101, not only the pellet 5100 but also However, zinc oxide may peel off. Zinc oxide is lighter than pellet 5100, so Therefore, it will reach the upper surface of the substrate 5120 first. A zinc oxide layer 5102 having a thickness of 0.5 nm to 2 nm is formed. A schematic cross-sectional view is shown in Figure 21.

[0310] As shown in FIG. 21(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 5105b slides on the pellet 5105b. In another aspect of 5a, a plurality of particles 5103 detached from the target along with zinc oxide. However, due to heating from the substrate 5120, it is crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0311] As shown in FIG. 21(B), the region 5105a1 is integrated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a2. It is arranged so as to be in contact with another side surface of 105b.

[0312] Next, as shown in FIG. 21(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then pellet 5105a2 and pellet 51 It slides on the pellet 5105b. It also slides towards the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0313] As shown in FIG. 21(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is arranged so that its side surface is in contact with the pellet 5105a. Also, the other side of the pellet 5105d is arranged so as to contact the other side of the pellet 5105c. In the process, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are deposited on the substrate. Heat from 5120 causes crystallization, forming region 5105d1.

[0314] As described above, the piled up pellets are arranged so that they come into contact with each other, and the pellets are formed on the side surfaces. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The individual pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth that occurred after deposition.

[0315] In addition, the gaps between the pellets become extremely small, so that one large pellet is formed. One large pellet may have a single crystal structure. For example, The thickness is 10 nm or more and 200 nm or less, or 15 nm or more and 100 nm or less, as viewed from the top surface; or In some cases, the thickness may be between 20 nm and 50 nm. In some cases, the channel formation region of a nitride semiconductor fits into a single large pellet. In other words, the region having a single crystal structure can be used as a channel forming region. As the size of the gate increases, the region having a single crystal structure becomes the channel formation region of the transistor, In some cases, they can be used as source and drain regions.

[0316] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0317] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. It is possible to form a CAAC-OS film even if the surface on which the film is to be formed does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. C-OS does not require laser crystallization and can form a uniform film even on large glass substrates. For example, if the structure of the upper surface (formation surface) of the substrate 5120 is an amorphous structure (e.g., non-crystalline structure), It is possible to form a CAAC-OS film even on a substrate made of amorphous silicon oxide.

[0318] In addition, the CAAC-OS can be formed even if the upper surface of the substrate 5120 has unevenness. For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will face down on a flat surface that is parallel to the ab plane. If the pellet 5100 has a uniform thickness, it is flat and has a uniform thickness. A layer with high crystallinity is formed. Then, the layer is stacked n levels (n is a natural number). By this, CAAC-OS can be obtained.

[0319] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510. The structure is made up of n layers (n is a natural number) of layers with 0s arranged along the unevenness. Since the surface of the CAAC-OS is uneven, gaps may easily occur between the pellets. However, even in this case, intermolecular forces act between the pellets 5100, and unevenness may occur. The pellets are arranged so that the gaps between them are as small as possible. It is possible to obtain a CAAC-OS having high crystallinity.

[0320] Since the CAAC-OS film is formed by such a model, the sputtered particles have a thin film thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0321] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface with an amorphous structure. It is possible to obtain a CAAC-OS having the formula:

[0322] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0323] (Embodiment 6) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to FIG. This will be described with reference to the following.

[0324] [Circuit configuration example] In the configurations shown in the above embodiments, the transistors, wirings, and electrode connections may be changed. By using the semiconductor device according to one embodiment of the present invention, various circuits can be configured. An example of a circuit configuration that can be realized by using the device will be described.

[0325] [CMOS Circuits] The circuit diagram shown in FIG. 22A includes a p-channel transistor 1701 and an n-channel The transistors 1700 are connected in series and the gates of the transistors are connected together. The figure shows the configuration of an OS circuit. Note that in the figure, a transistor in which an oxide semiconductor is used is used as the semiconductor. The data is indicated with the symbol "OS."

[0326] [Analog Switch] In addition, the circuit diagram shown in FIG. 22B shows that the transistors 1700 and 1701 are The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0327] [Example of storage device] By using a transistor according to one embodiment of the present invention, the contents of the memory can be read even when power is not supplied. An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written is shown in Figure 2. 2(C).

[0328] The semiconductor device shown in FIG. 22C includes a transistor 3200 using a first semiconductor material and The semiconductor device includes a transistor 3300 using an oxide semiconductor as a semiconductor and a capacitor 3400. Note that the transistor 3300 may be any of the transistors described in the above embodiments. There can be.

[0329] The transistor 3300 is a transistor in which a channel is formed in a semiconductor having an oxide semiconductor. Since the off-state current of the transistor 3300 is small, This means that the memory contents can be retained for a long period of time without requiring a refresh operation. Alternatively, the frequency of refresh operations can be extremely low. This makes it possible to sufficiently reduce power consumption.

[0330] In FIG. 22C, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the gate electrodes of the transistor 3300. The gate electrode of the transistor 3200 and the The other of the source electrode and the drain electrode of the transistor 3300 is connected to the electrode of the capacitor 3400. The fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400. is connected to.

[0331] In the semiconductor device shown in FIG. 22C, the potential of the gate electrode of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0332] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is Then, a certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By setting the transistor 3300 in the off state, the The charge applied to the gate electrode is retained (retention).

[0333] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrodes is maintained for a long period of time.

[0334] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode of th_ H The figure shows the state when a low-level charge is applied to the gate electrode of the transistor 3200. Threshold V th_L The apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 3200 is When a low-level charge is applied, the fifth wiring 3005 is in the "ON state". If the potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0335] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0336] The semiconductor device shown in FIG. 22D differs from the semiconductor device shown in FIG. 2 mainly in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and hold information. It is possible to create

[0337] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The change in the potential of the third wiring 3003 is proportional to the change in the potential of the first electrode of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0338] For example, the potential of the first electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of the first electrode of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0339] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0340] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. A transistor having an oxide semiconductor is used as the transistor 3300. The transistors may be stacked over the driver circuit.

[0341] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0342] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating film does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single bit, high speed operation can be easily achieved.

[0343] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0344] (Embodiment 7) In this embodiment, a R The F device will be described with reference to FIG.

[0345] The RF device in this embodiment has a memory circuit therein, and stores necessary information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RF devices can identify objects by reading their individual information. It can be used for individual authentication systems that distinguish between people. To achieve this, extremely high reliability is required.

[0346] The configuration of the RF device will be described with reference to Fig. 23. Fig. 23 shows the configuration of the RF device. FIG. 1 is a block diagram illustrating an example.

[0347] As shown in FIG. 23, an RF device 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The RF device 800 also includes a rectifier circuit 805, a constant voltage circuit 806, A demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811 are included. In addition, a reverse current is applied to a transistor having a rectifying effect included in the demodulation circuit 807. A material capable of sufficiently suppressing the noise, for example, an oxide semiconductor, may be used. This suppresses the degradation of the rectification caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit with respect to the input of the demodulation circuit is made nearly linear. The data transmission format is a pair of coils arranged facing each other and using mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses electromagnetic fields to communicate, and the The RF device 800 shown in this embodiment is The present invention can be applied to any of the above methods.

[0348] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is averaged by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for smoothing the input potential. A limiter circuit may be provided on the output side or the input side. When the internally generated voltage is large, power above a certain level is not input to the downstream circuit. This is a circuit for controlling the above.

[0349] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0350] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0351] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0352] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0353] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when the power supply is cut off. The memory circuit according to one embodiment of the present invention can be suitably used for an RF device. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance when reading and writing data. Furthermore, it is possible to prevent malfunctions or erroneous writing caused by insufficient power when writing data. It is possible.

[0354] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF device produced, This means that unique numbers can only be assigned to products that have been shipped, and the unique numbers of the products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0355] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0356] (Embodiment 8) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the above embodiment will be described.

[0357] FIG. 24 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 2 is a block diagram showing an example of a configuration.

[0358] The CPU shown in FIG. 24 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 24 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 24 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0359] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0360] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0361] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0362] In the CPU shown in FIG. 24, a memory cell is provided in the register 1196. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0363] In the CPU shown in FIG. 24, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0364] FIG. 25 is a circuit diagram of an example of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. It may further include other elements such as a converter.

[0365] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0366] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 1214 is selected.

[0367] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply voltage The other is electrically connected to a wiring (e.g., a GND line) that can supply a switch voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (the first terminal of the transistor 1214) is electrically connected to the The other of the source and drain is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) a first terminal of the switch 1204 (one of the source and drain of the transistor 1214) one of a pair of electrodes of a capacitor 1207, and an input terminal of a logic element 1206. , are electrically connected. Here, the connection point is designated as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. For example, It can be configured so that the power supply potential (GND, etc.) or high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a power supply that can supply a low power potential. The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND A power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.) can be input to the capacitance element 12. The other of the pair of electrodes of 08 is a wiring that can supply a low power supply potential (for example, GN D line).

[0368] The capacitors 1207 and 1208 are parasitic capacitances of transistors and wirings, etc. It is also possible to omit it by making active use of the above.

[0369] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive or non-conductive state between the first and second terminals, and When the first terminal and the second terminal of the switch are in a conductive state, the first terminal of the other switch and There is no electrical continuity between the second terminals.

[0370] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 25, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0371] In FIG. 25, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the drain (the other drain) is passed through the logic element 1206 and the circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the circuit 1201. The signal output from the other terminal of the transistor 1213 (the other of the source and drain of the transistor 1213) is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverted value of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0372] In addition, in FIG. 25, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed in oxide semiconductor layers. Alternatively, the memory element 1200 may include a transistor 1209 or In addition, a transistor in which a channel is formed in an oxide semiconductor layer may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be formed by

[0373] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0374] In the semiconductor device according to one embodiment of the present invention, a power supply voltage is not supplied to the memory element 1200. During this period, data stored in the circuit 1201 is transferred to the capacitor 12 in the circuit 1202. It can be retained by 08.

[0375] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer varies depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents ( It is possible to retain the data.

[0376] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operations, after the power supply voltage is resumed, the circuit 1201 This can shorten the time it takes to restore the original data.

[0377] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0378] Such a memory element 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0379] In the present embodiment, the memory element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, Also supports RF-ID (Radio Frequency Identification) It is possible to use.

[0380] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0381] (Embodiment 9) In this embodiment, a structure example of a display panel according to one embodiment of the present invention will be described.

[0382] [Configuration example] FIG. 26A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 26C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel FIG.

[0383] The transistors disposed in the pixel portion can be formed according to the above-described embodiment. In addition, since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be composed of a transistor of the same type as the transistor of the pixel part. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the above-mentioned capacitor, a highly reliable display device can be provided.

[0384] An example of a block diagram of an active matrix display device is shown in FIG. On the substrate 2100, a pixel portion 2101, a first scanning line driving circuit 2102, a second scanning line The pixel portion 2101 includes a driver circuit 2103 and a signal line driver circuit 2104. The signal line driver circuit 2104 is connected to a first scanning line driver circuit 2105, and a plurality of scanning lines are connected to a first scanning line driver circuit 2106. The scanning line driver circuit 2102 and the second scanning line driver circuit 2103 are arranged to extend from each other. At the intersections with the signal lines, pixels each having a display element are arranged in a matrix. In addition, the display device substrate 2100 is made of FPC (Flexible Printed Circuit). A timing control circuit (also called a controller or control IC) is connected through a connection such as a )

[0385] In FIG. 26A, a first scanning line driver circuit 2102, a second scanning line driver circuit 2103, The signal line driver circuit 2104 is formed on the same substrate 2100 as the pixel portion 2101. Therefore, the number of externally provided parts such as drive circuits can be reduced, leading to cost reduction. In addition, when a driving circuit is provided outside the substrate 2100, it becomes necessary to extend the wiring. If a driving circuit is provided on the same substrate 2100, the number of connections between the wiring is increased. This can reduce the number of defects, thereby improving reliability and improving yield.

[0386] [Liquid crystal panel] An example of the circuit configuration of a pixel is shown in FIG. 26(B). Here, a VA type liquid crystal display panel 4 shows a pixel circuit that can be applied to the pixel of

[0387] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be controlled. The signals applied to the pole layers can be controlled independently.

[0388] The gate wiring 2112 of the transistor 2116 and the gate wiring 2117 of the transistor 2117 113 are separated so that different gate signals can be applied. The source or drain electrode layer 2114 functioning as a transistor 2116 is It is commonly used with transistor 2117. The transistors described in the above embodiment can be appropriately used for the transistor 17. It is possible to provide a highly reliable liquid crystal display panel.

[0389] A first pixel electrode layer electrically connected to the transistor 2116 and a second pixel electrode layer electrically connected to the transistor 2117 The shape of the second pixel electrode layer electrically connected to the first pixel electrode layer will be described. The shape of the pixel electrode layer is divided by a slit. The first pixel electrode layer spreads in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0390] The gate electrode of the transistor 2116 is connected to the gate wiring 2112. The gate electrode of the gate electrode 117 is connected to the gate wiring 2113. By applying different gate signals to line 2113, transistors 2116 and 2117 By varying the operation timing, the alignment of the liquid crystal can be controlled.

[0391] In addition, a capacitance wiring 2110, a gate insulating film functioning as a dielectric, and a first pixel electrode layer Alternatively, a storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0392] The multi-domain structure has a first liquid crystal element 2118 and a second liquid crystal element 2119 in one pixel. The first liquid crystal element 2118 is made up of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 2119 is configured with a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. It is composed of:

[0393] Note that the pixel circuit shown in FIG. 26(B) is not limited to this. A switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit may be newly added to the pixel shown in FIG. etc. may be added.

[0394] [Organic EL Panel] Another example of the circuit configuration of a pixel is shown in FIG. 1 shows the pixel structure of a display panel.

[0395] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0396] FIG. 26C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0397] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain this in more detail.

[0398] The pixel 2120 includes a switching transistor 2121 and a driving transistor 2122. The switching transistor 2122 includes a light emitting element 2124 and a capacitor element 2123. 121, the gate electrode layer is connected to the scanning line 2126, and the first electrode (the source electrode layer and the drain The first electrode (one of the source and drain electrode layers) is connected to the signal line 2125, and the second electrode (one of the source and drain electrode layers) is connected to the signal line 2125. The other electrode layer is connected to the gate electrode layer of the driving transistor 2122. The transistor 2122 has a gate electrode layer connected to a power supply line 2127 via a capacitance element 2123. The first electrode is connected to a power supply line 2127, and the second electrode is connected to a first electrode (image The second electrode of the light emitting element 2124 corresponds to a common electrode 2128. The connection electrode 2128 is electrically connected to a common potential line formed on the same substrate.

[0399] The switching transistor 2121 and the driving transistor 2122 are the same as those in the above embodiment. In this way, a highly reliable organic transistor can be obtained. An EL display panel can be provided.

[0400] The potential of the second electrode (common electrode 2128) of the light emitting element 2124 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 2127. For example, GND, 0V, etc. can be set as the low power supply potential. The high and low power supply potentials are set so that the potential difference is equal to or greater than the threshold voltage in the positive direction. By applying a voltage to the element 2124, a current flows through the light emitting element 2124, causing it to emit light. The forward voltage of the light emitting element 2124 refers to a voltage required for achieving a desired luminance. At least the forward threshold voltage.

[0401] The gate capacitance of the driving transistor 2122 is used as the capacitor 2123. The gate capacitance of the driving transistor 2122 can be reduced by A capacitance may be formed between the region and the gate electrode layer.

[0402] Next, a signal to be input to the driving transistor 2122 will be described. In the case of the driving method, the driving transistor 2122 is in two states: fully on or fully off. A video signal that changes the display state to the driving transistor 2122 is input to the driving transistor 2122. In order to operate the transistor 2122 in the linear region, a voltage higher than the voltage of the power line 2127 is applied. A voltage is applied to the gate electrode layer of the driving transistor 2122. A voltage equal to or greater than the power supply line voltage plus the threshold voltage Vth of the driving transistor 2122 is applied. do.

[0403] When analog gradation driving is performed, a light emitting element is provided to the gate electrode layer of the driving transistor 2122. A value equal to or greater than the sum of the forward voltage of 2124 and the threshold voltage Vth of the driving transistor 2122 A video signal is applied so that the driving transistor 2122 operates in the saturation region. A signal is input to cause a current to flow through the light emitting element 2124. Also, the driving transistor 2122 is saturated. In order to operate the driving transistor 2122 in the low-side region, the potential of the power supply line 2127 is By making the video signal analog, the light emitting element 2124 receives the video signal. A current corresponding to the signal flows, enabling analog gray scale driving.

[0404] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. The pixel circuit shown in 6(C) is provided with a switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0405] When the transistors illustrated in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. The potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0406] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0407] (Embodiment 10) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, Image playback device equipped with a DVD: Digital Versatile Disk c) a device having a display capable of reproducing a recording medium and displaying the image. In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) (car audio, digital audio player), navigation systems, audio playback devices Layers, etc.), copiers, facsimiles, printers, printer-combinations, automated teller machines Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 27. .

[0408] FIG. 27A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 27(A) has two display units 903 and However, the number of display units that the portable game machine has is not limited to this. stomach.

[0409] FIG. 27B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit. The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The first display unit 913 and the second display unit 914 may be switched according to the angle between the first display unit 913 and the second display unit 914. At least one of the first display unit 912 and the second display unit 914 is provided with a function as a position input device. The function of the position input device may be achieved by touching the display device. The position input function can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0410] FIG. 27C shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0411] FIG. 27(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33 etc.

[0412] FIG. 27E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0413] FIG. 27(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, Light 954 etc.

[0414] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0415] (Embodiment 11) In this embodiment, a usage example of an RF device according to one embodiment of the present invention will be described with reference to FIG. The applications of RF devices are wide-ranging, but for example, Bonds, bearer bonds, certificates (driver's licenses, resident's certificates, etc., see Figure 28(A)), packaging containers (Wrapping paper and bottles, see Fig. 28(C)), recording media (DVDs and video tapes, see Fig. 28 (B)), vehicles (bicycles, etc., see Figure 28 (D)), personal belongings (bags, glasses, etc.), Food, plants, animals, the human body, clothing, daily necessities, medicines and other medical products, or electrical appliances. Items such as child devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Or it can be attached to a tag (see Figure 28(E) and Figure 28(F)) to be used. It is possible.

[0416] The RF device 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. For example, in a book, the sensor is embedded in the paper and fixed to the packaging made of organic resin. If so, it is embedded in the organic resin and fixed to each article. The F Device 4000 is small, thin, and lightweight, so even after it is fixed to an article, it remains attached to the article. It does not impair the design of the product itself. It can also be used for banknotes, coins, securities, bearer bonds, Alternatively, the RF device 4000 according to one aspect of the present invention may be provided on a document or the like, By utilizing this authentication function, counterfeiting can be prevented. Also, packaging containers, recording media, personal belongings, food, clothing, daily necessities, or electronic devices. By attaching an RF device according to one aspect of the present invention to a system such as an inspection system, In addition, the R according to one aspect of the present invention can be used for vehicles as well. By installing the F device, you can increase security against theft, etc. Cut.

[0417] As described above, the RF device according to one aspect of the present invention can be used for each of the applications described in this embodiment. By using this technology, the operating power consumption including writing and reading of information can be reduced, so the maximum communication It is possible to transmit information over long distances. Since it can be retained for a long period of time, it can be used for applications where writing and reading are not performed frequently. This can be done.

[0418] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0419] (Embodiment 12) In this embodiment, a method for producing a stack including a transistor that can be applied to the stack 10 and An example of the structure is shown in FIG. 30 to FIG. 34. In the figure, the a1-a2 cross section is a transistor. The cross section b1-b2 shows the wiring portion.

[0420] An insulator 2502 is formed on an insulator 2501. The insulator 2501 is formed by forming the insulator 2502 on the insulator 2501. The insulator 2502 may be made of the same material and by the same deposition method as the insulator 101 shown in FIG. The insulating film 2402 may be formed using the same material and film formation method as those of the insulator 2402 described in the second embodiment. Fig. 30(a)

[0421] Next, an opening or a groove is formed in the insulator 2502. In this case, a combination of materials with a large etching selectivity between the insulator 2502 and the insulator 2501 is used. It is preferable to select

[0422] When forming an opening or a groove in the insulator 2502, a photolithography method or the like is used. A resist mask is formed on the insulator 2502, and unnecessary parts of the insulator 2502 are removed. After that, the resist mask is removed to form an opening or a groove in the insulator 2502. It is possible to form the following.

[0423] The method for processing the film to be processed, such as photolithography, is the same as that shown in the second embodiment. can be used.

[0424] Next, a barrier film 2503 is provided on the insulator 2502 in which the opening or groove is formed. The aluminum oxide film 2503 is preferably made of aluminum oxide having a thickness of about 50 nm. (Figure 30(b))

[0425] The barrier film 2503 prevents water, hydrogen, and the like from diffusing from the lower layer to the upper layer. The barrier film 2503 is a layer having a function of blocking the electrodes or wiring provided thereover. The wiring has an opening or a plug for electrically connecting the wiring to an electrode or wiring provided below. It's fine.

[0426] The barrier film 2503 is made of the same material and formed by the same method as the barrier film 103 shown in the second embodiment. etc. can be used.

[0427] Next, a conductor 2504 is provided on the barrier film 2503. (FIG. 30(c))

[0428] The conductor 2504 is formed using the same material and deposition method as the conductor 104 shown in the second embodiment. It can be used.

[0429] The conductor 2504 is formed by chemical mechanical polishing (CMP). The surface may be planarized by a planarization process using a method such as a shingle method.

[0430] At this time, the conductor 2504 is attached to the barrier 2502 on the area where the opening or groove is not provided. The rear film 2503 is polished by the CMP method until the upper surface of the conductor 2504 is flush with the upper surface of the rear film 2503. You can continue or stop midway.

[0431] Next, a conductor formed in the opening or groove of the insulator 2502 is formed through a barrier film 2503. 2504 is etched to obtain a conductor 2504a. Here, the upper surface of the conductor 2504a 2502 and the upper surface of the barrier film 2503 on the area where the opening or groove of the insulator 2502 is not provided. It is preferable that the thickness is lower than the thickness of the semiconductor laser, and it is particularly preferable that the thickness is lower by about 50 nm.

[0432] Next, a barrier film 2601 is provided on the barrier film 2503 and the conductor 2504a. 31(a)) After the barrier film 2601 is formed, the surface may be flattened by a CMP method. In addition, in this embodiment, an example in which the barrier film 2601 is provided is shown, but in some cases, It is not necessary to do so.

[0433] The barrier film 2601 is the same as the barrier film 103 and the barrier film 105 shown in the second embodiment. Various materials and film formation methods can be used.

[0434] Next, an insulator 2602 having a thickness of about 100 nm is provided.

[0435] The insulator 2602 is formed using the same material and deposition method as the insulator 106 described in the second embodiment. In some cases, the insulator 2602 may be planarized by a CMP method. good.

[0436] Next, a semiconductor 2603 and a semiconductor 2604 are formed.

[0437] The semiconductor 2603 is formed using the same material and deposition method as the semiconductor 107 shown in the second embodiment. In addition, the semiconductor 2604 may be the same as the semiconductor 108 described in Embodiment 2. Similar materials, film formation methods, etc. can be used.

[0438] Next, a conductor 2605 is provided. The conductor 2605 is a conductor having a thickness of about 100 nm. It is preferable to use tinsten for the deposition of the conductor 2605. can be used.

[0439] The conductor 2605 is formed using the same material and deposition method as the conductor 109 described in the second embodiment. It can be used.

[0440] Next, an insulator 2606 is formed on the conductor 2605. For example, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide , aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc., are laminated or It can be used in a single layer. (Figure 31(b))

[0441] Next, an insulator 2606, a conductor 2605, a semiconductor 2604, a semiconductor 2603 ... semiconductor 2604, a semiconductor 2603, a semiconductor 2604, a semiconductor 2605, a semiconductor 2606, a semiconductor 26 602, barrier film 2601, barrier film 2503, insulator 2502, insulator 2501, etc. The opening is formed by photolithography or the like. A resist mask is formed on the insulating layer 2606 and the conductor 2605 to remove unnecessary portions of the insulating layer 2606 and the conductor 2605. After that, the resist mask and the like are removed, and the semiconductor 260 is formed using the conductor 2605 as a mask. 4, semiconductor 2603, insulator 2602, barrier film 2601, barrier film 2503, insulator 2 502, openings are formed in the insulator 2501, etc. In this way, openings 2607a, 2607 b is formed. (Figure 31(c))

[0442] By providing an insulator 2606 on a conductor 2605, the barrier films 2601 and 2503 When etching the insulators 2502, 2501, etc., the conductor 2605 is etched. This reduces the amount of heat generated by the conductive material 2605, and thus makes it possible to suppress the expansion of the opening formed in the conductive material 2605. do.

[0443] In addition, when the openings 2607a and 2607b are formed, the insulator 2606 is not provided, and the resist is A mask may be formed on the conductor 2605 and then openings 2607a, 2607b may be formed. stomach.

[0444] In addition, an anti-reflection film or an adhesion improving film is formed on the insulator 2606, and a resist mask is formed on the anti-reflection film or an adhesion improving film. Alternatively, the openings 2607a and 2607b may be formed after forming the mask. 05, an anti-reflection film or an adhesion improving film is formed on it, and then a resist mask is formed on it. Openings 2607a, 2607b may be formed.

[0445] When exposing a resist mask, the anti-reflection film is formed by a conductor 2605. By reducing the reflection of light, the resist ma This improves the machining accuracy of the mask, enabling finer machining.

[0446] The adhesion improving film is a film between the conductor 2605 and the resist mask, or between the insulator 2606 and By improving adhesion to the resist mask, finer processing becomes possible.

[0447] Next, a conductor 2701 is attached to the inside of the openings 2607a and 2607b and on the conductor 2605. (Figure 32(a))

[0448] The conductor 2701 is made of the same material as the conductors 111 and 112 described in the second embodiment. The material, film formation method, etc. can be used.

[0449] Next, the conductor 2701 may be planarized by a planarization process using a CMP method or the like. The surface of the conductor 2701 may also be etched by wet etching or the like.

[0450] Next, a resist mask is formed over the conductor 2701. , unnecessary portions of the conductor 2701 are removed, and conductors 2701a, 2701b, and 2701c are After that, the resist mask is removed (Figure 32(b)).

[0451] Next, a resist mask is formed on the conductor 2605, the conductors 2701a, 2701b, and 2701c. Using the resist mask, a conductor 2605, a semiconductor 2604, and a semiconductor The unnecessary parts of 2603 are removed to obtain conductors 2605a and 2605b. A part of the body 2602 may be removed. Therefore, the depth to which the part is removed may be taken into consideration. It is preferable to form the insulator 2602 to have a large thickness in advance (FIG. 33(a)).

[0452] Next, a resist mask is formed over the conductor 2605a, and unnecessary portions of the conductor 2605a are Then, the conductive bodies 2605c and 2605d are obtained (FIG. 33(b)).

[0453] Next, a semiconductor, an insulator, and a conductor are formed in this order. Then, a resist is formed on the conductor. A mask is formed and unnecessary portions of the conductor are removed. The resist mask is then removed. A conductor 2903a is obtained. Furthermore, the conductor 2903a is used as a mask to form an insulating layer and a semiconductor layer. Necessary portions are removed to obtain an insulator 2902a and a semiconductor 2901a. When obtaining the semiconductor 2901a, the resist mask used for obtaining the conductor 2903a is removed. The unnecessary parts of the insulator and semiconductor are removed to leave the insulator 2902a and the semiconductor 2 901a may be obtained. (Figure 34(a))

[0454] In this embodiment, unnecessary portions of the semiconductor and insulator are removed to form an insulator 290. 2a, an example of obtaining a semiconductor 2901a has been shown, but it is not necessary to remove unnecessary portions.

[0455] The semiconductor 2901a is made of the same material and formed by the same method as the semiconductor 113 shown in the second embodiment. The semiconductor 2901a functions as a part of the gate insulating film. In some cases.

[0456] Next, a barrier film 2904 is provided. The same material and film formation method as those for the rear film 103 can be used. (FIG. 34(b))

[0457] In this manner, a part of the stack 10 including the transistor is formed.

[0458] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The present invention can be implemented in various combinations, adaptations and substitutions.

[0459] (Embodiment 13) FIG. 35 illustrates an example of a semiconductor device according to one embodiment of the present invention. In this embodiment, In this embodiment, a single crystal silicon semiconductor is used as the laminate 20. An example in which a conductor is used and a laminate 10 is laminated on a laminate 20 will be described.

[0460] The semiconductor device includes a transistor 3600 and a transistor 3500. The transistor 3500 is disposed on the transistor 3600. A barrier film is provided between the transistor 3600 and the transistor 3600 .

[0461] The transistor 3600 is made up of a semiconductor 3011 that is a part of a semiconductor substrate 3010, an insulator 3012, a conductor 3013, and a low resistance region 3014 and a low resistance region 3015. The insulating film 3012 has a region that functions as a gate insulating film of a transistor. Region 3014 and low resistance region 3015 function as a source region and a drain region. Has an area.

[0462] The transistor 3600 may be either a p-channel type or an n-channel type. Appropriate transistors may be used depending on the type and driving method.

[0463] A region in which the channel of the semiconductor 3011 is formed and a region in the vicinity thereof, a low resistance region 3014, The low resistance region 3015 and the like may be the semiconductor 712 and the low resistance region 71 shown in the fourth embodiment. 3a, the same material and forming method as those for the low resistance region 713b can be used.

[0464] Here, the configuration including the transistor 3600 corresponds to the stacked body 20 in FIG.

[0465] Here, the transistor 3600 is replaced with the transistor 180 shown in FIG. Good too.

[0466] The conductor 3013 is covered with an insulator 3016, an insulator 3017, an insulator 3018, and an insulator The insulator 3016 is formed by laminating the insulator 7 shown in the fourth embodiment. The same material and forming method as those of the insulator 3017 of the fourth embodiment can be used. The insulator 3018 can be made of the same material and formed by the same method as the insulator 722 shown in FIG. The insulating film 724 can be formed using a material and a method similar to those of the insulator 723 shown in Embodiment 4. The insulator 3019 is made of the same material and is formed by the same method as the insulator 724 shown in the fourth embodiment. It is possible to do so.

[0467] The insulators 3016, 3017, 3018 and 3019 each have a low resistance region. A plug 3020 and a plug 3021 are electrically connected to the low resistance region 3014 and the low resistance region 3015. etc. may be embedded. If necessary, a plug is formed to electrically connect to the conductor 3013. You may do so.

[0468] On the insulator 3019, a wiring 3022, a wiring 3023, etc. are provided.

[0469] The wiring 3022 is electrically connected to the plug 3020. The wiring 3023 is electrically connected to the plug 3020. Electrically connect to 021.

[0470] The wiring 3022 and the wiring 3023 are the same as the wiring 731, the wiring 732, The same material and forming method as those for the wiring 733 can be used.

[0471] An insulator 3024 is provided on the wiring 3022 and the wiring 3023 .

[0472] When forming the wiring 3022, the wiring 3023, etc., the insulator 302 is formed on the insulator 3019. 4, an opening or a groove is formed in the insulator 3024, and then a conductor is formed as a film. The conductor remaining in the opening or groove formed in the insulator 3024 is treated by CMP or the like to form a wiring. 3022, wiring 3023, etc.

[0473] In addition, when forming the plug 3020, the plug 3021, the wiring 3022, the wiring 3023, etc. In this case, a dual damascene method or the like may be used.

[0474] The stack 10 is formed on the stack 20 described above. The stack 10 includes a transistor 3500. As an example of a part or all of the laminated body 10, FIG. 34(b) and the like can be used. It is possible to do this.

[0475] In this embodiment, an example in which the laminate shown in FIG. 34(b) is applied to a part of the laminate 10 is shown. An insulator 3025 is provided on the barrier film 2904 .

[0476] The barrier film 2904 and the insulator 3025 include conductors 2701a, 2701b, and 2701 Plugs 3026, 3027, and 3028 are provided to electrically connect to the do.

[0477] On the insulator 3025, the plugs 3026, 3027, and 3028 are electrically connected. There are provided a wiring 3029, a wiring 3030, and a wiring 3031 connected to each other.

[0478] In the semiconductor device according to one embodiment of the present invention, a transistor is provided on a stack including the transistor 3600. Since the semiconductor device has a laminate including the capacitor 3500, the area of ​​the semiconductor device can be reduced. This makes it possible to improve the integration density of semiconductor elements such as transistors. The barrier film provided between the transistor 600 and the transistor 3500 prevents the Impurities such as water and hydrogen present in the semiconductor device can be prevented from diffusing to the transistor 3500 side.

[0479] In this embodiment, the transistor 3600 is a p-type transistor. If the 3500 transistor is an n-type transistor, a CMOS inverter circuit can be constructed. In this way, the layout can be made by stacking the transistors that make up the unit circuits. This improves the degree of freedom and allows for increased integration.

[0480] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The above-mentioned embodiments may be combined, adapted, or substituted as desired.

[0481] (Embodiment 14) FIG. 36 illustrates an example of a semiconductor device according to one embodiment of the present invention. In this embodiment, In this embodiment, a part of the laminate 20 is made of single crystal silicon. An example in which a semiconductor is used and a laminate 10 is laminated on a laminate 20 will be described.

[0482] The laminate 20 may be the same as the laminate 20 shown in the thirteenth embodiment. is possible.

[0483] The stack 10 is formed over the stack 20. The stack 10 includes a transistor 3101.

[0484] In this embodiment, a laminate 10 having a partly modified from that shown in FIG. 34(b) is applied. Specifically, the conductors 2701a, 2701b, and 270 A structure that does not form 1c is applied.

[0485] An insulator 3025 is provided on the barrier film 2904. The body 3025 includes a plug 3126 for electrical connection with the wiring 3022, and a A plug 3128 is formed to electrically connect to the conductor 2605d. Forming lug 3127.

[0486] On the insulator 3025, the plugs 3126, 3127, and 3128 are electrically connected. There are provided wiring 3129, wiring 3130, and wiring 3131 connected to each other.

[0487] In the semiconductor device according to one embodiment of the present invention, a transistor is provided on a stack including the transistor 3600. Since the semiconductor device has a stacked body including the capacitor 3101, the area of ​​the semiconductor device can be reduced. This makes it possible to improve the integration density of semiconductor elements such as transistors. The barrier film provided between 600 and the transistor 3101 prevents the Impurities such as water and hydrogen present in the semiconductor device can be prevented from diffusing to the transistor 3101 side.

[0488] In this embodiment, the transistor 3600 is a p-type transistor. If the transistor 3101 is an n-type transistor, a CMOS inverter circuit can be constructed. In this way, the layout can be made by stacking the transistors that make up the unit circuits. This improves the degree of freedom and allows for increased integration.

[0489] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The above-mentioned embodiments may be combined, adapted, or substituted as desired.

[0490] (Embodiment 15) FIG. 37 illustrates an example of a semiconductor device according to one embodiment of the present invention. In this embodiment, In this embodiment, a single crystal silicon semiconductor is used as the laminate 20. An example in which a conductor is used and a laminate 10 is laminated on a laminate 20 will be described.

[0491] The laminate 20 may be the same as the laminate 20 shown in the thirteenth embodiment. is possible.

[0492] A stack body 10 is formed over the stack body 20. The stack body 10 includes a transistor 3201.

[0493] In this embodiment, a laminate 10 having a partly modified from that shown in FIG. 34(b) is applied. Specifically, after forming the barrier film 2601, the wiring 3022 is electrically connected to the barrier film 2601. and a plug 3232 and a wiring 3233 electrically connected to the wiring 3023. 34(b) and the conductors 2701a, 2701b, 2701c, 2701d, 2701e, 2701f, 2701g, 2701h, 2701i, 2701j, 2701p, 2701p, 2701p, 2701b ... A structure that does not form 701c is applied.

[0494] An insulator 3225 is provided on the barrier film 2904. The body 3225 includes a plug 3226 electrically connected to the wiring 3233, and a connector 3226 electrically connected to the wiring 3235. A plug 3228 is formed to electrically connect to the conductor 2605d. Forming lug 3227.

[0495] On the insulator 3225, a plug 3226, a plug 3227, and a plug 3228 are electrically connected. There are provided wiring 3229, wiring 3230, and wiring 3231 connected to each other.

[0496] In the semiconductor device according to one embodiment of the present invention, a transistor is provided on a stack including the transistor 3600. Since the semiconductor device has a stacked body including the capacitor 3201, the area of ​​the semiconductor device can be reduced. This makes it possible to improve the integration density of semiconductor elements such as transistors. The barrier film provided between 600 and the transistor 3201 prevents the Impurities such as water and hydrogen present in the semiconductor device can be prevented from diffusing to the transistor 3201 side.

[0497] In this embodiment, the transistor 3600 is a p-type transistor. If the transistor 3201 is an n-type transistor, a CMOS inverter circuit can be constructed. In this way, the layout can be made by stacking the transistors that make up the unit circuits. This improves the degree of freedom and allows for increased integration.

[0498] Note that a part or all of this embodiment may be independently modified in a part or all of another embodiment. The above-mentioned embodiments may be combined, adapted, or substituted as desired. [Explanation of symbols]

[0499] 10 Laminate 20 Laminate 30 Laminate 100 transistors 101 Insulators 102 Insulators 103 Barrier Film 104 Conductors 104a Electric conductor 105 Barrier membrane 105a Barrier film 106 Insulators 107 Semiconductors 107a Semiconductors 108 Semiconductors 108a Semiconductors 109 Conductors 109a Electric conductor 109b Conductors 109c Conductors 110 Aperture 111 Conductors 111a Conductor 111b Conductor 111c conductor 112 Conductors 112a Conductor 112b Conductor 113 Semiconductors 114 Insulators 115 Conductors 116 Barrier Membrane 120a plug 120b plug 130 capacity 180 Transistors 200 Transistors 708 Insulator 711 Semiconductor Substrate 712 Semiconductors 713a Low resistance region 713b Low resistance region 714 Gate insulating film 715 Gate electrode 721 Insulators 722 Insulators 723 Insulators 724 Insulators 725 Insulators 726 Insulators 727 Insulators 728 Insulator 729 Insulators 730 Insulators 731 Wiring 732 Wiring 733 Wiring 741 Insulators 742 Insulators 743 Insulators 744 Insulators 751 Wiring 752 Wiring 753 Wiring 754 Wiring 755 Wiring 756 Wiring 757 Wiring 758 Wiring 759 Wiring 761 Plug 762 Plug 763 Plug 764 Plug 765 Plug 766 Plug 767 Plug 768 Plug 769 Plug 770 Plug 771 Plug 772 Plug 773 Plug 781 Electrode 782 Insulator 783 Electrode 800 RF Devices 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 812 Semiconductors 814 Gate insulating film 815 Gate electrode 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 1700 Transistors 1701 Transistor 2100 Board 2101 Pixel section 2102 Scanning line driver circuit 2103 Scanning line driver circuit 2104 Signal line driver circuit 2110 Capacitance wiring 2112 Gate wiring 2113 Gate wiring 2114 Drain electrode layer 2116 Transistor 2117 Transistor 2118 Liquid crystal element 2119 Liquid crystal element 2120 pixels 2121 Switching transistor 2122 Driving transistor 2123 Capacitive element 2124 Light emitting element 2125 Signal Line 2126 scan lines 2127 Power line 2128 Common electrode 2402 Insulator 2501 Insulator 2502 Insulator 2503 Barrier film 2504 Conductor 2504a Conductor 2601 Barrier film 2602 Insulators 2603 Semiconductors 2604 Semiconductors 2605 Conductors 2605a Electric conductor 2605b Conductor 2605c conductor 2605d conductor 2606 Insulators 2607a aperture 2607b Aperture 2701 Conductors 2701a Conductor 2701b Electric conductor 2701c Conductor 2901a Semiconductor 2902a Insulator 2903a Electrical conductor 2904 Barrier membrane 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3010 Semiconductor substrate 3011 Semiconductors 3012 Insulator 3013 Conductors 3014 Low resistance region 3015 Low resistance area 3016 Insulators 3017 Insulators 3018 Insulator 3019 Insulators 3020 Plug 3021 Plug 3022 Wiring 3023 Wiring 3024 Insulator 3025 Insulator 3026 Plug 3027 Plug 3028 Plug 3029 Wiring 3030 Wiring 3031 Wiring 3101 Transistor 3126 Plug 3127 Plug 3128 Plug 3129 Wiring 3130 Wiring 3131 Wiring 3134 Plug 3200 Transistors 3201 Transistor 3225 Insulator 3226 Plug 3227 Plug 3228 Plug 3229 Wiring 3230 Wiring 3231 Wiring 3232 Plug 3233 Wiring 3235 Wiring 3300 Transistors 3400 Capacitive element 3500 Transistors 3600 Transistors 4000 RF Devices 5100 pellets 5100a Pellet 5100b Pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellet 5105a1 area 5105a2 Pellet 5105b Pellet 5105c Pellet 5105d Pellet 5105d1 area 5105e Pellet 5120 PCB 5130 Target 5161 area

Claims

[Claim 1] A first element; and a first insulator over the first element; and a first barrier film on the first insulator; a first conductor on the first barrier film; a second barrier film on the first conductor; and a second insulator on the second barrier film; a semiconductor on the second insulator; the first conductor is surrounded by the first barrier film and the second barrier film; Semiconductor device.

Images