Semiconductor device

Abstract

To control the position of substrate bonding.SOLUTION: A semiconductor device has adjacent insulating circuit boards 11 and a heat dissipation base 3. The heat dissipation base 3 has one insulating circuit board 11 bonded to the front surface 3a via a solder layer 17a and the other insulating circuit board 11 bonded via a solder layer 17b. The adjacent insulating circuit boards 11 face each other with a gap between them, and a gap resist section 4a is formed along the solder layers 17a and 17b in the gap on the front surface 3a. The gap resist section 4a contacts the edge 17a1 facing the solder layer 17b of the solder layer 17a and the edge 17b1 facing the solder layer 17a of the solder layer 17b, respectively.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] The semiconductor device includes a base substrate, an insulating circuit substrate provided on the base substrate via solder, and a semiconductor chip provided on the insulating circuit substrate via solder (see, for example, Patent Document 1). In such a semiconductor device, a resist is formed around the solder on the base substrate (see, for example, Patent Documents 2 and 3). Alternatively, a resist is formed around the solder on the insulating circuit substrate (see, for example, Patent Documents 4 and 5). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-164919 A [Patent Document 2] JP 2010-212723 A [Patent Document 3] JP 2013-201289 A [Patent Document 4] JP 2013-236037 A [Patent Document 5] JP 2017-117813 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device in which the bonding position of the substrate is controlled. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising: a first substrate and a second substrate; a heat dissipation base having a front surface to which the first substrate is bonded via a first solder layer and the second substrate is bonded via a second solder layer, the first substrate and the second substrate facing each other with a gap therebetween, and a resist formed along the first solder layer and the second solder layer in the gap on the front surface, the resist being in contact with a first edge portion of the first solder layer facing the second solder layer and a second edge portion of the second solder layer facing the first solder layer, respectively.

[0006] The first substrate may have a first insulating plate, a first conductive plate formed on the front surface of the first insulating plate, and a first metal plate formed on the rear surface of the first insulating plate and joined to the front surface of the heat dissipation base via the first solder layer, and the second substrate may have a second insulating plate, a second conductive plate formed on the front surface of the second insulating plate, and a second metal plate formed on the rear surface of the second insulating plate and joined to the front surface of the heat dissipation base via the second solder layer.

[0007] Furthermore, a length of the gap between the first solder layer and the second solder layer may be longer than a length between the first insulating plate of the first substrate and the second insulating plate of the second substrate. The resist may be composed mainly of a carbon or nickel oxide film.

[0008] Furthermore, the width of the gap in the resist parallel to the gap direction may be longer than 1 mm and shorter than 5 mm. Furthermore, the width of the gap in the resist parallel to the gap direction may be 2 mm or more and 4 mm or less.

[0009] Furthermore, the distance between the first edge of the first solder layer and the second edge of the second solder layer may be 1.5 mm or more and 2.5 mm or less.

[0010] The resist may include a first resist portion in contact with the first edge portion of the first solder layer, and a second resist portion in contact with the second edge portion of the second solder layer and spaced apart from the first resist portion.

[0011] Furthermore, the thickness of the resist may be thinner than the thicknesses of the first solder layer and the second solder layer.

[0012] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. Effect of the Invention

[0013] According to the disclosed technology, it is possible to control the joining positions of the substrates and realize high density mounting of the substrates. [Brief description of the drawings]

[0014] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Figure 4] 1 is a flowchart (part 1) of a method for manufacturing a semiconductor device according to a first embodiment. [Diagram 5] 4 is a flowchart (part 2) of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 3 is a plan view of a heat dissipation base prepared in a preparation step included in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 7] 3 is a plan view of a heat dissipation base on which a resist is formed, the heat dissipation base being prepared in a preparation step included in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 8] 4 is a plan view showing a semiconductor unit bonding step (setting of a positioning jig) included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9]4 is a cross-sectional view showing a semiconductor unit bonding step (setting of a positioning jig) included in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 10] 5 is a cross-sectional view showing a semiconductor unit bonding step (semiconductor unit setting) included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11] 5 is a cross-sectional view showing a semiconductor unit bonding step (cooling) included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 12] 10A to 10C are cross-sectional views showing a semiconductor unit bonding step (heating) included in the method for manufacturing a semiconductor device according to a reference example. [Figure 13] 10A to 10C are cross-sectional views showing a semiconductor unit bonding step (cooling) included in the method for manufacturing a semiconductor device according to a reference example. [Figure 14] 11 is a cross-sectional view of a main part showing a semiconductor unit bonding step (removal of a positioning jig) included in the manufacturing method of a semiconductor device according to a reference example. FIG. [Figure 15] 11 is a graph showing the amount of movement of an insulating circuit board relative to the width of a resist. [Figure 16] FIG. 11 is a plan view of a semiconductor device according to a second embodiment. [Figure 17] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiment will be described with reference to the drawings. In the following description, the "front surface" and "upper surface" refer to the XY surface facing upward (+Z direction) in the semiconductor device 1, 1a in the figure. Similarly, "upper" refers to the upward (+Z direction) direction in the semiconductor device 1, 1a in the figure. The "rear surface" and "lower surface" refer to the XY surface facing downward (-Z direction) in the semiconductor device 1, 1a in the figure. Similarly, "lower" refers to the downward (-Z direction) direction in the semiconductor device 1, 1a in the figure. The same directionality as above will be used in other figures as necessary. "Higher" and "upper" refer to the upper (+Z direction) position in the semiconductor device 1, 1a in the figure. Similarly, "lower" and "lower" refer to the lower (-Z direction) position in the semiconductor device 1 in the figure. The terms "front surface," "upper surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships, and do not limit the technical idea of ​​the present invention. For example, "top" and "bottom" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "top" and "bottom" are not limited to the direction of gravity. In addition, in the following description, "main component" refers to a content of 80 vol% or more (a ratio excluding filler if filler is included). Furthermore, "substantially the same" may be within a range of ±10%. Furthermore, "perpendicular," "orthogonal," and "parallel" may be within a range of ±10°.

[0016] [First embodiment] A semiconductor device according to a first embodiment will be described with reference to Figs. 1 to 3. Fig. 1 is a plan view of the semiconductor device according to the first embodiment, and Fig. 2 is a cross-sectional view of the semiconductor device according to the first embodiment. Fig. 3 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment. Fig. 1 shows a half of the semiconductor device 1 on the -Y direction side in a plan view. Fig. 2 is a cross-sectional view taken along dashed line YY in Fig. 1. Fig. 3 is an enlarged view of an area A surrounded by a dashed line in Fig. 2. The sealing member is not shown in Figs. 1 to 3.

[0017] As shown in FIG. 1 and FIG. 2, the semiconductor device 1 includes a semiconductor unit 10, a case 2, and a heat dissipation base 3. The storage area 22 of the case 2 may be sealed with a sealing member. The sealing member may be, for example, a thermosetting resin mixed with a filler. Examples of the thermosetting resin include epoxy resin, phenol resin, maleimide resin, and polyester resin. The filler may be, for example, a ceramic having insulating properties and high thermal conductivity. Such a filler is, for example, silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0018] Four semiconductor units 10 are arranged on the front surface 3a of the heat dissipation base 3. The four semiconductor units 10 are arranged in two rows and two columns at the center of the front surface 3a of the heat dissipation base 3 with gaps between them.

[0019] In this case, in the semiconductor unit 10, as shown in FIG. 3, if the distance between the insulating plates 12 of the insulating circuit board 11 is L1 and the distance between the metal plates 14 is W, the maximum distance between the solder layers 17a and 17b is also W. The longest point in the width direction (±X direction) of the gap resist portion 4a described later is width L2. In fact, since the thickness of the gap resist portion 4a is sufficiently thinner than the solder layers 17a and 17b, the length of the gap resist portion 4a in the width direction (±X direction) can be substantially regarded as width L2. In addition, this is a case where two adjacently arranged semiconductor units 10 are viewed in the +Y direction. Although not shown, the two semiconductor units 10 are joined to the heat dissipation base 3 via a solder layer in the same manner when the two adjacently arranged semiconductor units 10 are viewed in the -Y direction. When the two adjacently arranged semiconductor units 10 are viewed in the +X direction, the distances L1, W, and width L2 are the same as those described above.

[0020] In this case, the width L2 is longer than the distance L1. The width L2 is 1.5 mm or more and 2.5 mm or less, for example, 2.0 mm. The distance W between the metal plates 14 of the insulating circuit board 11 is 4.4 mm or more and 4.8 mm or less, for example.

[0021] Moreover, since the solder layers 17a and 17b include a fillet portion, the distance L3 between the ends of the fillet portions of the solder layers 17a and 17b is longer than the distance W. Moreover, the ends of the fillet portions of the solder layers 17a and 17b may be located inside the ends of the insulating plate 12. Therefore, it is considered that the width L2 corresponds to the distance L3 between the ends of the fillet portions of the solder layers 17a and 17b. Therefore, the distance between the ends of the fillet portions of the solder layers 17a and 17b is also 1.5 mm or more and 2.5 mm or less. The thickness of the solder layers 17a and 17b is, for example, 0.23 mm or more and 0.27 mm or less. The number of the semiconductor units 10 is an example. The number of the semiconductor units 10 may be provided according to the functions required for the semiconductor device 1.

[0022] The semiconductor unit 10 includes an insulating circuit board 11 and semiconductor chips 15a and 15b arranged via a solder layer 17c (see FIG. 3) on the front surface of the insulating circuit board 11. The back surface of the semiconductor unit 10 is joined to the front surface 3a of the heat dissipation base 3 via the solder layers 17a and 17b.

[0023] The solder layers 17a, 17b, and 17c are made of lead-free solder. The lead-free solder mainly contains at least one of the following alloys: an alloy of tin-silver-copper, an alloy of tin-zinc-bismuth, an alloy of tin-copper, and an alloy of tin-silver-indium-bismuth. The solder layers 17a, 17b, and 17c may further contain additives. The additives are, for example, nickel, germanium, cobalt, or silicon. The solder layers 17a, 17b, and 17c can have improved wettability, gloss, and bonding strength, thereby improving reliability.

[0024] The insulating circuit board 11 is rectangular in plan view. The insulating circuit board 11 includes an insulating plate 12, conductive plates 13a and 13b provided on the front surface of the insulating plate 12, and a metal plate 14 provided on the back surface of the insulating plate 12. The outer shapes of the conductive plates 13a and 13b and the metal plate 14 are smaller than the outer shape of the insulating plate 12 in plan view, and are formed inside the insulating plate 12. Note that the shapes and number of the conductive plates 13a and 13b are merely examples.

[0025] The conductive plates 13a and 13b have the semiconductor chips 15a and 15b bonded to the front surface thereof via a solder layer 17c. The conductive plates 13a and 13b are formed over the entire surface of the insulating plate 12 except for the edge portion. Preferably, in a plan view, the ends of the conductive plates 13a and 13b facing the outer periphery of the insulating plate 12 overlap with the outer periphery side end of the metal plate 14. Therefore, the insulating circuit board 11 maintains a stress balance with the metal plate 14 on the back surface of the insulating plate 12. Damage such as excessive warping and cracking of the insulating plate 12 is suppressed. The conductive plates 13a and 13b are made of a material having excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. It is also possible to perform plating processing on the conductive plates 13a and 13b using a material having excellent corrosion resistance. Examples of such materials include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The thickness of the plating film is 10 μm or less. The conductive plates 13a and 13b for the insulating plate 12 are obtained by forming a metal plate on the front surface of the insulating plate 12 and performing a process such as etching on the metal plate. Alternatively, the conductive plates 13a and 13b may be cut out in advance from a metal plate and bonded to the front surface of the insulating plate 12. Note that the conductive plates 13a and 13b included in the semiconductor device 1 of this embodiment are merely an example. The number, shape, size, etc. of the conductive plates may be appropriately selected as necessary. Note that the front surfaces of the conductive plates 13a and 13b are also the front surface of the insulating circuit board 11.

[0026] The back surface of the metal plate 14 is joined to the front surface 3a of the heat dissipation base 3 via solder layers 17a and 17b. The metal plate 14 is made of a metal with excellent thermal conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The thickness of the metal plate 14 may be, for example, 0.25 mm or more and 0.35 mm or less. In addition, in order to improve corrosion resistance, a plating process may be performed on the surface of the metal plate 14. In this case, the plating material contains nickel. Examples of such plating materials are nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The back surface of the metal plate 14 is also the back surface of the insulating circuit board 11.

[0027] Examples of the insulating circuit board 11 having such a configuration include a DCB (Direct Copper Bonding) board and an AMB (Active Metal Brazed) board. Alternatively, a resin insulating board may be used. The insulating circuit board 11 dissipates heat generated by semiconductor chips 15a and 15b (described later) by conducting the heat to the rear side of the insulating circuit board 11 via the conductive plates 13a and 13b, the insulating plate 12, and the metal plate 14.

[0028] The semiconductor chips 15a and 15b are mainly composed of, for example, silicon, silicon carbide, or gallium nitride. The semiconductor chip 15a includes a switching element. Examples of the switching element include an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). When the semiconductor chip 15a is an IGBT, it has a collector electrode as a main electrode (input electrode) on the back surface, and a gate electrode as a control electrode and an emitter electrode as a main electrode (output electrode) on the front surface. When the semiconductor chip 15a is a power MOSFET, it has a drain electrode as a main electrode (input electrode) on the back surface, and a gate electrode as a control electrode and a source electrode as a main electrode (output electrode) on the front surface.

[0029] The semiconductor chip 15b also includes a diode element. For example, a Schottky Barrier Diode (SBD) or a P-intrinsic-N (PiN) diode is used as a Free Wheeling Diode (FWD). The semiconductor chip 15b has a cathode electrode as a main electrode (output electrode) on the back surface and an anode electrode as a main electrode (input electrode) on the front surface.

[0030] Also, instead of the semiconductor chips 15a and 15b, a semiconductor chip including a switching element may be used. Such a semiconductor chip may be mainly composed of silicon, for example. An example of the switching element is an RC (Reverse-Conducting)-IGBT. The RC-IGBT is a semiconductor element in which an IGBT and an FWD are arranged in reverse parallel within one chip. In this case, the semiconductor chip may have a collector electrode as a main electrode (input electrode) on the back surface, and a gate electrode as a control electrode and an emitter electrode as a main electrode (output electrode) on the front surface.

[0031] As another switching element in place of the semiconductor chips 15a and 15b, a power MOSFET mainly made of silicon carbide may be used. In the power MOSFET, the body diode may function as the FWD. Such a semiconductor chip has, for example, a drain electrode as a main electrode (input electrode) on the back surface, a gate electrode as a control electrode, and a source electrode as a main electrode (output electrode) on the front surface.

[0032] The case 2 includes a frame portion 20 and external connection terminals 23 embedded in the frame portion 20. The frame portion 20 has a rectangular shape in a plan view and forms a frame shape surrounding a storage area 22. The storage area 22 is an area in which the center of a front surface 21 of the case 2 is opened.

[0033] Further, steps 22b are formed on the short sides of the frame 20 in the storage area 22. The steps 22b protrude from the inner walls of the opposing short sides of the frame 20 so as to face each other. The inner walls 22a connected to the steps 22b face the storage area 22.

[0034] Such a frame 20 is formed by injection molding using a thermoplastic resin containing a filler. Examples of such a resin include polyphenylene sulfide resin, polybutylene terephthalate resin, and polyamide resin. The filler may be composed mainly of, for example, glass fiber, glass beads, calcium carbide, talc, magnesium oxide, or aluminum hydroxide.

[0035] The external connection terminal 23 is flat and L-shaped in side view. The external connection terminal 23 is integrally molded with the frame portion 20. The external connection terminal 23 includes an inner end and an outer end. The inner end is disposed on the step 22b, extends toward the center of the storage area 22, and is electrically and mechanically connected to the insulating circuit board 11 of the semiconductor unit 10. The outer end is provided on the front surface 21 of the frame portion 20.

[0036] Such an external connection terminal 23 is made of a material having excellent electrical conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The external connection terminal 23 has a uniform thickness over the entirety. It is also possible to plate the external connection terminal 23 with a material having excellent corrosion resistance. Examples of such materials include aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or an alloy containing at least one of these.

[0037] The rear surface of the frame 20 of the case 2 is bonded by an adhesive (reference numeral omitted) to the outer periphery of the front surface 3a of the heat dissipation base to which the semiconductor unit 10 is bonded. As a result, the semiconductor unit 10 is stored in the storage area 22 of the frame 20. Although not shown in the drawings, the storage area 22 of the frame 20 may be covered with a lid (not shown) and bonded by an adhesive. Examples of the adhesive include a thermosetting resin adhesive and an elastomer adhesive. The thermosetting resin adhesive is mainly composed of, for example, epoxy resin or phenol resin. The elastomer adhesive is mainly composed of, for example, silicone rubber or chloroprene rubber.

[0038] Although not shown in Figs. 1 and 2, the frame 20 may integrally include a control terminal to which a control signal is input from the outside, similar to the external connection terminal 23. The control terminal may also include an inner end and an outer end. The inner end may be electrically connected to the control terminal of the semiconductor chip 15a by a wire. The outer end may be exposed from the front surface 21 of the frame 20. The wire is made of a material with excellent conductivity. The material may be, for example, gold, silver, copper, aluminum, or an alloy containing at least one of these.

[0039] Also, here, the case where external connection terminal 23 is electrically and mechanically connected to insulating circuit board 11 is illustrated. An inner end of external connection terminal 23 may be disposed on step 22b, and the inner terminal and insulating circuit board 11 may be connected by a wiring member. The wiring member is made of a material having excellent conductivity. Such a material may be, for example, gold, silver, copper, aluminum, or an alloy containing at least one of these. Examples of such wiring members include wires and lead frames.

[0040] The heat dissipation base 3 has a rectangular shape in a plan view. The shape and area of ​​the heat dissipation base 3 in a plan view may correspond to the shape and area of ​​the case 2 in a plan view. The four corners of the heat dissipation base 3 in a plan view may form a right angle, and may be R-chamfered or C-chamfered. The heat dissipation base 3 includes a front surface 3a. Furthermore, the heat dissipation base 3 includes a long side surface 3a1, a short side surface 3a2, a long side surface 3a3, and a short side surface 3a4 that surround the four sides of the front surface 3a in a plan view (see Figures 6 and 7). Furthermore, the heat dissipation base 3 has fixing holes 3b formed at each of the four corners in a plan view. The fixing holes 3b are holes that penetrate the heat dissipation base 3. The semiconductor device 1 is placed in a predetermined area, and the semiconductor device 1 is fixed by inserting bolts into the fixing holes 3b.

[0041] The heat dissipation base 3 is made of a metal having excellent thermal conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. Here, copper is included. The thickness of the heat dissipation base 3 depends on the size of the semiconductor device 1, and may be, for example, 2.5 mm or more and 3.5 mm or less.

[0042] Also, a cooling unit (not shown) may be attached to the rear surface of the heat dissipation base 3 via a thermally conductive member. The thermally conductive member is a thermal interface material (TIM). TIM includes various materials such as thermally conductive grease, elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, phase change material, solder, and silver solder. This can improve the heat dissipation of the semiconductor device 1. In this case, the cooling unit is made of, for example, a metal with excellent thermal conductivity. The metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. Also, the cooling unit is, for example, a heat sink with one or more fins or a water-cooled cooling device.

[0043] Furthermore, a resist 4 is formed on the front surface 3a of the heat dissipation base 3. The resist 4 may be mainly composed of, for example, carbon or a metal oxide. An example of the metal oxide is nickel oxide. In the case of carbon, the resist 4 is formed by drawing a line on the front surface 3a in a region where the resist 4 is to be formed with a pencil. In the case of nickel oxide, the resist 4, mainly composed of a nickel oxide film, is formed by irradiating the region where the resist 4 is to be formed on the front surface 3a of the heat dissipation base 3 that has been plated with a plating film containing nickel with a laser.

[0044] Such a resist 4 includes a gap resist portion 4a and a peripheral resist portion 4b. The thickness of the resist 4 may be generally uniform. The gap resist portion 4a is formed along the solder layer that joins the four insulating circuit boards 11 in the gaps between the four insulating circuit boards 11 in a plan view of the front surface 3a of the heat dissipation base 3. FIG. 3 shows a case where the gap resist portion 4a is formed in the gaps between the solder layers 17a and 17b that join the insulating circuit board 11 to the front surface 3a. Specifically, the gap resist portion 4a is in contact with an edge portion 17a1 of the solder layer 17a facing the solder layer 17b and an edge portion 17b1 of the solder layer 17b facing the solder layer 17a. That is, the gap resist portion 4a is formed on the front surface 3a of the heat dissipation base 3 so as to fill the entire gap between the solder layers 17a and 17b. The thickness of the gap resist portion 4a is sufficiently thinner than the thickness of the solder layers 17a, 17b. Such gap resist portion 4a has water repellency to solder and suppresses the solder layer that joins the insulating circuit board 11 and the front surface 3a of the heat dissipation base 3 from spreading inward.

[0045] The peripheral resist portion 4b is formed on the outer periphery surrounding the four insulating circuit boards 11 arranged on the front surface 3a of the heat dissipation base 3. The peripheral resist portion 4b includes a long side portion, a short side portion, a long side portion, and a short side portion that are parallel to the long side surface 3a1, the short side surface 3a2, the long side surface 3a3, and the short side surface 3a4 of the heat dissipation base 3, respectively, in a plan view. The connection points of the corners of the peripheral resist portion 4b may form a right angle. Alternatively, they may be R-chamfered or C-chamfered. Each portion of the peripheral resist portion 4b is provided between the inner wall of the frame portion 20 of the case 2 and the insulating circuit board 11 (solder layer). For example, as shown in FIG. 2, the peripheral resist portion 4b may be provided between the solder layers 17a, 17b that join the insulating circuit board 11 and the inner wall 22a of the frame portion 20. That is, unlike the gap resist portion 4a, the outer peripheral resist portion 4b does not need to fill the entire space between the solder layers 17a, 17b that join the insulating circuit board 11 and the inner wall 22a of the frame portion 20 in a side view. The width of the outer peripheral resist portion 4b may be narrower than the width L2 of the gap resist portion 4a. Such an outer peripheral resist portion 4b also suppresses the outward spreading of the solder layer that joins the insulating circuit board 11 and the front surface 3a of the heat dissipation base 3.

[0046] Next, a method for manufacturing such a semiconductor device 1 will be described with reference to Fig. 4 and Fig. 5. Fig. 4 and Fig. 5 are flowcharts of the method for manufacturing the semiconductor device according to the first embodiment. Note that step S3 in Fig. 4 is followed by step S4 in Fig. 5.

[0047] First, a preparation step is performed to prepare components of the semiconductor device 1 (step S1 in FIG. 4). The components prepared at this time are, for example, the insulating circuit board 11, the semiconductor chips 15a and 15b, the case 2, and the heat dissipation base 3. In addition to these, other components necessary for the semiconductor device 1 are also prepared. In addition, a manufacturing device used for manufacturing the semiconductor device 1 may also be prepared.

[0048] In the preparation step, a resist 4 is formed on the heat dissipation base 3. The formation of the resist 4 on the heat dissipation base 3 will be described. First, the heat dissipation base 3 is prepared (step S1a in FIG. 4). The heat dissipation base 3 will be described with reference to FIG. 6. FIG. 6 is a plan view of the heat dissipation base prepared in the preparation step included in the manufacturing method of the semiconductor device according to the first embodiment.

[0049] As shown in Fig. 6, the heat dissipation base 3 has a rectangular shape in a plan view, and the four corners may be rounded. The heat dissipation base 3 includes a front surface 3a. The heat dissipation base 3 also includes long side surfaces 3a1, short side surfaces 3a2, long side surfaces 3a3, and short side surfaces 3a4 that surround the front surface 3a on all four sides in a plan view. Furthermore, the heat dissipation base 3 has fixing holes 3b formed at each of the four corners in a plan view.

[0050] Moreover, arrangement regions 3c1, 3c2, 3c3, and 3c4 are respectively set on the front surface 3a of the heat dissipation base 3. The arrangement regions 3c1, 3c2, 3c3, and 3c4 may correspond to the size of the metal plate 14 included in the insulating circuit board 11 of the semiconductor unit 10. The gap between the arrangement regions 3c1, 3c2, 3c3, and 3c4 is a distance W, which may be, for example, 1.8 mm or more and 2.2 mm or less.

[0051] Next, a resist 4 is formed on the front surface 3a of the heat dissipation base 3 (Step S1b in FIG. 4). The formation of the resist 4 will be described with reference to FIG. 7. FIG. 7 is a plan view of the heat dissipation base on which a resist is formed, which is prepared in a preparation step included in the manufacturing method of the semiconductor device according to the first embodiment.

[0052] First, the peripheral resist portion 4b is formed on the front surface 3a parallel to the long side surface 3a1, the short side surface 3a2, the long side surface 3a3, and the short side surface 3a4, and at a predetermined distance from the arrangement regions 3c1, 3c2, 3c3, and 3c4. The peripheral resist portion 4b has a continuous ring shape in a plan view, forming a frame shape.

[0053] Moreover, the gap resist portion 4a is parallel to the long side surface 3a1, the short side surface 3a2, the long side surface 3a3, and the short side surface 3a4, and is formed in the gaps between the arrangement regions 3c1, 3c2, 3c3, and 3c4 on the front surface 3a. In FIG. 7, the gap resist portion 4a is shown to be formed so as to fill the gaps between the arrangement regions 3c1, 3c2, 3c3, and 3c4. In reality, the gap resist portion 4a is formed several millimeters away from the arrangement regions 3c1, 3c2, 3c3, and 3c4 in the gaps, taking into account the spread of the solder as described later. The gap resist portion 4a forms a cross shape in a plan view, and connects the short sides and long sides of the peripheral resist portion 4b.

[0054] Therefore, the resist 4 has a rectangular shape in a plan view and includes four opening regions 4c1, 4c2, 4c3, and 4c4. Opposing sides of the opening regions 4c1, 4c2, 4c3, and 4c4 correspond to opposing sides of the arrangement regions 3c1, 3c2, 3c3, and 3c4. It is sufficient that the resist 4 is drawn as shown in FIG. 7, and the order of forming the gap resist portion 4a and the peripheral resist portion 4b does not matter.

[0055] Next, a unit assembly process is performed (step S2 in FIG. 4) to assemble the semiconductor unit 10. The semiconductor chips 15a and 15b are respectively joined to the conductive plates 13a and 13b of the insulating circuit board 11 by the solder layers 17c to assemble the semiconductor unit 10. Here, four such semiconductor units 10 are assembled.

[0056] Next, a semiconductor unit bonding step is performed in which the semiconductor units 10 are bonded to the front surface 3a of the heat dissipation base 3 (step S3 in FIG. 4). In carrying out the semiconductor unit bonding step, first, a positioning jig 30 is placed on the front surface 3a of the heat dissipation base 3 (step S3a in FIG. 4). This step will be described with reference to FIGS. 8 and 9. FIG. 8 is a plan view showing the semiconductor unit bonding step (setting of the positioning jig) included in the manufacturing method of the semiconductor device of the first embodiment. FIG. 9 is a cross-sectional view showing the semiconductor unit bonding step (setting of the positioning jig) included in the manufacturing method of the semiconductor device of the first embodiment. Note that FIG. 9 is a cross-sectional view taken along dashed line YY in FIG. 8.

[0057] As shown in Figs. 8 and 9, the positioning jig 30 is set on the front surface 3a of the heat dissipation base 3. The positioning jig 30 is made of a material that is excellent in heat resistance and does not wet the solder. Examples of such materials include carbon or metal with an oxide film formed on the surface. The positioning jig 30 includes a front surface 30a that is substantially rectangular in plan view, and a long side surface 30a1, a short side surface 30a2, a long side surface 30a3, and a short side surface 30a4 that surround the four sides of the front surface 30a in order. Furthermore, the front surface 30a has positioning areas 32a, 32b, 32c, and 32d defined by a horizontal frame 31a and a vertical frame 31b. The positioning areas 32a, 32b, 32c, and 32d are large enough to accommodate the insulating circuit board 11 and may be larger than the arrangement areas 3c1, 3c2, 3c3, and 3c4 of the heat dissipation base 3. The front surface 30a of the positioning jig 30 may have the same shape as the heat dissipation base 3. The front surface 30a of the positioning jig 30 may have a size that allows at least the positioning regions 32a, 32b, 32c, and 32d to be formed. When the positioning jig 30 is set on the front surface 3a of the heat dissipation base 3, the peripheral resist portion 4b of the resist 4 may be located at the lower part of the edge of the positioning regions 32a, 32b, 32c, and 32d of the positioning jig 30. Alternatively, the peripheral resist portion 4b of the resist 4 may protrude inward from the edge portions parallel to the long side surface 30a1, the short side surface 30a2, the long side surface 30a3, and the short side surface 30a4 of the positioning regions 32a, 32b, 32c, and 32d of the positioning jig 30 in a plan view.

[0058] Furthermore, the width (length in the width direction) of the horizontal frame 31a and the vertical frame 31b may be narrower than the distance W of the gap between the arrangement regions 3c1, 3c2, 3c3, and 3c4. When the distance W is 2 mm, the width of the horizontal frame 31a and the vertical frame 31b may be, for example, 1.75 mm. Therefore, in a plan view, the gap resist portion 4a formed on the heat dissipation base 3 can be visually recognized from both sides in the longitudinal direction perpendicular to the width direction of the horizontal frame 31a and the vertical frame 31b.

[0059] Next, a solder plate is set on the front surface 3a of the heat dissipation base 3 (step S3b in FIG. 4). The solder plates are set in the arrangement areas 3c1, 3c2, 3c3, and 3c4 of the heat dissipation base 3 through the positioning areas 32a, 32b, 32c, and 32d of the positioning jig 30 set on the heat dissipation base 3, respectively (see FIG. 10 described later. In FIG. 10, solder plates 17a2 and 17b2 are shown).

[0060] Next, the semiconductor unit 10 is set on the front surface 3a of the heat dissipation base 3 (step S3c in FIG. 4). This step will be described with reference to FIG. 10. FIG. 10 is a cross-sectional view showing a semiconductor unit bonding step (setting of the semiconductor unit) included in the manufacturing method of the semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view corresponding to FIG. 9.

[0061] As shown in Fig. 10, the semiconductor units 10 are set in the arrangement areas 3c1, 3c2, 3c3, and 3c4 of the heat dissipation base 3 via solder plates through the positioning areas 32a, 32b, 32c, and 32d of the positioning jig 30 set on the heat dissipation base 3. Note that solder plates 17a2 and 17b2 are shown in Fig. 10.

[0062] Next, the heat dissipation base 3, the solder plate, and the semiconductor unit 10 are heated (step S3d in FIG. 4). By heating, the solder plate melts and spreads on the front surface 3a of the heat dissipation base 3. At this time, the resist 4 prevents the molten solder from spreading.

[0063] Next, the heat dissipation base 3, the solder, and the semiconductor unit 10 are cooled (step S3e in FIG. 4). This step will be described with reference to FIG. 11. FIG. 11 is a cross-sectional view showing the semiconductor unit bonding step (cooling) included in the manufacturing method of the semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view corresponding to FIG. 10.

[0064] 11, the insulating circuit board 11 of the semiconductor unit 10 is joined to the front surface 3a of the heat dissipation base 3 by a solder layer (solder layers 17a and 17b in FIG. 11). At this time, the semiconductor unit 10 is located on the arrangement areas 3c1, 3c2, 3c3, and 3c4 of the heat dissipation base 3.

[0065] Next, the positioning jig 30 is removed (Step S3f in FIG. 4). The positioning jig 30 is removed from the state shown in FIG. 11. As a result, the semiconductor units 10 are joined to the front surface 3a of the heat dissipation base 3 by the solder layer.

[0066] Next, a case mounting process is performed in which the case 2 is mounted on the heat dissipation base 3 (step S4 in FIG. 5). The case 2 is mounted on the heat dissipation base 3 via an adhesive. At this time, the semiconductor unit 10 is stored in the storage area 22 of the case 2. In addition, the inner end of the external connection terminal 23 is disposed to face the insulating circuit board 11 of the semiconductor unit 10.

[0067] Next, a wiring process is performed to wire the semiconductor unit 10 (step S5 in FIG. 5). The inner end of the external connection terminal 23 of the case 2 is joined to the conductive plate 13b of the insulating circuit board 11. The joining at this time is performed by, for example, ultrasonic joining. Furthermore, if necessary, wiring is performed to the semiconductor unit 10 by wire.

[0068] Next, a sealing process is performed to seal the inside of the storage area 22 of the case 2 with a sealing material (step S6 in FIG. 5). The sealing material is filled into the storage area 22 of the case 2 to seal the semiconductor unit 10, wires, etc. stored in the storage area 22. In this manner, the semiconductor device 1 shown in FIGS. 1 and 2 is obtained.

[0069] Here, a semiconductor device of a reference example will be described. The semiconductor device of the reference example includes the same configuration as the semiconductor device 1. However, in the semiconductor device of the reference example, the gap resist portion 4a of the resist 4 is not in contact with the edge portion 17a1 of the solder layer 17a facing the solder layer 17b and the edge portion 17b1 of the solder layer 17b facing the solder layer 17a, and is formed, for example, in the center of the gap between the solder layers 17a and 17b. A manufacturing method of a semiconductor device including such a gap resist portion 4a will be described with reference to Figs. 4 and 5, and Figs. 12 to 14. Fig. 12 is a cross-sectional view showing a semiconductor unit bonding step (heating) included in the manufacturing method of the semiconductor device of the reference example. Fig. 13 is a cross-sectional view showing a semiconductor unit bonding step (cooling) included in the manufacturing method of the semiconductor device of the reference example. Fig. 14 is a cross-sectional view of a main part showing a semiconductor unit bonding step (removal of a positioning jig) included in the manufacturing method of the semiconductor device of the reference example. Note that Figs. 12 and 13 are cross-sectional views opposite to Fig. 10. 14 shows an enlarged view of the gap between the semiconductor units 10 after removing the positioning jig 30. Here, the semiconductor device is described as viewed in the +Y direction. The same applies when the semiconductor device is viewed in the +X direction.

[0070] The semiconductor device of the reference example can also be manufactured according to the flowcharts of Figures 4 and 5. In the following description, the manufacturing method according to the flowcharts of Figures 4 and 5 may be simplified or omitted.

[0071] First, a preparation step (step S1 in FIG. 4) is performed in the same manner as in the first embodiment. At this time, a heat dissipation base 3 is also prepared (step S1a in FIG. 4), and a resist 4 is formed on the front surface 3a of the heat dissipation base 3 (step S1b in FIG. 4). The gap resist portions 4a of the resist 4 are formed in the center of the gaps between the arrangement regions 3c1, 3c2, 3c3, and 3c4 on the front surface 3a of the heat dissipation base 3 without contacting the opposing solder layer. Also, the width L2 of the gap resist portions 4a is smaller than the distance L1 between the semiconductor units 10 (insulated circuit boards 11), for example, as shown in FIG. 14.

[0072] Next, similarly to the first embodiment, a unit assembly process (step S2 in FIG. 4) and a semiconductor unit bonding process (step S3 in FIG. 4) are performed in order. In the semiconductor unit bonding process, a positioning jig 30 is set on the front surface 3a of the heat dissipation base 3 (step S3a in FIG. 4). Solder plates 17a2 and 17b2 are set in the arrangement areas 3c1, 3c2, 3c3, and 3c4 on the front surface 3a of the heat dissipation base 3 through the positioning areas 32a, 32b, 32c, and 32d of the positioning jig 30 (step S3b in FIG. 4), and the semiconductor units 10 are set on the solder plates 17a2 and 17b2, respectively (step S3c in FIG. 4).

[0073] Next, the heat dissipation base 3, the solder plates 17a2 and 17b2, and the semiconductor unit 10 are heated (step S3d in FIG. 4). By heating, the solder melted from the solder plates 17a2 and 17b2 spreads over the front surface 3a of the heat dissipation base 3. Furthermore, at this time, the heat dissipation base 3 expands mainly outward due to being heated. For example, when viewed in the +Y direction, the heat dissipation base 3 expands in the ±X directions as shown in FIG.

[0074] Next, the heat dissipation base 3, the molten solder, and the semiconductor unit 10 are cooled (step S3e in FIG. 4). As the molten solder cools and hardens, bonding of the semiconductor unit 10 to the heat dissipation base 3 begins. Furthermore, as the heat dissipation base 3 is cooled, it contracts in the ±X directions, as shown in FIG. 13. Because the semiconductor unit 10 is bonded to the heat dissipation base 3, the semiconductor unit 10 also moves toward the center in the ±X directions as the heat dissipation base 3 contracts.

[0075] In recent years, in order to arrange many semiconductor units 10 on the heat dissipation base 3, the semiconductor units 10 are arranged at narrower intervals on the front surface 3a of the heat dissipation base 3. Or, in order to miniaturize the semiconductor device, it is also necessary to narrow the intervals of the semiconductor units 10. In this way, when the intervals of the semiconductor units 10 are narrowed in order to densely mount the semiconductor units 10 (insulating circuit boards 11) on the heat dissipation base 3, the semiconductor units 10 joined to the heat dissipation base 3 move to the center of the heat dissipation base 3 in a plan view as the heat dissipation base 3 shrinks due to cooling. For example, as shown in FIG. 13, adjacent semiconductor units 10 that move to the center in the ±X direction clamp the vertical frame 31b of the positioning jig 30. Although not shown, the horizontal frame 31a of the positioning jig 30 is also clamped by adjacent semiconductor units 10 when viewed in the +X direction.

[0076] If the positioning jig 30 is clamped between the adjacent semiconductor units 10, it becomes difficult to remove the positioning jig 30 in step S3f of Fig. 4. In some cases, the positioning jig 30 may remain clamped between the adjacent semiconductor units 10 and become impossible to remove.

[0077] In addition, an impact is applied to the adjacent semiconductor unit 10 when the vertical frame 31b of the positioning jig 30 is clamped. Then, for example, as shown in Fig. 14, the end of the insulating plate 12 of the insulating circuit board 11 included in the semiconductor unit 10 is damaged and broken.

[0078] In this way, when attempting to mount semiconductor units 10 (semiconductor chips 15a, 15b) at a high density, assembly problems are likely to occur, manufacturing costs increase, and the insulating circuit board 11 may be damaged, degrading the quality of the semiconductor device.

[0079] On the other hand, in the semiconductor device 1 of the first embodiment, the width L2 of the gap resist portion 4a is longer than the distance L1 of the semiconductor unit 10 (insulating circuit board 11). Furthermore, the gap resist portion 4a contacts the opposing edges of adjacent solder layers.

[0080] Here, in the processes of steps S3d and S3e in Fig. 4, the amount of movement of the insulating circuit board 11 joined to the front surface 3a of the heat dissipation base 3 due to the expansion and contraction of the heat dissipation base 3 relative to the width of the gap resist portion 4a will be described with reference to Fig. 15. Fig. 15 is a graph showing the amount of movement of the insulating circuit board relative to the resist width.

[0081] For example, in FIG. 12, the amount of movement of insulating circuit board 11, which is placed on front surface 3a of heat dissipation base 3 via solder plate 17b2, was measured for various widths L2 of gap resist portion 4a when insulating circuit board 11 was joined through heating and cooling.

[0082] The horizontal axis of Fig. 15 indicates the width L2 (mm) of the gap resist portion 4a, which is the resist, and the vertical axis of Fig. 15 indicates the movement amount (mm) of the insulating circuit board 11 relative to the width L2 of the gap resist portion 4a.

[0083] The amount of movement is the distance moved from a preset reference position for the insulating circuit board 11. On the vertical axis of FIG. 15, 0 is the reference position, and α1, α2, α3, α4, and α5 represent numerical values. These numerical values ​​are α1<α2<α3<α4<α5. For example, referring to FIG. 12, the position of the end of the insulating circuit board 11 is taken as 0, which is the reference position. The amount of movement (in the negative direction) indicates how far the insulating circuit board 11 has moved from this reference position in the direction (-X direction) toward the horizontal frame 31a of the positioning jig 30. The amount of movement (in the positive direction) indicates how far the insulating circuit board 11 has moved from this reference position in the direction (+X direction) away from the horizontal frame 31a.

[0084] 15 is the amount of movement that causes insulating circuit board 11 to move in the negative direction and come into contact with positioning jig 30. The amount of movement that causes insulating circuit board 11 to move in the positive direction and exceed the allowable space for disposing insulating circuit board 11. In other words, when the amount of movement in Fig. 15 exceeds the upper limit, insulating circuit board 11 is not mounted at a high density.

[0085] Also, Fig. 15 shows the results of measuring the amount of movement of the insulating circuit board 11 multiple times for each width L2 of the gap resist portion 4a. For this reason, in Fig. 15, there is variation in the amount of movement of the insulating circuit board 11 for each width L2 of the gap resist portion 4a. The squares that include the amount of movement of the insulating circuit board 11 for each width L2 of the gap resist portion 4a are the average of the results of multiple measurements.

[0086] When the above measurements are performed, it can be seen that as the width L2 of the gap resist portion 4a increases, the amount of movement of the insulating circuit board 11 shifts generally in the positive direction, as shown in Fig. 15. This is because the gap resist portion 4a is water repellent to the molten solder, and therefore the gap resist portion 4a impedes the progress of the solder that melts, wets, and spreads. At this time, it is considered that the movement of the insulating circuit board 11 on the solder caused by the contraction of the heat dissipation base 3 is also impeded.

[0087] As the width L2 of the gap resist portion 4a increases, the amount of movement of the insulating circuit board 11 shifts in the positive direction. However, when the width L2 of the gap resist portion 4a is 1 mm or less, the amount of movement of the insulating circuit board 11 may exceed the lower limit. When the width L2 of the gap resist portion 4a is 2 mm or more, the amount of movement of the insulating circuit board 11 does not exceed the lower limit. Therefore, when the width L2 of the gap resist portion 4a is 2 mm or more, the insulating circuit board 11 does not abut against the horizontal frame 31a of the positioning jig 30. On the other hand, when the width L2 of the gap resist portion 4a is 5 mm or more, the amount of movement of the insulating circuit board 11 exceeds the upper limit. When the width L2 of the gap resist portion 4a is 5 mm or more, it is not suitable for mounting the insulating circuit board 11 on the heat dissipation base 3 at a high density.

[0088] From the above, when the width L2 of the gap resist portion 4a is longer than 1 mm and shorter than 5 mm, and preferably 2 mm or more and 4 mm or less, the insulating circuit board 11, which moves in conjunction with the expansion and contraction of the heat dissipation base 3, does not come into contact with the horizontal frame 31a of the positioning jig 30, and the insulating circuit board 11 can be mounted on the heat dissipation base 3 with high density.

[0089] 12, the distance W of the gap between adjacent insulating circuit boards 11 is 1.8 mm or more and 2.2 mm or less, as described above. For this reason, gap resist portion 4a formed in the gap between adjacent insulating circuit boards 11 preferably has width L2 of 2 mm or more and 4 mm or less, and thus contacts edge portion 17a1 of solder layer 17a facing solder layer 17b, and edge portion 17b1 of solder layer 17b facing solder layer 17a.

[0090] The semiconductor device 1 has adjacent insulating circuit boards 11 and a heat dissipation base 3. One insulating circuit board 11 is joined to the front surface 3a of the heat dissipation base 3 via a solder layer 17a, and the other insulating circuit board 11 is joined to the front surface 3a via a solder layer 17b. The adjacent insulating circuit boards 11 face each other with a gap therebetween, and a gap resist portion 4a is formed along the solder layers 17a and 17b in the gap on the front surface 3a. The gap resist portion 4a is in contact with an edge portion 17a1 of the solder layer 17a facing the solder layer 17b, and an edge portion 17b1 of the solder layer 17b facing the solder layer 17a, respectively. By forming such a gap resist portion 4a on the heat dissipation base 3, the joining position of the insulating circuit board 11 can be controlled even if the heat dissipation base 3 expands and contracts due to heating and cooling during the manufacturing process of the semiconductor device 1. Therefore, even if the insulating circuit boards 11 are mounted at high density on the heat dissipation base 3, it is possible to prevent assembly defects from occurring during the manufacturing process of the semiconductor device 1. Therefore, in the semiconductor device 1, high density mounting of the insulating circuit boards 11 is achieved.

[0091] [Second embodiment] In the semiconductor device of the second embodiment, the gap resist portion 4a of the semiconductor device 1 of the first embodiment includes a first resist portion in contact with the edge portion 17a1 of the solder layer 17a and a second resist portion in contact with the edge portion 17b1 of the solder layer 17b and separated from the first resist portion. The semiconductor device of the second embodiment in this case will be described with reference to Figures 16 and 17.

[0092] Fig. 16 is a plan view of a semiconductor device according to a second embodiment. Fig. 17 is a cross-sectional view of a main part of the semiconductor device according to the second embodiment. Fig. 16 is a plan view corresponding to Fig. 1 of the first embodiment. Fig. 17 corresponds to Fig. 3 of the first embodiment and is a cross-sectional view taken along dashed line YY in Fig. 16.

[0093] The semiconductor device 1a of the second embodiment has a similar configuration to the semiconductor device 1 of the first embodiment, except for the resist 4. The resist 4 of the semiconductor device 1a includes a first resist portion 4a1 and a second resist portion 4a2 as well as an outer peripheral resist portion 4b.

[0094] As shown in Figs. 16 and 17, the first resist portion 4a1 is in contact with the edge portion 17a1 of the solder layer 17a and is formed along the edge portion 17a1. The second resist portion 4a2 is in contact with the edge portion 17b1 of the solder layer 17b and is formed along the edge portion 17b1. Furthermore, the second resist portion 4a2 is parallel to the first resist portion 4a1 and is spaced apart from it. Note that Figs. 16 and 17 show the gap between adjacent insulating circuit boards 11 when viewed in the +Y direction. Not limited to this case, the first resist portion 4a1 and the second resist portion 4a2 are also formed in the gap between adjacent insulating circuit boards 11 when viewed in the +X direction, similarly to Figs. 16 and 17.

[0095] The width L2 between the sides of the first resist portion 4a1 and the second resist portion 4a2 that contact the edges 17a1, 17b1 of the solder layers 17a, 17b is the same as the width L2 of the gap resist portion 4a in the first embodiment. Like the gap resist portion 4a, the first resist portion 4a1 and the second resist portion 4a2 can also control the joining position of the insulating circuit board 11 even if the heat dissipation base 3 expands and contracts due to heating and cooling during the manufacturing process of the semiconductor device 1a.

[0096] Therefore, assembly defects during the manufacturing process of the semiconductor device 1a can be prevented even if the insulating circuit boards 11 are mounted at high density on the heat dissipation base 3. Therefore, in the semiconductor device 1a, high density mounting of the insulating circuit boards 11 is achieved. [Explanation of symbols]

[0097] 1,1a Semiconductor device 2 Cases 3 Heat dissipation base 3a Front 3a1,3a3 long side 3a2,3a4 short side 3b Fixing hole 3c1,3c2,3c3,3c4 placement area 4. Resist 4a Gap resist part 4a1 First resist section 4a2 Second resist section 4b Outer peripheral resist part 4c1,4c2,4c3,4c4 Opening area 10 Semiconductor Unit 11 Insulated circuit board 12 Insulating plate 13a,13b Conductive plate 14 Metal plate 15a, 15b Semiconductor chip 17a, 17b, 17c solder layers 17a1,17b1 Edge 17a2,17b2 Solder board 20 Frame 21 Front 22 Storage area 22a Inner wall 22b Step 23 External connection terminal 30 Positioning jig 30a Front 30a1,30a3 long side 30a2,30a4 short side 31a horizontal frame 31b Vertical frame 32a, 32b, 32c, 32d Positioning area

Claims

1. A first substrate and a second substrate; a heat dissipation base having a front surface to which the first substrate is bonded via a first solder layer and the second substrate is bonded via a second solder layer, the first substrate and the second substrate facing each other with a gap therebetween, and a resist formed along the first solder layer and the second solder layer in the gap on the front surface; having the resist is in contact with a first edge portion of the first solder layer facing the second solder layer and a second edge portion of the second solder layer facing the first solder layer, Semiconductor device.

2. the first substrate includes a first insulating plate, a first conductive plate formed on a front surface of the first insulating plate, and a first metal plate formed on a rear surface of the first insulating plate and joined to the front surface of the heat dissipation base via the first solder layer; the second substrate includes a second insulating plate, a second conductive plate formed on a front surface of the second insulating plate, and a second metal plate formed on a rear surface of the second insulating plate and joined to the front surface of the heat dissipation base via the second solder layer. The semiconductor device according to claim 1 .

3. a length of the gap between the first solder layer and the second solder layer is longer than a length between the first insulating plate of the first substrate and the second insulating plate of the second substrate; The semiconductor device according to claim 2 .

4. The resist is mainly composed of a carbon or nickel oxide film. The semiconductor device according to claim 1 .

5. The width of the gap in the resist parallel to the gap direction is longer than 1 mm and shorter than 5 mm. The semiconductor device according to claim 1 .

6. The width of the gap in the resist parallel to the gap direction is 2 mm or more and 4 mm or less. The semiconductor device according to claim 5 .

7. A distance between the first edge of the first solder layer and the second edge of the second solder layer is 1.5 mm or more and 2.5 mm or less. The semiconductor device according to claim 1 .

8. The resist is a first resist portion in contact with the first edge portion of the first solder layer; a second resist portion in contact with the second edge portion of the second solder layer and spaced apart from the first resist portion; Contains The semiconductor device according to claim 1 .

9. The thickness of the resist is smaller than the thicknesses of the first solder layer and the second solder layer. The semiconductor device according to claim 1 .

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