Semiconductor device and semiconductor device manufacturing method

Abstract

To provide a semiconductor device that exhibits sufficient heat dissipation efficiency from a semiconductor package to a cooling portion, has few restrictions on component placement, and is easy to assemble.SOLUTION: A semiconductor device 1 includes a semiconductor package 10 having a plurality of bumps 40 on its bottom surface, a circuit board 20 on which the semiconductor package 10 is mounted, a heat transport material that transports heat generated in the semiconductor package 10, and a cooling portion connected to the heat transport material. Each of the plurality of bumps 40 includes a wiring connection bump 42 electrically connected to the circuit board 20, and a heat dissipation bump 41 connected to the heat transport material. The heat transport material is independent from the circuit board 20.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In recent years, with the demand for miniaturization and cost reduction in electronic devices such as mobile communication terminals, efforts are being made to achieve high density mounting and high integration of mounted components. In particular, a flip chip structure in which a semiconductor package with bottom electrodes is mounted on a circuit board not only saves on the board footprint and efficiently reduces the mounting area, but is also effective in reducing assembly man-hours because the semiconductor package can be mounted in a batch on a surface mounting line. In addition, there is a growing demand for higher performance electronic devices. In recent years, transistors using gallium nitride (GaN) have come to be widely used, and the output is becoming higher. It is desirable for such semiconductor devices to be made up of components that have high heat dissipation and excellent assembly properties. The main approaches to improving heat dissipation are to improve the thermal conductivity of the material itself and to shorten the heat dissipation path (reduce the thermal resistance). For the former, specific examples include using graphite material for the heat spreader or Cu / Mo material for the housing. For the latter, an approach is applied in which the physical distance to the housing, which is the temperature-defined surface, is shortened or a TIM material (thermal interface material) is used to reduce the contact thermal resistance between components. In particular, in semiconductor devices using double-sided mounting boards, it is necessary to dissipate heat to the housing via the circuit board, so if a glass epoxy material with low thermal conductivity is used as the main heat dissipation path, the heat dissipation performance is significantly reduced.

[0003] As an example of a semiconductor device with excellent heat dissipation, Patent Document 1 introduces a structure in which the pitch of bumps provided at the center of the bottom surface of a semiconductor package is narrowed and the bumps are intentionally bridged when the semiconductor package is reflow-mounted on a circuit board, thereby increasing the cross-sectional area of ​​the heat dissipation path. Here, if the bumps are already bridged when they are formed on the semiconductor package, the coplanarity of the bump tips will deteriorate, and there is a concern that not all of the bumps will be able to contact the circuit board when the semiconductor package is mounted on the circuit board, resulting in mounting failure. However, the configuration disclosed in Patent Document 1 has the advantage of ensuring the connection reliability between the bumps and the circuit board without deteriorating the coplanarity. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-235672 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the semiconductor device shown in Patent Document 1, since the heat dissipation path is via the substrate, there is a limit to the reduction of the thermal resistance. A connection structure such as the semiconductor device 1B shown in FIG. 5 can be considered as a measure to reduce the thermal resistance of the circuit board. In the semiconductor device 1B, a structure is used in which heat dissipation vias 21 are arranged in the substrate to improve thermal conduction. However, there is a limit to the number of heat dissipation vias 21 that can be arranged without affecting the circuit configuration. Also, regarding the heat dissipation from the circuit board to the housing, a structure using a TIM material 90 is generally used to reduce the thermal resistance of the contact portion as much as possible. However, since the thermal conductivity of the TIM material is at most several W / (m·K), there is a limit to the reduction of the thermal resistance of the TIM material itself. Furthermore, in such a structure, it is common to provide a temperature-defined surface directly under the surface on which the semiconductor package is mounted, and to provide a cooling structure that actively dissipates heat from the temperature-defined surface. However, the constraints on the arrangement of heat sinks and cooling parts, etc., have been a factor that has hindered high density and miniaturization.

[0006] An object of the present disclosure is to provide a semiconductor device that exhibits sufficient heat dissipation efficiency from a semiconductor package to a cooling section, has few restrictions on component placement, and is easy to assemble. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure includes: a semiconductor package having a plurality of bumps on a bottom surface; a circuit board on which the semiconductor package is mounted; a heat transport material that transports heat generated in the semiconductor package; A cooling portion connected to the heat transport material; A semiconductor device comprising: the plurality of bumps include wiring connection bumps electrically connected to the circuit board and heat dissipation bumps connected to the heat transport material, The heat transport material is independent of the circuit board. Effect of the Invention

[0008] In the semiconductor device according to the present disclosure, the heat dissipation bumps on the bottom surface of the semiconductor package are connected to the heat transport material. Here, the heat transport material is independent of the circuit board. The cooling part is connected to the heat transport material. Therefore, according to the present disclosure, it is possible to provide a semiconductor device that fully exhibits heat dissipation efficiency from the semiconductor package to the cooling part, has few restrictions on component placement, and is easy to assemble. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment. [Diagram 2] 1A and 1B are diagrams showing a manufacturing flow of the semiconductor device 1 according to the first embodiment, in which (a) is a schematic cross-sectional view showing a circuit board 20, (b) is a schematic cross-sectional view showing the circuit board 20 and a graphite block 70, (c) is a schematic cross-sectional view showing how components on the upper surface side are mounted, (d) is a schematic cross-sectional view showing how components on the lower surface side are mounted, and (e) is a schematic cross-sectional view showing how the circuit board 20 is assembled to the housing 30. [Diagram 3] FIG. 11 is a schematic cross-sectional view of a semiconductor device 1A according to a second embodiment. [Figure 4] FIG. 11 is a schematic cross-sectional view of a semiconductor device 1 according to a third embodiment. [Diagram 5] FIG. 1 is a schematic cross-sectional view of a semiconductor device 1B according to a conventional technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the description of the embodiments and the drawings, the same elements and corresponding elements are denoted by the same reference numerals. Descriptions of elements denoted by the same reference numerals will be omitted or simplified as appropriate.

[0011] Embodiment 1 Hereinafter, the present embodiment will be described in detail with reference to the drawings.

[0012] ***Configuration Description*** 1 is an example of a schematic cross-sectional view of a semiconductor device 1 according to embodiment 1. The semiconductor device 1 includes a semiconductor package 10, a circuit board 20, a housing 30, and a temperature regulating surface 100. The semiconductor device 1 also includes a heat transport material. The circuit board 20 and the housing 30 are fastened together by screws 60. The housing 30 corresponds to a heat dissipation section. The screws 60 are male threads and correspond to fastening members. A specific example of the heat transport material is a material that has a thermal conductivity equal to or greater than that of copper (approximately 398 [W / (m·K)]), that can be soldered, and that has good workability so that the heat dissipation path can be freely changed. A specific example of the heat transport material is a graphite block 70 or a copper-based block.

[0013] The semiconductor package 10 has a semiconductor chip. Although the internal structure of the semiconductor package 10 is not shown, in the semiconductor package 10, the semiconductor chip is mounted on a daughter board in a face-up or face-down structure. The semiconductor chip is connected to the daughter board via bottom electrodes such as wire bonding or solder bumps. Furthermore, in the internal structure, the semiconductor chip is protected physically and electrically by using a resin mold or a metal cover to prevent the semiconductor chip from being exposed. The semiconductor device 1 has a structure in which the semiconductor chip is mounted on a circuit board 20 as the semiconductor package 10. The circuit board 20 is equipped with the semiconductor package 10. The circuit board 20 is the electrical connection destination of the semiconductor package 10. When the semiconductor chip is a GaN transistor, Si, SiC, gallium arsenide (GaAs), or the like is used as the material of the semiconductor chip. The material of the circuit board 20 can be various examples such as a single-layer or multi-layer ceramic board, a resin board, etc. However, the material of the circuit board 20 is not limited to any of these. The circuit board 20 has a mounting surface on which the semiconductor package 10 is mounted and a non-mounting surface that faces the mounting surface. The circuit board 20 has a through hole that penetrates between the mounting surface and the non-mounting surface. The through hole corresponds to an opening of the circuit board 20. Note that the semiconductor package 10 may also be mounted on the non-mounting surface.

[0014] The semiconductor package 10 has a plurality of bumps 40 on its bottom surface. The semiconductor package 10 and the circuit board 20 are connected via the bumps 40. A lead-free solder having a SnAgCu composition is generally used as the material for the bumps 40. However, the composition of the solder material is not limited to this. Furthermore, the semiconductor package 10 and the circuit board 20 do not necessarily need to be soldered together. The connection structure between the semiconductor package 10 and the circuit board 20 may be a connection structure that utilizes ultrasonic solid-state diffusion bonding using Au bumps. The bumps 40 are also called solder bumps. In order to improve the connectivity with the semiconductor package 10 regardless of the material of the bumps 40, it is desirable to plate the surface of the semiconductor package 10. The plating is mainly performed on the pad connection surface on the semiconductor package 10 side. The plating may be performed on the surface of the circuit board 20 in the portion to be soldered. The type of plating is not particularly limited, but a specific example is electroless Ni / Au plating. In this example, the plating thickness is preferably about 1 to 6 μm for Ni and about 0.3 to 2 μm for Au.

[0015] The bumps 40 are classified into heat dissipation bumps 41 and wiring connection bumps 42 according to their functions. That is, the plurality of bumps 40 include both the wiring connection bumps 42 and the heat dissipation bumps 41. The heat dissipation bumps 41 do not transmit or receive electrical signals, but are used as ground electrodes. The heat dissipation bumps 41 are connected to a heat transport material. The purpose of the heat dissipation bumps 41 is to directly thermally connect to the graphite block 70. The wiring connection bumps 42 are arranged mainly on the outer periphery of the semiconductor package 10 and are electrically connected to the circuit board 20 .

[0016] The graphite block 70 corresponds to a heat transport material. The heat transport material is independent of the circuit board 20, and transports heat generated in the semiconductor package 10. The graphite block 70 includes a semiconductor connection portion disposed so as to pass through the through hole, and a heat dissipation portion provided along the non-mounting surface. The surface of the graphite block 70 may be metal-plated. The heat dissipation portion is connected to a cooling portion. The shape of the graphite block 70 is not a simple flat plate, but has a convex shape at the portion that connects with the heat dissipation bump 41. In the example shown in FIG. 1, the convex shape protrudes from the non-mounting surface toward the mounting surface. The convex shape corresponds to the semiconductor connection portion. The purpose of this shape is to align the mounting surface height between the circuit board 20 and the graphite block 70 when the convex shape of the graphite block 70 is inserted into the through hole. This convex shape has the advantage of making it easier to mount the semiconductor package 10. The portion of the graphite block 70 other than the convex shape corresponds to the heat dissipation portion. In addition, in order to improve the mechanical strength of the graphite block 70, it is desirable to fix the graphite block 70 using the circuit board 20 and the fixing material 80. In the example shown in FIG. 1, the heat dissipation part is fixed to the non-mounting surface by the fixing material 80. Furthermore, the circuit board 20 and the graphite block 70 are configured to be mounted on the housing 30 via members such as the screws 60 and the grease 50. Therefore, the heat dissipation path of the semiconductor package is mainly a path from the heat dissipation bumps 41 to the housing 30 via the graphite block 70 and the grease 50. In the example shown in FIG. 1, the cooling part is a cooling surface. The cooling surface is a part of the housing 30, a part of the housing 30 to which the graphite block 70 is directly or indirectly connected, and a surface perpendicular to the circuit board 20. Each crystal plane constituting the graphite block 70 is a surface perpendicular to the cooling surface. The housing 30 is the attachment destination of the circuit board 20. The graphite block 70 is formed by laminating a plurality of graphene crystal planes. In the graphite block 70, the thermal conductivity differs between a plane parallel to the crystal plane and a plane crossing the crystal plane. In this embodiment, the graphite block 70 is arranged so that each crystal plane of the graphene, i.e., a plane with high thermal conductivity, is along the XY plane shown in FIG. 1. That is, each crystal plane constituting the graphite block 70 is a plane perpendicular to the bottom surface of the semiconductor package 10 and is a plane along a direction from the semiconductor connection portion toward the cooling surface. In addition, since the strength between the graphene crystal layers in the graphite block 70 is weak, there is a concern that friction during assembly may cause some of the crystal layers to break and generate carbon dust. Therefore, it is preferable to apply electrolytic copper plating or electrolytic Ni plating to the surface of the graphite block 70. Furthermore, in order to improve the connectivity between the graphite block 70 and the bumps 40, it is preferable to apply Au plating to the outermost surface of the graphite block 70.

[0017] In the first embodiment, a schematic diagram of the semiconductor package 10 mounted in a BGA (Ball Grid Array) has been introduced. However, as a specific example, a QFP (Quad Flat Package) mounting structure or a semiconductor package built into a metal case may be used as long as there is no electrical problem even if the entire bottom surface of the semiconductor package is installed.

[0018] ***Production Method Description*** 2 shows an example of a manufacturing flow of the semiconductor device 1 according to the embodiment 1. The manufacturing flow of the semiconductor device 1 corresponds to a semiconductor device manufacturing method.

[0019] First, as shown in (a) and (b), the circuit board 20 and the graphite block 70 are assembled. When fixing the graphite block 70, the mechanical strength can be improved by using a fixing material 80. Specific examples of the fixing material 80 include an epoxy-based or silicone-based adhesive, or a solder material having a higher melting point than lead-free solder for surface mounting.

[0020] Next, as shown in (c), the components on the upper side of the schematic diagram are mounted. At this time, the components may be mounted using the same procedure as general surface mounting. As a specific example, cream solder is supplied to the circuit board 20 and the electrode pads of the graphite block 70 by printing, and then the semiconductor package 10 and other components are mounted on the upper side using a general-purpose mounter. Thereafter, the assembly is placed in a reflow furnace to melt the solder and bond each component to the circuit board 20 and the graphite block 70. When mounting components on the opposite side of the semiconductor package 10, as shown in (d), cream solder is similarly supplied to the opposite side, the components are mounted, and then joined by reflow. If the size of the semiconductor package 10 is extremely large compared to other chip components, mounting the components on the opposite side first can prevent the previously mounted components from falling off during the secondary mounting reflow.

[0021] Once soldering is complete on both sides, as shown in (e), the device is attached to the housing 30 using screws 60. Since there is concern that poor contact between the housing 30 and the graphite block 70 may increase thermal resistance, it is preferable to apply grease 50 between the two to fill the gap from the standpoint of heat dissipation.

[0022] ***Explanation of the Effects of the First Embodiment*** As described above, according to this embodiment, by mounting heat dissipation bumps 41 provided on semiconductor package 10 directly on graphite block 70, it is possible to dissipate heat generated in semiconductor package 10 without passing through circuit board 20. Therefore, according to this embodiment, it is possible to significantly reduce the thermal resistance of semiconductor device 1 as a whole, compared to the conventional technology. Furthermore, according to this embodiment, by adopting a structure that takes orientation into consideration, such as making the shape of graphite block 70 L-shaped, it is possible to freely arrange the heat dissipation path from semiconductor package 10 to the cooling section.

[0023] Embodiment 2 The following mainly describes the differences from the above-described embodiment with reference to the drawings.

[0024] ***Configuration Description*** FIG. 3 is an example of a schematic cross-sectional view of a semiconductor device 1A according to the second embodiment. The cooling portion according to this embodiment is a wiring pattern provided on the circuit board 20 for transporting heat. The heat transport material according to this embodiment is provided so as to connect the heat dissipation bumps 41 and the cooling portion. In this embodiment, the non-mounting surface is the mounting surface of the circuit board 20. In the heat dissipation portion according to the present embodiment, each crystal plane constituting the graphite block 70 is a plane perpendicular to the circuit board 20.

[0025] The object thermally connected to the graphite block 70 does not necessarily have to be the housing 30, but may be the copper pattern 22 on the circuit board 20. The copper pattern 22 corresponds to a wiring pattern for transporting heat. As a specific example, as shown in Fig. 3, if heat can be transported to the copper pattern 22 located near the screw 60 fastening the housing 30 and the circuit board 20, the thermal resistance of the circuit board 20 at the copper pattern 22 is considered to be sufficiently small in terms of physical dimensions.

[0026] ***Explanation of the effect of the second embodiment*** In the first embodiment, it was necessary to mount graphite block 70 on the side of housing 30 equipped with a cooling unit. On the other hand, in the second embodiment, graphite block 70 is mounted on the side opposite housing 30. The configuration of the second embodiment reduces restrictions on component placement, and is expected to improve the degree of freedom in designing semiconductor devices.

[0027] Embodiment 3 The following mainly describes the differences from the above-described embodiment with reference to the drawings.

[0028] ***Configuration Description*** FIG. 4 is an example of a schematic cross-sectional view of the semiconductor device 1 according to the third embodiment. The semiconductor connection portion according to this embodiment is provided with a tapered shape that narrows from the non-mounting surface side toward the mounting surface side toward the semiconductor package 10. In this embodiment, a clearance exists between the semiconductor connection portion and the through hole, and the clearance gradually widens from the non-mounting surface side to the mounting surface side.

[0029] The side of the convex shape of the graphite block 70 does not necessarily have to be perpendicular to the circuit board 20 when the convex shape is disposed so as to penetrate the through hole. As a specific example, the convex shape may be a tapered shape with a difference in size between the top and bottom surfaces. Since the through hole of the circuit board 20 is generally drilled, it is possible that burrs are generated on the side of the through hole, which may cause an obstacle to the insertion of the graphite block 70. In addition, if the graphite block 70 can be inserted perpendicularly to the circuit board 20, there is no problem even if the side of the convex shape is perpendicular to the circuit board 20. However, when the circuit board 20 is thick, in particular, when the convex shape is inserted into the through hole at an angle to the circuit board 20, there is a concern that the graphite block 70 and the through hole may interfere with each other. Here, if the graphite block 70 is made small to prevent such interference, it will affect the heat dissipation. Therefore, the dimensions of graphite block 70 on the semiconductor package 10 side are designed to be smaller in consideration of ease of assembly, and the dimensions on the housing 30 side are designed to be as large as possible in consideration of the spread of heat, thereby achieving both ease of assembly and heat dissipation.

[0030] ***Explanation of the Effects of the Third Embodiment*** As described above, according to this embodiment, by providing a tapered shape to the convex shape of graphite block 70, both ease of assembly and heat dissipation are achieved.

[0031] ***Other embodiments*** The above-described embodiments may be freely combined, or any of the components in each embodiment may be modified, or any of the components in each embodiment may be omitted. Moreover, the embodiments are not limited to those shown in the first to third embodiments, and various modifications are possible as necessary. The procedures described may be modified as appropriate.

[0032] Various aspects of the present disclosure are summarized below as appendices.

[0033] (Appendix 1) a semiconductor package having a plurality of bumps on a bottom surface; a circuit board on which the semiconductor package is mounted; a heat transport material that transports heat generated in the semiconductor package; A cooling portion connected to the heat transport material; A semiconductor device comprising: the plurality of bumps include wiring connection bumps electrically connected to the circuit board and heat dissipation bumps connected to the heat transport material, The heat transport material is independent of the circuit board.

[0034] (Appendix 2) the cooling portion is a wiring pattern for heat transport provided on the circuit board, 2. The semiconductor device according to claim 1, wherein the heat transport material is provided so as to connect the heat dissipation bump and a cooling portion.

[0035] (Appendix 3) the heat transport material is a graphite block formed by stacking a plurality of graphene crystal planes; 3. The semiconductor device according to claim 1, wherein each crystal plane constituting the graphite block is perpendicular to a bottom surface of the semiconductor package.

[0036] (Appendix 4) the circuit board is provided with a through hole passing through a mounting surface on which the semiconductor package is mounted and a non-mounting surface opposite to the mounting surface; the graphite block includes a semiconductor connection portion disposed to pass through the through hole and a heat dissipation portion provided along the non-mounting surface, 4. The semiconductor device according to claim 3, wherein the heat dissipation portion is connected to the cooling portion.

[0037] (Appendix 5) the cooling portion is a cooling surface that is a part of a housing of the semiconductor device, the cooling surface is a surface perpendicular to the circuit board, 5. The semiconductor device according to claim 4, wherein each crystal plane constituting the graphite block is a plane perpendicular to the cooling surface.

[0038] (Appendix 6) 6. The semiconductor device according to claim 4, wherein the non-mounting surface is a mounting surface of the circuit board.

[0039] (Appendix 7) the semiconductor connection portion is provided with a tapered shape whose width narrows from the non-mounting surface side toward the mounting surface side toward the semiconductor package, 7. The semiconductor device according to claim 4, wherein a clearance exists between the semiconductor connection portion and the through hole.

[0040] (Appendix 8) 8. The semiconductor device according to claim 4, wherein the heat dissipation portion is fixed to the non-mounting surface by a fixing material.

[0041] (Appendix 9) 9. The semiconductor device according to claim 3, wherein a surface of the graphite block is metal-plated. [Explanation of symbols]

[0042] 1, 1A, 1B semiconductor device, 10 semiconductor package, 20 circuit board, 21 heat dissipation VIA, 22 copper pattern, 30 housing, 40 bump, 41 heat dissipation bump, 42 wiring connection bump, 50 grease, 60 screw, 70 graphite block, 80 fixing material, 90 TIM material, 100 temperature regulation surface.

Claims

1. a semiconductor package having a plurality of bumps on a bottom surface; a circuit board on which the semiconductor package is mounted; a heat transport material that transports heat generated in the semiconductor package; A cooling portion connected to the heat transport material; A semiconductor device comprising: the plurality of bumps include wiring connection bumps electrically connected to the circuit board and heat dissipation bumps connected to the heat transport material, The heat transport material is independent of the circuit board.

2. the cooling portion is a wiring pattern for heat transport provided on the circuit board, 2. The semiconductor device according to claim 1, wherein the heat transport material is provided so as to connect the heat dissipation bump and a cooling portion.

3. the heat transport material is a graphite block formed by stacking a plurality of graphene crystal planes; 3. The semiconductor device according to claim 1, wherein each crystal plane constituting the graphite block is perpendicular to a bottom surface of the semiconductor package.

4. the circuit board is provided with a through hole passing through a mounting surface on which the semiconductor package is mounted and a non-mounting surface opposite to the mounting surface; the graphite block includes a semiconductor connection portion disposed to pass through the through hole and a heat dissipation portion provided along the non-mounting surface, The semiconductor device according to claim 3 , wherein the heat dissipation portion is connected to the cooling portion.

5. the cooling portion is a cooling surface that is a part of a housing of the semiconductor device, the cooling surface is a surface perpendicular to the circuit board, 5. The semiconductor device according to claim 4, wherein each crystal plane constituting said graphite block is perpendicular to said cooling surface.

6. The semiconductor device according to claim 4 , wherein the non-mounting surface is a mounting surface of the circuit board.

7. the semiconductor connection portion is provided with a tapered shape that narrows from the non-mounting surface side toward the mounting surface side toward the semiconductor package, 5. The semiconductor device according to claim 4, wherein a clearance exists between the semiconductor connection portion and the through hole.

8. The semiconductor device according to claim 4 , wherein the heat dissipation portion is fixed to the non-mounting surface by a fixing material.

9. 4. The semiconductor device according to claim 3, wherein the surface of said graphite block is plated with a metal.

10. A method for manufacturing the semiconductor device according to claim 1 or 2.

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