Semiconductor device

Abstract

To miniaturize a semiconductor device.SOLUTION: A semiconductor device includes an interposer substrate including a plurality of wiring layers therein, a first semiconductor chip disposed on the interposer substrate, and a power supply circuit that transforms an externally supplied voltage and supplies the voltage to the first semiconductor chip. The power supply circuit has an inductor and a capacitor, each of which is constituted by a plurality of coil patterns formed on at least two wiring layers of the interposer substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices incorporating semiconductor memory chips and semiconductor controller chips are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-142084 A Summary of the Invention [Problem to be solved by the invention]

[0004] The disclosed embodiments facilitate miniaturization of semiconductor devices. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes an interposer substrate including a plurality of wiring layers therein, a first semiconductor chip disposed on the interposer substrate, and a power supply circuit that transforms an externally supplied voltage and supplies the transformed voltage to the first semiconductor chip. The power supply circuit includes an inductor and a capacitor, the inductor being configured by a plurality of coil patterns formed on at least two wiring layers of the interposer substrate. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a front view showing a front structure of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view showing a planar structure of a semiconductor device according to a first embodiment; [Diagram 3] 3 is a cross-sectional view showing a cross-sectional structure taken along line III-III in FIG. 2. [Figure 4]FIG. 1 is a circuit diagram showing a configuration of a power supply circuit according to a first embodiment. [Diagram 5] 3A to 3D are diagrams illustrating the planar structure of each of a plurality of coil patterns of the inductor of the first embodiment. [Figure 6] FIG. 2 is a perspective view illustrating a schematic perspective structure of the inductor according to the first embodiment. [Figure 7] 6A to 6D are diagrams illustrating the planar structure of each of a plurality of coil patterns of an inductor according to a modified example of the first embodiment. [Figure 8] FIG. 13 is a front view showing the front structure of a semiconductor device according to a second embodiment. [Figure 9] FIG. 11 is a circuit diagram showing the configuration of a power supply circuit according to a third embodiment. [Figure 10] FIG. 13 is a front view showing the front structure of the semiconductor device according to the third embodiment. [Figure 11] FIG. 13 is a plan view showing a planar structure of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In order to facilitate understanding of the description, the same components in the drawings are denoted by the same reference numerals as much as possible, and duplicated description will be omitted. 1. First embodiment A semiconductor device according to a first embodiment will be described. The semiconductor device according to this embodiment is a semiconductor package including a NAND flash memory chip. The semiconductor device according to this embodiment is, for example, a Universal Flash Storage (UFS) device mounted on a smartphone.

[0008] 1.1 Structure of semiconductor device 1 is a front view showing the front structure of a semiconductor device 1 according to the present embodiment. As shown in FIG.

[0009] The substrate 3 is, for example, a printed circuit board (PCB). The semiconductor device 1 can be mounted on a surface 30 of the substrate 3. Hereinafter, a direction perpendicular to the surface 30 of the substrate 3 will be referred to as a Z direction. Also, axial directions perpendicular to the Z direction and perpendicular to each other will be referred to as an X direction and a Y direction. The Z direction is an example of a first direction.

[0010] The semiconductor device 1 includes an interposer substrate 50, a controller chip 51, a plurality of memory chips 52, a spacer 53, and a sealing material 54. The semiconductor device 1 is a so-called semiconductor package in which the controller chip 51 and the plurality of memory chips 52 are integrally sealed with the sealing material 54. Note that Fig. 1 shows a cutaway cross-sectional structure in which a portion of the sealing material 54 is cut away, but hatching showing a cross section of the sealing material 54 is omitted. Hatching showing a cross section of the sealing material 54 is also omitted in other figures.

[0011] The interposer substrate 50 is disposed between the substrate 3 and the controller chip 51. The interposer substrate 50 has a multi-layer structure 500 and a plurality of external terminals 501. The interposer substrate 50 is used to establish electrical continuity between the substrate 3, the controller chip 51, and the memory chip 52.

[0012] The multi-layer structure 500 includes a plurality of insulating layers, a plurality of wiring layers, and vias. The multi-layer structure 500 has a structure in which insulating layers and wiring layers are alternately stacked in the Z direction. The multi-layer structure 500 of this embodiment has four wiring layers. The wiring layers are electrically connected through vias so as to penetrate one or more insulating layers in the Z direction. The insulating layers are made of an insulating material such as glass-containing resin. The wiring layers and vias are made of a conductive material such as Cu.

[0013] The multi-layer structure 500 has a bottom surface 500a. The bottom surface 500a faces the substrate 3. A plurality of external terminals 501 are provided on the bottom surface 500a. The plurality of external terminals 501 are electrically connected to at least one of a plurality of wiring layers formed inside the multi-layer structure 500 via electrodes formed on the bottom surface 500a. The external terminals 501 are protruding terminals formed by solder balls, solder plating, or the like. The bottoms of the respective plurality of external terminals 501 are in contact with electrodes provided on the substrate 3. This electrically connects the circuit inside the substrate 3 and the wiring layers inside the multi-layer structure 500.

[0014] The multi-layer structure 500 has an upper surface 500b. The upper surface 500b faces the controller chip 51. The upper surface 500b is in contact with a plurality of external terminals 510 formed on the controller chip 51. The upper surface 500b is provided with a plurality of electrodes with which the plurality of external terminals 510 of the controller chip 51 respectively come into contact. The controller chip 51 is electrically connected to a circuit inside the substrate 3 via the external terminals 510, the electrodes formed on the upper surface 500b, a wiring layer formed inside the multi-layer structure 500, the electrodes formed on the bottom surface 500a, the external terminals 501, and electrodes provided on the substrate 3.

[0015] In the following, the bottom surface 500a of the multilayer structure 500 is also referred to as the "bottom surface 500a of the interposer substrate 50," and the top surface 500b of the multilayer structure 500 is also referred to as the "top surface 500b of the interposer substrate 50." In this embodiment, the top surface 500b of the interposer substrate 50 corresponds to the main surface of the interposer substrate 50.

[0016] The controller chip 51 includes a plurality of external terminals 510. The controller chip 51 is, for example, a system on a chip (SoC) or an application specific integrated circuit (ASIC). Note that the controller chip 51 may be another integrated circuit (IC) or circuit. The controller chip 51 is an example of a first semiconductor chip.

[0017] The multiple memory chips 52 are arranged so as to be stacked above the controller chip 51. The memory chips 52 are arranged at a distance from the upper surface 500b of the interposer substrate 50 in the Z direction. Note that the arrangement of the controller chip 51 and the memory chips 52 is just an example, and the arrangements thereof can be changed as desired.

[0018] Fig. 2 is a plan view showing the planar structure of the semiconductor device 1. Fig. 3 is a cross-sectional view showing the cross-sectional structure taken along line III-III in Fig. 2.

[0019] 2 and 3, the semiconductor device 1 further includes bonding wires 55 that connect the multiple memory chips 52 to the interposer substrate 50. The multiple memory chips 52 are electrically connected to the controller chip 51 via the bonding wires 55, an internal wiring layer of the interposer substrate 50, and external terminals 510.

[0020] 1 and 3, the spacer 53 is disposed between a lowermost memory chip 52a, which is disposed at a position among the multiple memory chips 52 closest to the interposer substrate 50, and an upper surface 500b of the interposer substrate 50. The upper surface 500b of the interposer substrate 50 is bonded to a bottom surface 530 of the spacer 53 in the Z direction via an adhesive layer. The bottom surface of the lowermost memory chip 52a is bonded to an upper surface 531 of the spacer 53 in the Z direction via an adhesive layer.

[0021] The sealing material 54 is made of synthetic resin, etc. The sealing material 54 seals the controller chip 51, the multiple memory chips 52, the multiple bonding wires 55, and the spacer 53.

[0022] 1.2 Power supply circuit configuration The semiconductor device 1 of this embodiment further includes a power supply circuit 9 shown in Fig. 4. Fig. 4 is a circuit diagram showing the configuration of the power supply circuit 9 according to this embodiment. The power supply circuit 9 adjusts a voltage supplied from the outside and supplies the adjusted voltage to the controller chip 51. The power supply circuit 9 transforms (e.g., steps down) the voltage supplied from the outside. The power supply circuit 9 is a DC / DC converter. The stepped-down voltage is supplied to low-voltage systems such as the logic power supply and I / O power supply of the controller chip 51. For example, when the voltage supplied from the outside is 2.5V, the power supply circuit 9 steps down the voltage to, for example, 1.2V.

[0023] Next, a specific configuration of the power supply circuit 9 will be described. As shown in FIG 4, the power supply circuit 9 has an inductor 80, a capacitor 81, and a power device 82.

[0024] The power device 82 is built into the controller chip 51. The power device 82 has a control circuit 820 and two switching elements 821 and 822.

[0025] The two switching elements 821 and 822 are, for example, N-channel MOS transistors. The source terminal of the switching element 821 and the drain terminal of the switching element 822 are connected to each other. Therefore, the two switching elements 821 and 822 are electrically connected in series. An externally supplied voltage Vcc is applied to the drain terminal of the switching element 821. The external voltage Vcc is supplied to the controller chip 51 from the substrate 3 shown in FIG. 1 via the external terminal 501, the wiring layer of the interposer substrate 50, and the external terminal 510. A ground voltage Vss is supplied to the source terminal of the switching element 822.

[0026] 1 and 3, the inductor 80 is composed of a plurality of coil patterns 801-804 formed on the interposer substrate 50. The coil patterns 801-804 are formed on each of the four wiring layers of the interposer substrate 50. The coil patterns 801-804 are formed of a conductive material such as Cu.

[0027] 5(A) to (D) are plan views showing the planar structures of the coil patterns 801 to 804. As shown in FIG. 5(A), the coil pattern 801 is formed so as to extend in a rectangular shape curved about an axis m10. The axis m10 is an axis parallel to the Z direction. A first end 801a of the coil pattern 801 is connected to an intermediate portion 825 of the switching elements 821 and 822 as shown in FIG. 4 via the wiring layer of the interposer substrate 50. As shown in FIG. 5(A), a second end 801b of the coil pattern 801 is formed so as to protrude inward (Y direction).

[0028] As shown in FIG. 5B, the coil pattern 802 is formed to extend in a rectangular shape around the axis m10, similar to the coil pattern 801. A first end 802a and a second end 802b of the coil pattern 802 are formed to protrude inward. The first end 802a of the coil pattern 802 is disposed at a position overlapping the second end 801b of the coil pattern 801 shown in FIG. 5A in the Z direction. The first end 802a of the coil pattern 802 is connected to the second end 801b of the coil pattern 801 via a through hole 205 formed in the interposer substrate 50 to extend in the Z direction. The second end 802b of the coil pattern 802 is disposed to be shifted in the X direction with respect to the first end 802a.

[0029] As shown in FIG. 5(C), the coil pattern 803 is also formed to extend in a rectangular shape around the axis m10, similar to the coil pattern 801. A first end 803a and a second end 803b of the coil pattern 803 are formed to protrude inward. The first end 803a of the coil pattern 803 is disposed at a position overlapping the second end 802b of the coil pattern 802 shown in FIG. 5(B) in the Z direction. The first end 803a of the coil pattern 803 is connected to the second end 802b of the coil pattern 802 via a through hole 206 formed in the interposer substrate 50 to extend in the Z direction. The second end 803b of the coil pattern 803 is disposed to be shifted in the X direction with respect to the first end 803a.

[0030] As shown in FIG. 5(D), the coil pattern 804 is also formed to extend in a rectangular shape around the axis m10, similar to the coil pattern 801. The first end 804a of the coil pattern 804 is formed to protrude inward. The first end 804a of the coil pattern 804 is disposed at a position overlapping the second end 803b of the coil pattern 803 shown in FIG. 5(C) in the Z direction. The first end 804a of the coil pattern 804 is electrically connected to the second end 803b of the coil pattern 803 via a through hole 207 formed in the interposer substrate 50 to extend in the Z direction. The second end 804b of the coil pattern 804 is electrically connected to the controller chip 51 and the capacitor 81 as shown in FIG. 4 via the wiring layer of the interposer substrate 50.

[0031] Fig. 6 is a perspective view that typically illustrates the perspective structure of the coil patterns 801 to 804. As illustrated in Fig. 6, the portions of the coil patterns 801 to 804 other than the first ends 801a to 804a and the second ends 801b to 804b are formed to overlap when viewed from the Z direction. Therefore, the coil patterns 801 to 804 have approximately the same pattern shape.

[0032] When the switching element 821 shown in Fig. 3 is turned on, a voltage Vcc is applied to the first end 801a of the coil pattern 801. As a result, the current flowing through each of the coil patterns 801 to 804 increases as shown by the arrow I in Fig. 5 and Fig. 6. Specifically, the current flows from the first end 801a to the second end 801b of the coil pattern 801, through hole 205, from the first end 802a to the second end 802b of the coil pattern 802, through hole 206, from the first end 803a to the second end 803b of the coil pattern 803, through hole 207, and from the first end 804a to the second end 804b of the coil pattern 804 in this order.

[0033] 1, the coil patterns 801-804 are formed on the interposer substrate 50 below the spacer 53. As shown in Fig. 2, the coil patterns 801-804 are arranged at positions different from (i.e., not overlapping with) the wiring areas A11, A12 of the interposer substrate 50 when viewed from the Z direction. The wiring areas A11, A12 are regions in which, for example, the following (a1)-(a3) are arranged.

[0034] (a1) A portion of the wiring layer of the interposer substrate 50 that functions as wiring for electrically connecting the external terminals 501 on the bottom surface 500 a of the interposer substrate 50 and the controller chip 51 . (a2) A portion of the wiring layer of the interposer substrate 50 that functions as wiring for electrically connecting the controller chip 51 and the memory chip 52. (a3) A portion where bonding wires 55 that connect the interposer substrate 50 and the memory chip 52 are arranged.

[0035] In this way, by arranging the coil patterns 801 to 804 in positions different from the wiring areas A11 and A12 of the interposer substrate 50, interference between the coil patterns 801 to 804 and various wirings can be easily avoided.

[0036] 1 and 2 is provided on the interposer substrate 50. As shown in Fig. 2, the capacitor 81 may also be disposed at a position different from the wiring areas A11, A12 of the interposer substrate 50 when viewed from the Z direction. Since the capacitor 81 has a predetermined height in the Z direction, it is disposed so as not to interfere with the memory chip 52 and the bonding wires 55. The capacitor 81 is disposed so as to be aligned with the inductor 80 in the Y direction.

[0037] 4, the output voltage of the inductor 80 is applied to the control circuit 820 via the wiring layer of the interposer substrate 50. The control circuit 820 controls the gate voltages of the switching elements 821 and 822 to turn on / off the switching elements 821 and 822, thereby stepping down the external voltage Vcc and supplying it to the controller chip 51. At that time, the control circuit 820 controls the voltage supplied to the controller chip 51 to be a predetermined voltage (for example, 1.2 V), for example.

[0038] 1.3 Functions and Effects of the Semiconductor Device of the Present Embodiment As described above, the semiconductor device 1 of this embodiment includes the interposer substrate 50, the controller chip 51, and the power supply circuit 9. The interposer substrate 50 includes a plurality of wiring layers therein. The controller chip 51 is disposed on the interposer substrate 50. The power supply circuit 9 transforms an external voltage Vcc and supplies it to the controller chip 51. The power supply circuit 9 includes an inductor 80 and a capacitor 81. The inductor 80 is configured by a plurality of coil patterns 801-804 formed on the plurality of wiring layers of the interposer substrate 50, respectively.

[0039] According to this configuration, the inductor 80 can be placed inside the interposer substrate 50, thereby making it possible to reduce the size of the semiconductor device 1 compared to a case in which a component corresponding to the inductor 80 is placed, for example, on the upper surface 500b of the interposer substrate 50.

[0040] Four wiring layers are formed on the interposer substrate 50. Coil patterns 801 to 804 are formed on all of the four wiring layers. As shown in Fig. 6, the coil patterns 801 to 804 are disposed at positions overlapping each other when viewed from the Z direction.

[0041] According to this configuration, high magnetic coupling can be achieved by each of the coil patterns 801 to 804. Therefore, high inductance can be obtained even in a small area.

[0042] The inductance is proportional to the square of the number of turns of the coil pattern included in inductor 80. Considering the inductance required of inductor 80 in power supply circuit 9, it is beneficial to form four or more wiring layers on interposer substrate 50 and form four or more coil patterns (i.e., the number of turns is four or more).

[0043] The controller chip 51 incorporates switching elements 821 and 822 of the power supply circuit 9, and a control circuit 820 that controls the switching elements 821 and 822.

[0044] According to this configuration, compared to a case in which the switching elements 821 and 822 and the control circuit 820 are provided separately from the controller chip 51, the structure of the semiconductor device 1 can be simplified.

[0045] As shown in FIG. 3, the multiple coil patterns 801 to 804 are arranged at positions that overlap the memory chip 52 and the spacer 53, but do not overlap the controller chip 51, when viewed from the Z direction.

[0046] According to this configuration, it is possible to avoid interference between the wiring of the controller chip 51 formed in the interposer substrate 50 and the coil patterns 801 to 804.

[0047] As shown in FIG. 6, current flows through the coil patterns 801 to 804 in the same rotational direction about a predetermined axis m10.

[0048] According to this configuration, when a current flows through each of the coil patterns 801 to 804, the direction of the magnetic flux formed by each of the coil patterns 801 to 804 is the same, so that high magnetic coupling can be formed by each of the coil patterns 801 to 804. Therefore, high inductance can be realized.

[0049] 1.4 Variations Next, a modification of the semiconductor device 1 of the first embodiment will be described.

[0050] 7(A) to 7(D) are plan views showing the planar structures of coil patterns 801 to 804 according to the modified example. As shown in FIG. 7(A) to 7(D), the coil patterns 801 to 804 according to the modified example are formed in a spiral shape centered on the axis m10. More specifically, the coil patterns 801 and 803 are formed so as to spiral counterclockwise around the axis m10. The coil patterns 802 and 804 are formed so as to spiral clockwise around the axis m10. In the following description, the ends of the coil patterns 801 to 804 located on the outer periphery are referred to as outer ends 801c, 802c, 803c, and 804c. Also, the ends of the coil patterns 801 to 804 located near the center are referred to as inner ends 801d, 802d, 803d, and 804d.

[0051] As shown in FIG. 7(A), the outer end 801c of the coil pattern 801 is connected to the middle portion 825 of the switching elements 821 and 822 shown in FIG. 4. The inner end 801d of the coil pattern 801 is connected to the inner end 802d of the coil pattern 802 shown in FIG. 7(B) via the through hole 208. The outer end 802c of the coil pattern 802 is connected to the outer end 803c of the coil pattern 803 shown in FIG. 7(C) via the through hole 209. The inner end 803d of the coil pattern 803 is connected to the inner end 804d of the coil pattern 804 shown in FIG. 7(D) via the through hole 210. The outer end 804c of the coil pattern 804 is connected to the controller chip 51 and the capacitor 81 as shown in FIG. 4 via the wiring layer of the interposer substrate 50.

[0052] In the inductor 80 of this modified example, when the switching element 821 is turned on and a voltage Vcc is applied to the outer end portion 801c of the coil pattern 801, the current flowing in the counterclockwise direction around the axis m10 through each of the coil patterns 801 to 804 increases, as shown by arrow I in Figures 7(A) to (D).

[0053] According to this configuration, the direction of the magnetic flux formed in each of the coil patterns 801 to 804 is the same, so that high magnetic coupling can be formed in each of the coil patterns 801 to 804. As a result, the performance of the inductor 80 can be improved.

[0054] 2. Second embodiment Next, a semiconductor device according to a second embodiment will be described, focusing on the differences from the semiconductor device 1 according to the first embodiment.

[0055] 2.1 Configuration of semiconductor device As shown in Fig. 8, the semiconductor device 1 of the present embodiment further includes a power supply IC 56. The power supply IC 56 is sealed together with the controller chip 51, the memory chip 52, etc. by a sealing material 54. The power supply IC 56 is a semiconductor chip formed from the power device 82 shown in Fig. 3. The power supply IC 56 is an example of a second semiconductor chip.

[0056] 2.2 Functions and Effects of the Semiconductor Device of the Present Embodiment The power supply IC 56 of this embodiment is provided separately from the controller chip 51, and includes switching elements 821 and 822 and a control circuit 820.

[0057] According to this configuration, the power supply IC 56 can be manufactured by a process suitable for the power supply circuit 9, which makes it possible to improve the characteristics of the power supply circuit 9 and reduce manufacturing costs.

[0058] 3. Third embodiment Next, a semiconductor device according to a third embodiment will be described, focusing on the differences from the semiconductor device 1 according to the first embodiment.

[0059] 3.1 Power supply circuit configuration 9 is a circuit diagram showing the configuration of a power supply circuit 9 according to this embodiment. As shown in FIG. 9, the power supply circuit 9 according to this embodiment further includes an inductor 83. Hereinafter, the inductor 80 will be referred to as a "first inductor 80," and the inductor 83 will be referred to as a "second inductor 83." The second inductor 83 is electrically connected in parallel to the first inductor 80.

[0060] The power device 82 further includes two switching elements 823 and 824 connected in series. The switching elements 823 and 824 are connected to a second inductor 83. The switching elements 823 and 824 have the same or similar configuration as the switching elements 821 and 822, and therefore detailed description thereof will be omitted. The switching elements 823 and 824 are controlled by a control circuit 820.

[0061] Fig. 10 is a front view showing the front structure of the semiconductor device 1 of this embodiment. Fig. 11 is a plan view showing the planar structure of the semiconductor device 1 of this embodiment. Note that in Figs. 10 and 11, one direction of the X directions is indicated as the X1 direction, and the other direction of the X directions is indicated as the X2 direction. The X1 direction is an example of the second direction. The X2 direction is an example of the third direction.

[0062] 10 and 11, the second inductor 83 is disposed on the opposite side of the first inductor 80 with respect to the controller chip 51 in the X direction. The second inductor 83 is composed of coil patterns 831-834 formed on the wiring layer of the interposer substrate 50. The coil patterns 831-834 of the second inductor 83 have the same or similar shapes as the coil patterns 801-804 of the first inductor 80, respectively, and therefore detailed description thereof will be omitted. The coil patterns 801-804 are an example of a first coil pattern. The coil patterns 831-834 are an example of a second coil pattern.

[0063] A capacitor 81b corresponding to the second inductor 83 is provided on the upper surface 500b of the interposer substrate 50 in addition to the capacitor 81a corresponding to the first inductor 80. Hereinafter, the capacitor 81a will be referred to as the "first capacitor 81a" and the capacitor 81b will be referred to as the "second capacitor 81b." As shown in FIG. 11, the second capacitor 81b is arranged to be aligned with the second inductor 83 in the Y direction.

[0064] In the circuit diagram of the power supply circuit 9 shown in FIG. 9, the first capacitor 81a and the second capacitor 81b are collectively illustrated as one capacitor 81.

[0065] The control circuit 820 operates the switching elements 821, 822 and the switching elements 823, 824 with a phase difference of 180 degrees, thereby performing interleaved operation of the switching elements 821, 822 connected to the first inductor 80 and the switching elements 823, 824 connected to the second inductor 83. The switching elements 821, 822 are an example of a first switching element. The switching elements 823, 824 are an example of a second switching element.

[0066] 3.2 Functions and Effects of the Semiconductor Device of the Present Embodiment A plurality of inductors 80, 83 are formed on the interposer substrate 50. The first inductor 80 is disposed offset in the X1 direction with respect to the controller chip 51. The second inductor 83 is disposed offset in the X2 direction opposite to the X1 direction with respect to the first inductor 80, with the controller chip 51 sandwiched therebetween.

[0067] According to this configuration, the fluctuation of the output voltage can be suppressed by the two-interleave operation. Also, by increasing the distance between the inductor 80 and the inductor 83, the deterioration of characteristics due to magnetic coupling can be suppressed.

[0068] 4. Other embodiments The present disclosure is not limited to the above specific examples.

[0069] For example, the coil pattern constituting the inductor 80 does not need to be formed on all four wiring layers of the interposer substrate 50, and may be formed on only three wiring layers, for example.

[0070] 5A illustrates an example in which the second end 801b of the coil pattern 801 and the first end 802a of the coil pattern 802 protrude inward (+Y direction), but the second end 801b of the coil pattern 801 and the first end 802a of the coil pattern 802 may be formed to protrude outward (-Y direction). The same applies to the second protrusion 802b of the coil pattern 802, the first protrusion 803a and the second protrusion 803b of the coil pattern 803, and the first protrusion 804a of the coil pattern 804.

[0071] Although the interposer substrate 50 in each embodiment includes four wiring layers, the number of wiring layers included in the interposer substrate 50 can be changed as desired. Furthermore, the number of coil patterns for configuring the inductor 80 can also be changed as desired depending on the number of wiring layers. For example, when the interposer substrate 50 includes four or more wiring layers, the inductor 80 can be configured by four or more coil patterns formed on each of the four or more wiring layers of the interposer substrate 50.

[0072] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0073] 1: semiconductor device, 9: power supply circuit, 50: interposer substrate, 51: controller chip (first semiconductor chip), 52: memory chip, 56: power supply IC (second semiconductor chip), 80: inductor (first inductor), 81, 81a, 81b: capacitor, 83: second inductor, 801-804, 831-834: coil patterns, 821, 822: switching elements (first switching elements), 823, 824: switching elements (second switching elements).

Claims

1. an interposer substrate including a plurality of wiring layers therein; a first semiconductor chip disposed on the interposer substrate; a power supply circuit that transforms a voltage supplied from an external source and supplies the transformed voltage to the first semiconductor chip; The power supply circuit includes: an inductor including a plurality of coil patterns formed on at least two wiring layers of the plurality of wiring layers of the interposer substrate; A capacitor having Semiconductor device.

2. the interposer substrate includes four or more wiring layers as the plurality of wiring layers, The inductor is composed of four or more coil patterns formed on the four or more wiring layers of the interposer substrate. The semiconductor device according to claim 1 .

3. The plurality of coil patterns are formed on all of the plurality of wiring layers of the interposer substrate. The semiconductor device according to claim 1 .

4. The plurality of wiring layers are formed inside the interposer substrate by being stacked in a first direction, The plurality of coil patterns do not include a portion overlapping the first semiconductor chip when viewed from the first direction. The semiconductor device according to claim 1 .

5. The plurality of wiring layers are formed inside the interposer substrate by being stacked in a first direction, The plurality of coil patterns are disposed at positions overlapping each other when viewed from the first direction. The semiconductor device according to claim 1 .

6. The first semiconductor chip includes a switching element of the power supply circuit and a control circuit for controlling the switching element. The semiconductor device according to claim 1 .

7. a second semiconductor chip including a switching element of the power supply circuit and a control circuit for controlling the switching element, the second semiconductor chip being different from the first semiconductor chip; The semiconductor device according to claim 1 .

8. Further comprising a memory chip; The first semiconductor chip is a controller chip configured to control the memory chip. The semiconductor device according to claim 1 .

9. The plurality of wiring layers are formed inside the interposer substrate by being stacked in a first direction, The plurality of coil patterns are disposed at positions overlapping the memory chip when viewed from the first direction. The semiconductor device according to claim 8.

10. A memory chip; a spacer disposed between the memory chip and the interposer substrate; the first semiconductor chip is a controller chip configured to control the memory chip; The plurality of wiring layers are formed inside the interposer substrate by being stacked in a first direction, the memory chip is disposed apart from a main surface of the interposer substrate in the first direction; The plurality of coil patterns are disposed at positions overlapping the spacer when viewed from the first direction. The semiconductor device according to claim 1 .

11. The power supply circuit is configured to pass a current through the plurality of coil patterns in the same rotational direction about a predetermined axis. The semiconductor device according to claim 1 .

12. Each of the plurality of coil patterns is formed in a spiral shape. The semiconductor device according to claim 1 .

13. The power supply circuit includes at least two of the inductors. The semiconductor device according to claim 1 .

14. The plurality of wiring layers are formed inside the interposer substrate by being stacked in a first direction, The power supply circuit includes: a first inductor including a plurality of first coil patterns arranged to be shifted in a second direction perpendicular to the first direction with respect to the first semiconductor chip; a second inductor configured with a plurality of second coil patterns, the second inductor being shifted from the first inductor in a third direction opposite to the second direction with the first semiconductor chip interposed therebetween, as the at least two inductors. The semiconductor device according to claim 13.

15. Further comprising at least two switching elements including a first switching element and a second switching element; the first switching element and the second switching element are connected to the first inductor and the second inductor, respectively; The power supply circuit causes the first switching element and the second switching element to operate in an interleaved manner. The semiconductor device according to claim 14.

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