Memory system and control method

Abstract

To reduce the amount of calculation required for error correction.SOLUTION: A memory system includes a non-volatile memory and a memory controller. The memory controller reads read information from the non-volatile memory, obtains a plurality of decoded words on the basis of a syndrome calculated from a soft-decision input value based on the read information, calculates a plurality of metrics for the plurality of decoded words, stores the calculated metrics for the first decoded word in a metric array as metrics for bits to be corrected by the first decoded word, and calculates a soft-decision output value indicating a decoding result for the soft-decision input value using a first metric that is the smallest of the plurality of metrics, a second metric that is the second smallest, the soft-decision input value, and the plurality of metrics stored in the metric array.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The following embodiments relate to a memory system and a control method. [Background technology]

[0002] In general, in a memory system, data is stored that has been coded for error correction in order to protect the data stored in the memory system. Therefore, when data stored in the memory system is read, the coded data is decoded. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0352362 [Patent Document 2] US Patent Application Publication No. 2015 / 0039965 [Patent Document 3] US Patent Application Publication No. 2019 / 0199690 [Non-patent literature]

[0004] [Non-Patent Document 1] X. Wang and S. Tang, "Bit-Level Soft-Decision Decoding of Double and Triple-Parity Reed-Solomon Codes Through Binary Hamming Code Constraints," in IEEE Communications Letters, 2015. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiments of the present invention is to provide a memory system and a control method capable of reducing the amount of calculation required for error correction (decoding). [Means for solving the problem]

[0006] According to an embodiment, a memory system includes a non-volatile memory and a memory controller, the memory controller reads read information from the non-volatile memory, obtains a plurality of decoded words based on a syndrome calculated from a soft-decision input value based on the read information, calculates a plurality of metrics for the plurality of decoded words, stores the calculated metrics for the first decoded word in a metric array as metrics of bits corrected by the first decoded word, and calculates a soft-decision output value indicating a decoding result for the soft-decision input value using a first metric that is the smallest of the plurality of metrics, a second metric that is the second smallest, the soft-decision input value, and the plurality of metrics stored in the metric array. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram of a memory system according to a first embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of the schematic configuration of a decoder. [Diagram 3] FIG. 11 is a diagram showing an example of the flow of a decoding process in a comparative example. [Figure 4] 6 is a flowchart of a decryption process performed by the memory system according to the first embodiment. [Diagram 5] 6 is a flowchart of an update process performed by the memory system of the first embodiment. [Figure 6] 4 is a flowchart of a calculation process performed by the memory system according to the first embodiment. [Figure 7] FIG. 4 is a diagram showing an example of an update process according to the first embodiment. [Figure 8] FIG. 4 is a diagram showing an example of a calculation process according to the first embodiment. [Figure 9] 13 is a flowchart of a decoding process performed by a memory system according to a modified example. [Figure 10]FIG. 13 is a diagram showing an example of a flip region. [Figure 11] 13 is a flowchart of an update process according to a modified example. [Figure 12] FIG. 1 shows an example of a Tanner graph used in decoding an RS code. [Figure 13] FIG. 2 is a diagram for explaining an SPC code constraint and a Hamming code constraint. [Figure 14] FIG. 13 is a diagram showing an example of an RS frame. [Figure 15] FIG. 4 is a diagram for explaining a calculation procedure for first-dimensional data. [Figure 16] A diagram summarizing data notation, number of elements, and calculation formulas. [Figure 17] FIG. 4 is a diagram for explaining a calculation procedure for second-dimensional data. [Figure 18] A diagram summarizing data notation, number of elements, and calculation formulas. [Figure 19] 13 is a flowchart of a decryption process performed by the memory system according to the second embodiment. [Figure 20] A diagram summarizing the data names, notations, and number of elements. [Figure 21] 13 is a flowchart of the first dimension process. [Figure 22] 2 is a flowchart of a second dimension process. [Figure 23] FIG. 13 is a conceptual diagram showing a decoding method according to the third embodiment. [Figure 24] FIG. 13 is a diagram for explaining examples of symbols used in the third embodiment. [Diagram 25] A diagram summarizing the data names, notations, and number of elements. [Figure 26] 13 is a flowchart of a decryption process performed by the memory system according to the third embodiment. [Figure 27] 13 is a flowchart of a decoding process (first time) for an ECC frame. [Figure 28] Flowchart of RS first dimension processing. [Figure 29] Flowchart of RS 2D processing. [Diagram 30] 13 is a flowchart of a decoding process (other than the first time) for an ECC frame. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to the following embodiments.

[0009] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration example of a memory system according to the first embodiment. As shown in Fig. 1, the memory system 1 includes a memory controller 10 and a non-volatile memory 20. The memory system 1 can be connected to a host 30, and Fig. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0010] The nonvolatile memory 20 is a nonvolatile memory that stores data in a nonvolatile manner, for example, a NAND memory. In the following description, a case where a NAND memory is used as the nonvolatile memory 20 is exemplified, but it is also possible to use a storage device other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistance Random Access Memory), or a FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. In addition, it is not essential that the nonvolatile memory 20 is a semiconductor memory, and this embodiment can be applied to various storage media other than semiconductor memories.

[0011] The memory system 1 may be a memory card or the like in which the memory controller 10 and the nonvolatile memory 20 are configured as one package, or may be an SSD (Solid State Drive) or the like.

[0012] The memory controller 10 controls writing to the non-volatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the non-volatile memory 20 in accordance with a read request from the host 30. The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are connected to each other via an internal bus 16.

[0013] The host I / F 15 performs processing in accordance with the interface standard with the host 30, and outputs commands received from the host 30, user data to be written, and the like to the internal bus 16. In addition, the host I / F 15 transmits user data read and restored from the non-volatile memory 20, responses from the control unit 11, and the like to the host 30.

[0014] The memory I / F 13 performs a write process to the non-volatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the non-volatile memory 20 based on an instruction from the control unit 11.

[0015] The control unit 11 performs overall control of each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, the control unit 11 performs control according to the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 according to the instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 according to the instruction from the host 30.

[0016] Furthermore, when the control unit 11 receives a write request for user data from the host 30, it accumulates the user data in the data buffer 12 and determines a storage area (memory area) in the nonvolatile memory 20 for the user data. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area in the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0017] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0018] In a NAND memory, writing and reading are generally performed in data units called pages, and erasure is performed in data units called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. When the memory cells are single level cells (SLC), one memory cell group corresponds to one page. When the memory cells are multi-level cells (MLC), one memory cell group corresponds to multiple pages. Each memory cell is connected to a word line and also to a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0019] Furthermore, in response to a read instruction from the memory controller 10 , the NAND memory applies a read voltage to the word lines, thereby reading data from a plurality of memory cells and transmitting the read data to the memory controller 10 .

[0020] The memory cells are, for example, field-effect transistors. The memory cells include a semiconductor layer, a gate insulating film, and a gate electrode. The gate insulating film includes a charge storage layer (insulating film or conductive film). The amount of charge in the charge storage layer falls into one of a number of distributions (threshold distributions). When reading data from a number of memory cells, the voltage to be applied to the word line changes depending on the amount of charge in the charge storage layer.

[0021] For the sake of simplicity, an example of 1 bit / cell in which one memory cell stores one bit will be described. In the case of 1 bit / cell, one of two threshold distributions corresponds to "0" and the other corresponds to "1". When a voltage is applied to a word line, a current may or may not flow when the voltage is applied, with a voltage value according to the charge amount of the memory cell as the boundary. This voltage as the boundary is determined according to the charge amount of the memory cell. This voltage determined according to the charge amount of the memory cell is called a threshold voltage or a reference read voltage. A NAND memory can determine whether the data stored in this memory cell is 1 by applying a reference read voltage to a word line.

[0022] Hereinafter, reading data from a memory cell as a hard decision value of 1 or 0 is referred to as a hard bit read. In a hard bit read by the memory controller 10, a reference read voltage is applied as a read voltage to a word line connected to the memory cell, and it is determined whether the data stored in the memory cell is 1 or 0, and the result of the determination is output as read data to the memory controller 10. In addition, in a hard bit read, the read voltage may be changed from the reference read voltage, and in this case, the difference between the read voltage and the reference read voltage is specified by a read instruction from the memory controller 10.

[0023] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 until the data is stored in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 until the data is transmitted to the host 30. For the data buffer 12, for example, a general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) can be used.

[0024] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data to generate a codeword. The encoding / decoding unit 14 also decodes a received word read from the non-volatile memory 20 to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoder 17 and a decoder 18. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0025] Next, the write process of this embodiment will be described. When writing user data to the non-volatile memory 20, the control unit 11 instructs the encoder 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the codeword in the non-volatile memory 20, and also instructs the memory I / F 13 of the determined storage location.

[0026] The encoder 17 generates a codeword by encoding the user data on the data buffer 12 based on an instruction from the control unit 11. For example, an encoding method using an error correction code including a Hamming code in at least a part of its internal structure can be adopted. The error correction code including a Hamming code in at least a part of its internal structure is, for example, a Hamming code, an RS (Reed-Solomon) code, or a concatenated code having at least one of a Hamming code and an RS code as a component code. The concatenated code is a code made by combining a plurality of codes, and includes, for example, a product code.

[0027] An error-correcting code is composed of at least one or more symbols as building blocks. One symbol is composed of, for example, one bit (an element of a binary field) or an element of the alphabet of a finite field other than a binary field. For ease of explanation, the following will use an example of a binary error-correcting code in which one symbol is composed of one bit. In the explanation, there may be places where symbols and bits are used interchangeably, but both have the same meaning.

[0028] In the first embodiment, an example using a Hamming code will be described. An example using an RS code will be described in the second and third embodiments. The memory I / F 13 controls storing the codeword in a memory location on the non-volatile memory 20 instructed by the control unit 11.

[0029] Next, a process of reading from the nonvolatile memory 20 in this embodiment will be described. When reading from the nonvolatile memory 20, the control unit 11 designates an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoder 18 to start decoding. The memory I / F 13 reads the received word from the designated address in the nonvolatile memory 20 in accordance with the instruction of the control unit 11, and inputs the read received word to the decoder 18. The decoder 18 decodes the received word read from the nonvolatile memory 20.

[0030] The decoder 18 decodes the received word read from the non-volatile memory 20. Fig. 2 is a block diagram showing a schematic configuration example of the decoder 18. The decoder 18 includes a HIHO (hard-input hard-output) decoding unit 181 that receives a hard decision value as an input, performs decoding, and outputs a hard decision value as a result, and a SISO (soft-input soft-output) decoding unit 182 that receives a soft decision value (soft decision input value), performs decoding, and outputs a soft decision value (soft decision output value) as a result.

[0031] Generally, SISO decoding has a feature that it has a higher error correction capability than HIHO decoding, but requires a longer processing time. Therefore, in this embodiment, the HIHO decoding unit 181 is configured to first HIHO decode the received word read from the non-volatile memory 20 as a hard decision value, and to read the received word that could not be decoded by the hard decision decoding as a soft decision value. Then, the SISO decoding unit 182 is configured to SISO decode the received word read as the soft decision value. However, the present invention is not limited to such a configuration, and various modifications are possible, such as a configuration in which HIHO decoding is omitted and SISO decoding is performed on all received words.

[0032] The SISO decoding unit 182 may include a memory (read information memory) that stores read information (received word) read from the non-volatile memory 20 by soft decision. Of the read information, data corresponding to a hard decision value, which is binary information that determines whether each bit is 0 or 1, may be called hard bit data. Also, data corresponding to a portion of the read information excluding the hard bit data may be called soft bit data. The read information memory may include a hard bit memory (HMEM) that stores hard bit data, and a soft bit memory (CMEM) that stores soft bit data.

[0033] In the decoding process, data called a channel value may be required. The channel value indicates a log-likelihood ratio (LLR) value corresponding to a set of hard bit data and soft bit data. The channel value may be called channel LLR data. The channel value is determined, for example, by an LLR table that associates a set of hard bit data and soft bit data with a channel value. The channel value is an example of a soft decision input value based on soft decision read information read from the non-volatile memory 20.

[0034] For example, in a readout by soft decision (soft bit read), one hard bit data and multiple soft bit data are obtained. The one hard bit data is obtained using a readout voltage (hereinafter referred to as VrH) that is the same as the readout voltage used in the readout by hard decision (hard bit read). The multiple soft bit data are obtained using multiple readout voltages including a readout voltage having a value smaller than VrH and a readout voltage having a value larger than VrH. The LLR table is, for example, a table in which a channel value is associated with each pair of one hard bit data and multiple soft bit data. The SISO decoding unit 182 can determine a corresponding channel value from the one hard bit data and multiple soft bit data included in the readout information using such an LLR table.

[0035] In this embodiment, where a symbol is an element of a binary field, the LLR represents probability information regarding whether a bit is 0 or 1. In the following, the LLR is assumed to be positive when the bit is highly likely to be 0, and negative when the bit is highly likely to be 1. In this embodiment, the soft input value and the soft output value are also assumed to be expressed by the LLR.

[0036] The LLR can be expressed by contracting it to binary information of 0 or 1 depending on whether the value is positive or negative. In the following, such binary information may be referred to as the hard decision value of the LLR. In addition, in the following, if the LLR is positive, the hard decision value is set to 0, if the LLR is negative, the hard decision value is set to 1, and if the LLR is 0, the hard decision value is determined according to a predetermined rule (for example, the hard decision value is set to 0).

[0037] The "hard decision value of the channel value" corresponds to information in which the channel value represented by the LLR is expressed as a binary value according to whether the value is positive or negative, as described above. Similarly, the "hard decision value of the soft decision input value" corresponds to information in which the soft decision input value represented by the LLR is expressed as a binary value according to whether the value is positive or negative, as described above.

[0038] As a SISO decoding method for a Hamming code, there is a decoding method in which list decoding is performed to find multiple decoded words, and a soft decision output value is calculated by the Max-Log-MAP (Maximum A Posteriori) method using a metric for each of the multiple decoded words found. Below, an overview of a comparative example in which this decoding method is executed will be described. Figure 3 is a diagram showing an example of the flow of the decoding process of the comparative example.

[0039] In the Max-Log-MAP method, for example, the soft decision output value L i (out) is calculated.

number

[0040] i represents the position (address) of n bits (n is an integer equal to or greater than 2) included in the soft decision value (soft decision input value, soft decision output value). For example, i is an integer that satisfies 0≦i≦n-1. n corresponds to the code length of the Hamming code. L i (in) represents the value of the bit at address i of the soft decision input value (hereinafter, sometimes referred to as bit i). sgn(a) represents a function that outputs the code of a. M(decoded word) represents the metric for the decoded word. D i (c) D denotes the set of decoded words that correct bit i. i (nc) Let denote the set of decoded words that do not correct bit i.

[0041] The metric is an index corresponding to the distance between the soft decision input value and the decoded word. The metric is calculated, for example, by the sum of the absolute values ​​of the soft decision input values ​​at the correction positions, but may be calculated by any other method.

[0042] The first term in the brackets where the difference on the right hand side of equation (1) is calculated corresponds to the minimum metric among the metrics for multiple decoded words that correct bit i. The second term corresponds to the minimum metric among the metrics for multiple decoded words that do not correct bit i.

[0043] In the comparative example, two (two-dimensional) metric arrays are used to store metrics used in the calculation of equation (1). Each metric array includes n (code length) metrics. The two metric arrays are a metric array with correction and a metric array without correction. In the metric array with correction, metrics of a decoded word are stored at the positions of bits corrected by the found decoded word. In the metric array without correction, metrics of a decoded word are stored at the positions of bits not corrected by the found decoded word.

[0044] In the comparative example, a soft decision output value indicating a decoding result for a soft decision input value is calculated, for example, by the following procedure. (A1) Calculate a syndrome from the hard decision value of the soft decision input value. (A2) Update the two-dimensional metric array while performing list decoding using the syndrome. (A3) A two-dimensional metric array is used to calculate the soft decision output value.

[0045] FIG. 3 corresponds to a diagram mainly showing a specific example of the process of (A2). FIG. 3 shows an example of updating a two-dimensional metric array when three decoded words are found. FIG. 3 also shows an example in which a soft decision input value of code length n=5 in which bits of addresses 0 to 4 are 1, 2, 3, 4, and -5, respectively, is input. More specifically, a syndrome (not shown) is calculated from the hard decision value shown in FIG. 3 (the hard decision value of the input soft decision input value), and the result of the syndrome calculation is used to perform list decoding such as Chase decoding and OSD to obtain the decoded word D shown in FIG. 3. (1) ~D (3) The syndrome is calculated, for example, by multiplying the parity check matrix of the error correcting code by the hard decision values.

[0046] First discovered decrypted word D (1) In this case, the bit of address 4 (bit 4) is corrected. (1)The metric of is calculated as the sum of absolute values ​​of the soft decision input value “−5” at the correction position (address 4), which is 5.

[0047] In the two-dimensional metric array, the calculated metric is stored at a position corresponding to the correction position (address 4) in the metric array with correction, and the calculated metric is stored at positions other than the correction position (addresses 0 to 3) in the metric array without correction.

[0048] Similarly, the second and third decoded words D (2) and the decoded word D (3) For, metrics 7 and 3 are calculated, and the metrics for the positions corresponding to the correction positions are updated for each of the two metric arrays.

[0049] Thus, in the comparative example, every time a decoded word is found, processing equivalent to the code length is required to update the two-dimensional metric array.

[0050] Therefore, in this embodiment, there is one metric array (one-dimensional metric array), and instead there are provided a memory min1 (first metric memory) that stores the smallest metric (first metric) among multiple metrics calculated for multiple decoded words, and a memory min2 (second metric memory) that stores the second smallest metric (second metric) among the multiple metrics. Note that, hereinafter, the metric stored in memory min1 may be referred to as metric min1, and the metric stored in memory min2 may be referred to as metric min2.

[0051] When a decoded word is found, the entry of the correction position of the one-dimensional metric array, memory min1 (metric min1), and memory min2 (metric min2) are updated using the metric calculated for the decoded word. In this embodiment, the one-dimensional metric array stores the metric calculated for the decoded word DA as the metric of the bit corrected by the decoded word DA (first decoded word) included in the multiple decoded words. In this way, in this embodiment, the amount of processing equivalent to the number of correction positions + 2 is required. Note that no distinction is made between the processing of only comparing values ​​and the processing of comparing and updating values, and both are considered as one processing. For example, in the case of 1-bit flip decoding, the maximum number of correction positions is 2, so the maximum number of processing is 4. In this way, in this embodiment, the amount of calculation is reduced to "the number of correction positions + 2" compared to the amount of calculation for the code length in the comparative example.

[0052] Next, a flow of a decoding process by the memory system 1 of the first embodiment will be described. In the following, an example of applying 1-bit flip decoding as SISO decoding for a Hamming code will be described. FIG. 4 is a flowchart showing an example of a decoding process by the memory system of the first embodiment.

[0053] The control unit 11 reads the error correction code from the non-volatile memory 20 to obtain read information (step S101). The control unit 11 transfers and stores the obtained read information, for example, in a read information memory in the SISO decoding unit 182. The read information includes, for example, hard bit data and soft bit data.

[0054] The SISO decoding unit 182 calculates a syndrome s from the hard decision value of the soft decision input value (channel value) (step S102). The channel value can be obtained as a log-likelihood ratio corresponding to the hard bit data and the soft bit data included in the read information, for example, by using the above-mentioned LLR table. The syndrome s is a symbol string used by the error correction code to calculate the error position, and is obtained by, for example, multiplying the parity check matrix of the error correction code by the hard decision value.

[0055] The SISO decoding unit 182 determines whether the calculated syndrome s is 0 (step S103). If the syndrome s is not 0 (step S103: No), the SISO decoding unit 182 executes an update process of the metric array, memory min1, and memory min2 (step S104). The details of the update process will be described later.

[0056] After the update process, and if the syndrome s is 0 (step S103: Yes), the SISO decoding unit 182 executes a calculation process of a soft decision output value (step S105). The details of the calculation process will be described later.

[0057] The decoder 18 determines whether the decoding is successful (step S106). Successful decoding may mean, for example, that a decoded word that can be determined to be correct has been found. If the decoding is successful (step S106: Yes), the decoder 18 notifies an external control unit or the like of the success of the decoding and the decoded word (step S107), and ends the decoding process. If the decoding is not successful (step S106: No), the decoder 18 notifies an external control unit or the like of a failure of the decoding (step S108), and ends the decoding process.

[0058] Next, details of the update process in step S104 will be described below. Fig. 5 is a flowchart showing an example of the update process by the memory system of the first embodiment.

[0059] In the update process, for example, the syndrome s and the absolute value A of the soft decision input value are input, and the metric array m, the metric min1, and the metric min2 are output. The absolute value A is expressed as follows: A=(A0,A1,...,A n-1 ), a vector containing n elements. A metric array m is an array containing n metrics, for example, m = (m0, m1, . . . , m n-1 )

[0060] The SISO decoding unit 182 executes an initialization process for various parameters used in the update process (step S201). The parameters include, for example, the address i of the target bit, the metric m i (i=0, 1, . . . , n-1), and metrics min1 and min2. The SISO decoding unit 182 initializes these parameters, for example, as follows: INF denotes a predetermined initial value. Address i=0 m0=m1==m n-1 =INF min1=min2=INF

[0061] The SISO decoder 182 uses the current address i to obtain the metric m i It is determined whether the metric m is equal to INF (step S202). i If metric m is not equal to INF, i.e., if a value different from the initial value is set, it means that a decoded word that corrects the bit of address i has already been found. i If is not equal to INF (step S202: No), the SISO decoding unit 182 skips the processes of steps S203 to S207 and transitions to step S208.

[0062] Metric m i If INF is equal to (step S202: Yes), the SISO decoding unit 182 calculates a modified syndrome s' by modifying the syndrome s (step S203). The modified syndrome s' is obtained by reflecting the effect of flipping the bit i in the syndrome. For example, the SISO decoding unit 182 calculates the syndrome s and the i-th column vector h i The modified syndrome s' is calculated by exclusive ORing with

[0063] The SISO decoding unit 182 determines whether or not the modified syndrome s'≠0 (step S204). Note that the modified syndrome s'=0 indicates that a decoded word with a 1-bit correction position has been found.

[0064] If the modified syndrome s'≠0 (step S204: Yes), the SISO decoding unit 182 obtains the correction position j from the modified syndrome s' (step S205). For example, the SISO decoding unit 182 can obtain the correction position j for the modified syndrome s' by using correspondence information (such as a table) that outputs a correction position for an input syndrome.

[0065] After obtaining the correction position j, or if it is determined in step S204 that the modified syndrome s' is not 0 (step S204: No), the SISO decoding unit 182 uses the soft decision input value, the modified syndrome s', and the correction position j to obtain the metric m i Calculate the calculated metric m i in the corresponding position of the metric array (step S206). The corresponding positions include the position corresponding to bit i and the position corresponding to correction position j when correction position j is a valid position.

[0066] The SISO decoding unit 182 calculates the metric m according to the conditions of the correction syndrome s' and the correction position j, for example, as follows: i Calculate. If s'=0, m i =A i If s' ≠ 0 and the correction position j is a valid position, m i =m j =A i +A j If s' ≠ 0 and the correction position j is an invalid position, m i =A i +B

[0067] The value B may be, for example, one of the following values: (B1) Predefined fixed value (B2) The average value of the absolute values ​​of the soft decision input values ​​for multiple bits (e.g., bit 0 to bit n-1) multiplied by 2

[0068] Here, we will explain valid and invalid positions. m ) For the Hamming code above, if it is not shortened, the code length is n=2 m -1, and the information length is k=nm=2 m Here, by treating some of the information bits, for example s bits, as 0, the code length becomes n=2 m -1-s, information length is k=2 m We can consider a shortened Hamming code with a length of 2 -1-ms. m Among the positions of (-1), the positions that are fixed to 0 by shortening are called "invalid positions", and the other positions are called "valid positions".

[0069] The method of fixing the s bits is not limited to fixing them to 0, but may be fixing them to 1, or changing whether the bit is fixed to 0 or 1 depending on the bit, but usually all shortened positions are fixed to 0. This is because if the value is 0, the contribution of the shortened positions can simply be set to 0 during encoding and syndrome calculation.

[0070] Next, the reason for changing the metric calculation method depending on whether the correction position j is a valid position or an invalid position will be explained.

[0071] In step S205, as described above, the m-bit correction position j corresponding to the m-bit syndrome s' is found by referring to the correspondence information (table). Note that there is a one-to-one correspondence between the m bits of the input (syndrome and absolute value of the soft decision input value) and the m bits of the output (metric array). However, if the syndrome is 0, this means that there is no correction position, so if the syndrome is 0, step S205 of referring to the correspondence information is skipped.

[0072] When the Hamming code is shortened, a situation may occur in which the correction position j found using the correspondence information corresponds to an "invalid position." This corresponds to the fact that no decoded word that corrects two bits including position i is found, that is, when position i is the correction position, there are at least two other correction positions. Within the scope of one-bit flip decoding, the correction position cannot be found in such a situation.

[0073] Therefore, in this embodiment, when the correction position j is in a state equivalent to an "invalid position", the metric is calculated approximately. i =A i +B corresponds to the metric that is approximately calculated.

[0074] The reason why the value B is obtained by multiplying the average value of the absolute values ​​of the soft decision input values ​​for multiple bits by 2 as in (B2) is that it is assumed that there are two other correction positions, and it is plausible that the contributions of those positions should be taken as the overall average value. However, if the amount of calculation required to calculate the average value increases, (B1) using a predetermined fixed value may be adopted. The fixed value may be determined by prior evaluation, etc., as a value equivalent to twice the average value.

[0075] Note that, for invalid positions (positions where no decoded word to be corrected is found), the SISO decoding unit 182 may set bits of the soft decision output value corresponding to the invalid positions to a predetermined fixed value.

[0076] Returning to the description of Fig. 5, the SISO decoding unit 182 updates the memory min1 and the memory min2 (step S207). For example, the metric calculated for the first decoded word found is the smallest metric and is stored in the memory min1. If the metric calculated for the second or subsequent decoded word found is smaller than the metric already stored in the memory min1, the metric stored in the memory min1 is stored in the memory min2, and the newly calculated metric is stored in the memory min1. If the metric calculated for the second or subsequent decoded word found is larger than the metric already stored in the memory min1 and smaller than the metric already stored in the memory min2, the newly calculated metric is stored in the memory min2.

[0077] The SISO decoding unit 182 adds 1 to the address i (step S208), and determines whether the address i after the addition satisfies i=n (step S209). If i=n is not satisfied (step S209: No), the SISO decoding unit 182 returns to step S202 and repeats the process. If i=n is satisfied (step S209: Yes), the SISO decoding unit 182 ends the update process.

[0078] Next, the calculation process in step S105 will be described in detail. The calculation process is divided into two types: when it is determined in step S103 that the syndrome s is not 0, and when it is determined that the syndrome s is 0. First, the calculation process when it is determined that the syndrome s is not 0 will be described with reference to Fig. 6. Fig. 6 is a flowchart showing an example of the calculation process by the memory system of the first embodiment.

[0079] In the calculation process, for example, the following input data and output data are used. Input data: The sign of each bit of the soft decision input value (sgn(L0 (in) ),sgn(L1 (in) ),···,sgn(L n-1 (in) )) Metric array m = (m0,m1,...,m n-1 ) Metrics min1, min2 Output data: Soft decision output value L (out) =(L0 (out) ,L1 (out) ,···,L n-1 (out) )

[0080] If an output format as a bit sequence (that is, a decoded word) is desired instead of a soft decision output value (LLR sequence), a hard decision value of the soft decision output value may be output as output data.

[0081] The SISO decoding unit 182 initializes an address i to 0 (step S301). The SISO decoding unit 182 uses the current address i to calculate a metric m i It is determined whether the metric m is equal to the metric min1 (step S302). i If the metric m is not equal to the metric min1 (step S302: No), the SISO decoding unit 182 sets the variable x to the metric min1 (step S303). i If x is equal to the metric min1 (step S302: Yes), the SISO decoding unit 182 sets the variable x to the metric min2 (step S304).

[0082] The SISO decoding unit 182 calculates the soft decision output value of the address i (step S305). For example, the SISO decoding unit 182 calculates the soft decision output value L i (out) Calculate.

number

[0083] Equation (2) corresponds to a rewrite of equation (1) by utilizing the fact that “the smallest metric among the metrics for multiple decoded words for which bit i is not corrected” (the second term in parentheses) in equation (1) is metric min1 or min2.

[0084] (m i -x) is the metric m i If metric min1 is equal to metric min1 (step S302: Yes), metric m i min2, or metric m i If metric min1 is not equal to metric min2 (step S302: No), metric m i min1.

[0085] In addition, the soft decision output value L obtained by equation (2) i (out) is the sign sgn(L i (in) ) is obtained as a result of multiplication by the soft decision output value L i (out) is a value that expresses probability information of whether each bit is 0 or 1 in the form of LLR, and is sometimes called a posteriori value (posteriori value LLR).

[0086] In addition, when multiple codes are concatenated and used, one bit may be protected by multiple code constraints (e.g., product code). In such a case, a decoding method is available in which a decoding process is first performed under a first code constraint (hereinafter, code constraint C1), and then a decoding process is performed under a second code constraint (hereinafter, code constraint C2) after obtaining probability information from the code constraint C1 (turbo decoding). In such a decoding method, the probability information (in the form of LLR) passed from the code constraint C1 to the code constraint C2 is called an extrinsic value (extrinsic value LLR). On the code constraint C2 side, the sum of the channel LLR data and the extrinsic value LLR is used as a soft decision input value for the decoding process. In this way, the sum of the channel LLR data and the extrinsic value LLR may be used as a soft decision input value based on the read information.

[0087] When such a code is used, the SISO decoding unit 182 converts the extrinsic value (extrinsic value LLR) calculated using the following equation (3) instead of equation (2) into the soft decision output value L i (out) Equation (3) is the output of the bit value L of the address i of the soft decision input value from the a posteriori value. i (in) The soft decision output value L is the value based on the external value with i (out) The value based on the external value is, for example, a value obtained by multiplying the external value by a scale coefficient c described below.

number

[0088] In the decoding process, a process that performs some approximation may be performed. In such a case, the accuracy of the extrinsic LLR decreases compared to an ideal decoding process (without approximation). In particular, the accuracy often deteriorates in the direction in which the absolute value of the extrinsic LLR increases. A scale factor may be used as a measure to suppress such deterioration. c in equation (3) corresponds to such a scale factor. The scale factor c is, for example, a fixed value between 0 and 1. In this way, the scale factor c is used to suppress the amplitude of the extrinsic LLR and suppress deterioration of the decoding accuracy when the extrinsic value is used.

[0089] Returning to the description of Fig. 6, the SISO decoding unit 182 adds 1 to the address i (step S306) and determines whether the address i after the addition satisfies i = n (step S307). If i = n is not satisfied (step S307: No), the SISO decoding unit 182 returns to step S302 and repeats the process. If i = n is satisfied (step S307: Yes), the SISO decoding unit 182 ends the calculation process.

[0090] Next, a description will be given of the calculation process when it is determined that the syndrome s is 0. In the calculation process in this case, for example, the following input data and output data are used. Input data: The sign of each bit of the soft decision input value (sgn(L0 (in) ),sgn(L1 (in) ),···,sgn(L n-1 (in) )) Output data: Soft decision output value L (out) =(L0 (out) ,L1 (out) ,···,L n-1 (out) )

[0091] Similarly to the above, when an output format as a bit sequence (that is, a decoded word) is desired instead of a soft output value (LLR sequence), a hard decision value of the soft output value may be output as output data.

[0092] The SISO decoding unit 182 calculates the soft decision output value L i (out) Calculate.

number

[0093] W is a predetermined fixed value. For example, the value calculated as follows can be set as the fixed value. Maximum value of LLR amplitude handled by the decoder 182 The value obtained by multiplying the maximum LLR amplitude handled by the decoder 182 by a scale coefficient (a value between 0 and 1)

[0094] W may be set to a different fixed value depending on whether a posterior value (posterior value LLR) or an extrinsic value (extrinsic value LLR) is output as the soft decision output value. For example, the fixed value when the posterior value is output may be set to a value equal to or greater than the fixed value when the extrinsic value is output.

[0095] Next, a specific example of the decryption process according to the first embodiment will be described with reference to Fig. 7 and Fig. 8. Fig. 7 is a diagram showing an example of the update process according to the first embodiment. Fig. 8 is a diagram showing an example of the calculation process according to the first embodiment.

[0096] Similar to FIG. 3, FIG. 7 shows an example in which soft decision input values ​​of code length n=5 in which bits of addresses 0 to 4 are 1, 2, 3, 4, and −5, respectively, are input and three decoded words are found.

[0097] In this embodiment, the first decrypted word D (1) The calculated metric for is stored in the one-dimensional metric array at a position corresponding to the correction position (address 4). Also, the calculated metric (5) is stored in memory min1.

[0098] Similarly, the second and third decoded words D (2) and decrypted word D (3) For the 1-bit flip decoding, metrics 7 and 3 are calculated, and the metrics at the positions corresponding to the correction positions in the one-dimensional metric array are updated. Also, depending on the magnitude relationship of the values, the memory min1 and / or the memory min2 are updated. In the case of 1-bit flip decoding, the amount of calculation in this embodiment is "the number of correction positions + 2".

[0099] Fig. 8 shows the soft decision output value L (out) For example, for address 0 (i=0), metric m0 is equal to metric min1 (step S302: Yes), so metric min2 is set to x, and 3-5=-2 is calculated as the subtraction value obtained by subtracting x (metric min2) from metric m0. Also, the sign sgn(L0 (in) ) is positive, so the soft decision output value L (out) The soft decision output value L i (out)) is calculated.

[0100] (Modification) So far, an example has been described in which one-bit flip decoding is applied as SISO decoding for a Hamming code. The applicable decoding method is not limited to this, and any other decoding method may be used. In a modified example, an example in which Chase decoding is applied as SISO decoding for a Hamming code will be described. This modified example can also be applied as a modification of the second and third embodiments described below. Instead of Chase decoding, a configuration may be used in which multiple decoded words are obtained by OSD (Ordered Statistics Decoding).

[0101] Fig. 9 is a flowchart showing an example of a decoding process by the memory system of this modified example. The decoding process of the modified example differs from that of Fig. 4 showing the decoding process of the above embodiment in that a flip region selection process (step S404) is added. Also, the update process of the metric array, memory min1 and memory min2 in step S405 differs from step S104 in Fig. 4. The other steps S401 to S403 and steps S406 to S409 are similar to steps S101 to S103 and steps S105 to S108 in Fig. 4, and therefore will not be described.

[0102] The flip region selection process in step S404 will be described below. For example, the SISO decoding unit 182 sorts the soft decision input values ​​in ascending order of absolute value, and selects a flip region indicating a range of bits in which bits are to be flipped (inverted) from among the sorted soft decision input values.

[0103] Fig. 10 is a diagram showing examples of flip regions. Fig. 10 shows an example in which 13-bit soft decision input values ​​are sorted from the left in descending order of absolute value. Fig. 10 also shows examples of selected flip regions (1-bit flip region, 2-bit flip region, ..., M-bit flip region).

[0104] In the flip region selection process, the following parameter values ​​are determined in advance. Maximum number of flips M: M is a value greater than or equal to 1. Flip region list (f1,f2,...,f M ): where n (code length) ≥ f1 ≥ f2 ≥ ≥ f M ≧M.

[0105] The SISO decoding unit 182 selects the position of the flip target bit for each flip number g=1, . . . , M as follows. The soft decision input values ​​are sorted in ascending order of absolute value, g The bit group at this position is set as a bit group to be flipped for the flip number g. Generate all combinations of g different positions from the flip bit group of flip number g, and set each combination as a flip pattern of flip number g. In other words, the total number of flip patterns of flip number g is expressed by the following formula (5).

number

[0106] Let the total number of all flip patterns be T, and each flip pattern be numbered t = 0, 1, ..., T-1.

[0107] Next, the update process in step S405 will be described below. Fig. 11 is a flowchart showing an example of the update process in the modified example.

[0108] The initialization process in step S501 is similar to step S201 in the update process (FIG. 5) in the above embodiment.

[0109] The SISO decoding unit 182 calculates a modified syndrome s' by modifying the syndrome s (step S502). The modified syndrome s' is obtained by generating the t-th flip pattern and reflecting the influence of the generated flip pattern on the syndrome s. For example, if the flip positions of the flip pattern with the flip number g are i1, i2, . . . , i g Then, the syndrome s and the i1, i2, . . . , ig The exclusive OR with the column vector is calculated as the modified syndrome s'.

[0110] The SISO decoding unit 182 determines whether the modified syndrome s'≠0 (step S503). If the modified syndrome s'≠0 (step S503: Yes), the SISO decoding unit 182 executes bounded distance decoding using the modified syndrome s' (step S504).

[0111] The SISO decoding unit 182 determines whether the decoding is successful (step S505). If the decoding is successful (step S505: Yes) and if it is determined in step S503 that the modified syndrome s' is not 0 (step S503: No), the SISO decoding unit 182 decodes the metric m i Calculate the calculated metric m i is stored in the corresponding position of the metric array (step S506).

[0112] For example, the SISO decoding unit 182 calculates the metric I by the following formula (6). Q represents the total number of correction positions found by the flip positions and distance-bounded decoding. q is an integer satisfying 1≦q≦Q. C q represents the qth flip or correction position.

number

[0113] The SISO decoding unit 182 detects the position C q For each metric, compare the metric value stored in the corresponding position of the metric array with the calculated metric I, and if metric I is smaller, q Metric I is stored in the location corresponding to

[0114] The updating of the memories min1 and min2 in step S507 is similar to step S207 in the update process in the above embodiment.

[0115] After step S507, or if it is determined that the decoding has failed in step S505 (step S505: No), the SISO decoding unit 182 determines whether t=T-1 is satisfied (step S508). If t=T-1 is not satisfied (step S508: No), the SISO decoding unit 182 adds 1 to t (t=t+1) (step S509), returns to step S502, and repeats the process.

[0116] If t=T−1 is satisfied (step S508: Yes), the SISO decoding unit 182 ends the update process.

[0117] As described above, in the first embodiment, when SISO decoding is performed on a Hamming code, a soft decision output value is calculated using one metric array, a memory that stores the smallest metric among multiple metrics, and a memory that stores the second smallest metric. In contrast to the comparative example that requires a calculation amount equivalent to the code length by using two metric arrays, in this embodiment, the calculation amount can be reduced to "the number of correction positions + 2".

[0118] Second embodiment In the second embodiment, an example using an RS code will be described. SISO decoding of an RS code generally requires a large amount of calculation. Therefore, a technique for performing SISO decoding by considering the RS code constraint as a combination of a single parity check (SPC) code constraint and a Hamming code constraint has been proposed. SISO decoding for the SPC code constraint can be easily performed by, for example, the Min-Sum method. In this embodiment, the same decoding method as in the first embodiment is used for SISO decoding for the Hamming code constraint. This makes it possible to realize SISO decoding with a reduced overall amount of calculation.

[0119] FIG. 12 is a diagram showing an example of a Tanner graph used in decoding the RS code. FIG. 12 shows an example of a Tanner graph used in decoding the RS code in a Galois field GF(2 3 ) with code length n=7, information length k=5, roots 1 and α(α is in GF(2 3) is a primitive element on ).

[0120] The circles in Figure 12 represent variable nodes. i,j represents the jth (j=0,1,2) bit of the ith (i=0,1,...,6) symbol. White squares represent check nodes corresponding to the SPC code constraint. Black squares represent check nodes corresponding to the Hamming code constraint. The constraints of the RS code can be interpreted as being divided into a dimension related to the SPC code constraint and a dimension related to the Hamming code constraint. In what follows, the dimension related to the SPC code constraint is referred to as the first dimension, and the dimension related to the Hamming code constraint is referred to as the second dimension.

[0121] A check node group 1201 includes a check node corresponding to a first dimension. A check node group 1202 includes a check node corresponding to a second dimension. In this embodiment, the decoding of the RS code is realized by repeatedly executing the first-dimensional SISO decoding and the second-dimensional SISO decoding using a Tanner graph as shown in FIG.

[0122] FIG. 13 is a diagram for explaining the SPC code constraint and the Hamming code constraint. The codeword 1301 is a Galois field GF(2 8 ) with code length n=10, information length k=8, roots 1 and α(α is in GF(2 8 13. The codeword 1301 is a codeword of an RS code with sigma x = 10, sigma y ...

[0123] The exclusive OR (XOR) of the 10 bits in each column corresponds to the codeword of the SPC code. Note that a symbol with a "+" in a circle indicates a symbol that takes an exclusive OR. For example, the codeword 1311 corresponds to the codeword of the SPC code obtained by XORing the 10 bits in the fourth column. The constraint that each codeword of the SPC code is 0 corresponds to the SPC code constraint.

[0124] The codeword 1312 corresponds to the codeword of the Hamming code. Each bit of the codeword 1312 corresponds to a plurality of diagonal lines (hereinafter referred to as diagonal lines) as shown in FIG. 13, and is calculated by the XOR of one or more bits on the corresponding diagonal line. That the codeword 1312 satisfies the constraints of the Hamming code corresponds to the Hamming code constraints.

[0125] Hereinafter, the process of dividing the constraints of the RS code into two dimensions will be further described. First, the RS code will be described. FIG. 14 is a diagram showing an example of an RS frame. The RS frame is a unit of encoding and decoding of the RS code, and corresponds to the codeword 1301 in FIG. 13, for example.

[0126] Consider an RS code over the Galois field GF(2 m ) with code length n, information length (n - 2), and parity length 2. The maximum value of the code length n max is n max = 2 m - 1, and it is necessary to satisfy 3 ≤ n ≤ n max . When n < n max , it means that the code is shortened. Assume the roots are 1 and α. α is a primitive element over GF(2 m ).

[0127] The RS code (RS frame) contains n symbols. In FIG. 14, one row corresponds to one symbol. For example, symbol 1401 corresponds to one symbol of the RS code. The size of each symbol is m bits (the RS code is a multi - ary code). In FIG. 14, one cell represents 1 bit.

[0128] i (0 ≤ i < n) is an index representing which symbol it is. For example, the 0th and 1st (i = 0, 1) symbols correspond to parity symbols, and the remaining (i = 2 to n - 1) symbols correspond to information symbols. j (0 ≤ j < m) is an index representing which bit within the symbol it is.

[0129] Note that L = min(n max,n+m-1) is used in the following description.

[0130] Next, data used in the first-dimensional SISO decoding will be described. Hereinafter, data used in the first-dimensional SISO decoding will be referred to as first-dimensional data. As will be described later, the first-dimensional data includes a plurality of types of data.

[0131] FIG. 15 is a diagram for explaining the calculation procedure of the first dimensional data. i,j represents the LLR of the j-th bit of the i-th symbol contained in the RS frame. The number of elements of the first-dimensional data is m. The dashed arrow indicates the data contraction direction when calculating the first-dimensional data. Below, this direction may be referred to as the first-dimensional direction.

[0132] The first dimension data includes, for example, the following three pieces of data: 1st dimension XOR data · First dimension min1 data First dimension min2 data

[0133] Figure 16 shows the notations, number of elements, and calculation formulas for these three data. Each process will be explained below using these notations.

[0134] In addition, h(L i,j ) is L i,j represents the hard decision value of L i,j ≧0, h(L i,j )=0, and L i,j <0 when h(L i,j )=1. |L i,j | is L i,j represents the absolute value of .min represents the symbol taking the minimum value. In this embodiment, smin is used as the symbol taking the second smallest value.

[0135] The SISO decoding unit 182 receives the LLR (L i,j), the first-dimensional XOR data x, the first-dimensional min1 data y, and the first-dimensional min2 data z are used to calculate the first-dimensional extrinsic LLR data L according to the following equation (7). i,j (e1) Calculate.

number

[0136] s i,j is the value x of the first-dimension XOR data at position j j From LLR(L i,j ) is excluded. i,j is the absolute value of the LLR associated with position j (L 0,j ,L 1,j ,···,L n-1,j ) to L i,j It corresponds to the minimum value among the values ​​excluding. c represents the scale factor in the first dimension (hereinafter, the first dimension scale factor).

[0137] Next, data used in second-dimensional SISO decoding will be described. Hereinafter, data used in second-dimensional SISO decoding will be referred to as second-dimensional data. The second-dimensional data includes multiple types of data.

[0138] FIG. 17 is a diagram for explaining the calculation procedure for the second-dimensional data. The number of elements of the second-dimensional data is L=min(2 m -1, n+m-1). max =2 m -1, the number of elements L is the above L=min(n max ,n+m-1). The dashed arrow indicates the data contraction direction when calculating the second-dimensional data. Below, this direction may be referred to as the second-dimensional direction.

[0139] The second dimension data includes, for example, the following three pieces of data: 2nd Dimension XOR Data 2nd dimension min1 data 2nd dimensional min2 data

[0140] 18 is a diagram summarizing the notations, number of elements, and calculation formulas for these three data. Each process will be explained below using these notations.

[0141] In addition, the following notation "i+j≡l(mod 2 m -1)” is “i+j multiplied by 2 m This means "take the combination (i,j) such that when divided by -1, the remainder is l."

[0142] The SISO decoding unit 182 receives the LLR (L i,j ), the second-dimensional XOR data x', the second-dimensional min1 data y', and the second-dimensional min2 data z' are used to calculate the second-dimensional extrinsic LLR data L according to the following equation (8). i,j (e2) Calculate.

number

[0143] s' i,j is the value x' of the second-dimensional XOR data position l l From LLR(L i,j ) is excluded. i,j is the absolute value of the LLR associated with position l (L l,0 ,L l-1,1 ,L l-2,2 , ) to L i,j It corresponds to the minimum value among the values ​​excluding. c' represents the scale factor in the second dimension (hereinafter, the second-dimensional scale factor).

[0144] Next, a flow of the decryption process by the memory system 1 of the second embodiment will be described below. Fig. 19 is a flowchart showing an example of the decryption process by the memory system of the second embodiment.

[0145] The control unit 11 reads the error correction code from the non-volatile memory 20 and obtains the read information (step S601).

[0146] The SISO decoding unit 182 initializes an index p indicating the number of iterations to 1 (step S602). The SISO decoding unit 182 executes a first-dimensional process corresponding to the SISO decoding of the SPC code (step S603). The SISO decoding unit 182 executes a second-dimensional process corresponding to the SISO decoding of the Hamming code (step S604). The first-dimensional process and the second-dimensional process will be described in detail later.

[0147] The SISO decoding unit 182 determines whether or not to check the syndrome (step S605). For example, the SISO decoding unit 182 makes the determination by referring to a setting value indicating whether or not to check the syndrome. The setting value may be externally settable, for example.

[0148] When checking the syndrome (step S605: Yes), the SISO decoding unit 182 determines whether the syndrome is 0 (step S606). The SISO decoding unit 182 calculates the syndrome from the hard decision value of the posterior LLR, for example, and determines whether the calculated syndrome is 0.

[0149] If the syndrome is not 0 (step S606: No) and if it is determined in step S605 that the syndrome check is not to be performed (step S605: No), the SISO decoding unit 182 checks whether the index p is equal to or smaller than a predetermined maximum value p max It is determined whether it is equal to (step S607).

[0150] Index p is the maximum value p max If not (step S607: No), the SISO decoding unit 182 adds 1 to the index p (step S608), and returns to step S603 to repeat the process.

[0151] Index p is the maximum value p max(step S607: Yes) and if it is determined that the syndrome is 0 in step S606 (step S606: Yes), the SISO decoding unit 182 outputs the data of the processing result (step S609) and ends the decoding process.

[0152] Next, the first dimension processing and the second dimension processing will be described in detail. Here, the definitions of various data used in the description will be described. Figure 20 is a diagram summarizing the names, notations, and numbers of elements of multiple data used in the following description.

[0153] Each piece of data will be explained below. Channel LLR data: Data obtained by converting read information read from the non-volatile memory 20 into a sequence of LLRs (LLR data input to the decoder 18) LLR data 1: Data used to create second-dimensional data in first-dimensional processing. The first iteration is equal to the channel LLR data, and the second iteration and after is equal to the channel LLR data plus the second-dimensional extrinsic value LLR data. 1st-dimension XOR data: Data obtained by taking the exclusive OR in the 1st dimension using the hard decision value of LLR data 1. 1st dimension min1 data: Data that takes the minimum value in the 1st dimension direction using the absolute value of LLR data 1. 1st dimension min2 data: Data that takes the second smallest value in the 1st dimension using the absolute value of LLR data 1. 1st-dimension extrinsic value LLR data: Extrinsic value LLR for each bit obtained by 1st-dimension processing. It is calculated from 1st-dimension XOR data, 1st-dimension min1 data, and 1st-dimension min2 data. LLR data 2: Data used to create second-dimensional data in second-dimensional processing. It is equal to the data obtained by adding the first-dimensional extrinsic value LLR data to the channel LLR data. 2nd-dimensional XOR data: Data obtained by taking the exclusive OR in the 2nd dimension using the hard decision value of LLR data 2. 2nd dimension min1 data: Data obtained by taking the minimum value in the 2nd dimension direction using the absolute value of LLR data 2. 2nd dimension min2 data: Data that takes the second smallest value in the 2nd dimension using the absolute value of LLR data 2. Hamming code input LLR data: Data calculated from 2nd-dimensional XOR data and 2nd-dimensional min1 data. Hamming code extrinsic LLR data: Extrinsic LLR data obtained by performing SISO decoding of the Hamming code using the Hamming code input LLR data. Used to update the 2nd-dimension XOR data, 2nd-dimension min1 data, and 2nd-dimension min2 data. 2nd-dimension extrinsic value LLR data: Extrinsic value LLR for each bit obtained by 2nd-dimension processing. It is calculated from 2nd-dimension XOR data, 2nd-dimension min1 data, and 2nd-dimension min2 data. A posteriori LLR data: A posteriori LLR for each bit obtained as a result of the decoding process. It is equal to the data obtained by adding the first-dimension extrinsic value LLR data and the second-dimension extrinsic value LLR data to the channel LLR data.

[0154] Next, the first dimension processing will be described with reference to a flowchart shown in FIG.

[0155] The SISO decoding unit 182 determines whether or not the index p is equal to 1 (step S701). If the index p is equal to 1 (step S701: Yes), the SISO decoding unit 182 sets the channel LLR data as LLR data 1, as shown in the following equation (9) (step S702).

number

[0156] If the index p is not equal to 1 (step S701: No), the SISO decoding unit 182 sets the value obtained by adding the second-dimensional extrinsic value LLR data to the channel LLR data as LLR data 1 (step S703), as shown in the following equation (10).

number

[0157] The SISO decoding unit 182 calculates the first-dimensional XOR data, the first-dimensional min1 data, and the first-dimensional min2 data (step S704) using the LLR data 1. For example, the SISO decoding unit 182 calculates these data according to the procedure described with reference to FIGS.

[0158] The SISO decoding unit 182 calculates the first-dimension extrinsic value LLR data by using the calculated first-dimension XOR data, the first-dimension min1 data, and the first-dimension min2 data, for example, according to the above equation (7) (step S705).

[0159] The SISO decoding unit 182 calculates LLR data 2 by adding the first-dimension extrinsic value LLR data to the channel LLR data as shown in the following equation (11) (step S706), and ends the first-dimension processing.

number

[0160] Next, the second dimension processing will be described with reference to a flowchart shown in FIG.

[0161] The SISO decoding unit 182 calculates the second-dimensional XOR data, the second-dimensional min1 data, and the second-dimensional min2 data (step S801) using the LLR data 2. For example, the SISO decoding unit 182 calculates these data according to the procedure described with reference to FIGS.

[0162] The SISO decoding unit 182 uses the calculated second-dimensional XOR data and second-dimensional min1 data to calculate Hamming code input LLR data, for example, by the following equation (12) (step S802).

number

[0163] The SISO decoding unit 182 executes SISO decoding of the Hamming code and calculates Hamming code extrinsic value LLR data (step S803). The SISO decoding of the Hamming code is executed in the same procedure as in the first embodiment, for example.

[0164] The SISO decoding unit 182 updates the second-dimensional XOR data, the second-dimensional min1 data, and the second-dimensional min2 data using the Hamming code extrinsic value LLR data (step S804). The SISO decoding unit 182 updates the second-dimensional XOR data, for example, by the following equation (13).

number

[0165] The SISO decoding unit 182 updates the second-dimension min1 data and the second-dimension min2 data in the following procedure. ·|L l (eh) | <y’ l Then, first, z' l y' l Then update with y' l |L l (eh) Update with |. ·y' l ≦|L l (eh) | <z’ l Then, z' l |L l (eh) Update with |. ·z' l <|L l (eh) If |, no update is performed.

[0166] The SISO decoding unit 182 calculates the second-dimensional extrinsic value LLR data by using the second-dimensional XOR data, the second-dimensional min1 data, and the second-dimensional min2 data, for example, according to the above equation (8) (step S805).

[0167] The SISO decoding unit 182 calculates the posterior value LLR data by adding the second-dimensional extrinsic value LLR data to the LLR data 2, for example, as shown in the following equation (14) (step S806).

number

[0168] Next, an example of the data output process in step S609 will be described. The data to be output may be, for example, a posteriori LLR or a hard decision value (decoded word) of the a posteriori LLR.

[0169] The posteriori LLR may be expressed in the form of, for example, the following formula (15). The method of outputting the posteriori LLR corresponds to a use case in which it is desired to output not only the hard decision value (0 or 1) of each bit but also probability information.

number

[0170] The hard decision value of the a posteriori LLR may be expressed in the form of, for example, the following formula (16). The method of outputting the hard decision value of the a posteriori LLR corresponds to a use case in which it is sufficient to output a hard decision value (0 or 1) for each bit, for example.

number

[0171] As described above, in the second embodiment, the same method as in the first embodiment is applied to the decoding of the Hamming code included as an internal structure in the RS code, thereby making it possible to reduce the amount of calculation required for decoding the RS code.

[0172] (Third embodiment) In the third embodiment, a decoding method (turbo decoding) is used that repeatedly performs SISO decoding on a concatenated code of the RS code of the second embodiment and a code CA (first code) different from the RS code. The same method as in the second embodiment is applied to the decoding of the RS code included in the concatenated code.

[0173] Fig. 23 is a conceptual diagram showing a decoding method of the third embodiment. As shown in Fig. 23, in this embodiment, soft decision information obtained by SISO decoding using the code CA and soft decision information obtained by SISO decoding using the RS code are exchanged between each other, and decoding is repeated. The RS code includes a plurality of SPC code groups and a Hamming code as an internal structure. The code CA may be any code, and is, for example, the following code. ·Generalized LDPC code (Generalized Low Density Parity Check Code) ·BCH (Bose-Chandhuri-Hocquenghem) code Multidimensional error-correcting codes (such as product codes) in which symbols are multiply protected by multiple smaller component codes

[0174] First, the code (concatenated code) used in this embodiment will be described. Fig. 24 is a diagram for explaining an example of the code used in the third embodiment. As shown in Fig. 24, the code of this embodiment includes a plurality of RS frames and a plurality of ECC (Error Correcting Code) frames.

[0175] The RS frame is in the Galois field GF(2 m ) In this embodiment, the size of one symbol is m bits. In the following, m bits are assumed to be 1 byte. The RS frame is an RS code with a code length of n (bytes), an information length of (n-2) (bytes), and a parity length of 2 (bytes). The part corresponding to the parity length 2 corresponds to the RS parity 2411. There are two roots, 1 and α. α is a function of GF(2 m ) is a primitive element on

[0176] The ECC frame is a code with a code length N (bytes) and an information length K (bytes) (K is a natural number smaller than N). The part corresponding to the difference between the code length N and the information amount K corresponds to the ECC parity 2412.

[0177] In the example of FIG. 24, the range corresponding to the information length K of the ECC frame is protected by K RS frames. Note that the range protected by the RS frame does not have to be K (bytes), and it may be shorter or longer than K (bytes).

[0178] The entire RS frame described in FIG. 14 corresponds to one RS frame in FIG. 24 (for example, corresponding to RS frame 2401. That is, in FIG. 24, one cell represents m bits (= 1 byte). i (0 ≦ i < n) is an index representing which ECC frame it is. Hereinafter, for convenience of explanation, the ECC frame to be corrected is set to i = n - 1. In FIG. 24, ECC frame 2402 corresponds to the (n - 1)th ECC frame. r (0 ≦ r < N) is an index representing which RS frame it is. j (0 ≦ j < m) is an index representing which bit in the symbol (byte) it is. Thus, compared with the second embodiment, in this embodiment, an index r representing which RS frame it is is added.

[0179] FIG. 25 is a diagram summarizing the names, notations, and numbers of elements of a plurality of data used in the description of the third embodiment.

[0180] Hereinafter, each data will be described. ·LLR data 1: Data used when creating first-dimensional data in the first-dimensional process. In this embodiment, the read information read from the non-volatile memory 20 is converted into a series of LLRs, that is, equal to the channel LLR. ·Decoded word data: Data obtained when soft-bit decoding (SB decoding) of the ECC frame is successful. 1st-dimension XOR data: Data obtained by taking the exclusive OR in the 1st dimension direction of the hard decision values ​​of all ECC frames. Note that the hard decision value represents the decoded word data for ECC frames that are successfully decoded (hereinafter, "decoded successfully ECC frames"), and represents the hard decision value of LLR data 1 for ECC frames that are unsuccessful in decoding (hereinafter, "decoded unsuccessful ECC frames"). 1st dimension min1 data: Data that takes the minimum value in the 1st dimension direction for the absolute value of LLR data 1 of the decoded unsuccessful ECC frame. 1st dimension min2 data: Data that has the second smallest absolute value in the 1st dimension for LLR data 1 of the decoded ECC frame. First-dimensional extrinsic value LLR data: Extrinsic value LLR for each bit obtained by first-dimensional processing. LLR data 2: Data used to create second-dimensional data in second-dimensional processing. It is equal to the data obtained by adding the first-dimensional extrinsic value LLR data to the channel LLR data. 2nd-dimension XOR data: Data obtained by taking the exclusive OR of the "hard decision values" of all ECC frames in the 2nd dimension. Note that the "hard decision value" refers to the decoded word data for successful decoding ECC frames, and the hard decision value of LLR data 2 for unsuccessful decoding ECC frames. 2nd dimension min1 data: Data that takes the minimum value in the 2nd dimension direction for the absolute value of LLR data 2 of the decoded ECC frame. Second-dimension min2 data: The data that has the second smallest absolute value in the second dimension for the LLR data 2 of the decoded ECC frame. Hamming code extrinsic LLR data: Extrinsic LLR data obtained by performing SISO decoding of the Hamming code using the Hamming code input LLR data calculated from the second-dimensional XOR data and the second-dimensional min1 data. Used to update the second-dimensional XOR data, second-dimensional min1 data, and second-dimensional min2 data. 2nd-dimension extrinsic value LLR data: Extrinsic value LLR for each bit obtained by 2nd-dimension processing. It is calculated from 2nd-dimension XOR data, 2nd-dimension min1 data, and 2nd-dimension min2 data. ·LLR data 3: The posterior LLR for each bit obtained as a result of the decoding process by the RS code. It is equal to the data obtained by adding the first-dimensional extrinsic value LLR data and the second-dimensional extrinsic value LLR data to the channel LLR data.

[0181] As described above, when taking the minimum value or the second smallest value, the decryption failure ECC frame is targeted, and the decryption success ECC frame is not targeted. This is because in the decryption success ECC frame, the decrypted word has been obtained, and all bits can be regarded as highly reliable, and there is no need to consider them when calculating the minimum value or the second smallest value.

[0182] Note that f used in the calculation of the number of elements in FIG. 25 represents the number of decryption failure ECC frames. Since it is not necessary to execute the decryption process of the ECC frame again in the decryption success ECC frame, there is data that only needs to be prepared for the number of decryption failure ECC frames. The data whose number of elements is calculated using the number of decryption failure ECC frames f in FIG. 25 corresponds to such data.

[0183] Also, l (0 ≦ l < L) used in the notation of FIG. 25 is an index representing which data in the second dimension direction of the RS frame.

[0184] Next, the flow of the decoding process by the memory system 1 of the third embodiment will be described. FIG. 26 is a flowchart showing an example of the decoding process by the memory system of the third embodiment.

[0185] Note that the decoding process of this embodiment is mainly divided into the following three processes. The details of the three processes will be described in FIGS. 27 to 30 below. · Decoding process for ECC frame (first time): Steps S901 to S903 · Decoding process for RS frame: Steps S906, S907 · Decoding process for ECC frame (other than the first time): Steps S908 to S910

[0186] The SISO decoding unit 182 executes soft bit decoding (SB decoding) on ​​the ECC frame to be corrected (step S901). The SB decoding is, for example, SISO decoding that inputs a soft decision input value and outputs a soft decision output value.

[0187] The SISO decoding unit 182 determines whether the decoding is successful (step S902). If the decoding is not successful (step S902: No), the SISO decoding unit 182 executes SB decoding on ECC frames other than the ECC frame to be corrected (step S903).

[0188] The SISO decoding unit 182 determines whether or not to end the iterative correction (step S904). For example, the SISO decoding unit 182 determines to end the iterative correction when the following conditions are satisfied: The number of iterations has reached the set number. - The number of ECC frames that have failed decoding is greater than the threshold (EF threshold). - The number of ECC frames that failed to decode has not decreased since the previous iteration

[0189] If iterative correction is not to be ended (step S904: No), the SISO decoding unit 182 determines whether the number of decoding-failure ECC frames is 2 or less (step S905). If the number of decoding-failure ECC frames is not 2 or less (step S905: No), the SISO decoding unit 182 executes RS first-dimensional processing (step S906) and RS second-dimensional processing (step S907). The RS first-dimensional processing corresponds to SISO decoding in the first dimension direction of the RS code. The RS second-dimensional processing corresponds to SISO decoding in the second dimension direction of the RS code.

[0190] Thereafter, the SISO decoding unit 182 executes the second and subsequent (other than the first) decoding processes on the ECC frame. That is, the SISO decoding unit 182 corrects the LLR data of the ECC frame to be corrected, and executes SB decoding (step S908).

[0191] The SISO decoding unit 182 determines whether the decoding is successful (step S909). If the decoding is not successful (step S909: No), the SISO decoding unit 182 corrects the LLR data in the ECC frame that has failed to be decoded other than the ECC frame to be corrected, executes SB decoding (step S910), and returns to step S904 to repeat the process.

[0192] If it is determined in step S904 that the iterative correction is to be ended (step S904: Yes), the SISO decoding unit 182 notifies an external control unit or the like of a failure in decoding (step S911), and ends the decoding process.

[0193] If it is determined in step S905 that the number of decoded unsuccessfully ECC frames is two or less (step S905: Yes), the SISO decoding unit 182 performs erasure correction to correct errors (step S912).

[0194] After the erasure correction, if it is determined in step S902 that the decoding is successful (step S902: Yes), and if it is determined in step S909 that the decoding is successful (step S909: Yes), the SISO decoding unit 182 notifies an external control unit or the like of the success of the decoding and the decoded word (step S913), and ends the decoding process.

[0195] Next, details of the decoding process (first time) on an ECC frame, which corresponds to steps S901 to S903 in Fig. 26, will be described with reference to Fig. 27. Fig. 27 is a flowchart showing an example of the decoding process (first time) on an ECC frame.

[0196] The SISO decoding unit 182 executes an initialization process for each piece of data used in decoding (step S1001). For example, the SISO decoding unit 182 initializes each piece of data as follows. First dimension XOR data, second dimension XOR data: Initialize all elements to 0 1st dimension min1 data, 1st dimension min2 data, 2nd dimension min1 data, 2nd dimension min2 data: Initialize all elements with the maximum LLR value

[0197] The SISO decoder 182 sets i to n - 1 (step S1002). The SISO decoder 182 performs SB decoding using the LLR data 1 of the i-th ECC frame (step S1003).

[0198] The SISO decoder 182 determines whether the decoding was successful (step S1004). If the decoding was successful (step S1004: Yes), the SISO decoder 182 determines whether i = n - 1 holds (step S1005). If i = n - 1 (step S1005: Yes), the SISO decoder 182 ends the process as a successful decoding (step S1006).

[0199] If i ≠ n - 1 (step S1005: No), the SISO decoder 182 updates the first-dimensional XOR data and the second-dimensional XOR data using the decoded word data of the i-th ECC frame (step S1007).

[0200] For example, the SISO decoder 182 updates the first-dimensional XOR data x r,j by the following equation (17). Also, the SISO decoder 182 updates the second-dimensional XOR data x' r,j by the following equation (18). [Number] [Number]

[0201] In equations (17) and (18), i is fixed, and r and j take all combinations in the range 0 ≤ r < K, 0 ≤ j < m. l is a value that satisfies l ≡ i + j (mod 2 m - 1).

[0202] If it is determined that the decoding has failed in step S1004 (step S1004: No), the SISO decoder 182 updates the first-dimensional XOR data, the first-dimensional min1 data, and the first-dimensional min2 data using the LLR data 1 of the i-th ECC frame (step S1008).

[0203] For example, the SISO decoder 182 updates the first-dimensional XOR data x r,j by the following equation (19). Similar to equations (17) and (18), i is fixed, and r and j take all combinations in the range of 0 ≦ r < K and 0 ≦ j < m.

Equation

[0204] The SISO decoder 182 updates the first-dimensional min1 data y r,j , and the first-dimensional min2 data z r,j by the following procedure. i is fixed, and r and j take all combinations in the range of 0 ≦ r < K and 0 ≦ j < m. ·When |L r,i,j (1) | < y r,j , first, z r,j is updated with y r,j , and then y r,j is updated with |L r,i,j (1) |. ·When y r,j ≦ |L r,i,j (1) | < z r,j , z r,j is updated with |L r,i,j (1) |. ·When z r,j < |L r,i,j (1) |, no update is performed.

[0205] After steps S1007 and S1008, the SISO decoding unit 182 determines whether i=0 is true (step S1009). If i=0 is not true (step S1009: No), the SISO decoding unit 182 subtracts 1 from i (step S1010) and returns to step S1003 to repeat the process. If i=0 is true (step S1009: Yes), the SISO decoding unit 182 ends the process.

[0206] In this way, when decoding is successful (step S1004: Yes), both the first dimension data and the second dimension data are updated. Note that when decoding is successful, there is no need to update the min1 data and the min2 data. Also, when decoding fails (step S1004: No), only the first dimension data is updated. This is because the first dimension data is calculated using the channel LLR data, while the second dimension data is updated using LLR data 2, that is, data obtained by adding the first dimension extrinsic value LLR data to the channel LLR data.

[0207] Next, details of the RS first dimension processing in step S906 will be described with reference to Fig. 28. Fig. 28 is a flowchart showing an example of the RS first dimension processing.

[0208] The SISO decoding unit 182 initializes the second-dimension min1 data and the second-dimension min2 data (step S1101). For example, the SISO decoding unit 182 initializes all elements of the second-dimension min1 data and the second-dimension min2 data to the maximum value of LLR.

[0209] The SISO decoding unit 182 sets i to n-1 (step S1102). The SISO decoding unit 182 determines whether or not the i-th ECC frame is a decoding-failed ECC frame (step S1103).

[0210] When it is an ECC frame with decoding failure (step S1103: Yes), the SISO decoder 182 calculates the first-dimensional extrinsic value LLR data by the following equation (20) using the LLR data 1, the first-dimensional XOR data, the first-dimensional min1 data, and the first-dimensional min2 data (step S1104).

[0211] [Number]

[0212] Comparing with the equation (7) used in the second embodiment, the equation (20) is different in that the subscript r is added.

[0213] The SISO decoder 182 calculates the LLR data 2 by adding the first-dimensional extrinsic value LLR data to the LLR data 1 as shown in the following equation (21) (step S1105). i is fixed, and r and j take all combinations in the range of 0 ≤ r < K and 0 ≤ j < m. [Number]

[0214] The SISO decoder 182 updates the second-dimensional XOR data using the LLR data 2 as shown in the following equation (22) (step S1106). i is fixed, and r and j take all combinations in the range of 0 ≤ r < K and 0 ≤ j < m. l is a value that satisfies l ≡ i + j (mod 2 m -1). [Number]

[0215] The SISO decoder 182 updates the second-dimensional min1 data y’ r,j , the second-dimensional min2 data z’ r,j using the LLR data 2 by the following procedure (step S1107). i is fixed, and r and j take all combinations in the range of 0 ≤ r < K and 0 ≤ j < m. l is a value that satisfies l ≡ i + j (mod 2 m-1). ·|L r,i,j (2) | <y’ r,l Then, first, z' r,l y' r,l Then update with y' r,l |L r,i,j (2) Update with |. ·y' r,l ≦|L r,i,j (2) | <z’ r,l Then, z' r,l |L r,i,j (2) Update with |. ·z' r,l <|L r,i,j (2) If |, no update is performed.

[0216] After step S1107, or if it is determined in step S1103 that the ECC frame is not a decoding failure ECC frame (step S1103: No), the SISO decoding unit 182 determines whether i=0 holds (step S1108). If i=0 does not hold (step S1108: No), the SISO decoding unit 182 subtracts 1 from i (step S1109) and returns to step S1103 to repeat the process.

[0217] If i=0 (step S1108: Yes), the first-dimension min1 data and the first-dimension min2 data are initialized for the next iterative process (step S1110), and the RS first-dimension process is terminated. For example, the SISO decoding unit 182 initializes all elements of the first-dimension min1 data and the first-dimension min2 data with the maximum LLR value. Note that the first-dimension XOR data and the second-dimension XOR data are updated every time a difference occurs, so they do not need to be initialized for each iteration.

[0218] Next, details of the RS two-dimensional processing in step S907 will be described with reference to Fig. 29. Fig. 29 is a flowchart showing an example of the RS two-dimensional processing.

[0219] The SISO decoder 182 initializes r to 0 (step S1201). The SISO decoder 182 calculates the Hamming code input LLR data of the r-th RS frame using the second-dimensional XOR data and the second-dimensional min1 data according to the following equation (23) (step S1202).

Number

[0220] The SISO decoder 182 performs SISO decoding of the Hamming code in the r-th RS frame and calculates the Hamming code external value LLR data (step S1203). The SISO decoding of the Hamming code is performed, for example, in the same procedure as in the first embodiment.

[0221] The SISO decoder 182 updates the second-dimensional XOR data, the second-dimensional min1 data, and the second-dimensional min2 data using the Hamming code external value LLR data of the r-th RS frame (step S1204).

[0222] The SISO decoder 182 updates the second-dimensional XOR data, for example, according to the following equation (24). Note that r is fixed and l satisfies 0 ≦ l < L.

Number

[0223] Also, the SISO decoder 182 updates the second-dimensional min1 data y’ r,j , the second-dimensional min2 data z’ r,j according to the following procedure. r is fixed and l satisfies 0 ≦ l < L. ·|L r,l (eh) |<y’ r,l When, first, z’ r,l is updated with y’ r,l , and then y’ r,l is updated with |L r,l (eh) . ·y’ r,l ≦|L r,l(eh) | <z’ r,l Then, z' r,l |L r,l (eh) Update with |. ·z' r,l <|L r,l (eh) If |, no update is performed.

[0224] The SISO decoding unit 182 determines whether r=K-1 is true (step S1205). If r=K-1 is not true (step S1205: No), the SISO decoding unit 182 adds 1 to r (step S1206) and returns to step S1202 to repeat the process.

[0225] If r=K−1 is satisfied (step S1205: Yes), the SISO decoding unit 182 ends the RS second-dimensional process.

[0226] Next, details of the decoding process (other than the first time) on an ECC frame, which corresponds to steps S908 to S910 in Fig. 26, will be described with reference to Fig. 30. Fig. 30 is a flowchart showing an example of the decoding process (other than the first time) on an ECC frame.

[0227] The SISO decoding unit 182 sets i to n-1 (step S1301). The SISO decoding unit 182 determines whether or not the i-th ECC frame is a decoding-failed ECC frame (step S1302).

[0228] If the ECC frame is a decoded unsuccessfully (step S1302: Yes), the SISO decoding unit 182 uses the LLR data 2, the second-dimensional XOR data, the second-dimensional min1 data, and the second-dimensional min2 data to calculate the second-dimensional extrinsic value LLR data by the following equation (25) (step S1303).

number

[0229] The SISO decoder 182 calculates the LLR data 3 by adding the second - dimensional extrinsic value LLR data to the LLR data 2 according to the following equation (26) (step S1304). i is fixed, and r and j take all combinations in the range of 0 ≤ r < K, 0 ≤ j < m.

Number

[0230] The SISO decoder 182 performs SB decoding using the LLR data 3 (step S1305). The SISO decoder 182 determines whether the decoding is successful (step S1306).

[0231] If the decoding is successful (step S1306: Yes), and if it is determined in step S1302 that the frame is not a decoding - failed ECC frame (step S1302: No), the SISO decoder 182 determines whether i = n - 1 holds (step S1307). If i = n - 1 (step S1307: Yes), the SISO decoder 182 ends the process as a successful decoding (step S1308).

[0232] If i ≠ n - 1 (step S1307: No), the SISO decoder 182 updates the first - dimensional XOR data and the second - dimensional XOR data using the decoded word data (step S1309). For example, the SISO decoder 182 updates the first - dimensional XOR data x r,j according to the following equation (27). i is fixed, and r and j take all combinations in the range of 0 ≤ r < K, 0 ≤ j < m.

Number

[0233] Also, the SISO decoder 182 updates the second - dimensional XOR data x' r,j according to the following equation (28). i is fixed, and r and j take all combinations in the range of 0 ≤ r < K, 0 ≤ j < m. l is a value that satisfies l ≡ i + j (mod 2 m - 1). [Number]

[0234] If it is determined that the decoding fails in step S1306 (step S1306: No), the SISO decoder 182 updates the first-dimensional min1 data and min2 data using the LLR data 1 (step S1310).

[0235] For example, the SISO decoder 182 updates the first-dimensional min1 data y r,j , and the first-dimensional min2 data z r,j as follows. i is fixed, and r and j take all combinations in the range of 0 ≦ r < K and 0 ≦ j < m. ·When |L r,i,j (1) | < y r,j , first, z r,j is updated with y r,j , and then y r,j is updated with |L r,i,j (1) |. ·When y r,j ≦ |L r,i,j (1) | < z r,j , z r,j is updated with |L r,i,j (1) |. ·When z r,j < |L r,i,j (1) |, no update is performed.

[0236] After steps S1309 and S1310, the SISO decoder 182 determines whether i = 0 holds (step S1311). If i ≠ 0 (step S1311: No), the SISO decoder 182 subtracts 1 from i (step S1312) and returns to step S1302 to repeat the process. If i = 0 (step S1311: Yes), the SISO decoder 182 ends the process.

[0237] As described above, in the third embodiment, when a decoding method that repeatedly executes SISO decoding between an RS code and another code is used, the same method as in the first embodiment is applied to the decoding of a Hamming code included as an internal structure in the RS code, thereby making it possible to reduce the amount of calculation required for decoding the RS code.

[0238] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0239] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffer 13 Memory I / F 14 Encoding / Decoding Section 15 Host I / F 16 Internal Bus 17 Encoder 18 Decoder 20 Non-volatile memory 30 Host

Claims

1. a non-volatile memory that stores an error correction code including a Hamming code; Reading read information from the non-volatile memory; Calculating a syndrome using hard decision values ​​corresponding to the soft decision input values ​​based on the read information; determining a plurality of decoded words based on the syndrome; calculating a plurality of metrics representative of distances between each of a plurality of said decoded words and said soft decision input values; storing the metric calculated for the first decoded word as a metric for a bit corrected by the first decoded word included in the plurality of decoded words in a metric array including a plurality of metrics corresponding to a plurality of bits included in the plurality of decoded words; storing a first metric in a first metric memory, the first metric being the smallest of the plurality of metrics calculated for the plurality of decoded words; storing a second metric that is a second smallest of the plurality of metrics in a second metric memory; calculating a soft-decision output value indicating a decoding result for the soft-decision input value using the soft-decision input value, the plurality of metrics stored in the metric array, the first metric, and the second metric; A memory controller; A memory system comprising:

2. The memory controller includes: For bit i of address i (i is an integer satisfying 0≦i≦n−1) included in n bits (n is an integer equal to or greater than 2) of the metric array, ｉ If the first metric is equal to the metric m ｉ Metric m of bit i is calculated by subtracting the second metric from ｉ If metric m is not equal to the first metric, ｉ a subtraction value obtained by subtracting the first metric from the soft-decision input value, and calculating a posterior value, which is a multiplication result of the calculated subtraction value and the sign of the bit of the address i of the soft-decision input value, as the value of the bit of the address i of the soft-decision output value.

2. The memory system of claim 1.

3. The memory controller includes: For bit i of address i (i is an integer satisfying 0≦i≦n−1) included in n bits (n is an integer equal to or greater than 2) of the metric array, ｉ If the first metric is equal to the metric m ｉ Metric m of bit i is calculated by subtracting the second metric from ｉ If metric m is not equal to the first metric, ｉ a subtraction value obtained by subtracting the first metric from the first metric, a posterior value which is a multiplication result of the calculated subtraction value and the sign of the bit of the address i of the soft decision input value, and a value based on an extrinsic value obtained by subtracting the value of the bit of the address i of the soft decision input value from the calculated posterior value is calculated as the value of the bit of the address i of the soft decision output value.

2. The memory system of claim 1.

4. The memory controller includes: a value obtained by multiplying the extrinsic value by a predetermined scale coefficient, which is greater than 0 and equal to or less than 1, is calculated as a value of a bit at address i of the soft decision output value; 4. The memory system of claim 3.

5. The memory controller includes: obtaining a plurality of the decoded words by inverting one or more bits among a plurality of bits included in the hard decision value; 2. The memory system of claim 1.

6. The memory controller includes: Obtaining the plurality of decoded words by OSD (Ordered Statistics Decoding); 2. The memory system of claim 1.

7. The memory controller includes: storing a sum of an absolute value of the soft decision input value for the first bit and a value obtained by multiplying an average value of the absolute values ​​of the soft decision input values ​​for the plurality of bits by 2 as a metric for a first bit for which no decoded word to be corrected is found among the plurality of bits; 2. The memory system of claim 1.

8. The memory controller includes: storing a sum of an absolute value of the soft decision input value at a first bit for which no decoded word to be corrected is found among the plurality of bits and a predetermined fixed value as a metric for the first bit; 2. The memory system of claim 1.

9. The memory controller includes: setting a predetermined fixed value as the soft decision output value for a first bit for which no decoded word to be corrected is found among the plurality of bits; 2. The memory system of claim 1.

10. the error correction code is a Reed-Solomon (RS) code, The memory controller includes: Decoding the RS code as a combination of a single parity check code and a Hamming code, and performing decoding of the single parity check code and decoding of the Hamming code; calculating the soft decision input value to be used as an input for decoding the Hamming code when decoding the Hamming code is performed; 2. The memory system of claim 1.

11. the error-correcting code is a concatenated code of an RS (Reed-Solomon) code and a first code different from the RS code, The memory controller includes: Decoding the first code and decoding the RS code; When performing decoding of the RS code, the RS code is regarded as a combination of a single parity check code and a Hamming code, and a single parity check code and a Hamming code are decoded; calculating the soft decision input value to be used as an input for decoding the Hamming code when decoding the Hamming code is performed; 2. The memory system of claim 1.

12. A control method executed by a memory controller that controls a non-volatile memory that stores an error correction code including a Hamming code, comprising: Reading read information from the non-volatile memory; Calculating a syndrome using hard decision values ​​corresponding to the soft decision input values ​​based on the read information; determining a plurality of decoded words based on the syndrome; calculating a plurality of metrics representative of distances between each of a plurality of said decoded words and said soft decision input values; storing the metric calculated for the first decoded word as a metric for a bit corrected by the first decoded word included in the plurality of decoded words in a metric array including a plurality of metrics corresponding to a plurality of bits included in the plurality of decoded words; storing a first metric in a first metric memory, the first metric being the smallest of the plurality of metrics calculated for the plurality of decoded words; storing a second metric that is a second smallest of the plurality of metrics in a second metric memory; calculating a soft-decision output value indicating a decoding result for the soft-decision input value using the soft-decision input value, the plurality of metrics stored in the metric array, the first metric, and the second metric; The control method includes:

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