Inkjet head driving circuit

Abstract

To provide an inkjet head driving circuit configured to prevent a protection function from being invalidated unintentionally.SOLUTION: An inkjet head driving circuit according to an embodiment comprises: a driving part that drives an actuator; a protection circuit that executes a protection function of the inkjet head driving circuit; and a setting data register that stores setting data including specified data of a plurality of bits for designating validation or invalidation of the protection function and outputs the specified data of the plurality of bits to the protection circuit. The protection circuit invalidates the protection function only when each bit value of the specified data of the plurality of bits matches each bit value of invalidation designated data of a plurality of bits for designating invalidation of the protection function. The protection circuit validates the protection function when each bit value of the specified data of the plurality of bits does not match each bit value of the invalidation designation data of the plurality of bits.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to an inkjet head drive circuit. [Background technology]

[0002] Generally, an inkjet head has a pressure chamber that contains ink, an actuator that expands and contracts the pressure chamber, and an inkjet head drive circuit that drives the actuator. The inkjet head drive circuit expands and contracts the pressure chamber with the actuator, causing ink to be ejected from a nozzle that communicates with the pressure chamber. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-050492 A Summary of the Invention [Problem to be solved by the invention]

[0004] In general, an inkjet head drive circuit has protection functions such as a thermal shutdown function to prevent abnormal heat generation, and a function to prevent short circuits caused by switching elements with different power levels being turned on simultaneously.

[0005] However, there are cases where you may want to disable the protection function, such as when you want to perform operation tests in a high-temperature environment or at high temperatures due to overload, or when you want to set different power supply levels to the same potential and drive the switch elements by turning them on simultaneously.

[0006] Protection functions are disabled by setting data. However, protection functions can be unintentionally disabled due to incorrect settings or bit errors. It is desirable to prevent unintentional disabling of protection functions as much as possible.

[0007] An object of the present invention is to provide an inkjet head drive circuit that prevents unintentional disabling of a protection function. [Means for solving the problem]

[0008] An inkjet head drive circuit according to an embodiment includes a drive unit that drives an actuator that expands and contracts a pressure chamber that contains ink to eject ink from a nozzle, a protection circuit that executes a protection function of the inkjet head drive circuit, and a setting data register that stores setting data including multiple-bit designation data that designates whether the protection function is enabled or disabled and outputs the multiple-bit designation data to the protection circuit. The protection circuit disables the protection function only when each bit value of the multiple-bit designation data matches each bit value of multiple-bit disable designation data that designates the disablement of the protection function. The protection circuit enables the protection function when each bit value of the multiple-bit designation data does not match each bit value of the multiple-bit disable designation data. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an inkjet printer including an inkjet head drive circuit according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of a conventional inkjet head driving circuit. [Diagram 3] FIG. 3 is a diagram showing an example of a register map of setting data relating to enabling and disabling of a protection function according to a conventional example. [Figure 4] FIG. 4 is a diagram showing specific register values ​​indicating enablement and disablement in the register map of the setting data shown in FIG. [Diagram 5] FIG. 5 is a block diagram showing an example of the configuration of an inkjet head driving circuit according to an embodiment of the present invention. [Figure 6] FIG. 6 is a diagram showing an example of a register map of setting data related to enabling and disabling of protection functions according to an embodiment. [Figure 7]FIG. 7 is a diagram showing specific register values ​​indicating enablement and disablement in the register map of the setting data shown in FIG. [Figure 8] FIG. 8 is a diagram showing a truth table of a logic circuit based on a combination of multiple bits. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of a gate driver of an inkjet head driving circuit. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a waveform pattern generating section of an inkjet head driving circuit. [Figure 11] FIG. 11 is a diagram showing an example of an ON switch that is enabled by disabling the short circuit prevention function. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Inkjet printer) First, an inkjet printer 200 having an inkjet head 100 including an inkjet head driving circuit 101 according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of the inkjet printer 200. In the following description, the inkjet printer 200 will be abbreviated as printer 200, the inkjet head 100 will be abbreviated as head 100, and the inkjet head driving circuit 101 will be abbreviated as head driving circuit 101.

[0011] The printer 200 has a head 100. The head 100 has a head drive circuit 101 and an actuator group 102. The actuator group 102 has a plurality of actuators. Each actuator is a drive element for expanding and contracting a pressure chamber that contains ink, and ejecting ink droplets from a nozzle that communicates with the pressure chamber. For example, each actuator is a piezoelectric drive element made of PZT (lead zirconate titanate). The head drive circuit 101 is a circuit that generates a drive signal for the actuator group 102. Each actuator of the actuator group 102 operates according to the drive signal supplied from the head drive circuit 101 to expand and contract a pressure chamber, and eject ink droplets from a nozzle.

[0012] In addition to the head 100, the printer 200 has a processor 201, a ROM (Read Only Memory) 202, a RAM (Random Access Memory) 203, an operation panel 204, a communication interface 205, a conveying motor 206, a motor drive circuit 207, a pump 208, and a pump drive circuit 209. In the drawings, the interface is abbreviated as "IF."

[0013] The printer 200 also has bus lines 210 such as an address bus and a data bus. The processor 201, ROM 202, RAM 203, operation panel 204, communication interface 205, motor drive circuit 207, pump drive circuit 209, and head drive circuit 101 are connected to the bus line 210 directly or via an input / output circuit, and can transmit and receive data among them.

[0014] The processor 201 corresponds to the central part of a computer. The processor 201 controls each part to realize various functions of the printer 200 according to an operating system and application programs. The processor 201 is, for example, a CPU (Central Processing Unit).

[0015] The ROM 202 corresponds to a read-only main memory of the computer. The ROM 202 stores the operating system and application programs. The ROM 202 may also store data necessary for the processor 201 to execute processes for controlling each unit.

[0016] The RAM 203 corresponds to a rewritable main memory portion of the computer. The RAM 203 stores data necessary for the processor 201 to execute processing. The RAM 203 is also used as a work area where information is appropriately rewritten by the processor 201. The work area includes an image memory where print data is expanded.

[0017] The operation panel 204 has an operation section and a display section. The operation section has function keys such as a power key, a paper feed key, an error reset key, etc. The display section can display various states of the printer 200.

[0018] The communication interface 205 receives print data from a client terminal connected via a network such as a LAN (Local Area Network). For example, when an error occurs in the printer 200, the communication interface 205 transmits a signal notifying the client terminal of the error.

[0019] A motor drive circuit 207 controls the drive of the transport motor 206. The transport motor 206 functions as a drive source for a transport mechanism that transports a recording medium such as printing paper. When the transport motor 206 starts, the transport mechanism starts transporting the recording medium. The transport mechanism transports the recording medium to a printing position by the head 100. The transport mechanism ejects the recording medium after printing has been completed from an ejection port (not shown) to the outside of the printer 200.

[0020] A pump drive circuit 209 controls the drive of the pump 208. When the pump 208 is driven, ink in an ink tank (not shown) is supplied to the head 100.

[0021] The head drive circuit 101 drives the actuator group 102 of the head 100 based on the print data. The actuator group 102 expands and contracts pressure chambers that contain ink, causing ink droplets to be ejected from nozzles that communicate with the pressure chambers. In this way, the head 100 ejects ink onto a recording medium transported by a transport mechanism, and prints an image or the like on the recording medium.

[0022] (Conventional head drive circuit) Next, a conventional head drive circuit 101 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of the conventional head drive circuit 101.

[0023] The head driving circuit 101 has an I / O section 110, a logic section 120, and an analog section 130. The I / O section 110, the logic section 120, and the analog section 130 form a driving section that drives the actuator group 102.

[0024] The I / O unit 110 includes a comparator 111 and a serial-to-parallel conversion unit 112. In the drawings, the "serial-to-parallel conversion unit" is abbreviated to "conversion unit."

[0025] A clock signal CLK and a data signal DI of low voltage differential signaling (LVDS) are input to the comparator 111. The data signal DI includes print data, setting data, etc. The comparator 111 outputs the data of the clock signal CLK and the data of the data signal DI to a serial-parallel conversion unit 112.

[0026] The serial-parallel conversion unit 112 converts the serial format data input from the comparator 111 into parallel format data. It acquires the data of the data signal DI at the rising edge of the clock signal CLK. More specifically, it acquires the value (0 or 1) of the setting data and print data included in the data signal DI at the timing when the clock signal CLK changes from 0 to 1. The serial-parallel conversion unit 112 outputs the data of the parallel format data signal DI to the logic unit 120. In addition, the serial-parallel conversion unit 112 outputs the data of the clock signal CLK to the logic unit 120 and the analog unit.

[0027] The logic section 120 includes a start byte recognition section 121, a setting data register 122, a print data register 123, and a waveform pattern generation section .

[0028] Start byte recognition unit 121 recognizes a start byte in the data of parallel data signal DI input from serial-parallel conversion unit 112, and separates the data into setting data and print data. Start byte recognition unit 121 outputs the setting data to setting data register 122, and outputs the print data to print data register 123.

[0029] The setting data register 122 stores the setting data input from the start byte recognition unit 121 .

[0030] The print data register 123 stores the print data input from the start byte recognition unit 121 .

[0031] The waveform pattern generating unit 124 obtains the setting data from the setting data register 122 and the print data from the print data register 123, and generates a waveform pattern based on the setting data and the print data. The waveform pattern generating unit 124 outputs the generated waveform pattern to the analog unit 130.

[0032] The analog section 130 includes a level shifter 131 , a pre-buffer 132 , and a gate driver 133 .

[0033] The level shifter 131 converts the waveform pattern input from the waveform pattern generating unit 124 into a high voltage waveform pattern. The level shifter 131 outputs the waveform pattern converted into a high voltage waveform pattern to the pre-buffer 132.

[0034] The pre-buffer 132 appropriately amplifies and shapes the waveform pattern input from the level shifter 131. The pre-buffer 132 outputs the appropriately amplified and shaped waveform pattern to the gate driver 133.

[0035] The gate driver 133 controls ON / OFF of a plurality of switch elements included in the gate driver 133 based on the waveform pattern input from the pre-buffer 132, thereby outputting a drive waveform for driving the actuator group 102 of the head 100 to an output electrode OUT to which the actuator group 102 is connected. In other words, the gate driver 133 is a drive waveform output unit that outputs a drive waveform based on the waveform pattern. For example, the switch element is a MOSFET, and the gate driver 133 controls ON / OFF of the MOSFET by applying a control signal (gate voltage) to the gate of the MOSFET.

[0036] (Protection function) The head drive circuit 101 also has a thermal shutdown function and a short circuit prevention function as protection functions. The thermal shutdown function is a function for preventing abnormal heat generation in the head drive circuit 101. The short circuit prevention function is a function for preventing the occurrence of a short circuit in the gate driver 133 when multiple switch elements with different power supply levels are turned ON simultaneously.

[0037] There are cases where you may want to disable the thermal shutdown function and short circuit prevention function, such as when you want to perform operation tests in a high-temperature environment or at high temperatures due to overload, or when you want to set different power supply levels to the same potential and drive the switch elements by turning them on simultaneously.

[0038] The thermal shutdown function and the short circuit prevention function can be switched between enabled and disabled by the setting data held in the setting data register 122. In other words, the setting data held in the setting data register 122 includes designation data that designates the enabling and disabling of the thermal shutdown function and the short circuit prevention function.

[0039] (Thermal shutdown function) The head drive circuit 101 has a temperature sensor unit 140 as a protection circuit for executing a thermal shutdown function. The temperature sensor unit 140 has a temperature sensor 141, a reference power supply 142, and a comparator 143. The temperature sensor 141 detects the temperature of the head drive circuit 101 and outputs a voltage signal indicating the temperature. The reference power supply 142 provides a reference voltage that serves as a threshold for determining abnormal heat generation. The comparator 143 compares the voltage signal output by the temperature sensor 141 with the reference voltage.

[0040] Depending on the comparison result, the comparator 143 outputs binary data TS indicating whether the head drive circuit 101 is in an abnormally hot state or not. For example, when the temperature is equal to or higher than a threshold value, the comparator 143 outputs binary data TS of "1", which indicates that the head drive circuit 101 is in an abnormally hot state. The binary data TS of "1" is control data that instructs the execution of a thermal shutdown function. On the other hand, when the temperature is less than the threshold value, the comparator 143 outputs binary data TS of "0", which indicates that the head drive circuit 101 is not in an abnormally hot state. The binary data TS of "0" is control data that does not instruct the execution of a thermal shutdown function.

[0041] The thermal shutdown function can be enabled or disabled by designation data of the setting data held in the setting data register 122. The setting data register 122 outputs designation data DTS that designates whether the thermal shutdown function is enabled or disabled.

[0042] FIG. 3 shows an example of a register map of designation data for designating whether the thermal shutdown function and short circuit prevention function are enabled or disabled. In FIG. 3, thermal shutdown is abbreviated as shutdown. This is the same in FIG. 4, FIG. 7, and FIG. 8. The setting data register 122 holds, at a predetermined address, name information representing the thermal shutdown function and designation data DTS for designating whether the thermal shutdown function is enabled or disabled associated with the name information. The setting data register 122 holds the setting data as 8-bit data (D0 to D7). The setting data register 122 also holds the designation data DTS for designating whether the thermal shutdown function is enabled or disabled as the least significant bit (D0) data.

[0043] Fig. 4 is a diagram showing specific register values ​​representing the enablement and disablement of the thermal shutdown function and short circuit prevention function in the register map of the designated data shown in Fig. 3. The register value representing the enablement of the thermal shutdown function is "00000001". Also, the register value representing the disablement of the thermal shutdown function is "00000000".

[0044] When the thermal shutdown function is enabled, the setting data register 122 outputs the binary data of the least significant bit (D0), i.e., "1." On the other hand, when the thermal shutdown function is disabled, the setting data register 122 outputs the binary data of the least significant bit (D0), i.e., "0."

[0045] 2, the description of the head drive circuit 101 continues. The head drive circuit 101 also has an AND circuit 145 that receives as input the output of the temperature sensor unit 140 and the output of the setting data register 122. The input from the setting data register 122 to the AND circuit 145 is binary data of "1" or "0" that indicates whether the thermal shutdown function is enabled or disabled.

[0046] The AND circuit 145 outputs "0" when both the input data from the temperature sensor unit 140 and the input data from the setting data register 122 are not "1." In other words, the AND circuit 145 outputs "0" when the head drive circuit 101 is not in an abnormally hot state, or when the head drive circuit 101 is in an abnormally hot state but the thermal shutdown function is disabled. The output data "0" from the AND circuit 145 is data that instructs the logic unit 120 and analog unit 130 of the head drive circuit 101 to continue driving.

[0047] On the other hand, the AND circuit 145 outputs "1" when the input data from the temperature sensor unit 140 and the input data from the setting data register 122 are both "1". In other words, the AND circuit 145 outputs "1" only when the head driving circuit 101 is in an abnormally hot state and the thermal shutdown function is enabled. The output data "1" from the AND circuit 145 is data that instructs the logic unit 120 and analog unit 130 of the head driving circuit 101 to stop driving.

[0048] The head driving circuit 101 is capable of receiving a reset signal that forcibly stops the logic unit 120 and the analog unit 130. The reset signal is input to the logic unit 120 and the analog unit 130. The logic unit 120 and the analog unit 130 stop when the reset signal is input. For example, the reset signal is binary data "1". Driving the logic unit 120 and the analog unit 130 may be stopped by any method, such as stopping the reception process of print data or stopping the output of a gate driver.

[0049] The head drive circuit 101 also has an OR circuit 146 that receives as input a reset signal and the output of the AND circuit 145. The OR circuit 146 outputs "1" when at least one of the output of the AND circuit 145 and the reset signal is "1." In other words, the output data "1" of the OR circuit 146 is data that instructs the logic unit 120 and analog unit 130 of the head drive circuit 101 to stop driving.

[0050] (Short circuit prevention function) The head drive circuit 101 has a short circuit prevention circuit 125 in the waveform pattern generation unit 124 as a protection circuit for performing a short circuit prevention function. The short circuit prevention circuit 125 is a circuit that prevents the waveform pattern generation unit 124 from generating a waveform pattern in which switch elements with different power supply levels in the gate driver 133 are simultaneously turned ON.

[0051] The short circuit prevention function can be enabled or disabled by designation data held in the setting data register 122. The setting data register 122 outputs designation data DSP that designates whether to enable or disable the short circuit prevention function to the waveform pattern generation unit 124. The waveform pattern generation unit 124 enables or disables the short circuit prevention circuit 125 in accordance with the designation data DSP.

[0052] Next, enabling and disabling of the short circuit prevention function will be described with reference to Fig. 3. As described above, Fig. 3 is a diagram showing an example of a register map of data specifying enabling and disabling of the thermal shutdown function and the short circuit prevention function.

[0053] As with the thermal shutdown function, the setting data register 122 holds, at a specific address, name information representing the short circuit prevention function and associated data DSP indicating whether the short circuit prevention function is enabled or disabled. The setting data register 122 holds the setting data as 8-bit (D0 to D7) data. The setting data register 122 also holds designation data DSP for designating whether the short circuit prevention function is enabled or disabled as the least significant bit (D0) data.

[0054] As shown in Figure 4, like the thermal shutdown function, the register value that indicates that the short circuit prevention function is enabled is "00000001." Also, the register value that indicates that the short circuit prevention function is disabled is "00000000."

[0055] In a setting for enabling the short circuit prevention function, the setting data register 122 outputs binary data of the least significant bit (D0), i.e., "1", to the waveform pattern generating unit 124. The output data "1" of the setting data register 122 is data for enabling the short circuit prevention circuit 125. In this case, the waveform pattern generating unit 124 uses the short circuit prevention circuit 125 to generate a waveform pattern to be output to the analog unit 130.

[0056] On the other hand, in a setting to disable the short circuit prevention function, the setting data register 122 outputs binary data of the lowest bit (D0), i.e., "0", to the waveform pattern generating unit 124. The output data "0" of the setting data register 122 is data for disabling the short circuit prevention circuit 125. In this case, the waveform pattern generating unit 124 generates a waveform pattern to be output to the analog unit 130 without using the short circuit prevention circuit 125.

[0057] (Head driving circuit according to an embodiment) In the head driving circuit 101 according to the conventional example described above, the designation data for designating whether to enable or disable the protection functions (i.e., the thermal shutdown function and the short circuit prevention function) is 1-bit data held by the setting data register 122. When the designation data is 1-bit data, the protection functions may be unintentionally disabled due to an operational error when inputting the setting data or a bit error during data processing. Unintentional disabling of the protection functions can cause malfunctions, so it is desirable to prevent this from happening as much as possible.

[0058] The head driving circuit 101 according to the embodiment has a configuration for suppressing unintended disabling of protective functions (that is, thermal shutdown function and short circuit prevention function) with respect to designation data for designating enabling and disabling of protective functions.

[0059] Hereinafter, the head drive circuit 101 according to the embodiment will be described with reference to Fig. 5. Fig. 5 is a block diagram showing an example of the configuration of the head drive circuit 101 according to the embodiment. In Fig. 5, members with the same reference symbols as those shown in Fig. 2 are similar members, and detailed descriptions thereof will be omitted. The following description will focus on the different parts.

[0060] In the head driving circuit 101 according to the embodiment, the setting data register 122 holds designation data for designating whether to enable or disable the protection functions (i.e., the thermal shutdown function and the short circuit prevention function) as multi-bit data. That is, the setting data register 122 outputs multi-bit designation data as designation data for designating whether to enable or disable the protection functions (i.e., the thermal shutdown function and the short circuit prevention function).

[0061] For example, the setting data register 122 outputs 8-bit designation data DTS[7,0] as designation data for designating whether to enable or disable the thermal shutdown function. Also, the setting data register 122 outputs 8-bit designation data DSP[7,0] as designation data for designating whether to enable or disable the short circuit prevention function.

[0062] To generate one-bit designation data from multiple-bit designation data, the head driving circuit 101 according to the embodiment has a logic circuit 148 based on multiple-bit combinations and a logic circuit 126 based on multiple-bit combinations. Hereinafter, the logic circuit based on multiple-bit combinations will be abbreviated as a combinational circuit.

[0063] The combinational circuit 148 generates 1-bit designation data to be input to the AND circuit 145 from the 8-bit designation data DTS[7,0] that designates whether to enable or disable the thermal shutdown function output by the setting data register 122. The combinational circuit 148 constitutes a part of a protection circuit for executing the thermal shutdown function. In other words, the head driving circuit 101 according to the embodiment has a temperature sensor unit 140 and the combinational circuit 148 as a protection circuit for executing the thermal shutdown function. The combinational circuit 148 is also configured to suppress the occurrence of unintended disabling of the thermal shutdown function.

[0064] The combinational circuit 126 generates 1-bit designation data to be input to the waveform pattern generating unit 124 from the 8-bit designation data DSP[7,0] that designates whether to enable or disable the short circuit prevention function output by the setting data register 122. The combinational circuit 126 constitutes a part of a protection circuit for executing the short circuit prevention function. The head driving circuit 101 according to the embodiment has a short circuit prevention circuit 125 and a combinational circuit 126 as protection circuits for executing the short circuit prevention function. The combinational circuit 126 is configured to suppress the occurrence of unintended disabling of the short circuit prevention function.

[0065] In the head driving circuit 101 according to the embodiment, an example of a register map of data held by the setting data register 122 to specify whether to enable or disable the thermal shutdown function and the short circuit prevention function is shown in FIG.

[0066] The setting data register 122 holds, at a predetermined address, name information representing a thermal shutdown function and 8-bit designation data DTS[7,0] that specifies whether to enable or disable the associated thermal shutdown function. Similarly, the setting data register 122 holds, at a predetermined address, name information representing a short circuit prevention function and 8-bit designation data DSP[7,0] that specifies whether to enable or disable the associated short circuit prevention function. As described above, the setting data register 122 holds setting data as 8-bit (D0 to D7) data.

[0067] In the head drive circuit 101 according to the conventional example, the least significant bit (D0) of the 8-bit (D0 to D7) setting data held by the setting data register 122 is assigned to the designation data DTS that designates whether the thermal shutdown function is enabled or disabled. The same applies to the designation data DSP that designates whether the short circuit prevention function is enabled or disabled.

[0068] In contrast, in the head driving circuit 101 according to the embodiment, all of the 8 bits (D0 to D7) of the setting data held by the setting data register 122 are assigned to the designation data DTS[7,0] that designates whether to enable or disable the thermal shutdown function. The same applies to the designation data DSP[7,0] that designates whether to enable or disable the short circuit prevention function.

[0069] FIG. 7 is a diagram showing specific register values ​​representing the enablement and disablement of the thermal shutdown function and short circuit prevention function in the register map of the specified data shown in FIG. 6. The register value representing the disablement of the thermal shutdown function is "11101010". Note that the register value "XXXXXXXX" representing the enablement of the thermal shutdown function indicates that it is a value different from "11101010". Also, the register value representing the disablement of the short circuit prevention function is "11011010". Note that the register value "XXXXXXXX" representing the enablement of the short circuit prevention function indicates that it is a value different from "11011010".

[0070] Next, a truth table of the combinational circuit 148 will be described with reference to FIG. 8. FIG. 8 is a diagram showing a truth table of the combinational circuit 148, which is a logic circuit based on a combination of multiple bits. In FIG. 8, D0 to D7 respectively represent each bit value of the 8-bit specified data. D0 represents the least significant bit value, and D7 represents the least significant bit value. Also, OUT represents the bit value output by the combinational circuit 148. Each bit value is represented by 0 or 1. "X" indicates that it may be either 0 or 1.

[0071] As shown in Fig. 7, the register value representing the disablement of the thermal shutdown function is "11101010." In Fig. 8, the second line represents that each bit value of the 8-bit designation data matches each bit value of the register value "11101010," and in that case, the combinational circuit 148 outputs the 1-bit designation data "0" representing the disablement of the thermal shutdown function.

[0072] In FIG. 8, from the third line onwards, if any of the bit values ​​of the 8-bit designation data does not match the bit values ​​of the register value "11101010", then the combinational circuit 148 outputs the 1-bit designation data "1", which indicates that the thermal shutdown function is enabled.

[0073] In other words, the combinational circuit 148 outputs a 1-bit designation data "0" representing the disabling of the thermal shutdown function only when each bit value of the 8-bit designation data DTS[7,0] specifying whether to enable or disable the thermal shutdown function output by the setting data register 122 exactly matches each bit value of the register value "11101010" specifying the disabling of the thermal shutdown function, and otherwise outputs a 1-bit designation data "1" representing the enablement of the thermal shutdown function.

[0074] The combinational circuit 148 outputs 1-bit designated data "0" or "1" to the AND circuit 145. The functions of the AND circuit 145 that receives the output of the combinational circuit 148 are the same as those of the AND circuit 145 in the head drive circuit 101 according to the conventional example.

[0075] That is, the AND circuit 145 outputs "0" when both the input data from the temperature sensor unit 140 and the input data from the combinational circuit 148 are not "1." That is, the AND circuit 145 outputs "0" when the head drive circuit 101 is not in an abnormally hot state, or when the head drive circuit 101 is in an abnormally hot state but the thermal shutdown function is disabled. The output data "0" from the AND circuit 145 is data that instructs the logic unit 120 and analog unit 130 of the head drive circuit 101 to continue driving.

[0076] On the other hand, the AND circuit 145 outputs "1" when the input data from the temperature sensor unit 140 and the input data from the combinational circuit 148 are both "1". In other words, the AND circuit 145 outputs "1" only when the head driving circuit 101 is in an abnormally hot state and the thermal shutdown function is enabled. The output data "1" from the AND circuit 145 is data that instructs the logic unit 120 and analog unit 130 of the head driving circuit 101 to stop driving.

[0077] Moreover, the functions of the OR circuit 146 that receives the output of the AND circuit 145 are the same as those of the OR circuit 146 in the head drive circuit 101 according to the conventional example.

[0078] The functions of the combinational circuit 126 are similar to those of the combinational circuit 148. That is, the combinational circuit 126 outputs 1-bit designation data "0" representing the disablement of the short circuit prevention function only when each bit value of the 8-bit designation data DTS[7,0] specifying the enablement or disablement of the short circuit prevention function output by the setting data register 122 completely matches each bit value of the register value "11011010" specifying the disablement of the short circuit prevention function, and outputs 1-bit designation data "1" representing the enablement of the short circuit prevention function in other cases.

[0079] (effect) As described above, in the head driving circuit 101 according to the embodiment, all of the 8 bits of the setting data held by the setting data register 122 are assigned to the designation data that designates whether the protection function is enabled or disabled. Therefore, even if an operational error occurs when inputting the setting data or a bit error occurs during data processing, it is unlikely that all of the bit values ​​of the designation data will completely match the register value that designates the disablement of the protection function. It can be considered that such a situation will never occur. Therefore, it is considered that the head driving circuit 101 according to the embodiment can prevent the occurrence of unintended disablement of the protection function.

[0080] (Short circuit prevention function) The short circuit prevention function will be described below with reference to Figures 9 to 11. First, a configuration example of the gate driver 133 included in the analog unit 130 of the head drive circuit 101 will be described below, followed by a configuration example of the waveform pattern generation unit 124 included in the logic unit 120 of the head drive circuit 101, and then a description of an operation example of the gate driver 133 and the waveform pattern generation unit 124 when the short circuit prevention function is enabled and disabled.

[0081] (Gate driver) First, the gate driver 133 will be described with reference to Fig. 9. Fig. 9 is a block diagram showing an example of the configuration of the gate driver 133. The gate driver 133 shown in Fig. 9 is for one actuator PZT in the actuator group 102.

[0082] The gate driver 133 has a plurality of switch elements QS, QA, QB, QC, and QD. An appropriate power supply level is provided to the switch elements QS, QA, QB, QC, and QD by a drive power supply PS.

[0083] For example, the driving power supply PS has multiple power supplies PSA, PSB, PSC, and PSD. The power supply PSA provides a power supply level VA to the switch element QA relative to the reference potential VSS. The power supply PSB provides a power supply level VB to the switch element QB relative to the reference potential VSS. The power supply PSC provides a power supply level VC to the switch element QC relative to the reference potential VSS. The power supply PSD provides a power supply level VD to the switch element QD relative to the reference potential VSS. For example, the reference potential VSS is a negative potential, and the power supply levels VA, VB, VC, and VD are positive potentials.

[0084] The switch element QS connects between a pair of electrodes of the actuator PZT. The switch elements QA, QB, QC, and QD connect between the actuator PZT and the power supplies PSA, PSB, PSC, and PSD, respectively. In more detail, the switch element QA connects the other electrode of the actuator PZT to the other power supply terminal of the power supply PSA. The switch element QB connects the other electrode of the actuator PZT to the other power supply terminal of the power supply PSB. The switch element QC connects the other electrode of the actuator PZT to the other power supply terminal of the power supply PSC. The switch element QD connects the other electrode of the actuator PZT to the other power supply terminal of the power supply PSD.

[0085] For example, each of the switch elements QS, QA to QD is a MOSFET. The switch element QS is turned ON by the gate voltage of NSg, and the output level at that time is VSS. The switch element QA is turned ON by the gate voltage of PAg, and the output level at that time is VA. The switch element QB is turned ON by the gate voltage of PBg, and the output level at that time is VB. The switch element QC is turned ON by the gate voltage of PCg, and the output level at that time is VC. The switch element QD is turned ON by the gate voltage of PDg, and the output level at that time is VD.

[0086] (Waveform pattern generation section) Next, the waveform pattern generating unit 124 will be described with reference to Fig. 10. Fig. 10 is a block diagram showing an example of the configuration of the waveform pattern generating unit 124.

[0087] The waveform pattern generating unit 124 includes a waveform timer 171 , a decoder state machine 172 , a waveform level selector 173 , and a waveform level selector 174 .

[0088] The waveform timer 171 is a timer circuit that generates a pulse signal for forming ink drops in a multi-drop system. Fire1, Fire2, ..., Fire14 each correspond to an ink drop (tone). Timer [7:0] indicates that the pulse signal is 8-bit data.

[0089] Decoder state machine 172 outputs data specifying the waveform output level to waveform level selector 173 and waveform level selector 174 based on the pulse signal generated by waveform timer 171. FW[4:0] represents 5-bit data corresponding to the power supply levels VSS, VA, VB, VC, and VD shown in FIG.

[0090] The waveform level selectors 173, 174 are used differently depending on the ink drop (gradation). The waveform level selectors 173, 174 have the same basic function. The waveform level selectors 173, 174 output signals (gate voltages) NSg, PAg, PBg, PCg, and PDg to the gate driver 133 based on the print data to turn on each of the switch elements QS, QA, QB, QC, and QD.

[0091] Based on the print data and setting data, the waveform pattern generation unit 124 controls the ON / OFF of the switch elements QS, QA, QB, QC, and QD in the gate driver 133. As a result, the gate driver 133 outputs a drive waveform that drives one actuator PZT in the actuator group 102 of the head 100.

[0092] (Example of operation) In the gate driver 133 shown in FIG. 9, a plurality of switch elements connected in series, specifically, the switch element QS and any of the switch elements QA, QB, QC, and QD, are not permitted to be turned ON at the same time.

[0093] In addition, the power supply levels VA, VB, VC, and VD of the switching elements QA, QB, QC, and QD are generally different. In this case, it is not permitted to turn on two or more of the switching elements QA, QB, QC, and QD connected in parallel at the same time.

[0094] However, it is permitted to simultaneously turn on the switch elements QA, QB, QC, and QD having the same power supply levels VA, VB, VC, and VD.

[0095] 11 is a diagram showing a list of waveform output levels, ON switches, and ON resistances of the drive waveforms output by the gate driver 133. An ON switch refers to a switch element that is turned ON to obtain a desired waveform output level, and an ON resistance refers to the resistance when the switch element is in the ON state.

[0096] As shown in Figure 11, the ON resistance of each of the switch elements QS, QA, QB, QC, and QD is 200Ω. If the power supply levels VB, VC, and VD are the same, the switch elements QB, QC, and QD are allowed to be turned ON simultaneously. In this case, the combined ON resistance (parallel resistance) of the switch elements QB, QC, and QD is 66.7Ω.

[0097] The magnitude of the ON resistance (parallel resistance) is related to the speed of the rise and fall of the drive waveform that drives the PZT actuator. When the ON resistance (parallel resistance) is low, the rise and fall of the drive waveform is faster than when the ON resistance (parallel resistance) is high.

[0098] For this reason, it is possible to disable the short circuit prevention function for multiple switch elements connected in parallel and with the same power supply level, and to simultaneously turn on these switch elements, thereby enabling control such as speeding up the rise and fall of the drive waveform of the actuator PZT.

[0099] For this reason, the decoder state machine 172 (see FIG. 10) determines whether or not to permit multiple switch elements connected in parallel to be turned on simultaneously, based on the power supply level data included in the setting data and the designation data DSP that designates whether to enable or disable the short circuit prevention function, and then determines the waveform pattern to be output from the waveform level selectors 173, 174. That is, the decoder state machine 172 includes the short circuit prevention circuit 125 (see FIG. 2), and enables or disables the short circuit prevention function.

[0100] (others) The program according to the present embodiment may be transferred in a state where it is stored in an electronic device, or in a state where it is not stored in an electronic device. In the latter case, the program may be transferred via a network, or in a state where it is stored in a storage medium. The storage medium is a non-transitory tangible medium. The storage medium is a computer-readable medium. The storage medium may be in any form, such as a CD-ROM or a memory card, as long as it is capable of storing a program and is computer-readable.

[0101] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0102] 100...inkjet head, 101...inkjet head driving circuit, 102...actuator group, 110...I / O section, 111...comparator, 112...serial-to-parallel conversion section, 120...logic section, 121...start byte recognition section, 122...setting data register, 123...print data register, 124...waveform pattern generation section, 125...short circuit prevention circuit, 126...combination circuit, 130...analog section, 131...level shifter, 132...pre-buffer, 133...gate driver, 140...temperature sensor section, 141 ...temperature sensor, 142...reference power supply, 143...comparator, 145...AND circuit, 146...OR circuit, 148...combination circuit, 171...waveform timer, 172...decoder state machine, 173...waveform level selector, 174...waveform level selector, 200...inkjet printer, 201...processor, 202...ROM, 203...RAM, 204...operation panel, 205...communication interface, 206...conveyor motor, 207...motor drive circuit, 208...pump, 209...pump drive circuit, 210...bus line.

Claims

1. An inkjet head drive circuit for driving an inkjet head having a pressure chamber for storing ink, a nozzle communicating with the pressure chamber, and an actuator for expanding and contracting the pressure chamber to eject ink from the nozzle, comprising: A drive unit that drives the actuator; a protection circuit for performing a protection function for the inkjet head driving circuit; a setting data register that stores setting data including multiple bits of designation data that designates whether the protection function is enabled or disabled, and outputs the multiple bits of designation data to the protection circuit; the protection circuit disables the protection function only when each bit value of the multiple-bit designation data matches each bit value of multiple-bit disable designation data that designates the disablement of the protection function; the protection circuit enables the protection function when each bit value of the multiple-bit designation data does not match each bit value of the multiple-bit disable designation data. Inkjet head drive circuit.

2. the protection circuit has a logic circuit that generates one bit of designated data from the multiple bits of designated data; 2. The inkjet head drive circuit according to claim 1.

3. the logic circuit receives as input each bit value of the multiple-bit designation data, and outputs "0" when each bit value of the multiple-bit designation data matches each bit value of the multiple-bit invalidation designation data, and outputs "1" when each bit value of the multiple-bit invalidation designation data does not match each bit value of the multiple-bit invalidation designation data.

3. The inkjet head drive circuit according to claim 2.

4. a temperature sensor that detects the temperature of the inkjet head drive circuit; a comparator that compares the temperature detected by the temperature sensor with a threshold value; The protection circuit stops the driving unit when the detected temperature is equal to or higher than the threshold value.

2. The inkjet head drive circuit according to claim 1.

5. the driving section has a plurality of switch elements with different power supply levels; The protection circuit prevents the plurality of switch elements from being turned ON simultaneously.

2. The inkjet head drive circuit according to claim 1.

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