Memory system

Abstract

To provide a memory system capable of improving the performance of read processing by utilizing a read buffer efficiently.SOLUTION: A controller of a memory system issues a first memory read request to read first data at the head among pieces of read objective data out of a first memory die to the first memory die. When the read objective data includes the remaining data following the first data, the controller transfers a first identifier from a first command queue to a second command queue corresponding to a second memory die stored with second data at the head among the remaining data. The controller issues a second memory read request to read the second data out of the second memory die to the second memory die in response to the transfer of the first identifier to the second command queue.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art In recent years, a solid-state drive (SSD) that includes a nonvolatile memory and a controller that controls the nonvolatile memory is known as a memory system that has become widespread.

[0003] The controller reads the read target data from the non-volatile memory based on the read command received from the external host, and transmits the read read target data to the external host. When the transfer length (size of the read target data) specified by the read command is relatively large, the read target memory die may span multiple memory dies of the non-volatile memory. In this case, multiple read operations based on the same read command are executed in parallel on multiple memory dies, so that multiple data portions included in the read target data are read from the multiple memory dies in an order that is unrelated to the order of the logical addresses of these data portions.

[0004] In addition, some hosts may require the SSD to transfer the read target data specified by the read command issued by the host to the host in logical address order, that is, in the order of the data portion corresponding to the first logical address to the data portion corresponding to the last logical address. In the case where the read target data is transferred to the host in logical address order, the multiple data portions read from the multiple memory dies may include data portions that cannot be transferred to the host immediately after being read. Such data portions are retained in the read buffer. If many data portions are retained in the read buffer, the capacity of the read buffer available for processing the subsequent read command is reduced, which causes a decrease in the performance of the read processing of the memory system.

[0005] Therefore, in memory systems such as SSDs, there is a need for technology that can improve the performance of read processing by efficiently utilizing the read buffer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2022 / 0253248 [Patent Document 2] U.S. Patent No. 7,506,114 [Patent Document 3] U.S. Patent No. 6,581,111 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a memory system capable of improving the performance of a read process by efficiently utilizing a read buffer. [Means for solving the problem]

[0008] According to an embodiment, a memory system is connectable to a host. The memory system includes a non-volatile memory including a plurality of memory dies, and a controller configured to control the plurality of memory dies. In response to receiving a first read command from the host requesting reading of data to be read, the controller divides the data to be read into a plurality of data portions corresponding to a plurality of clusters, and generates a plurality of read requests, each of which includes memory address information indicating a storage location in the non-volatile memory where the corresponding data portion is stored. The controller stores the plurality of read requests, from a read request corresponding to a first cluster of the plurality of clusters to a read request corresponding to a last cluster of the plurality of clusters, in a first read request queue associated with a first identifier added to the first read command, such that the plurality of read requests are linked in this order. The controller stores the first identifier in a first command queue corresponding to a first memory die in which a first data portion corresponding to the first cluster is stored. In response to storing the first identifier in the first command queue, the controller identifies a first storage area of ​​the first memory die in which a first data portion of the read target data, including at least the first data portion, is stored by referring to the plurality of read requests stored in the first read request queue from a read request corresponding to the first cluster. The controller generates a first memory read request for reading the first data from the first storage area of ​​the first memory die. The controller issues the first memory read request to the first memory die. When remaining data following the first data is included in the read target data, the controller transfers the first identifier from the first command queue to a second command queue corresponding to a second memory die in which a second data portion corresponding to a first cluster of one or more clusters corresponding to the remaining data is stored.In response to transferring the first identifier to the second command queue, the controller identifies a second storage area of ​​the second memory die in which a first second data portion of the remaining data is stored, the first second data portion including at least the second data portion, by referencing unprocessed read requests stored in the first read request queue from a read request corresponding to a first cluster of the one or more clusters. The controller generates a second memory read request for reading the second data from the second storage area of ​​the second memory die. The controller issues the second memory read request to the second memory die. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of a nonvolatile memory in the memory system according to the embodiment. [Diagram 3] 1 is a block diagram showing an example of the configuration of each of a plurality of memory dies included in a nonvolatile memory of a memory system according to an embodiment. [Figure 4] 11 is a diagram showing a process executed in a cluster read request generating unit of the memory system according to the embodiment. [Diagram 5] 1 is a block diagram showing an overview of a configuration example of a linked list management unit and a command dispatcher in a memory system according to an embodiment. [Figure 6] 2 is a diagram showing an example of the configuration of a linked list managed by a linked list management unit of the memory system according to the embodiment; [Figure 7] 1 is a diagram for explaining a more detailed configuration example of a linked list management unit and a command dispatcher used in the memory system according to the embodiment, taking as an example processing at the time of executing a read. [Figure 8] 11 is a diagram showing an example of management of read data in a memory system according to a comparative example. [Figure 9]1 is a diagram showing an example of management of read data in a memory system according to an embodiment; [Figure 10] 1 is a flowchart showing the procedure of a read process executed in a memory system according to an embodiment. [Figure 11] 11 is a flowchart showing the procedure of a page read request issuing process executed in the memory system according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described with reference to the drawings. 1 is a block diagram showing an example of the configuration of an information processing system 1 including a memory system according to an embodiment. The information processing system 1 includes a host (host device) 2 and an SSD (solid state drive) 3 as a memory system. The host 2 and the SSD 3 can be connected via a bus 7.

[0011] The host 2 is, for example, an information processing device such as a personal computer, a server computer, or a mobile terminal. The host 2 is connected to the SSD 3 and can access the SSD 3. Specifically, the host 2 transmits a write command to the SSD 3 for writing data. The host 2 also transmits a read command to the SSD 3 for reading data.

[0012] The SSD3 is also called a storage device, and is capable of writing data to an internal non-volatile memory and reading data from the internal non-volatile memory.

[0013] The communication between the SSD 3 and the host 2 is performed via a bus 7. The bus 7 is a transmission path that connects the host 2 and the SSD 3. The bus 7 is, for example, a PCI express TM (PCIe TM) bus. The PCIe bus is a full duplex transmission path. The full duplex transmission path includes both a transmission path for transmitting data and input / output (I / O) commands from the host 2 to the SSD 3, and a transmission path for transmitting data and responses from the SSD 3 to the host 2. The I / O commands are transmitted from the host 2 to the SSD 3, and include a write command for writing data to the nonvolatile memory, or a read command for reading data from the nonvolatile memory.

[0014] The logical interface connecting host 2 and SSD 3 is, for example, NVM express TM (NVMe TM ) standard may be used. In an interface conforming to the NVMe standard, communication between the host 2 and the SSD 3 is performed using a pair of queues including at least one submission queue (SQ) and a completion queue (CQ) associated with the submission queue (SQ). This pair of queues is called a submission queue / completion queue pair (SQ / CQ pair). FIG. 1 shows a case where five submission queues (SQ1 to SQ5) 221-1 to 221-5 and one completion queue (CQ1) 222-1 are used by the host 2 to send each I / O command and to receive a response to each I / O command.

[0015] Each of the submission queues (SQ1 to SQ5) 221-1 to 221-5 is a queue used to issue an I / O command to the SSD 3. Each of the submission queues (SQ1 to SQ5) 221-1 to 221-5 includes a plurality of slots. Each of the plurality of slots is capable of storing one I / O command. The host 2 creates the submission queues (SQ1 to SQ5) 221-1 to 221-5 in the memory 22 of the host 2. The host 2 also issues a submission queue create command to the SSD 3. The SSD 3 is notified by the submission queue create command of the addresses indicating the storage positions in the memory 22 where each of the submission queues (SQ1 to SQ5) 221-1 to 221-5 was created, the sizes of each of SQ1 to SQ5, the identifier of the completion queue CQ1 associated with SQ1 to SQ5, and the like.

[0016] The completion queue (CQ1) 222-1 is a queue used to receive a completion response from the SSD 3 indicating the completion of an I / O command. The completion response includes information indicating a status indicating the success or failure of processing the completed command. The completion response is also called a command completion or a command completion notification. The completion queue (CQ1) 222-1 includes a plurality of slots. Each of the plurality of slots is capable of storing one completion response. The host 2 creates the completion queue (CQ1) 222-1 in the memory 22 of the host 2. The host 2 also issues a completion queue create command to the SSD 3. The address indicating the storage location in the memory 22 where the completion queue (CQ1) 222-1 is created, the size of this CQ1, and the like are notified to the SSD 3 by the completion queue create command.

[0017] Next, the configuration of the host 2 will be described.

[0018] The host 2 includes a processor 21 and a memory 22 , and the processor 21 and the memory 22 are interconnected via an internal bus 20 .

[0019] The processor 21 is, for example, a CPU (Central Processing Unit). The processor 21 executes software (host software) loaded into the memory 22 from the SSD 3 or another storage device connected to the host 2. The host software includes, for example, an operating system, a file system, and an application program.

[0020] The memory 22 is, for example, a volatile memory. The memory 22 is also referred to as a main memory, a system memory, or a host memory. The memory 22 is, for example, a dynamic random access memory (DRAM). A part of the storage area of ​​the memory 22 is used to store SQ / CQ pairs. Another part of the storage area of ​​the memory 22 is used as a data buffer. The data buffer stores write data to be written to the SSD 3 or read data transferred from the SSD 3.

[0021] In communication between the host 2 and the SSD 3, an SQ / CQ pair is used to issue an I / O command from the host 2 to the SSD 3 and to send a completion response from the SSD 3 to the host 2. The transfer of the I / O command, data, and completion response between the host 2 and the SSD 3 is performed via the bus 7.

[0022] Furthermore, in communication between the host 2 and the SSD 3, a separate SQ / CQ pair (not shown) for an admin command is used to issue the admin command from the host 2 to the SSD 3 and to send a completion response from the SSD 3 to the host 2. The transfer of the admin command and the completion response between the host 2 and the SSD 3 is also performed via the bus 7. The management command is a command for managing the SSD 3. The management command includes, for example, a completion queue create command, a submission queue create command, various other commands related to the configuration and management of the SSD 3, and the like.

[0023] Next, the internal configuration of the SSD 3 will be described. The SSD 3 includes a controller 4 and a non-volatile memory 5. An example of the non-volatile memory 5 is, for example, a NAND type flash memory. In the following, it is assumed that the non-volatile memory 5 is realized as a NAND type flash memory. In the following, the non-volatile memory 5 is referred to as a NAND type flash memory 5. The NAND type flash memory 5 may be a flash memory with a secondary structure or a flash memory with a three-dimensional structure. The SSD 3 may further include a random access memory, for example, a dynamic random access memory (DRAM) 6.

[0024] The controller 4 is a memory controller. The controller 4 is, for example, a control circuit such as a System-on-a-Chip (SoC). The controller 4 is electrically connected to each of the NAND flash memory 5 and the DRAM 6. The controller 4 processes each I / O command received from the host 2. When the controller 4 receives a write command, it executes a process of writing data to the NAND flash memory 5. When the controller 4 receives a read command, it executes a process of reading data from the NAND flash memory 5. For example, a Toggle NAND flash interface or an Open NAND flash interface (ONFI) is used as a physical interface connecting the controller 4 and the NAND flash memory 5. The functions of each part of the controller 4 can be realized by dedicated hardware, a processor that executes a program, or a combination of these.

[0025] The NAND flash memory 5 is a non-volatile memory. The NAND flash memory 5 includes, for example, a plurality of memory dies. The memory dies are also called memory chips. Each of the plurality of memory dies is realized as a NAND flash memory die. Hereinafter, the memory die is also called a flash die or simply a die.

[0026] The DRAM 6 is a volatile memory and includes, for example, a storage area for storing a look-up table (LUT) 61 and a storage area used as a read buffer 62.

[0027] The LUT 61 is a logical-physical address conversion table that stores mapping information. The mapping information is information that indicates the mapping between each logical address and each physical address of the NAND flash memory 5 in units of clusters. The logical address is an address in the logical address space of the SSD 3. For example, a logical cluster address (LCA) or a logical block address (LBA) is used as the logical address. The LCA is an address that indicates a position in the logical address space of the SSD 3 in units of clusters. The LBA is an address used by the host 2 to access the SSD 3. The physical address is memory address information that indicates a storage location in the NAND flash memory 5. For example, a media cluster address (MCA) is used as the physical address. The MCA is a memory address that indicates each storage location in the NAND flash memory 5 in units of clusters. The size of data corresponding to one cluster is, for example, 4 KiB. On the other hand, the size of data associated with one LBA is, for example, 512 B or 4 KiB.

[0028] When the size of data associated with one LBA is 512B and the size of data corresponding to one cluster is 4KiB, the controller 4 converts the LBA to an LCA and manages the correspondence between the LCA and the MCA using mapping information.

[0029] When the size of data associated with one LBA is 4KiB and the size of data corresponding to one cluster is 4KiB, the LBA matches the LCA. Therefore, in this case, the controller 4 manages the correspondence between the LBA (=LCA) and the MCA using mapping information, without converting the LBA to the LCA.

[0030] The read buffer 62 is a storage area used to temporarily store read data read from the NAND flash memory 5. In addition, other storage areas of the DRAM 6 are used by the controller 4, for example, as write buffers for temporarily storing data to be written to the NAND flash memory 5.

[0031] Next, a description will be given of the internal configuration of the controller 4. The controller 4 includes components such as a host interface (host I / F) 41, a CPU 42, a static RAM (SRAM) 43, a linked list manager (LLM) 44, a CPU 45, a NAND interface (NAND I / F) 46, an error correction circuit 47, and a DRAM interface (DRAM I / F) 48. These components are connected to each other via an internal bus 40.

[0032] Among the components of the controller 4, the component that controls communication with the host 2 is called a front-end (FE) unit. The front-end unit includes a host interface 41 and a CPU 42. For example, the front-end unit interprets various commands received from the host 2.

[0033] The host interface 41 is a communication interface circuit that executes communication with the host 2. The host interface 41 is realized by, for example, a PCIe controller. In addition, for example, the host interface 41 includes an arbitration mechanism. This arbitration mechanism is a mechanism that selects a submission queue from which an I / O command should be fetched from the submission queues (SQ1 to SQ5) 221-1 to 221-5 of the host 2. The arbitration mechanism is, for example, a round robin arbitration mechanism or a weighted round robin arbitration mechanism.

[0034] The CPU 42 is a processor that controls the processing in the front end unit. The CPU 42 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (not shown) into the SRAM 43. The CPU 42 then executes this firmware to perform various processes. The firmware may be loaded into the DRAM 6.

[0035] The CPU 42 includes a cluster read request generator 421. The cluster read request generator 421 may be realized by dedicated hardware in the controller 4 (for example, a front-end unit).

[0036] In response to receiving a read command requesting reading of the read target data from the host 2, the cluster read request generating unit 421 divides the read target data into a plurality of data portions corresponding to a plurality of clusters, and generates a plurality of read requests, each including memory address information (MCA) indicating the storage location in the NAND flash memory 5 where the corresponding data portion is stored. The cluster read request generating unit 421 will be described in detail later with reference to FIG. 4.

[0037] Among the components of the controller 4, the components that control the NAND flash memory 5 are referred to as a back-end (BE) unit. The back-end unit includes an SRAM 43, a linked list management unit 44, a CPU 45, a NAND interface 46, an error correction circuit 47, and a DRAM interface 48. For example, the back-end unit instructs the NAND flash memory 5 to write data or read data.

[0038] The SRAM 43 is a volatile memory. A storage area of ​​the SRAM 42 is used, for example, as a read buffer (RB) 431. The read buffer (RB) 431 is a storage area in which data read from the NAND flash memory 5 is temporarily stored. When data is read from the NAND flash memory 5 in a state in which there is not enough available space in the SRAM 43, the data read from the NAND flash memory 5 is temporarily stored in the read buffer 62 of the DRAM 6. In addition, another storage area of ​​the SRAM 43 may be used as a write buffer to temporarily store data to be written to the NAND flash memory 5.

[0039] The linked list management unit 44 is a circuit that collectively manages cluster read requests for each command context ID (CCID). The CCID is an identifier for uniquely identifying a read command received from the host 2. The CCID is assigned to each received read command by the controller 4 (more specifically, the front-end unit). The linked list management unit 44 stores a plurality of cluster read requests including the same CCID, that is, a plurality of cluster read requests generated from one read command, in a read request queue associated with this CCID. Hereinafter, the read request queue is also referred to as a CCID queue. Details of the linked list management unit 44 will be described later with reference to FIGS. 5 to 7. The function of the linked list management unit 44 may be realized by the CPU 45.

[0040] The CPU 45 is a processor that controls processing in the back-end section of the controller 4. The CPU 45, for example, as a flash translation layer (FTL), manages data stored in the NAND flash memory 5 and manages blocks included in the NAND flash memory 5. The management of data stored in the NAND flash memory 5 includes, for example, management of mapping information. The CPU 45 manages the mapping information using the LUT 62. In addition, the management of blocks included in the NAND flash memory 5 includes management of defective blocks (bad blocks) included in the NAND flash memory 5, wear leveling, and garbage collection.

[0041] The CPU 45 includes command dispatchers (CD0 to CDm) 451-0 to 451-m and a read buffer (RB) allocation unit 452. That is, the command dispatchers (CD0 to CDm) 451-0 to 451-m and the read buffer (RB) allocation unit 452 are realized by firmware executed by the CPU 45. Note that the command dispatchers (CD0 to CDm) 451-0 to 451-m and the read buffer (RB) allocation unit 452 may be realized by dedicated hardware in the controller 4.

[0042] Each of the command dispatchers (CD0 to CDm) 451-0 to 451-m generates a memory read request for one or more predetermined flash dies, and issues the generated memory read request to the one or more flash dies via the NAND interface (NAND I / F) 46. Details of the command dispatchers (CD0 to CDm) 451-0 to 451-m will be described later with reference to FIGS. 5 and 7.

[0043] If the SRAM 43 has an available storage area of ​​a first size or more, the read buffer (RB) allocation unit 452 allocates the storage area of ​​the SRAM 43 as a read buffer (RB) for temporarily storing data read from the NAND flash memory 5. If the SRAM 43 does not have an available storage area of ​​the first size or more, the read buffer allocation unit 452 allocates the storage area of ​​the DRAM 6 as a read buffer. Data can be written to and read from the SRAM 43 at a higher speed than data can be written to and read from the DRAM 6. Therefore, by using the storage area of ​​the SRAM 43 as a read buffer, the performance of the read process of the SSD 3 can be improved.

[0044] The NAND interface 46 is a circuit that controls the NAND flash memory 5. The NAND interface 46 is electrically connected to a plurality of flash dies included in the NAND flash memory 5.

[0045] The error correction circuit 47 performs an encoding process when data is written to the NAND flash memory 5. In the encoding process, the error correction circuit 47 adds an error correction code (ECC) as a redundant code to the data to be written to the NAND flash memory 5. In the decoding process, the error correction circuit 47 performs a decoding process when data is read from the NAND flash memory 5. In the decoding process, the error correction circuit 47 uses the ECC added to the data read from the NAND flash memory 5 to perform error correction on the data.

[0046] The DRAM interface 48 is a circuit that controls the DRAM 6. The DRAM interface 48 stores data in the DRAM 6. In addition, the DRAM interface 48 reads the data stored in the DRAM 6.

[0047] Next, there will be described an example of the internal configuration of the NAND flash memory 5. Fig. 2 is a block diagram showing an example of the configuration of a non-volatile memory (for example, a NAND flash memory) in the memory system according to the embodiment.

[0048] FIG. 2 shows an example in which the NAND flash memory 5 includes 32 flash dies #0 to #31. Each flash die can operate independently. Therefore, the flash dies function as a unit capable of operating in parallel. The NAND interface 46 includes, for example, NAND controllers 461-0, 461-1, ..., 461-7. The NAND controllers 461-0, 461-1, ..., 461-7 are connected to channels ch0, ch1, ..., ch7, respectively. Each of the NAND controllers 461-0, 461-1, ..., 461-7 is connected to one or more flash dies via a corresponding channel. FIG. 2 shows an example in which four flash dies are connected to each of the channels ch0, ch1, ..., ch7. In this case, the NAND controller 461-0 is connected to the flash dies #0, #8, #16, and #24 via the channel ch0. The NAND controller 461-1 is connected to the flash dies #1, #9, #17, and #25 via a channel ch1. And the NAND controller 461-7 is connected to the flash dies #7, #15, #23, and #31 via a channel ch7. The flash dies #0, #1, ..., #7 are treated as a bank BNK0 by the controller 4. The flash dies #8, #9, ..., #15 are treated as a bank BNK1 by the controller 4. The flash dies #16, #17, ..., #23 are treated as a bank BNK2 by the controller 4. Similarly, the flash dies #24, #25, ..., #31 are treated as a bank BNK3 by the controller 4. The bank is a unit for operating multiple flash dies in parallel by interleaving operation.

[0049] In the configuration of the NAND flash memory 5 shown in FIG. 2, the controller 4 can access the flash dies #0 to #31 in parallel by using eight channels and bank interleaving operations. Therefore, the controller 4 can write or read data to a maximum of 32 flash dies in parallel (number of parallel accesses=32). Each of the flash dies #0 to #31 may have a multi-plane configuration having multiple planes. For example, if each of the flash dies #0 to #31 includes four planes, the controller 4 can write or read data to a maximum of 128 planes in parallel (number of parallel accesses=128).

[0050] Next, the internal configuration of the flash die will be described. FIG. 3 is a block diagram showing an example of the configuration of each of a plurality of memory dies (flash dies) included in a non-volatile memory (for example, a NAND flash memory 5) of a memory system according to an embodiment. In FIG. 3, the configuration of the flash die will be described with attention to the flash die #0. The other flash dies included in the NAND flash memory 5 also have the same configuration as the flash die #0. The flash die #0 includes, for example, a plurality of planes (four planes PLN0, ..., PLN3 in this case). Each of the planes PLN0, ..., PLN3 includes a peripheral circuit 51 and a memory cell array 52.

[0051] The peripheral circuit 51 is a circuit that controls the memory cell array 52. ​​The peripheral circuit 51 includes, for example, a row decoder, a column decoder, a sense amplifier, a page buffer, etc. The peripheral circuit 51 executes a data write operation, a data read operation, or a data erase operation on the memory cell array.

[0052] The memory cell array 52 includes a plurality of blocks (BLK0, BLK1, ..., BLKx-1). Each block BLK is the minimum unit of a data erase operation. Each of the multiple blocks includes a plurality of pages (P0, P1, ..., Py-1). Each page P is the unit of a data write operation and a data read operation. A page includes a set of memory cells connected to the same word line. A page is also referred to as a physical page.

[0053] Next, the cluster read request generation process will be explained. Fig. 4 is a diagram showing the process executed in the cluster read request generation unit 421 of the SSD 3 according to the embodiment. Here, it is assumed that the controller 4 receives a read command CMD0 from the host 2.

[0054] The read command CMD0 is a command that requests the reading of the read target data. The read command CMD0 specifies, for example, a start logical address (start LBA) corresponding to the read target data, a transfer length indicating the size of the read target data, a memory address (data pointer) indicating the position in the memory 22 to which the read target data should be transferred, and the like.

[0055] Upon receiving the read command CMD0, the controller 4 (more specifically, the host interface 41) assigns a CCID (for example, CCID0) to the read command CMD0.

[0056] Here, it is assumed that the data to be read has a size equivalent to 8 clusters. In this case, the start LBA specified by the read command CMD0 indicates the LBA corresponding to the first cluster of the 8 clusters of the data to be read, and the transfer length specified by the read command indicates the length of 8 clusters.

[0057] The cluster read request generator 421 of the controller 4 generates one or more cluster read requests based on the received read command CMD0. Because the read target data associated with the read command CMD0 has a size equivalent to eight clusters, the cluster read request generator 421 divides the read target data into eight data portions corresponding respectively to the eight clusters, and generates eight cluster read requests R0 to R7 corresponding respectively to the first cluster to the last cluster of the eight clusters.

[0058] The cluster read request R0 is a read request for reading a 4KiB data portion d0 corresponding to the first cluster of the eight clusters from the NAND flash memory 5. The cluster read request R1 is a read request for reading a 4KiB data portion d1 corresponding to the second cluster of the eight clusters from the NAND flash memory 5. The cluster read request R2 is a read request for reading a 4KiB data portion d2 corresponding to the third cluster of the eight clusters from the NAND flash memory 5. The cluster read request R3 is a read request for reading a 4KiB data portion d3 corresponding to the fourth cluster of the eight clusters from the NAND flash memory 5. The cluster read request R4 is a read request for reading a 4KiB data portion d4 corresponding to the fifth cluster of the eight clusters from the NAND flash memory 5. The cluster read request R5 is a read request for reading a 4KiB data portion d5 corresponding to the sixth cluster of the eight clusters from the NAND flash memory 5. The cluster read request R6 is a read request for reading a 4 KiB data portion d6 corresponding to the seventh cluster of the eight clusters from the NAND flash memory 5. The cluster read request R7 is a read request for reading a 4 KiB data portion d7 corresponding to the last cluster of the eight clusters from the NAND flash memory 5.

[0059] Each of the cluster read requests R0 to R7 includes an SQID, a CCID0, an LBA, an MCA, and the like.

[0060] SQID is an identifier of the submission queue SQ from which the read command CMD0 was fetched. For example, when the read command CMD0 is fetched from the submission queue SQ1 by the host interface 41, each of the cluster read requests R0 to R7 includes SQID1. SQID1 is an identifier of the submission queue SQ1.

[0061] As described above, CCID0 is an identifier assigned to the read command CMD0. Since the cluster read requests R0 to R7 belong to the read command CMD0, each of the cluster read requests R0 to R7 includes CCID0.

[0062] The LBA is an LBA corresponding to one cluster's worth of data that is requested to be read by each cluster read request. For example, the LBA included in the cluster read request R0 is an LBA corresponding to the data portion d0 corresponding to the first cluster of the eight clusters corresponding to the data to be read (i.e., the start LBA specified by the read command CMD0). If the size of the data corresponding to one LBA is 4 KiB, the LBA included in the cluster read request R1 is the start LBA+1, and the LBA included in the cluster read request R7 is the start LBA+7.

[0063] The MCA is memory address information indicating the storage location in the NAND flash memory 5 where one cluster's worth of data portion requested to be read by each cluster read request is stored. The MCA included in each cluster read request is obtained from the LUT 61 by referring to the LUT 61 using the LBA included in each cluster read request. The process of obtaining the MCA from the LUT 61 may be executed by the cluster read request generating unit 421, or may be executed by another module located between the front end unit and the back end unit in the controller 4, for example.

[0064] In order to increase the parallelism of the write operation, the controller 4 executes sequential write, for example, in units of page size across multiple flash dies. For example, when the page size is 16KiB, sequential write of 32KiB data is executed, for example, in units of 4 clusters across two flash dies. Therefore, when the transfer length specified by the read command is relatively large, it is necessary to read the read target data from multiple flash dies.

[0065] Now assume that data portions d0-d3 are stored in four memory locations in a first page of a first flash die, and data portions d4-d7 are stored in four memory locations in a second page of a second flash die.

[0066] The MCA included in cluster read request R0 indicates a first memory location within a first page of a first flash die, the MCA included in cluster read request R1 indicates a second memory location within the first page of the first flash die, the MCA included in cluster read request R2 indicates a third memory location within the first page of the first flash die, and the MCA included in cluster read request R3 indicates a fourth memory location within the first page of the first flash die.

[0067] The MCA included in cluster read request R4 indicates a first memory location within the second page of the second flash die, the MCA included in cluster read request R5 indicates a second memory location within the second page of the second flash die, the MCA included in cluster read request R6 indicates a third memory location within the second page of the second flash die, and the MCA included in cluster read request R7 indicates a fourth memory location within the second page of the second flash die.

[0068] The eight cluster read requests R0 to R7 generated by the cluster read request generating unit 421 are sent to the back-end unit of the controller 4 in the order of R0 to R7. The back-end unit instructs the NAND flash memory 5 to execute a data read operation based on the received eight cluster read requests R0 to R7. As a result, the eight data portions d0 to d7 are read from the NAND flash memory 5. The controller 4 transfers (sends) the eight read data portions d0 to d7 to the host 2 in LBA order, that is, in the order of data portions d0, d1, ..., d7. This completes the processing of the read command CMD0.

[0069] Next, a description will be given of the read process executed in the back-end unit of the controller 4. Fig. 5 is a block diagram showing an outline of a configuration example of the linked list manager (LLM) 44 of the SSD 3 and each command dispatcher (here, a command dispatcher (CD0) 451-0 and a command dispatcher (CD1) 451-1).

[0070] The linked list manager (LLM) 44 includes a plurality of CCID queues 100-0 to 100-n. The CCID queues 100-0 to 100-n may be realized by a latch circuit in the linked list manager (LLM) 44, or may be stored in the SRAM 43. Each of the CCID queues 100-0 to 100-n is a queue used to store a cluster read request associated with a certain CCID. Each CCID queue is also referred to as a read request queue. The CCID queue 100-0 is associated with CCID0. The CCID queue 100-n is associated with CCIDn. The linked list manager (LLM) 44 stores each cluster read request including CCID0 in the CCID queue 100-0, and stores each cluster read request including CCIDn in the CCID queue 100-n. The number of the plurality of CCID queues 100-0 to 100-n may correspond to a queue depth (QD). The queue depth is the number of commands that can be issued from host 2 to SSD 3 at one time.

[0071] Here, a case is assumed in which the command dispatcher (CD0) 451-0 is in charge of read processing for the flash die #0, and the command dispatcher (CD1) 451-1 is in charge of read processing for the flash die #x.

[0072] In this case, the command dispatcher (CD0) 451-0 includes one or more command queues corresponding to the flash die #0. In Fig. 5, a case is illustrated as an example in which the command dispatcher (CD0) 451-0 includes command queues 200-0-1 to 200-0-5 corresponding to the submission queues SQ1 to SQ5, respectively.

[0073] The command dispatcher (CD1) 451-1 includes one or more command queues corresponding to the flash die #x. In Fig. 5, a case is illustrated as an example in which the command dispatcher (CD1) 451-2 includes command queues 200-x-1 to 200-x-5 corresponding to the submission queues SQ1 to SQ5, respectively.

[0074] The command queues 200-0-1 to 200-0-5 and the command queues 200-x-1 to 200-x-5 may be stored in the SRAM 43.

[0075] Next, the operations performed by the linked list manager (LLM) 44 and each command dispatcher will be described.

[0076] Prior to describing the operation of the linked list manager (LLM) 44 and each command dispatcher, an overview of the read process executed by the controller 4 will be given.

[0077] In response to receiving a read command from the host 2, the controller 4 generates a plurality of cluster read requests by dividing the read target data into a plurality of data portions corresponding to a plurality of clusters. For example, when the read command CMD0 in Fig. 4 is received, the controller 4 generates cluster read requests R0 to R7.

[0078] The controller 4 stores the cluster read requests R0 to R7, from the cluster read request R0 corresponding to the first cluster of the clusters to the cluster read request R7 corresponding to the last cluster of the clusters, in the CCID queue 100-0 associated with the CCID0 assigned to the read command CMD0 so that the cluster read requests R0 to R7 are linked in this order. For example, the linked list management unit 44 manages the cluster read requests R0 to R7 stored in the CCID queue 100-0 using a linked list. Details of the data structure of the linked list will be described later with reference to FIG. 6. Hereinafter, the first cluster of the clusters corresponding to the data to be read is also referred to as the first cluster of the data to be read, and the last cluster of the clusters is also referred to as the last cluster of the data to be read.

[0079] The controller 4 stores CCID0 in the command queue corresponding to the flash die in which the data portion d0 corresponding to the first cluster of the read target data is stored. In this case, the controller 4 can identify the flash die in which the data portion d0 is stored based on the MCA included in the cluster read request R0. For example, if the flash die in which the data portion d0 is stored is flash die #0 and the SQID included in the cluster read request R0 is SQID1, the controller 4 stores CCID0 in the command queue 200-0-1 of the command dispatcher (CD0) 451-1.

[0080] In response to storing CCID0 in the command queue 200-0-1, the controller 4 refers to the cluster read requests R0-R7 stored in the CCID queue 100-0 starting from the first cluster read request R0 of the data to be read, thereby identifying the first storage area of ​​the flash die #0 in which the first data (data portions d0-d3) of the data to be read, including at least the data portion d0, is stored. The controller 4 generates a memory read request (page read request) for reading the first data (data portions d0-d3) of the data to be read from the first storage area of ​​the flash die #0. The controller 4 then issues the generated page read request to the flash die #0 via the NAND interface 46.

[0081] In the process of identifying the storage area, the controller 4 identifies each of the four storage locations of the flash die #0 where the data portions d0 to d3 are stored based on the MCAs included in the cluster read requests R0 to R3. Then, based on the identified four storage locations, the controller 4 generates a page read request for reading the first data (data portions d0 to d3) from the page (first storage area) including these four storage locations.

[0082] Here, unprocessed cluster read requests R4 to R7 remain in the CCID queue 100-0. In other words, the remaining data following the first data (data portions d0 to d3) is included in the read target data. In this case, the controller 4 transfers CCID0 from the command queue 200-0-1 to the command queue corresponding to the flash die in which the second data portion d4 corresponding to the first cluster of one or more clusters (here, four clusters) corresponding to the remaining data is stored.

[0083] The controller 4 can identify the flash die in which the second data portion d4 is stored based on the MCA included in the first cluster read request R4 among the unprocessed cluster read requests R4 to R7. For example, if the flash die in which the second data portion d4 is stored is flash die #x, the controller 4 transfers CCID0 from the command queue 200-0-1 to the command queue 200-x-1 of the command dispatcher (CD1) 451-2.

[0084] The transfer of CCID0 from command queue 200-0-1 to command queue 200-x-1 is executed via linked list management unit 44. That is, command dispatcher (CD0) 451-0 returns CCID0 to linked list management unit 44. Then, linked list management unit 44 transmits the returned CCID0 to command dispatcher (CD1) 451-1. As a result, CCID0 is stored in command queue 200-x-1.

[0085] In response to transferring CCID0 to the command queue 200-x-1, the controller 4 refers to the unprocessed cluster read requests (R4 to R5) stored in the CCID queue 100-0 from the cluster read request (R4) corresponding to the top cluster of one or more clusters (four clusters in this case) corresponding to the remaining data, thereby identifying the second storage area of ​​the flash die #x in which the top second data (data parts d4 to d5 in this case) of the remaining data, including at least the second data part d4, is stored. The controller 4 generates a memory read request (page read request) for reading the second data (data parts d4 to d5) from the second storage area of ​​the flash die #x. Then, the controller 4 issues the generated page read request to the flash die #x via the NAND interface 46.

[0086] In this case, the controller 4 identifies the four storage locations of the flash die #x where the data d4-d5 are stored based on the MCAs included in the cluster read requests R4-R7. Then, based on the identified four storage locations, the controller 4 generates a page read request to read data from the page including these four storage locations.

[0087] Through the above process, it is possible to generate a page read request for reading data d4-d7 from flash die #x after generating a page read request for reading data d0-d3 from flash die #0. Therefore, the first data (d0, d1, d2, d3) at the beginning of the read target data can be read from flash die #0 in the order of d0-d3, and then the second data (d4, d5, d6, d7) following the first data can be read from flash die #x in the order of d4-d7.

[0088] If the cluster read requests R0 to R7 were simultaneously distributed to the command queue corresponding to flash die #0 and the command queue corresponding to flash die #x, the second data that cannot be transferred to the host 2 immediately after being read would remain in the read buffer 431 of the SRAM 43 for a long time. This is because the process of transferring the second data to the host 2 cannot start until the process of transferring the first data to the host 2 is completed.

[0089] In this embodiment, it is possible to read the second data from the flash die #x after reading the first data from the flash die #0. Therefore, immediately after the first data is read from the flash die #0, the process of transferring the first data to the host 2 can be started, and immediately after the second data is read from the flash die #x, the process of transferring the second data to the host 2 can be started. In addition, while the first data is being read from the flash die #0, the flash die #x can be used for a data read operation associated with another read command. Therefore, compared to the case in which the cluster read requests R0 to R7 are simultaneously distributed to the command queue corresponding to the flash die #0 and the command queue corresponding to the flash die #x, it is possible to efficiently use the read buffer 431 of the SRAM 43, thereby improving the performance of the read process.

[0090] Next, the operation of the linked list manager (LLM) 44 and each command dispatcher will be described.

[0091] Here, a case will be described in which eight cluster read requests R0 to R7 generated by the cluster read request generator 421 in FIG. 4 are sent to the backend unit.

[0092] The linked list management unit 44 of the controller 4 receives the cluster read requests R0 to R7 from a front-end (FE) unit (for example, the cluster read request generation unit 421).

[0093] The linked list management unit 44 selects a CCID queue by referring to the CCIDs included in the received cluster read requests R0 to R7. Here, the linked list management unit 44 selects the CCID queue 100-0 associated with CCID0 included in the received cluster read requests R0 to R7.

[0094] The linked list management unit 44 stores the received cluster read requests R0 to R7 in the selected CCID queue 100-0. The linked list management unit 44 stores the cluster read requests R0 to R7 in the CCID queue 100-0 so that the cluster read requests R0 to R7 are linked in the same order as they were received.

[0095] The linked list management unit 44 determines which flash die contains the storage location where the data portion d0 associated with the cluster read request R0 stored in the CCID queue 100-0 is stored. Specifically, the linked list management unit 44 refers to the MCA included in the cluster read request R0. Then, the linked list management unit 44 determines that the storage location indicated by the MCA of the cluster read request R0 is included in the flash die #0.

[0096] The linked list management unit 44 transmits CCID0 to the command dispatcher (CD0) 451-0 corresponding to the flash die #0. The command dispatcher (CD0) 451-0 includes five command queues 200-0-1 to 200-0-5. As described above, the five command queues 200-0-1 to 200-0-5 correspond to the submission queues SQ1 to SQ5, respectively. If the read command CMD0 corresponding to CCID0 is stored in the submission queue SQ1, the command dispatcher (CD0) 451-0 stores CCID0 in the command queue 200-0-1.

[0097] The command dispatcher (CD0) 451-0 selects one command queue from which the CCID is to be fetched from among the command queues 200-0-1 to 200-0-5. For example, the command dispatcher (CD0) 451-0 may select one command queue from which the CCID is to be fetched by using round-robin arbitration.

[0098] In response to fetching CCID0 from command queue 200-0-1, command dispatcher (CD0) 451-0 obtains cluster read requests R0 to R3 from CCID queue 100-0 corresponding to CCID0.

[0099] The command dispatcher (CD0) 451-0 generates a page read request for reading the data portions d0 to d3 based on the acquired cluster read requests R0 to R3. The command dispatcher (CD0) 451-0 transmits the generated page read request to the flash die #0 via the NAND interface 46.

[0100] After generating the page read request, the command dispatcher (CD0) 451-0 returns CCID0 to the linked list management unit 44. Furthermore, the command dispatcher (CD0) 451-0 notifies the linked list management unit 44 of the number of processed cluster read requests (here, 4).

[0101] When CCID0 is returned, the linked list management unit 44 deletes the cluster read requests R0 to R3 from the CCID queue 100-0. The linked list management unit 44 refers to the first cluster read request R4 among the remaining cluster read requests R4 to R7 in the CCID queue 100-0. Based on the MCA included in the cluster read request R4, the linked list management unit 44 determines that the data portion d4 associated with the cluster read request R4 is stored in the flash die #x. The linked list management unit 44 transmits CCID0 to the command dispatcher (CD1) 451-2 corresponding to the flash die #x. The command dispatcher (CD1) 451-1 stores CCID0 in the command queue 200-x-1 corresponding to the submission queue SQ1.

[0102] The command dispatcher (CD1) 451-1 selects the command queue 200-x-1 and obtains CCID0.

[0103] In response to acquiring CCID0, the command dispatcher (CD1) 451-1 acquires the unprocessed cluster read requests R4 to R7 from the CCID queue 100-0 corresponding to CCID0.

[0104] The command dispatcher (CD1) 451-1 generates a page read request for reading the data portions d4 to d7 based on the acquired cluster read requests R4 to R7. The command dispatcher (CD1) 451-1 transmits the generated page read request to the flash die #x via the NAND interface 46.

[0105] After generating the page read request, the command dispatcher (CD1) 451-1 returns the acquired CCID0 to the linked list management unit 44. Furthermore, the command dispatcher (CD1) 451-1 notifies the linked list management unit 44 of the number of processed cluster read requests (here, 4).

[0106] When CCID0 is returned, the linked list management unit 44 deletes the cluster read requests R4 to R7 from the CCID queue 100-0. Then, since no unprocessed cluster read requests are stored in the CCID queue 100-0 corresponding to the returned CCID0, the linked list management unit 44 releases the correspondence between the read command CMD0 and CCID0. Then, CCID0 becomes an identifier that can be assigned to a new read command.

[0107] Next, a CCID queue realized as a linked list will be described. Fig. 6 is a diagram showing an example of the configuration of a linked list managed by the linked list management unit 44 of the SSD 3 according to the embodiment.

[0108] Linked list management unit 44 manages a plurality of CCID queues 100-0 to 100-n. CCID queues 100-0 to 100-n correspond to CCID0 to CCIDn, respectively. Each of CCID queues 100-0 to 100-n stores a cluster read request generated based on a read command corresponding to each of CCID0 to CCIDn. The cluster read requests stored in each of CCID queues 100-0 to 100-n are managed by a linked list.

[0109] One or more cluster read requests generated based on a read command corresponding to a certain CCID are managed by one linked list. In the linked list, a node corresponding to each cluster read request is managed. Each node includes information indicating the contents of the cluster read request and a pointer indicating the node of the subsequent cluster read request. Instead of the information indicating the contents of the cluster read request, the node may include a pointer indicating a storage location in the memory of the linked list management unit 44 where the information indicating the contents of the cluster read request is stored.

[0110] Specifically, the cluster read requests R0 to R7 stored in the CCID queue 100-0 are managed in one linked list. These cluster read requests R0 to R7 are cluster read requests generated based on the read command CMD0 corresponding to CCID0. In this linked list, the node corresponding to the cluster read request R0 is managed as the first node. The pointer included in the node corresponding to the cluster read request R0 indicates the node corresponding to the subsequent cluster read request R1. And the pointer included in the node corresponding to the cluster read request R1 indicates the node corresponding to the cluster read request R2. In this way, the pointers of the nodes corresponding to the cluster read requests R0 to R6 indicate the nodes corresponding to the subsequent cluster read requests. Also, the pointer included in the last cluster read request R7 may be set to, for example, an invalid value. The linked list management unit 44 can determine that the cluster read request R7 is the last cluster read request by referring to the pointer set to an invalid value.

[0111] In this way, the controller 4 manages the cluster read requests R0 to R7 stored in the CCID queue 100-0 using a linked list for linking the cluster read requests R0 to R7 in the order of cluster read request R0 corresponding to the first cluster of the data to be read to cluster read request R7 corresponding to the last cluster.

[0112] Also, the cluster read requests stored in the other CCID queues 100-1 to 100-n are each managed by one linked list, and a linked list similar to the linked list corresponding to CCID0 described above is used.

[0113] In this way, by managing the cluster read requests R0 to R7 using a linked list for linking the cluster read requests R0 to R7, it is possible to easily delete processed cluster read requests, add new cluster read requests, and so on, while correctly maintaining the order relationship between the cluster read requests R0 to R7.

[0114] Here, we have described the case where cluster read requests stored in the CCID queue are managed using a linked list, but not only cluster read requests stored in the CCID queue, but also CCIDs stored in the command queue can be managed using a linked list.

[0115] Next, a detailed configuration of the linked list management unit 44 and the command dispatcher 451 will be described. Fig. 7 is a diagram for explaining a more detailed configuration example of the linked list management unit and the command dispatcher used in the SSD 3 according to the embodiment, taking a process at the time of executing a read as an example.

[0116] First, the configuration of the linked list management unit and the command dispatcher will be described in more detail.

[0117] The linked list management unit 44 assigns a leading or following attribute to each of the multiple CCIDs. For a read command in which the read process of the first cluster has not yet started, the linked list management unit 44 assigns the leading attribute to the CCID of the read command. For a read command in which the read process of the first cluster has already started, the linked list management unit 44 assigns the following attribute to the CCID of the read command.

[0118] Linked list management unit 44 includes multiplexer 101, demultiplexer 102, demultiplexer 103, multiplexer 104, and message memory 105, in addition to CCID queues 100-0 to 100-4.

[0119] When the multiplexer 101 receives a cluster read request from the front-end unit and the CCID has a leading attribute, in other words, when the multiplexer 101 receives a cluster read request from the front-end unit corresponding to the first cluster of the read command, the multiplexer outputs the CCID contained in the received cluster read request and an attribute indicating leading to the demultiplexer 102.

[0120] In addition, when a CCID is returned from the command dispatcher CD and there is an unprocessed cluster read request in the CCID queue corresponding to that CCID, the multiplexer 101 outputs the returned CCID and an attribute indicating following to the demultiplexer 102.

[0121] The demultiplexer 102 distributes the CCID and leading / following attribute output from the multiplexer 101 to a command dispatcher CD responsible for the flash die in which the data portion corresponding to the first cluster (in the case of leading, the first cluster of the data to be read, and in the case of following, the first cluster of the remaining unprocessed data) is stored.

[0122] The demultiplexer 103 selects a CCID queue from the CCID queues 100-0 to 100-4 that corresponds to the CCID included in the cluster read request received from the front end unit, and distributes the received cluster read request to the selected CCID queue.

[0123] 7, the cluster read request itself is stored in the message memory 105. The CCID queue stores a pointer indicating the storage location in the message memory 105 where the cluster read request is stored.

[0124] The CCID queues 100-0 to 100-4 and the message memory 105 can be referenced by all command dispatchers CD.

[0125] The multiplexer 104 selects one of the CCID queues 100-0 to 100-4 based on a read access request from the command dispatcher CD, and transmits the information stored in the selected CCID queue to the command dispatcher CD.

[0126] The message memory 105 stores each cluster read request received by the linked list manager 44 .

[0127] Next, the configuration of the command dispatcher CD will be described. Here, the description focuses on the command dispatcher (CD0) 451-0 corresponding to the flash die #0, but other command dispatchers (for example, the command dispatcher (CD1) 451-1) also have a similar configuration to the command dispatcher (CD0) 451-0.

[0128] The command dispatcher (CD0) 451-0 is responsible for, for example, planes PLN0 to PLN3 of flash die #0, planes PLN0 to PLN3 of flash die #1, ..., and planes PLN0 to PLN3 of flash die #N. Here, the following description focuses on the components of the command dispatcher (CD0) 451-0 that correspond to plane PLN0 of flash die #0.

[0129] The command dispatcher (CD0) 451-0 includes a following queue 200F-00, leading queues 200L-00-1 to 200L-00-5, a demultiplexer 301, a demultiplexer 302, a demultiplexer 303, a multiplexer 304, a multiplexer 305, a page read request generator 306, a demultiplexer 307, and a multiplexer 308.

[0130] The following queue 200F-00 and the leading queues 200L-00-1 to 200L-00-5 are used as a command queue group corresponding to the plane PLN0 of the flash die #0.

[0131] The following queue 200F-00 stores one or more CCIDs. The following queue 200F-00 stores CCIDs having following attributes.

[0132] Each of the leading queues 200L-00-1 to 200L-00-5 stores one or more CCIDs. Each of the leading queues 200L-00-1 to 200L-00-5 stores a CCID having a leading attribute. The leading queues 200L-00-1 to 200L-00-5 correspond to the submission queues SQ1 to SQ5, respectively. The leading queues 200L-00-1 to 200L-00-5 store CCIDs corresponding to read commands issued via the corresponding submission queues.

[0133] The page read queues 300-000 to 300-N3X store page read requests. The page read queues 300-000 to 300-N3X correspond to combinations of a flash die, a plane, and a domain. The total number of domains 0 to X may be two or more. The controller 4 manages the correspondence between the domains 0 to X and the submission queues SQ1 to SQ5 so that one or more of the submission queues SQ1 to SQ5 belong to one domain. For example, when two domains (domain 0 and domain 1) are managed, each of the submission queues SQ1 to SQ5 belongs to only one of the domains, either domain 0 or domain 1. The correspondence between the domains 0 to X and the submission queues SQ1 to SQ5 may be specified in advance by the host 2. The controller 4 also manages a plurality of weights (priorities) associated with the domains 0 to X. For this reason, the domains are also referred to as priority groups. Each page read queue is also referred to as a domain queue.

[0134] Also, the correspondence between multiple domains (0 to X) and multiple name spaces may be managed, for example, so that two or more submission queues are assigned to one domain. A name space is uniquely identified by a name space identifier (NSID). When a name space is used, the read command and the cluster read request may include the name space identifier. Also, when the SSD 3 includes multiple ports (e.g., dual ports), that is, when the controller 4 includes multiple host interfaces, the correspondence between multiple domains (0 to X) and multiple ports may be managed, for example, so that two or more submission queues are assigned to one domain. In the following, a case where the correspondence between each domain and each SQ is managed will be described.

[0135] For the plane PLN0 of the flash die #0, the controller 4 manages X+1 page read queues corresponding to the domains 0 to X, respectively.

[0136] For example, page read queue 300-000 is a domain queue corresponding to (flash die #0, plane PLN0, domain 0). Page read queue 300-000 stores page read requests generated based on cluster read requests belonging to read commands fetched from any of the submission queues belonging to domain 0, among page read requests for reading data in storage locations included in plane PLN0 of flash die #0.

[0137] Similarly, the page read queue 300-00X is a domain queue corresponding to (flash die #0, plane PLN0, domain X). The page read queue 300-00X stores page read requests generated based on cluster read requests belonging to read commands fetched from any of the submission queues belonging to domain X, among page read requests for reading data in memory locations included in plane PLN0 of flash die #0.

[0138] When a page read request is output from a page read queue, a release request is sent to message memory 105. The release request is a request to release the storage area in message memory 105 in which the cluster read request used to generate the page read request is stored. The released storage area becomes available for storing new cluster read requests.

[0139] The demultiplexer 301 distributes the received CCID based on the flash die and plane. The demultiplexer 301 identifies the flash die and plane in which the data portion associated with the first cluster read request stored in the CCID queue corresponding to the received CCID is stored. The demultiplexer 301 then distributes the received CCID to one of the command queues (the following queue and the multiple leading queues) corresponding to the identified flash die and plane.

[0140] If the received CCID has a following attribute, the demultiplexer 302 stores this CCID in the following queue 200F-00. If the received CCID has a leading attribute, the demultiplexer 302 passes this CCID to the demultiplexer 303.

[0141] The demultiplexer 303 distributes the received CCID to one of the leading queues 200L-00-1 to 200L-00-5. Specifically, the demultiplexer 303 selects the leading queue corresponding to the submission queue from which the read command corresponding to the received CCID is fetched. The demultiplexer 303 then stores the received CCID in the selected leading queue.

[0142] If the read command corresponding to the received CCID is, for example, a read command fetched from the submission queue SQ1, the demultiplexer 303 stores the received CCID in the reading queue 200L-00-1. If the read command corresponding to the received CCID is, for example, a read command fetched from the submission queue SQ3, the demultiplexer 303 stores the received CCID in the reading queue 200L-00-1.

[0143] The multiplexer 304 selects a leading queue from which the CCID should be fetched. The multiplexer 304 is realized, for example, by a round robin arbitration mechanism. The multiplexer 304 sequentially selects a leading queue that stores the CCID from among the leading queues 200L-00-1 to 200L-00-5. Then, the multiplexer 304 outputs the CCID stored in the selected leading queue.

[0144] The multiplexer 305 selects the CCID to be processed. If a CCID is stored in the following queue 200F-00, the multiplexer 305 acquires the CCID stored in the following queue 200F-00 and transmits it to the page read request generating unit 306. If no CCID is stored in the following queue 200F-00, the multiplexer 305 selects the CCID output from the multiplexer 304 and transmits the selected CCID to the page read request generating unit 306.

[0145] In this way, the multiplexer 305 selects the CCID stored in the following queue 200F-00 as the CCID to be processed, giving priority over the CCIDs stored in the leading queues 200L-00-1 to 200L-00-5.

[0146] The page read request generator 306 generates a page read request based on the CCID received from the multiplexer 305 (i.e., the CCID to be processed). The page read request generator 306 sequentially refers to the cluster read requests stored in the CCID queue corresponding to the CCID to be processed, starting from the top, and obtains, for example, four pointers indicating storage locations where the four cluster read requests are stored from the CCID queue. Then, based on the received pointers, the page read request generator 306 obtains the four cluster read requests from the message memory 105. The page read request generator 306 generates a page read request based on the received four cluster read requests.

[0147] After generating the page read request, the page read request generator 306 returns the CCID to be processed to the linked list manager 44. The timing of returning the CCID to the linked list manager 44 can be changed depending on the workload and the like.

[0148] The demultiplexer 307 distributes the page read request to one of the page read queues 300-000 to 300-00X based on the domain to which the submission queue from which the read command corresponding to the CCID to be processed is fetched belongs. For example, if the submission queue from which the read command corresponding to the CCID to be processed is fetched is the submission queue SQ1 and the submission queue SQ1 belongs to domain 0, the demultiplexer 307 selects the page read queue 300-000 corresponding to domain 0 and stores the page read request in the page read queue 300-000.

[0149] The multiplexer 308 selects a page read queue from which the page read request should be fetched. That is, the multiplexer 308 performs an arbitration process to select a page read queue from which the page read request should be fetched from the page read queues 300-000 to 300-00X based on the weights associated with the domains 0 to X, respectively. This arbitration process is performed based on, for example, weighted fair queuing. The multiplexer 308 issues the page read request stored in the selected page read queue to the flash die #0 (more specifically, the plane PLN0 of the flash die #0) via the NAND interface 46.

[0150] Next, the procedure (steps (S1) to (S9)) of the read process executed using the linked list management unit and the command dispatcher explained in Fig. 7 will be explained with reference to the same figure. In response to receiving a cluster read request from the front-end unit, the back-end unit of the controller 4 starts the read process.

[0151] Step (S1): The linked list management unit 44 stores the received cluster read request in a CCID queue. The CCID queue in which the cluster read request is stored is a CCID queue corresponding to the CCID included in the received cluster read request. In this case, for example, the linked list management unit 44 stores information indicating the contents of the cluster read request in the message memory 105, and stores a node including a pointer or the like indicating the storage position in the message memory 105 where the contents of the cluster read request are stored in the CCID queue as an element of the linked list.

[0152] Step (S2): When a cluster read request is received from the front end unit and the CCID included in the received cluster read request is a leading attribute, the linked list management unit 44 transmits this CCID and an attribute indicating leading to the command dispatcher CD in charge of the flash die in which the data portion corresponding to the first cluster is stored. The first cluster is the first cluster of the read target data associated with the read command corresponding to this CCID. The linked list management unit 44 identifies the flash die in which the data portion corresponding to the first cluster is stored based on the MCA included in the first cluster read request among the cluster read requests including this CCID.

[0153] In addition, when a CCID is returned from a certain command dispatcher CD and an unprocessed cluster read request exists in the CCID queue corresponding to the returned CCID, the linked list management unit 44 transmits the CCID and an attribute indicating following to the command dispatcher CD in charge of the flash die in which the data portion corresponding to the first cluster of the remaining unprocessed data is stored. The data portion corresponding to the first cluster of the remaining data is a data portion associated with the first cluster read request of the unprocessed cluster read requests including this CCID. The linked list management unit 44 identifies the flash die in which the data portion corresponding to the first cluster of the remaining data is stored based on the MCA included in the first cluster read request of the unprocessed cluster read requests including this CCID.

[0154] For example, if the data portion corresponding to the first cluster is stored in plane PLN0 of flash die #0, the linked list management unit 44 transmits the CCID and the leading / following attribute of this CCID to the command dispatcher (CD0) 451-0.

[0155] Step (S3): The command dispatcher CD that has received the CCID selects a command queue in which the received CCID should be stored, based on the plane in which the data portion corresponding to the first cluster is stored, the die that contains that plane, the attributes of the received CCID, and the submission queue SQ from which the corresponding read command was fetched.

[0156] For example, if the data portion corresponding to the first cluster is stored in plane PLN0 of flash die #0 and the received CCID has a leading attribute, the command dispatcher (CD0) 451-0 selects a leading queue from the leading queues 200L-00-1 to 200L-00-5 that corresponds to the submission queue SQ from which the corresponding read command was fetched. Then, the command dispatcher (CD0) 451-0 stores the received CCID in the selected leading queue.

[0157] Also, for example, if the data portion corresponding to the first cluster is stored in plane PLN0 of flash die #0 and the received CCID has a following attribute, the command dispatcher (CD0) 451-0 selects the following queue 200F-00 and stores the received CCID in the selected following queue 200F-00.

[0158] Step (S4): The command dispatcher (CD0) 451-0 selects a leading queue from which the CCID should be fetched from among the leading queues 200L-00-1 to 200L-00-5, taking into consideration fairness among the submission queues SQ1 to SQ5. The command dispatcher (CD0) 451-0 obtains the CCID from the selected leading queue.

[0159] Step (S5): If a CCID is stored in the following queue 200F-00, the command dispatcher (CD0) 451-0 acquires the CCID stored in the following queue 200F-00 and transmits it to the page read request generation unit 306. If a CCID is not stored in the following queue 200F-00, the command dispatcher (CD0) 451-0 transmits the CCID acquired from the leading queue in step (S4) to the page read request generation unit 306.

[0160] Step (S6): The page read request generating unit 306 generates a page read request by referring to the cluster read requests stored in the CCID queue corresponding to the CCID received in step (S5), starting from the first cluster read request. In this case, the page read request generating unit 306 generates a page read request for reading one page of data based on four cluster read requests. Note that if the number of read commands received from the host 2 is small and there is sufficient available space in the SRAM 43, the page read request generating unit 306 may generate multiple page read requests based on a larger number of cluster read requests stored in the CCID queue. Then, the page read request generating unit 306 returns the received CCID to the linked list managing unit 44.

[0161] When the CCID is returned to the linked list manager 44, the linked list manager 44 removes the processed cluster read requests (the four cluster read requests used to generate the page read request) from the CCID queue.

[0162] Step (S7): The command dispatcher (CD0) 451-0 distributes the page read request generated in step (S6) to one of the page read queues 300-000 to 300-N3X. In this case, the command dispatcher (CD0) 451-0 determines the page read queue to which the page read request should be distributed based on the plane storing the data to be read, the flash die including this plane, and the domain to which the submission queue from which the corresponding read command is fetched belongs. Then, the command dispatcher (CD0) 451-0 transmits a release request to the message memory 105, and releases the storage area of ​​the message memory 105 in which the cluster read request used to generate the page read request is stored. Note that the linked list management unit 44 may release the storage area of ​​the message memory 105 based on the release request from the command dispatcher (CD0) 451-0.

[0163] Step (S8): The command dispatcher (CD0) 451-0 executes an arbitration process (WFQ) for selecting a page read queue from which the page read request should be fetched from among the page read queues 300-000 to 300-N3X based on the weights associated with the domains 0 to X, respectively. This WFQ makes it possible to fairly select domains associated with the same weight among several domains belonging to the same flash die. Then, the command dispatcher (CD0) 451-0 issues the page read request stored in the selected page read queue to the NAND flash memory 5. For example, when the page read queue 300-000 is selected, the command dispatcher (CD0) 451-0 issues the page read request stored in the page read queue 300-000 to the plane PLN0 of the flash die #0.

[0164] Here, the read process corresponding to the cluster read requests R0 to R7 explained in Fig. 4 will be explained. In the following, it is assumed that the first data (d0 to d3) corresponding to the cluster read requests R0 to R3 is stored in the flash die #0, and the second data (d4 to d7) corresponding to the cluster read requests R4 to R7 is stored in the flash die #x. The command dispatcher CD in charge of the flash die #0 is the command dispatcher CD0, and the command dispatcher CD in charge of the flash die #x is the command dispatcher CD1.

[0165] The controller 4 manages the five leading queues corresponding to the submission queues SQ1 to SQ5 as a leading queue group corresponding to the flash die #0. Furthermore, the controller 4 manages the five leading queues corresponding to the submission queues SQ1 to SQ5 as a leading queue group corresponding to the flash die #x.

[0166] First, a read process in which a page read queue group corresponding to a domain group is not used will be described.

[0167] 4 is fetched from the submission queue SQ1, the controller 4 selects a reading queue corresponding to the submission queue SQ1 from the reading queue group corresponding to the flash die #0. The controller 4 stores the identifier (CCID0) assigned to the read command CMD0 in the selected reading queue.

[0168] The controller 4 executes an arbitration process to select a reading queue from which a CCID should be fetched from the reading queue group corresponding to the flash die #0. When CCID0 is fetched from the reading queue corresponding to the submission queue SQ1 by this arbitration process, the controller 4 generates a page read request to read the first data (d0 to d3) from the flash die #0, and issues the generated page read request to the flash die #0.

[0169] Next, a read process when using a page read queue group corresponding to a domain group will be described.

[0170] The controller 4 manages the correspondence between the domains 0 to X and the submission queues SQ1 to SQ5 so that one or more of the submission queues SQ1 to SQ5 belongs to one domain.

[0171] For the flash die #0, the controller 4 manages X+1 first page read queues corresponding to the domains 0 to X. For the flash die #x, the controller 4 manages X+1 second page read queues corresponding to the domains 0 to X.

[0172] In response to generating a page read request for reading the first data (d0 to d3) from the flash die #0, the controller 4 selects one of the X+1 first page read queues corresponding to one domain to which the submission queue (here, SQ1) from which the read command CMD0 is fetched belongs. Then, the controller 4 stores the generated page read request in the selected one of the first page read queues.

[0173] The controller 4 performs an arbitration process (WFQ) to select a page read queue from which the page read request should be fetched from among the X+1 first page read queues based on a plurality of weights associated with the domains 0 to X.

[0174] When a page read queue in which a page read request for reading the first data (d0 to d3) is stored is selected by WFQ, the controller 4 fetches the page read request for reading the first data (d0 to d3) from the selected page read queue. Then, the controller 4 issues the page read request for reading the first data (d0 to d3) to the flash die #0.

[0175] Next, a process that is executed after generating a page read request for reading the second data (d4 to d7) from the flash die #x will be described.

[0176] In response to generating the page read request for reading the second data (d4 to d7) from the flash die #x, the controller 4 selects one of the X+1 second page read queues corresponding to one domain to which the submission queue (here, SQ1) from which the read command CMD0 is fetched belongs. Then, the controller 4 stores the generated page read request in the selected one of the second page read queues.

[0177] The controller 4 performs an arbitration process (WFQ) to select a page read queue from which the page read request should be fetched from among the X+1 second page read queues based on a plurality of weights associated with the domains 0 to X.

[0178] When the page read queue in which the page read request for reading the second data (d4 to d7) is stored is selected by WFQ, the controller 4 fetches the page read request for reading the second data (d4 to d7) from the selected page read queue. Then, the controller 4 issues the page read request for reading the second data (d4 to d7) to the flash die #x.

[0179] Next, an example of how the read buffer 431 is used in a read process will be described. First, an example of how the read buffer is used in a comparative example will be considered. Fig. 8 is a diagram showing an example of how read data is managed in a memory system according to the comparative example.

[0180] In FIG. 8, it is assumed that data is written across two flash dies (die#0, die#1) such that four clusters' worth of data is written per flash die.

[0181] As shown in FIG. 8A, each of the read commands CMD-A, CMD-B, and CMD-D is a read command for reading data stored in two flash dies (die#0, die#1). The read command (CCID0) CMD-A is associated with read target data having a size of 9 clusters. The read command (CCID1) CMD-B is associated with read target data having a size of 6 clusters. The read command (CCID2) CMD-C is associated with read target data having a size of 2 clusters. The read command (CCID3) CMD-D is associated with read target data having a size of 5 clusters.

[0182] As shown in FIG. 8B, cluster read requests in number corresponding to the size of the read target data associated with each read command are generated based on each read command. For example, based on read command (CCID0) CMD-A, nine cluster read requests are generated for reading data parts A0 to A8, respectively. Based on read command (CCID1) CMD-B, six cluster read requests are generated for reading data parts B0 to B5, respectively. Based on read command (CCID2) CMD-C, two cluster read requests are generated for reading data parts C0 to C1, respectively. Based on read command (CCID3) CMD-D, five cluster read requests are generated for reading data parts D0 to D4, respectively.

[0183] For flash die #0, multiple cluster read requests are performed such that the data portions are read in the following order: A0, A1, A2, A3, A8, B0, B1, B2, B3, D4, and for flash die #1, multiple cluster read requests are performed such that the data portions are read in the following order: A4, A5, A6, A7, B4, B5, C0, C1, D0, D1, D2, D3.

[0184] First, when data portion A0 is read from flash die #0 and data portion A4 is read from flash die #1, a first read buffer RB1 is allocated from SRAM and data portion A0 is stored in the first read buffer RB1, and a second read buffer RB2 is allocated from SRAM and data portion A4 is stored. The controller transfers data portion A0 to the host. On the other hand, data portion A4 is data that cannot be transferred to the host until data portion A3 is transferred to host 2, and therefore occupies the second read buffer RB2. In other words, data portion A4 is retained in the second read buffer RB2.

[0185] Therefore, in order to temporarily store the data that is subsequently read, it becomes necessary to allocate other read buffers (the third read buffer RB3 to the fifth read buffer RB5) from the SRAM.

[0186] Specifically, when data portion A1 is read from flash die #0 and data portion A5 is read from flash die #1, data portion A1 is stored in the first read buffer RB1, and data portion A5 is stored in the third read buffer RB3 newly allocated from the SRAM. The controller transfers data portion A1 to the host. Meanwhile, data portion A5 occupies the third read buffer RB3 because data portion A5 cannot be transferred to the host until data portion A4 is transferred to host 2.

[0187] Next, when data portion A2 is read from flash die #0 and data portion A6 is read from flash die #1, data portion A2 is stored in the first read buffer RB1, and data portion A6 is stored in the fourth read buffer RB4 newly allocated from the SRAM. The controller transfers data portion A2 to the host. Meanwhile, data portion A6 occupies the fourth read buffer RB4 because data portion A6 cannot be transferred to the host until data portion A5 is transferred to host 2.

[0188] Next, when data portion A3 is read from flash die #0 and data portion A7 is read from flash die #1, data portion A3 is stored in the first read buffer RB1, and data portion A7 is stored in the fifth read buffer RB5 newly allocated from the SRAM. The controller transfers data portion A3 to the host. Meanwhile, data portion A7 occupies the fifth read buffer RB5 because data portion A7 cannot be transferred to the host until data portion A6 is transferred to host 2.

[0189] When data portion A3 is transferred to the host, data portion A4, which had been occupying read buffer RB2, becomes available for transfer to the host. When data portion A4 is transferred, subsequent data portions A5, A6, and A7 also become available for transfer in sequence, and read buffers RB3, RB4, and RB5 become available for use again.

[0190] When data portion A8 is read from flash die #0 and data portion B4 is read from flash die #1, data portion A8 is stored in the first read buffer RB1, and data portion B4 is stored in the second read buffer RB2, which becomes available after data portion A4 is transferred to the host. Data portion A8 stored in the first read buffer RB1 becomes transferable after data portion A7 is transferred to the host. On the other hand, data portion B4 occupies the second read buffer RB2 because it cannot be transferred to the host until data portion B3, which has not yet been read from flash die #3, is transferred.

[0191] In this way, in the comparative example, data reading based on cluster read requests corresponding to the same CCID is executed simultaneously on two flash dies, so that data portions that cannot be immediately transferred to the host are stored in the read buffer. Therefore, as shown in FIG. 9, the first read buffer RB1 to the fifth read buffer RB5 are required when reading data portions A0 to A8 corresponding to the read command CMD-A.

[0192] On the other hand, in the read process in this embodiment, when the page read request generating unit 306 generates a page read request, the CCID is returned to the linked list managing unit 44, and then the CCID is transferred to the command dispatcher for the subsequent page read request. Therefore, the subsequent page read request is issued after the preceding page read request is issued. Figure 9 is a diagram showing an example of management of read data in the memory system according to the embodiment.

[0193] FIG. 9A also shows a case where a cluster read request similar to that in FIG. 8A is generated.

[0194] 9B, multiple cluster read requests are executed in flash die #0 such that multiple data portions are read in the following order: A0, A1, A2, A3, B0, B1, B2, B3, D4, A8, and multiple cluster read requests are executed in flash die #1 such that multiple data portions are read in the following order: C0, C1, D0, D1, D2, D3, A4, A5, A6, A7, B4, B5.

[0195] First, when data portion A0 is read from flash die #0 and data portion C0 is read from flash die #1, a first read buffer RB1 is allocated from SRAM 43 and data portion A0 is stored in the first read buffer RB1, and a second read buffer RB2 is allocated from SRAM 43 and data portion C0 is stored in the second read buffer RB2. The controller 4 transfers data portion A0 to the host 2. Then, when the transfer of data portion A0 is completed, the controller 4 transfers data portion C0 to the host 2. Since data portion A0 and data portion C0 are the first data portions of the data portions corresponding to the read command CMD-A and the read command CMD-C, respectively, there is no need to wait for the other data portions to be transferred to the host 2.

[0196] As a result, the first read buffer RB1 and the second read buffer RB2 are in a state in which new data can be stored until the reading of the subsequent data portions A1 and C1 is completed.

[0197] Thereafter, when data portion A1 is read from flash die #0 and data portion C1 is read from flash die #1, data portion A1 is stored in the first read buffer RB1 and data portion C1 is stored in the second read buffer RB2. When data portion A1 is read, the transfer of data portion A0 has already been completed, so the controller 4 transfers data portion A1 to the host 2. Then, when the transfer of data portion A1 is finished, the transfer of data portion C0 has already been completed, so the controller 4 transfers data portion C1 to the host 2. This completes the reading of the data portion corresponding to the read command CMD-C.

[0198] Next, when data portion A2 is read from flash die #0 and data portion D0 is read from flash die #1, data portion A2 is stored in the first read buffer RB1, and data portion D0 is stored in the second read buffer RB2. When data portion A2 is read, the transfer of data portion A1 has already been completed, so the controller 4 transfers data portion A2 to the host 2. Then, when the transfer of data portion A2 is completed, data portion D0 is transferred to the host 2. Since data portion D0 is the first data portion among the data portions corresponding to the read command CMD-D, there is no need to wait for other data portions.

[0199] Next, when data portion A3 is read from flash die #0 and data portion D1 is read from flash die #1, data portion A3 is stored in the first read buffer RB1 and data portion D1 is stored in the second read buffer RB2. When data portion A3 is read, the transfer of data portion A2 has already been completed, so the controller 4 transfers data portion A3 to the host 2. Then, when the transfer of data portion A3 is finished, the transfer of data portion D0 has already been completed, so the controller 4 transfers data portion D1 to the host 2.

[0200] Next, when data portion B0 is read from flash die #0 and data portion D2 is read from flash die #1, data portion B0 is stored in the first read buffer RB1, and data portion D2 is stored in the second read buffer RB2. Since data portion B0 is the first data portion among the data portions corresponding to the read command CMD-B, when data portion B0 is read, the controller 4 transfers data portion B0 to the host 2. Then, when the transfer of data portion B0 is finished, since the transfer of data portion D1 has already been completed, the controller 4 transfers data portion D1 to the host 2.

[0201] Next, when data portion B1 is read from flash die #0 and data portion D3 is read from flash die #1, data portion B1 is stored in the first read buffer RB1 and data portion D3 is stored in the second read buffer RB2. Since the transfer of data portion B0 has already been completed, when data portion B1 is read, the controller 4 transfers data portion B1 to the host 2. Then, when the transfer of data portion B1 is finished, since the transfer of data portion D2 has already been completed, the controller 4 transfers data portion D3 to the host 2.

[0202] Next, when data portion B2 is read from flash die #0 and data portion A4 is read from flash die #1, data portion B2 is stored in the first read buffer RB1 and data portion A4 is stored in the second read buffer RB2. Since the transfer of data portion B1 has already been completed, when data portion B2 is read, the controller 4 transfers data portion B2 to the host 2. Then, when the transfer of data portion B2 is finished, since the transfer of data portion A3 has already been completed, the controller 4 transfers data portion A4 to the host 2.

[0203] Next, when data portion B3 is read from flash die #0 and data portion A5 is read from flash die #1, data portion B3 is stored in the first read buffer RB1 and data portion A5 is stored in the second read buffer RB2. Since the transfer of data portion B2 has already been completed, when data portion B3 is read, the controller 4 transfers data portion B3 to the host 2. Then, when the transfer of data portion B3 is finished, since the transfer of data portion A4 has already been completed, the controller 4 transfers data portion A5 to the host 2.

[0204] Next, when data portion D4 is read from flash die #0 and data portion A6 is read from flash die #1, data portion D4 is stored in the first read buffer RB1 and data portion A6 is stored in the second read buffer RB2. Since the transfer of data portion D3 has already been completed, when data portion D4 is read, the controller 4 transfers data portion D4 to the host 2. This completes the reading of the data portion corresponding to the read command CMD-D. Then, when the transfer of data portion D4 is finished, since the transfer of data portion A5 has already been completed, the controller 4 transfers data portion A6 to the host 2.

[0205] Next, when the data portion A7 is read from the flash die #1, the data portion A7 is stored in the first read buffer RB1. Since the transfer of the data portion A6 has already been completed, when the data portion A7 is read, the controller 4 transfers the data portion A7 to the host 2.

[0206] Next, when data portion A8 is read from flash die #0 and data portion B4 is read from flash die #1, data portion A8 is stored in the first read buffer RB1 and data portion B4 is stored in the second read buffer RB2. Since the transfer of data portion A7 has already been completed, when data portion A8 is read, the controller 4 transfers data portion A8 to the host 2. This completes the reading of the data portion corresponding to the read command CMD-A. Then, when the transfer of data portion A8 is finished, since the transfer of data portion B3 has already been completed, the controller 4 transfers data portion B4 to the host 2.

[0207] Next, when data portion B5 is read from flash die #1, data portion B5 is stored in the first read buffer RB1. Since the transfer of data portion B4 has already been completed, the controller 4 transfers data portion B5 to the host 2. This completes the reading of the data portion corresponding to the read command CMD-B.

[0208] Thus, in this embodiment, the data portion read from the NAND flash memory 5 is in a state that can be transferred to the host 2 because the previous data in LBA order has already been transferred to the host 2. Therefore, when reading the data portion corresponding to the read commands CMD-A to CMD-D, only the first read buffer RB1 and the second read buffer RB2 are required.

[0209] In other words, in this embodiment, a page read request is issued to prevent two flash dies from operating simultaneously when reading data related to the same CCID, thereby eliminating data congestion in the read buffer 431 and reducing the amount of read buffer 431 required.

[0210] Here, a process of transferring the data portions corresponding to the cluster read requests R0 to R7 described with reference to FIG. 4 to the host 2 will be described.

[0211] In response to the first data portion d0 of the first data (d0 to d3) being read from the flash die #0, the controller 4 executes a process of storing the first data portion d0 in the read buffer 431 and a process of transferring the first data portion d0 to the memory 22 of the host 2.

[0212] Upon completion of the transfer of the leading data portion d0 to the memory 22 of the host 2, the controller 4 releases the area of ​​the read buffer 431 in which the leading data portion d0 was stored.

[0213] In response to the second data portion d1 included in the first data being read from the flash die #0, the controller 4 executes a process of storing the second data portion d1 in the read buffer 431 and a process of transferring the second data portion d1 to the memory 22 of the host 2.

[0214] Upon completion of the transfer of the second data portion d1 to the memory 22 of the host 2, the controller 4 releases the area of ​​the read buffer 431 in which the second data portion d1 was stored.

[0215] In response to the last data portion d3 of the multiple data portions included in the first data being read from the flash die #0, the controller 4 executes a process of storing the last data portion d3 in the read buffer 431 and a process of transferring the last data portion d3 to the memory 22 of the host 2.

[0216] Upon completion of the transfer of the last data portion d3 to the memory 22 of the host 2, the controller 4 releases the area of ​​the read buffer 431 in which the last data portion d3 was stored.

[0217] In response to the first data portion d4 included in the second data (d4 to d7) being read from the flash die #x after the last data portion d3 has been transferred to the memory 22 of the host 2, the controller 4 executes a process of storing the first data portion d4 of the second data in the read buffer 431 and a process of transferring the first data portion d4 of the second data to the memory 22 of the host 2.

[0218] Upon completion of the transfer of the leading data portion d4 of the second data to the memory 22 of the host 2, the controller 4 releases the area of ​​the read buffer 431 in which the leading data portion d4 of the second data was stored.

[0219] In this way, the controller 4 transfers the data portions d0 to d7 corresponding to the cluster read requests R0 to R7 to the host 2 in LBA order.

[0220] 10 is a flowchart showing the procedure of the read process executed in the memory system according to the embodiment (steps S21 to S29). In response to receiving a read command from the host 2, the controller 4 starts the read process.

[0221] The controller 4 interprets the read command for reading the read target data, and generates a plurality of cluster read requests (step S21).

[0222] The controller 4 stores the multiple cluster read requests generated in S21 in a CCID queue associated with the CCID of the received read command (step S22). For example, the controller 4 manages the multiple cluster read requests by a linked list so that the multiple cluster read requests are linked in LBA order.

[0223] The controller 4 refers to the CCID queue and identifies a first flash die in which a data portion corresponding to the first cluster of the read target data is stored (step S23). The controller 4 identifies a flash die in which a data portion corresponding to the first cluster is stored based on an MCA included in a first cluster read request among the multiple cluster read requests stored in the CCID queue.

[0224] The controller 4 stores the CCID corresponding to the read command received from the host 2 in a reading queue corresponding to the first flash die (step S24). This reading queue corresponds to the submission queue in which the read command received by the controller 4 was stored.

[0225] The controller 4 identifies a first memory area of ​​the first flash die in which a first data of the read target data is stored by referring to the multiple cluster read requests stored in the CCID queue, starting from the first cluster read request (step S25).

[0226] The controller 4 generates a first memory read request to read the first data from the first memory area of ​​the first flash die identified in S25, and issues the generated first memory read request to the first flash die (step S26).

[0227] The controller 4 transfers the CCID from the leading queue corresponding to the first flash die to the following queue corresponding to the second flash die in which a data portion corresponding to the first cluster of the second data following the first data is stored (step S27).

[0228] The controller 4 identifies the second memory area of ​​the second flash die in which the second data is stored by referring to the unprocessed cluster read requests stored in the CCID queue, starting from the first cluster read request (step S28).

[0229] The controller 4 generates a second memory read request to read the second data from the second memory area of ​​the second flash die identified in S28, and issues the second memory read request to the second flash die (step S29).

[0230] As a result, the controller 4 executes a process of issuing a first memory read request to the first flash die to read the first data, and then a process of issuing a second memory read request to the second flash die to read the second data. Therefore, the controller 4 can read a plurality of data portions of the read target data according to the LBA order in the read target data. Since the data portion corresponding to the LBA immediately before the LBA of the read data portion has already been transferred to the host 2, the controller 4 can immediately transfer the read data portion to the host 2. Therefore, the time that the read data portion remains in the read buffer 431 is shortened.

[0231] Next, the procedure of the page read request issuing process will be described. Fig. 11 is a flowchart showing the procedure of the page read request issuing process executed in the SSD 3 according to the embodiment (steps S31 to S36). The command dispatcher 451 of the controller 4 starts the page read request issuing process in response to the CCID being stored in a command queue (following queue or leading queue). Here, it is assumed that the CCID is stored in the command queue corresponding to the second flash die.

[0232] The controller 4 determines whether or not a CCID is stored in the following queue corresponding to the second flash die (step S31).

[0233] If a CCID is stored in the following queue (Yes in S31), the controller 4 executes a process corresponding to the CCID stored in the following queue (step S32).

[0234] The controller 4 returns the CCID stored in the following queue to the linked list management unit 44 (step S33). Then, the controller 4 returns to S31 and determines whether or not a subsequent CCID is stored in the command queue.

[0235] If the CCID is not stored in the following queue (No in S31), the controller 4 determines whether or not the CCID is stored in the leading queue corresponding to the second flash die (step S34).

[0236] If a CCID is stored in the leading cue (Yes in S34), the controller 4 executes the process corresponding to the CCID stored in the leading cue (step S35).

[0237] The controller 4 returns the CCID stored in the leading queue to the linked list management unit 44 (step S36). Then, the controller 4 returns to S31 and determines whether or not a subsequent CCID is stored in the command queue.

[0238] If no CCID is stored in the reading queue (No in S34), the controller 4 determines that there is no CCID waiting to be processed, and ends the page read request issuing process.

[0239] In this way, the controller 4 can prioritize the process of generating a page read request based on the CCID stored in the following queue over the process of generating a page read request based on the CCID stored in the leading queue. This makes it possible to avoid a situation where the subsequent page read request issuance process is not executed for a read command for which the read process of the first cluster has already started.

[0240] As described above, according to this embodiment, the controller 4 issues a first memory read request to the first flash die to read the first data corresponding to the first cluster of the read target data associated with a certain read command. Then, a second memory read request can be issued to the second flash die to read the second data following the first data of the read target data. As a result, it is possible to prevent two flash dies from being operated simultaneously by the read process based on the same read command. Therefore, it is possible to avoid a situation in which data that would remain in the read buffer 431 for a long time even if it is read from the NAND flash memory 5 is read from the NAND flash memory 5 early.

[0241] As the data read from the NAND flash memory 5 remains in the read buffer 431, a situation may occur in which new data read from the NAND flash memory 5 cannot be stored in the read buffer 431. In this case, the data read from the NAND flash memory 5 is temporarily stored in the read buffer 62 of the DRAM 6. The read buffer 62 has a slower data write / read speed than the read buffer 431 of the SRAM 43. Therefore, if the situation described above occurs and the read buffer 62 of the DRAM 6 is used for temporary data storage, the read performance of the SSD 3 will be degraded. Therefore, the read performance of the SSD 3 can be improved by executing the read process using the read buffer 431 of the SRAM 43 as much as possible.

[0242] In other words, by preventing data from accumulating in the read buffer 431, the read buffer 431 is used efficiently, and therefore the read performance of the SSD 3 can be prevented from deteriorating.

[0243] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0244] 1...information processing system, 2...host, 3...SSD, 4...controller, 5...NAND flash memory, 6...DRAM, 7...bus, 20...internal bus, 21...processor, 22...memory, 40...internal bus, 41...host interface, 42...CPU, 43...SRAM, 44...linked list management unit, 45...CPU, 46...NAND interface, 47...error correction circuit, 48...DRAM interface, 51...peripheral circuit, 52...memory cell array, 61...LUT, 62...read buffer, 221...submission queue, 222...completion queue, 421...cluster read request generation unit, 431...read buffer, 451...command dispatcher, 452...read buffer allocation unit, 461...NAND controller.

Claims

1. 1. A memory system connectable to a host, comprising: a non-volatile memory including a plurality of memory dies; a controller configured to control the plurality of memory dies; The controller: in response to receiving a first read command from the host requesting reading of the read target data, dividing the read target data into a plurality of data portions corresponding to a plurality of clusters, and generating a plurality of read requests, each including memory address information indicating a storage location in the non-volatile memory where the corresponding data portion is stored; storing the plurality of read requests from a read request corresponding to a first cluster of the plurality of clusters to a read request corresponding to a last cluster of the plurality of clusters in a first read request queue associated with a first identifier assigned to the first read command such that the plurality of read requests are linked in this order; storing the first identifier in a first command queue corresponding to a first memory die in which a first data portion corresponding to the first cluster is stored; in response to storing the first identifier in the first command queue, by referencing the plurality of read requests stored in the first read request queue from a read request corresponding to the first cluster, identify a first storage area of ​​the first memory die in which a first data portion of the data to be read is stored, the first data portion including at least the first data portion; generating a first memory read request to read the first data from the first storage area of ​​the first memory die; issuing the first memory read request to the first memory die; When the remaining data following the first data is included in the read target data, the first identifier is transferred from the first command queue to a second command queue corresponding to a second memory die in which a second data portion corresponding to a first cluster of one or more clusters corresponding to the remaining data is stored; in response to transferring the first identifier to the second command queue, by referencing unprocessed read requests stored in the first read request queue from a read request corresponding to a first cluster of the one or more clusters, identify a second memory area of ​​the second memory die in which a first second data portion of the remaining data is stored, the second data portion including at least the second data portion; generating a second memory read request to read the second data from the second storage area of ​​the second memory die; configured to issue the second memory read request to the second memory die. Memory system.

2. The controller: managing a first leading queue for storing an identifier of a read command for which a read process of a leading cluster has not yet started, and a first following queue for storing an identifier of a read command for which a read process of a leading cluster has already started, as the first command queue corresponding to the first memory die; A second leading queue for storing an identifier of a read command for which a read process of a leading cluster has not yet started, and a second following queue for storing an identifier of a read command for which a read process of a leading cluster has already started are managed as the second command queue corresponding to the second memory die. storing the first identifier in the first reading queue corresponding to the first memory die; transferring the first identifier from the first leading queue corresponding to the first memory die to the second following queue corresponding to the second memory die; and further configured to execute the process of generating the second memory read request based on the first identifier transferred to the second following queue corresponding to the second memory die in priority to the process of generating another memory read request for reading another data from the second memory die based on an identifier stored in the second reading queue corresponding to the second memory die.

2. The memory system of claim 1.

3. The controller: managing a plurality of first reading queues corresponding to a plurality of submission queues in the memory of the host as the first reading queue corresponding to the first memory die; managing a plurality of second reading queues corresponding to the plurality of submission queues, respectively, as the second reading queue corresponding to the second memory die; when the first read command is fetched from a first submission queue of the plurality of submission queues, selecting one first reading queue from the plurality of first reading queues corresponding to the first submission queue, and storing the first identifier in the one first reading queue; performing an arbitration process to select a leading queue from which an identifier should be fetched from among the plurality of first reading queues; generating the first memory read request when the first identifier is fetched from the one of the first reading queues; further configured to issue the first memory read request to the first memory die.

3. The memory system of claim 2.

4. The controller: managing a correspondence relationship between a plurality of domains and the plurality of submission queues such that one or more of the plurality of submission queues belong to one domain; For the first memory die, manage a plurality of first domain queues corresponding to the plurality of domains; For the second memory die, manage a plurality of second domain queues corresponding to the plurality of domains; In response to generating the first memory read request, selecting one first domain queue from the plurality of first domain queues corresponding to one domain to which the first submission queue belongs, and storing the first memory read request in the one first domain queue; performing an arbitration process to select a domain queue from which a memory read request should be fetched from among the plurality of first domain queues based on a plurality of weights associated with the plurality of domains; and further configured to issue the first memory read request to the first memory die when the first memory read request is fetched from the one first domain queue.

4. The memory system of claim 3.

5. The controller: in response to generating the second memory read request, selecting one second domain queue from the plurality of second domain queues corresponding to one domain to which the first submission queue belongs, and storing the second memory read request in the one second domain queue; performing an arbitration process to select a domain queue from which a memory read request should be fetched from among the second domain queues based on the weights; and further configured to issue the second memory read request to the second memory die when the second memory read request is fetched from the one second domain queue.

5. The memory system of claim 4.

6. The controller: In response to the first data portion of a plurality of data portions included in the first data being read from the first memory die, a process of storing the first data portion in a read buffer and a process of transferring the first data portion to a memory of the host; release an area of ​​the read buffer in which the first data portion was stored in response to completion of the transfer of the first data portion to the memory of the host; In response to a second data portion of a plurality of data portions included in the first data being read from the first memory die, a process of storing the second data portion in the read buffer and a process of transferring the second data portion to the memory of the host; release an area of ​​the read buffer in which the second data portion was stored in response to completion of the transfer of the second data portion to the memory of the host; When a last data portion of a plurality of data portions included in the first data is read from the first memory die, a process of storing the last data portion in the read buffer and a process of transferring the last data portion to the memory of the host are executed; release an area of ​​the read buffer in which the last data portion was stored in response to completion of the transfer of the last data portion to the memory of the host; in response to the second data portion included in the second data being read from the second memory die after the final data portion has been transferred to the memory of the host, performing a process of storing the second data portion in the read buffer and a process of transferring the second data portion to the memory of the host; and releasing an area of ​​the read buffer in which the second data portion was stored in response to completion of the transfer of the second data portion to the memory of the host.

2. The memory system of claim 1.

7. the controller is further configured to allocate a storage area of ​​the static RAM as the read buffer if there is an available storage area in the static RAM that is equal to or greater than a first size.

7. The memory system of claim 6.

8. the controller is further configured to allocate a storage area of ​​a dynamic RAM as the read buffer if there is no available storage area in the static RAM that is equal to or greater than the first size.

8. The memory system of claim 7.

9. The controller is configured to manage the plurality of read requests stored in the first read request queue using a linked list for linking the plurality of read requests in the order from the read request corresponding to the first cluster to the read request corresponding to the last cluster.

2. The memory system of claim 1.

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