Neuromorphic computing circuit and control method

Abstract

To improve extensibility of hardware of neuromorphic computing.SOLUTION: A neuromorphic computing circuit includes a plurality of nodes which generate a spike including a counter relating to the presence time of the spike and a transmission source, and a transmission array which connects the plurality of nodes to each other. The transmission array includes a plurality of transmission circuits which transfer the spike by one or more transmission circuits on a transmission path corresponding to the spike. Each transmission circuit updates the value of the counter of the spike when transferring the spike, and sets the time difference calculated based on the values of the counters of both spikes to a first spike when detecting the confluence of the first spike from a first node to a second node and a second spike from the second node to the first node. The second node specifies a time difference which is equal to or less than a threshold value Δ tth among the time differences of the plurality of received spikes, accumulates the coupling strength between the transmission source node of the spike including the specified time difference and the second node, and generates a spike when the accumulated sum result exceeds a threshold value Wth.SELECTED DRAWING: Figure 24

Description

[Technical field]

[0001] The present invention relates to a neuromorphic computing circuit and a control method. [Background technology]

[0002] In large-scale neural networks such as those used in natural language processing or general-purpose AI (Artificial Intelligence), a large number of calculations are performed using hardware such as a CPU (Central Processing Unit) or a GPU (Graphical Processing Unit).When using such hardware for machine learning, there are concerns about limitations in the scalability of the hardware and the increase in power consumption when expanding the hardware.

[0003] As an alternative approach to these concerns, neuromorphic computing (hereinafter sometimes referred to as NC), which mimics the functions and structures of the brain, is known.

[0004] NC is a computational model that mimics the mechanism of spike firing in a neural circuit network (brain neural network) formed by connecting nerve cells (neurons) via synapses, and is implemented in hardware (circuits).

[0005] A spike occurs when a neuron emits a high electrical potential called a spike via the axon, which is the transmission path for the spike, to the preceding and succeeding neurons when ion molecules flowing in from a preceding neuron exceed a threshold.

[0006] Neural networks function by firing and transmitting spikes, which are a series of neurons that interpret the input and collectively form some kind of meaning. The spikes are the communication information for meaning formation.

[0007] The spike-timing dependent plasticity (STDP) model is known as one of the learning rules of NC. STDP means plasticity determined by the difference between the time when a spike caused by firing of a neuron arrives at its synapse and the time when a spike caused by firing of a preceding neuron arrives at its synapse.

[0008] For example, NCs operate to transfer spikes fired by neurons and merge multiple spikes at synapses. The time difference (time lag) between the firing of each spike and the merging of these spikes at a synapse changes the degree of connection (connection strength W) between neurons at the synapse. The connection strength W of a synapse changes the amount of current of ionic molecules (ionic compound current, ionic current) flowing from the synapse to the neuron, which in turn changes the amount of current required to fire a spike in the neuron. In other words, the transmission of spikes is affected by the connection strength W at the synapse between neurons. The connection strength W corresponds to a parameter (weight) in deep learning. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Special Publication No. 2022-509754 [Patent Document 2] US Patent Application Publication No. 2022 / 0309327 Summary of the Invention [Problem to be solved by the invention]

[0010] When implementing NC hardware capable of performing machine learning and inference using digital circuits (digital implementation), there are limitations to the scalability of the NC hardware, which can hinder the scale-up of the hardware.

[0011] One example of the constraints on the scalability of NC hardware is the maximum number of spikes per neuron. In the digital implementation, a global counter is used as a time stamp to calculate the time difference between the above-mentioned spikes in STDP.

[0012] However, the maximum possible value of the global counter is equal to the maximum number of spikes that can occur. The size of the global counter determines the time range that can be defined, and therefore limits the maximum number of spikes per neuron that can perform time difference calculations. This can hinder hardware scaling to increase the maximum number of spikes.

[0013] In one aspect, an object of the present invention is to improve the scalability of hardware for neuromorphic computing. [Means for solving the problem]

[0014] In one aspect, the neuromorphic computing circuit may include a plurality of nodes that generate spikes, the spikes including a counter related to the existence time of the spikes and information indicating a source of the spikes, and a transmission array that interconnects the plurality of nodes and forms a transmission path for the spikes. The transmission array may include a plurality of transmission circuits that transfer the spikes by one or more transmission circuits on a transmission path corresponding to the spikes. Each of the plurality of transmission circuits may update the value of the counter for the spike when transferring the spike. Furthermore, each of the plurality of transmission circuits may set a time difference calculated based on the values ​​of the counters for the first spike and the second spike to the first spike to be transferred when detecting a merger between a first spike transmitted from a first node to a second node among the plurality of nodes and a second spike transmitted from the second node to the first node. Furthermore, the second node may include a spike generating circuit. The spike generation circuit may identify a time difference that is equal to or less than a first threshold among the multiple time differences set in the multiple spikes received from the transmission array, accumulate the coupling strength between the source node of a third spike in which the identified time difference is set and the second node, and generate a fourth spike if the result of the accumulation exceeds a second threshold. Effect of the Invention

[0015] In one aspect, the present invention can improve hardware scalability for neuromorphic computing. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram for explaining an example of a neuron. [Diagram 2] FIG. 1 illustrates an example of a formal neuron model. [Diagram 3] FIG. 1 is a diagram illustrating an example of an STDP model. [Figure 4] FIG. 13 is a diagram showing an example of measurement results of cranial nerves. [Diagram 5]FIG. 13 is a diagram for explaining an example of time difference calculation using a global counter. [Figure 6] FIG. 13 is a diagram for explaining an implementation example of an inference scheduler. [Figure 7] FIG. 1 is a diagram showing an example of neural connections of neurons. [Figure 8] FIG. 1 is a diagram for explaining an example of hardware implementation for NC inference. [Figure 9] FIG. 13 is a diagram showing an example of a feasible hardware scale when constraints (a) to (c) are imposed. [Figure 10] FIG. 13 is a diagram for explaining inconveniences related to physical distances when arranging formal neuron models. [Figure 11] FIG. 2 is a diagram illustrating an example of a network model of an NC according to an embodiment. [Figure 12] FIG. 1 is a block diagram showing an example of the configuration of neuromorphic computing hardware according to an embodiment. [Figure 13] FIG. 2 is a diagram illustrating an example of a data structure of a spike according to an embodiment. [Figure 14] FIG. 2 is a block diagram showing an example of a hardware configuration of an ignition node. [Figure 15] FIG. 2 is a block diagram showing an example of hardware implementation of a time difference calculation circuit and a router. [Figure 16] FIG. 2 is a block diagram showing an example of a hardware configuration of a router. [Figure 17] 4 is a block diagram showing an example of the hardware configuration of a time difference calculation circuit; [Figure 18] FIG. 2 illustrates an example of a comparator. [Figure 19] 11 is a flowchart illustrating an example of a time difference calculation process performed by a time difference calculation circuit and a router according to an embodiment. [Figure 20] FIG. 13 is a diagram for explaining an example of transmission of a spike (time difference). [Figure 21] FIG. 13 is a diagram for explaining an example of transmission of a spike (time difference). [Figure 22] FIG. 13 is a diagram for explaining an example of transmission of a spike (time difference). [Figure 23] FIG. 13 is a diagram for explaining an example of transmission of a spike (time difference). [Figure 24] FIG. 2 is a block diagram showing an example of a hardware configuration of a firing mechanism. [Diagram 25] FIG. 13 is a diagram illustrating an example of a method for calculating a target time difference. [Figure 26] 11A to 11C are diagrams illustrating an example of the operation of the ignition mechanism. [Figure 27] FIG. 2 is a block diagram showing an example of a hardware configuration of a connection strength mechanism. [Figure 28] FIG. 13 is a diagram showing an example of the configuration of an NC used to explain an example of the operation of a coupling strength mechanism. [Figure 29] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 30] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 31] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 32] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 33] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 34] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 35] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 36] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Figure 37] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Figure 38] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Figure 39] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 40] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 41] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. [Diagram 42] 1A and 1B are diagrams for explaining an example of spike transmission between multiple firing nodes in an NC and an example of the operation of a connection strength mechanism. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications or application of techniques not specified below. For example, this embodiment can be modified in various ways without departing from the spirit of the invention. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[0018] [A] Explanation of Neuromorphic Computing Fig. 1 is a diagram for explaining an example of a neuron 100. As illustrated in Fig. 1, the neuron 100 includes parts called synapses 110, dendrites 120, and axons .

[0019] The synapse 110 is a site that connects neurons 100 together. The synapse 110 receives spikes, which are ion molecules (ionic compound currents), from the preceding neuron 100. The amount of ion molecules received by the synapse 110 depends on the connection strength W at the synapse 110. The dendrite 120 is a site that groups together multiple synapses 110. The axon 130 is a site that is connected to the synapses 110 of multiple subsequent neurons 100 and serves as a spike transmission path to the connected neuron 100.

[0020] In Fig. 1, a fire is an event in which a neuron 100 emits a high potential called a spike when the amount (potential) of ion molecules flowing into the neuron 100 exceeds a threshold. Spike transmission is affected by the connection strength W at the synapse 110 between the neurons 100. A neural network formed by multiple neurons 100 functions by firing and the transmission of spikes generated by it.

[0021] FIG. 2 is a diagram showing an example of a formal neuron model 200, and FIG. 3 is a diagram showing an example of an STDP model 300.

[0022] The formal neuron model 200 is a formal model used to express a neuron as a mathematical model. As shown in Fig. 2, the formal neuron model 200 has a dendrite, which is a collection of synapses 210 with connection strength, and a fire function, and the connection strength of each synapse 210 is defined by the fire function.

[0023] The STDP model 300 is an example of the formal neuron model 200, and is one of the learning rules based on the Hebb rule, which is a rule about synaptic plasticity in the brain. Hereinafter, in NC, it is assumed that the STDP model 300 is applied as the learning rule.

[0024] FIG. 3 shows an example of an STDP model 300 in which neurons 301 and 302 (represented as "Neuron-i" and "Neuron-j", respectively) are connected via a synapse 310. The STDP model 300 is designed based on the synapse 310 and conditions for the neurons 301 and 302 to fire spikes. As shown in FIG. 3, each of the neurons 301 and 302 fires and transfers a spike via an axon path or a dendrite path, and the spikes join at the synapse 310. In the STDP model 300 based on the formal neuron model 200, the propagation delay of the spikes does not need to be taken into account.

[0025] The time difference between the merged spikes changes the connection strength W of synapse 310. This changes the amount of current flowing into neurons 301 and 302, and the amount of current required for firing also changes. Thus, the connection strength W of synapse 310 corresponds to a resistance value to the ionic compound currents flowing into neurons 301 and 302.

[0026] Neuron 302 fires a spike (post-spike) in response to a spike (pre-spike) input from neuron 301 or a spike input from another neuron (conditional on the input). In other words, it can be said that the firing of a post-spike is correlated with the firing of a pre-spike.

[0027] Fig. 4 is a diagram showing an example of the measurement results of the cranial nerves. In the graph of Fig. 4, the horizontal axis indicates spike timing, i.e., the spike arrival time difference (time difference) Δt [ms], and the vertical axis indicates the change in connection strength W Δw(Δt) [%]. Each plot of a white circle and a shaded square in the graph indicates a measurement result by a different measurer or measurement method. In the graph, pre indicates a neuron (e.g., neuron 301 in Fig. 3) preceding a certain synapse 310 (see Fig. 3), and post indicates the own neuron (e.g., neuron 302 in Fig. 3).

[0028] The connection strength W of the synapse 310 at a certain time (timing) t t is expressed by the following formula (1). Bond strength W t =W t-1 +Δw(Δt) (1)

[0029] As shown in the above formula (1), the bond strength W t changes according to the time difference Δt between the timing of the spike arriving at the synapse 310 from the neuron 301 (pre) and the timing of the spike arriving at the synapse 310 from the neuron 302 (post). This means that the change in the connection strength W at the synapse 310 contributes to machine learning.

[0030] In the above formula (1), the amount of change Δw(Δt) is expressed by the following formula (2) or (3) depending on whether Δt is positive or negative. Note that A and B in the following formula (2) and D and E in the following formula (3) are constants. Change Δw(Δt)=Ae BΔt (Δt>0) (2) Change Δw(Δt)=-De E(-Δt) (Δt<0) (3)

[0031] From the above formulas (2) and (3), it can be seen that when the time lag Δt is small, the connection strength of the synapse 310 changes sharply due to spike-timing dependent plasticity (STDP). In the STDP model 300, machine learning is performed using the time lag Δt according to the above formula (1).

[0032] Here, we consider the case where an NC capable of simultaneously executing machine learning and inference (e.g., capable of executing machine learning again after inference) is implemented using digital circuits. The larger the scale of the NC hardware is (scaling), the more types of inference can be performed, so it is desirable to scale the NC hardware as much as possible. However, the scalability of the NC hardware is subject to the following constraints (a) to (c).

[0033] (a) The maximum possible value of the global counter is equal to the maximum number of firings. Fig. 5 is a diagram for explaining an example of time difference calculation using a global counter. As shown in Fig. 5, the synapse 310 (see Fig. 3) calculates the time difference Δt between the timing (t=2) of the spike from neuron 302 (post) and the timing (t=6) of the spike from neuron 301 (pre) by referring to the value (0 to 8) of the global counter. In the example of Fig. 5, the time difference Δt is 2-6=-4.

[0034] From Figure 5, the maximum number of spikes per neuron is the maximum value of the global counter + 1. Thus, the value of the global counter is equal to the maximum number of spikes that can occur. The size of the global counter determines the time range that can be defined, and therefore limits the maximum number of spikes per neuron that can perform time difference calculations. This may hinder hardware scaling to increase the maximum number of spikes.

[0035] (b) The buffer size is equal to the maximum number of spikes that can be timed. Fig. 6 is a diagram for explaining an implementation example of an inference scheduler 400. As shown in Fig. 6, the hardware for inference of an NC includes a scheduler 400 that adjusts the timing of spikes. As a method for adjusting the timing, for example, AER (Address-Event Representation) can be mentioned.

[0036] The example in Figure 6 shows a case where spikes occur in the order of neurons A, C, and B. A spike has address information of its destination and source, for example, a neuron ID (Identifier). In Figure 6, the address information of the spikes output from neurons A, C, and B, respectively, is represented as "Addr-A," "Addr-C," and "Addr-B."

[0037] The scheduler 400 includes a circular buffer 410. The scheduler 400 inserts (stores) spikes in the circular buffer 410 and manages the spikes using a tail pointer TAIL and a head pointer HEADER, thereby guaranteeing the order of the spikes.

[0038] The scheduler 400 determines the read line to be output based on the address information (address value). In the circular buffer 410, slots are consumed from the address of the tail pointer TAIL. Fig. 6 shows an example in which these spikes are stored in slots 411 to 413, which are storage areas of the circular buffer 410, in the order of neurons A, C, and B.

[0039] In scheduler 400, the size of circular buffer 410 imposes a constraint on the maximum number of spikes that can be timed, which may inhibit scaling of the hardware to increase the maximum number of spikes.

[0040] (c) The number of on-chip memory cells functioning as synapses, or the number of crosspoints of a crossbar, is equal to the maximum number of connections of a neuron. FIG. 7 is a diagram showing an example of neural connections of neurons, and FIG. 8 is a diagram for explaining an example of implementation of hardware for inference of the NC600.

[0041] FIG. 7 shows a plurality of cell bodies 510, 531, 532, and 533. For convenience, each "cell body" may be written as a "neuron." The neuron 510 outputs spikes (Fan-out), and spikes are input (Fan-in) to each of the neurons 531 to 533. FIG. 7 also shows synaptic weights 521 to 523 between neurons. The weight 521 is the connection strength W of the synapse between the neurons 510 and 531, the weight 522 is the connection strength W of the synapse between the neurons 510 and 532, and the weight 523 is the connection strength W of the synapse between the neurons 510 and 533.

[0042] Figure 8 shows NC600, which implements the neural connections shown in Figure 7 as inference hardware. In NC600, the set of neurons shown in Figure 7 is implemented in on-chip memory.

[0043] As shown in FIG. 8, the NC 600 includes an AER decoder 610, a crossbar 620, an offset memory 630, a plurality of neurons (cell bodies) 640, and an AER encoder 650.

[0044] The crossbar 620 is a crossbar switch in which a plurality of switches are arranged in a matrix. Each switch (cross point) corresponds to a synapse 621. A row of a plurality of synapses 621 enclosed in a square in FIG. 8 corresponds to a dendrite 622 provided on a neuron 640 located on an extension of the row. That is, in the NC 600, the synapses 621 and the dendrites 622 are implemented by the crossbar 620. The number of synapses 621 provided in the crossbar 620 is the number of connections to the neuron 640, and is the maximum number of Fan-in (input). The number of dendrites 622 provided in the crossbar 620 is the number of neurons 640 to which spikes are sent, and is the maximum number of Fan-out (output).

[0045] Thus, in the NC 600, the number of cross points of the crossbar 620 functioning as the synapse 621 is equal to the maximum number of connections of the neuron (cell body) 640. This can inhibit hardware scaling that increases the maximum number of connections of the neuron (cell body) 640.

[0046] In the NC 600 shown in Fig. 8, the AER decoder 610 receives spikes from the outside (AER encoder 650 in a set of other neurons) and performs timing adjustment (see Fig. 6). In the following, it is assumed that the spike 611 read from the AER decoder 610 is a spike from the neuron 510 in Fig. 7.

[0047] In this case, spike 611 propagates in the horizontal (right) direction on the paper through crossbar 620 by the path indicated by the dashed line, and is then switched to propagate in the vertical (down) direction on the paper at synapse 621 indicated by the shaded circle. Switching the crosspoint corresponds to switching a switch from off to on.

[0048] Then, spike 611 flows into neuron 640 together with weights (weights 521 to 523 in FIG. 7) read from offset memory 630 that stores weights obtained as a result of machine learning. Spike 611 and weights are cumulatively summed in neuron 640. In FIG. 8, neuron 640 indicated by a shaded square corresponds to neurons 531 to 533 shown in FIG. 7, respectively.

[0049] When the neuron 640 to which the spike 611 and weighting have flowed in fires, the spike accompanying the firing is input to the AER encoder 650. The AER encoder 650 outputs the spike to the AER decoder 610 or to the outside, depending on the transmission destination.

[0050] Fig. 9 is a diagram showing an example of a achievable hardware scale when the above-mentioned constraints (a) to (c) are imposed. As shown in Fig. 9, the imposition of each of the constraints (a) to (c) causes the actually achievable hardware scale to be significantly reduced from the theoretical scale of the NC. In other words, the constraints (a) to (c) inhibit the hardware scalability of the NC.

[0051] Therefore, in one embodiment, a method for improving the hardware scalability of an NC will be described. For example, in one embodiment, by adopting a configuration in which the use of a global counter can be omitted in an NC, at least the above-mentioned constraint (a) can be eliminated, and the hardware scalability can be improved.

[0052] By the way, using the global counter to calculate the time difference Δt contributes to solving the following problems (i) to (iii) related to the physical distance when arranging the formal neuron model.

[0053] (i) The physical distance between neurons depends on the arrangement of the neurons. Fig. 10 is a diagram for explaining the inconvenience of the physical distance when arranging the formal neuron model. For convenience, the lengths (physical distances) of the axon path and the dendrite path in Fig. 10 are called the physical distance between neurons. The physical distance depends on the arrangement of the neurons.

[0054] (ii) The physical distance between a synapse and a neuron depends on the placement of the neuron (the firing mechanism). The physical distance between the synapse and the neuron depends on the location of the firing mechanism. As shown in Figure 10, it is unclear where the firing mechanism (Fire) is located within the neuron.

[0055] (iii) The actual distance and transit time from source to destination may vary.

[0056] Therefore, when the use of the global counter used for calculating the time difference Δt is omitted, the above-mentioned problems (i) to (iii) occur. In one embodiment, a method for solving the above-mentioned problems (i) to (iii) that occur when the use of the global counter is omitted will be described.

[0057] [B] Configuration example of one embodiment FIG. 11 is a diagram showing an example of a network model 10 of an NC according to one embodiment, and FIG. 12 is a block diagram showing an example configuration of neuromorphic computing hardware 1 (hereinafter, sometimes simply referred to as NC1) according to one embodiment.

[0058] 11, in one embodiment, a network model 10 including a plurality of ignition nodes 11 (referred to as nodes a to e in FIG. 11) is assumed. Note that an "ignition node" may be simply referred to as a "node."

[0059] The firing node 11 is a node capable of firing a spike, and is, for example, a cell body or a computational model of a neuron. The firing node 11 may act as, for example, one or both of a source and a destination of a spike.

[0060] 11 shows, as a directed graph, the connections between firing nodes 11 in the network model 10. The firing node 11 at the origin of the arrow in the directed graph is the source (pre) of the spike, and the firing node 11 at the tip of the arrow is the destination (post) of the spike.

[0061] In the network model 10, graph levels are set in ascending order for each layer from a shallow layer (the source side of the arrow) to a deep layer (the tip side of the arrow) of the ignition node 11. In the example of Fig. 11, graph level 1 is set for nodes d and e, graph level 2 is set for nodes b and c, and graph level 3 is set for node a.

[0062] 12 is hardware that is realized by arranging and wiring the network model 10 shown in Fig. 11. As illustrated in Fig. 12, the NC1 may include a plurality of firing nodes 11 and a time difference calculation circuit array 2.

[0063] The time difference calculation circuit array 2 is an example of a transmission array that connects multiple firing nodes 11 to each other and forms a spike transmission path. For example, the time difference calculation circuit array 2 calculates a time difference for calculating weights used in machine learning.

[0064] 12, the time difference calculation circuit array 2 may include a plurality of time difference calculation circuits 3, and a plurality of routers 4 that connect the time difference calculation circuits 3 so that they can communicate with each other. The router 4 may be, for example, an on-chip router formed on an IC (Integrated Circuit) chip together with the time difference calculation circuits 3.

[0065] The time difference calculation circuit array 2 calculates the time difference Δt in the time difference calculation circuit 3 where the pre and post spikes join. The time difference calculation may be performed in the time difference calculation circuit 3, but may also be performed in the firing node 11. The time difference calculation by the time difference calculation circuit array 2 realizes the following (I) to (III).

[0066] (I) It is possible to calculate the time difference without using a global counter. The time difference calculation circuit 3 does not use a global counter, but performs time difference calculation by a method described later. This eliminates the restriction (a) on the maximum number of spike firings.

[0067] In addition, the time difference calculation circuit array 2 does not express physical distances because it is based on a formal neuron model that applies STDP as a learning rule. Not expressing physical distances means that the firing nodes 11 can be freely arranged.

[0068] Furthermore, the paths on the time difference calculation circuit array 2 do not handle firing time information and do not logically include time. Instead, the paths on the time difference calculation circuit array 2 use firing timing using a theoretical unit time.

[0069] (II) By performing time difference calculations using parallel distributed processing, the need for a scheduler is eliminated. The time difference calculation circuit array 2 may arrange a plurality of time difference calculation circuits 3 and routers 4 in a two-dimensional or three-dimensional mesh, and form a transmission path according to the spike 5 by routing in the order of dimensions. In the example of Figure 12, the time difference calculation circuit array 2 arranges a plurality of time difference calculation circuits 3 and routers 4 in a two-dimensional mesh, and is premised on XY or YX routing.

[0070] 12, with the horizontal direction of the page being the X-axis and the vertical direction being the Y-axis, nodes a, d, and e of the odd-numbered graph level are arranged along the Y-axis, and are each connected along the X-axis to time difference calculation circuits 3 of the time difference calculation circuit array 2. Furthermore, nodes b and c of the even-numbered graph level are arranged along the X-axis, and are each connected along the Y-axis to time difference calculation circuits 3 of the time difference calculation circuit array 2.

[0071] For example, in the case of XY routing, a spike moves in the X-axis direction from node a, d, or e in an odd-numbered graph level, then moves in the Y-axis direction and flows into node b or c in an even-numbered graph level. In this way, in the time difference calculation circuit array 2, the transmission (propagation) path of the spike is fixed, so the order in which the spikes join is guaranteed. This makes it possible to eliminate the constraint (b) on the maximum number of spikes whose timing can be adjusted, while eliminating the need for waiting by a scheduler.

[0072] Also, the XY or YX routing algorithm can avoid spike deadlock.

[0073] The routing method in the time difference calculation circuit array 2 is not limited to XY or YX routing, and various other routing methods may be applied.

[0074] (III) By placing the function of synapse (updating connection strength after calculating the time difference) within the firing mechanism, memory cell arrays and cross-point arrays are no longer necessary. For example, in the time difference calculation circuit array 2, since the firing node 11 is equivalent to a fully connected network, there is no restriction on the number of Fan-in / Fan-out. This makes it possible to eliminate (e.g. relax) the restriction (c) on the maximum number of synaptic connections to a neuron. For example, in the time difference calculation circuit array 2, time difference calculations can be performed simultaneously for as many time difference calculation circuits 3 as there are time difference calculation circuits.

[0075] In addition, since the time difference calculation circuit array 2 is equivalent to a fully connected network for the firing nodes 11, it is possible to guarantee the appearance of all spikes between the firing nodes 11. Therefore, by combining with the above-mentioned (I), it is possible to omit the use of a global counter and to eliminate the inconveniences of the above-mentioned (i) to (iii).

[0076] As described above, the time difference calculation circuit array 2 can solve the restrictions (a) to (c) and inconveniences (i) to (iii) caused by time difference calculation by improving the time difference calculation.

[0077] The number of stages of the time difference calculation circuit array 2 may be appropriately determined according to the structure of the network model 10 used for machine learning. In the example shown in Fig. 12, the time difference calculation circuit array 2 is a 4 x 4 array, but when performing large-scale inference, the scale of the array may be increased (the number of stages may be increased) to increase the number of time difference calculation circuits 3 capable of calculating time differences or to increase the number of firing nodes 11.

[0078] [B-1] Example of spike data structure Next, an example of the data structure of spike 5 according to an embodiment will be described.

[0079] Fig. 13 is a diagram showing an example of the data structure of spike 5 according to an embodiment. As shown in Fig. 13, spike 5 may include the following items (fields): "spike attribute flag", "counter J", "counter C", "Δt", "source address", and "destination address". These data held by spike 5 may be scalar data. In the example of Fig. 13, it is assumed that the time difference calculation circuit array 2 performs XY or YX routing.

[0080] The "spike attribute flag" is information that can distinguish whether spike 5 is pre or post. For example, the spike attribute flag may be added to spike 5 at the location where spike 5 fires (e.g., firing node 11). Pre represents the source, and post represents the destination. For example, firing node 11 at the origin of the arrow in the directed graph shown in FIG. 11 may set a flag indicating pre in the spike attribute flag when outputting spike 5. Fire node 11 at the destination of the arrow in the directed graph shown in FIG. 11 may set a flag indicating post in the spike attribute flag when outputting spike 5.

[0081] Hereinafter, a spike 5 whose spike attribute flag has a flag set indicating pre may be referred to as a "pre spike 5," and a spike 5 whose spike attribute flag has a flag set indicating post may be referred to as a "post spike 5."

[0082] The pre-spike 5 is an example of a first spike 5 transmitted from a first firing node 11 to a second firing node 11 among the multiple firing nodes 11. The post-spike 5 is an example of a second spike 5 transmitted from the second firing node 11 to the first firing node 11.

[0083] "Counter J" is an example of merging information indicating whether or not a merging has occurred, and is a counter indicating the number of mergings. The initial value of counter J is 0, and is incremented (1 is added) when merging with another spike 5. Note that counter J may be various information other than a counter, for example, as long as the initial value indicates "not yet merging" and a value other than the initial value indicates "already merging."

[0084] "Counter C" is an example of a counter related to the existence time of spike 5, and is a counter that holds "existence" time information. The initial value of counter C is 0, and it is updated by incrementing (adding 1) by a clock. Note that counter C may be updated by adding a value other than 1.

[0085] Also, if the maximum time difference Δt allowed in NC1 is determined, the counter C may be updated by setting the initial value to a value corresponding to the maximum time difference Δt and decrementing (subtracting 1) the counter C by the clock. Alternatively, in this case, the counter C may be updated by subtracting a value other than 1.

[0086] The counters J and C may be updated in the time difference calculation circuit 3 and the source and destination firing nodes 11. Note that the counters J and C may be set in both the pre-spike 5 and the post-spike 5.

[0087] "Δt" is the time difference Δt calculated based on the value of the counter C of each spike 5 in the time difference calculation circuit 3 or the firing node 11 where the post spike 5 and the pre spike 5 join, and is set in the pre spike 5 from the source firing node 11. For example, the time difference Δt is calculated by multiplying the value of the counter C of the post spike 5 (C post ) and the value of counter C at pre-spike 5 (C pre It may be calculated as the difference between the Time difference Δt=C post -C pre (4)

[0088] In this way, the time difference calculation circuit array 2 transfers the pre-spike 5 from the source firing node 11 to the destination firing node 11 together with information about the time difference Δt calculated by the time difference calculation circuit 3 where the pre-spike 5 and post-spike 5 join together.

[0089] The "source address" is an example of information indicating the source of the spike 5, for example the address of the firing node 11 that is the source of the spike 5. The "destination address" is an example of information indicating the destination of the spike 5, for example the address of the firing node 11 that is the destination of the spike 5.

[0090] The above-mentioned spike 5 is transferred from the source address to the destination address by XY or YX routing in the time difference calculation circuit array 2. At that time, the value of the counter C of the spike 5 is updated (incremented) at each clock in the firing node 11 or the time difference calculation circuit 3, and may be updated or discarded if the following conditions are met:

[0091] After the arrival of the spike 5, the destination or source firing node 11 updates (increments) the value of the counter C if the value of the counter J (the number of mergers) is 0.

[0092] After the arrival of spike 5, the destination or source firing node 11 discards the spike 5 if the value of counter J (number of junctions) is other than 0. This is because the fact that the value of counter J (number of junctions) is other than 0 means that the spike 5 has already merged with another spike 5 on the route up to this point (time difference calculation circuit 3).

[0093] When spikes 5 merge in its own time difference calculation circuit 3, the time difference calculation circuit 3 discards the post spike 5 from the transmission earlier firing node 11 among the merged spikes 5. This is because the value of the counter J (number of merges) of the post spike 5 is other than 0.

[0094] The reason for discarding the post spike 5 is that the time difference calculation circuit array 2 transfers the spike 5 for the purpose of calculating the time difference Δt, and once the time difference Δt has been calculated, the post spike 5 in the opposite direction used for that calculation is no longer necessary.

[0095] The clock may mean the time interval in which the spike 5 travels through one time difference calculation circuit 3, in other words, the time interval in which the spike 5 travels through a transmission path (one hop) between adjacent time difference calculation circuits 3. Since NC1 is a formal neuron model, the transmission path does not represent a physical distance.

[0096] One or more transmission paths (paths on the time difference calculation circuit array 2) between a source neuron of spike 5 and a destination neuron of spike 5 may correspond to one synapse between the source and destination neurons. For example, the synapse between firing node d and firing node c shown in the directed graph in Fig. 11 is represented by the path shown by the dashed arrow from firing node d to firing node c in Fig. 12, that is, by a plurality of time difference calculation circuits 3 and routers 4 through which spike 5 passes in the time difference calculation circuit array 2.

[0097] [B-2] Example of hardware configuration of firing node Fig. 14 is a block diagram showing an example of a hardware configuration of the firing node 11. As shown in Fig. 14, the firing node 11 may include an input buffer 11a, a connection strength mechanism 11b, and a firing mechanism 11c.

[0098] When the input buffer 11a receives a spike 5 from an adjacent time difference calculation circuit 3, in which the address of its own firing node 11 is set as the destination address, it outputs the time difference Δt and the source address set in the received spike 5 to the connection strength mechanism 11b.

[0099] For example, when the value of counter J set in spike 5 is 0, input buffer 11a may increment the value of counter C set in spike 5. Also, when the value of counter J set in spike 5 is other than 0, input buffer 11a may discard spike 5.

[0100] Furthermore, when the input buffer 11a receives a Nack (Negative acknowledgement) from the firing mechanism 11c via the coupling strength mechanism 11b, it transmits (replies) the Nack to the source address (firing node 11) of the spike 5. The Nack is output, for example, when the buffer in the firing node 11 becomes insufficient.

[0101] The connection strength mechanism 11b outputs the connection strength W between the firing node 11 corresponding to the source address set in the received spike 5 and its own firing node 11 and the time difference Δt to the firing mechanism 11c. In addition, the connection strength mechanism 11b calculates (updates) the updated connection strength W based on the time difference Δt in accordance with the above formula (1), and stores the time difference Δt and the updated connection strength W.

[0102] For example, the connection strength mechanism 11b may include a buffer 11d for storing the time difference Δt and the source address input from the input buffer 11a, and a connection strength memory 11e for storing the connection strength W. The connection strength mechanism 11b may read the connection strength W corresponding to the source address from the connection strength memory 11e, output it together with the time difference Δt to the firing mechanism 11c, and write the connection strength W updated based on the connection strength W and the time difference Δt back to the connection strength memory 11e.

[0103] The firing mechanism 11c judges whether or not to fire a spike 5 from its own firing node 11 based on the time difference Δt and the connection strength W input from the connection strength mechanism 11b, and transmits the spike 5 if it judges that the spike should be fired.

[0104] For example, the firing mechanism 11c may include a circular buffer 11f that stores the time difference Δt and the connection strength W input from the connection strength mechanism 11b. The firing mechanism 11c uses the circular buffer 11f to perform cumulative summation of the connection strength W in the STDP model 300, thereby determining whether or not to fire the spike 5.

[0105] In this way, the NC1 according to one embodiment can eliminate the need for a memory cell array or a cross-point array by providing the function of synapse (updating the connection strength after calculating the time difference) in the firing node 11 (connection strength mechanism 11b).

[0106] The coupling strength mechanism 11b and the firing mechanism 11c will be described in detail later.

[0107] [B-3] Example of hardware configuration for time difference calculation circuit array Fig. 15 is a block diagram showing an example of hardware implementation of the time difference calculation circuit 3 and the router 4. As shown in the example of Fig. 15, the time difference calculation circuit 3 and the router 4 that transmits spikes 5 to the time difference calculation circuit 3 may be implemented on a chip 6 such as an IC.

[0108] In one embodiment, the time difference calculation circuit array 2 is premised on XY or YX routing. A pair of a time difference calculation circuit 3 and a router 4 illustrated in Fig. 15 is an example of one transmission circuit, and adjacent pairs of a time difference calculation circuit 3 and a router 4 may be communicatively connected to each other by coupling the routers 4 to each other. For example, a router 4 may be communicatively connected to at least one of the routers 4 adjacent to the north, south, west, and east, which correspond to the up, down, left, and right directions on the paper surface of Fig. 12.

[0109] In this way, the time difference calculation circuit array 2 includes a plurality of transmission circuits (time difference calculation circuits 3 and routers 4) that transfer the spike 5 via one or more transmission circuits on a transmission path in response to the spike 5.

[0110] The time difference calculation circuit array 2 and the firing node 11 included in the NC1 according to one embodiment will be described in detail below.

[0111] [C] Explanation of the time difference calculation circuit array First, the time difference calculation circuit array 2 according to one embodiment will be described in detail.

[0112] [C-1] Detailed configuration example of time difference calculation circuit array Fig. 16 is a block diagram showing an example of a hardware configuration of the router 4. As shown in Fig. 16, the router 4 may include FIFOs (First-In First-Out) 41a to 41e, a crossbar 42, a controller 43, an arbiter 44, and output units (Out) 45i to 45e.

[0113] The FIFOs 41a to 41e are input buffers (memories) that use a FIFO (first-in, first-out) method. Hereinafter, when there is no need to distinguish between the FIFOs 41a to 41e, they may be simply referred to as FIFO 41.

[0114] The FIFOs 41a to 41d store the spikes 5 received from the adjacent routers 4 of the North, East, West, and South, respectively, and output the spikes 5 to the crossbar 42. At this time, the FIFOs 41a to 41d may update (increment) the value of the counter C set in the spike 5. Note that the value of the counter C may be updated by the output unit 45e or the time difference calculation circuit 3, instead of the FIFOs 41a to 41d.

[0115] The FIFO 41 e stores the spike 5 received from the time difference calculation circuit 3 and outputs the spike 5 to the crossbar 42 .

[0116] The crossbar 42 transmits the spike 5 input from the FIFO 41 to one of the output units 45a to 45e in accordance with the control by the control unit 43 and the arbitration unit 44.

[0117] The control unit 43 controls switching of the paths of the crossbar 42. For example, the control unit 43 may switch the crossbar 42 so that the spike 5 stored in the FIFOs 41a to 41d is output to the output unit 45e. The control unit 43 may also switch the crossbar 42 so that the spike 5 from the time difference calculation circuit 3 stored in the FIFO 41e is output to the output units 45a to 45d corresponding to the destination address set in the spike 5.

[0118] When spikes 5 are stored in two or more (for example, an even number) FIFOs 41a to 41d, the control unit 43 may switch the crossbar 42 so as to output these two or more spikes 5 simultaneously (at the same clock) to the output unit 45e. The two or more spikes 5 are, for example, a pre-spike 5 and a post-spike 5 that are joined together in the time difference calculation circuit 3.

[0119] The arbitration unit 44 arbitrates the switching of the crossbar 42 by the control unit 43 (for example, adjusts the timing, etc.).

[0120] The output units 45a to 45d transmit the spikes 5 input from the crossbar 42 to the adjacent routers 4 of the North, East, West, and South, respectively. The output unit 45e transmits the spikes 5 input from the crossbar 42 to the time difference calculation circuit 3.

[0121] In this way, the router 4 increments the value of the counter C for the spike 5 received in the FIFO 41a to 41d, and then outputs the spike 5 from the output unit 45e to the time difference calculation circuit 3. The router 4 also outputs the spike 5 input from the time difference calculation circuit 3 from the FIFO 41e to one of the output units 45a to 45d, which is the transfer destination.

[0122] Fig. 17 is a block diagram showing an example of the hardware configuration of the time difference calculation circuit 3. As shown in Fig. 17, the time difference calculation circuit 3 may include a comparator array 31, a selection value generation circuit 32, a plurality of (two in the example of Fig. 17) selection circuits 33, and a plurality of (two in the example of Fig. 17) calculation units (denoted as "Δt calculation" and "J+=1") 34.

[0123] The comparator array 31 compares the source address of one spike 5 and the destination address of the other spike 5 input to the time difference calculation circuit 3, and if the comparison results in a match, outputs merging information indicating that these spikes 5 have merged to the selection value generation circuit 32. What is meant by one spike 5 and the other spike 5 depends on whether attention is paid to a post spike 5 or a pre spike 5. The time difference calculation circuit 3 may, for example, distinguish between a pre spike 5 and a post spike 5 based on a spike attribute flag set in the spike 5.

[0124] The comparator array 31 may, for example, compare the source address of post spike 5 with the destination address of pre spike 5, or may compare the source address of pre spike 5 with the destination address of post spike 5. Alternatively, the comparator array 31 may both compare the source address of post spike 5 with the destination address of pre spike 5, and compare the source address of pre spike 5 with the destination address of post spike 5. In the following explanation of the time difference calculation circuit array 2, attention is focused on the post spike 5, and an example of comparing the source address of post spike 5 with the destination address of pre spike 5 will be shown.

[0125] In the example shown in FIG. 17, the time difference calculation circuit array 2 is a two-dimensional mesh (see FIG. 12), and the time difference calculation circuit 3 supports four inputs and four outputs, so the comparator array 31 can support a total of four spikes 5 (two pairs of pre spike 5 and post spike 5).

[0126] As shown in Fig. 17, the comparator array 31 may include a plurality of comparators 31a (12 in the example of Fig. 17). Each comparator 31a compares the source address of the post spike 5 with the destination address of the pre spike 5 among the spikes 5 input from the FIFOs 41a to 41d (represented as N, E, W, and S, respectively, in Fig. 17). For this purpose, the comparator array 31 crosses a signal line transmitting the source address of the post spike 5 for each of N, E, W, and S with a signal line transmitting the destination address of the pre spike 5 for each of N, E, W, and S, and provides a comparator 31a that compares the address values ​​at the intersection of each signal line.

[0127] Fig. 18 is a diagram showing an example of the comparator 31a. As shown in Fig. 18, the comparator 31a compares the source address of spike 5 (for example, post spike 5) with the destination address of spike 5 (for example, pre spike 5). If the comparison results in a match, this means that the post spike 5 and the pre spike 5 have merged in the time difference calculation circuit 3. If the comparison results in a match, the comparator 31a outputs pair information (merging information) indicating that the pair of the post spike 5 and the pre spike 5 has merged, for example, information specifying any two pairs among the FIFOs 41a to 41d corresponding to the two signal lines compared by the comparator 31a, to the selection value generation circuit 32.

[0128] The selection value generation circuit 32 generates a selection value for selecting between the counters C and J set in the post spike 5 and the counters C and J set in the pre spike 5 in accordance with the pair information notified from the comparator array 31, and outputs the selection value to the selection circuit 33. Note that when the selection value generation circuit 32 is notified of pair information from each of the two comparators 31a, it may output separate pair information to each selection circuit 33.

[0129] The selection circuit 33 selects the counters C and J set in the post spike 5 and the counters C and J set in the pre spike 5 based on the selection value, and outputs the selected counters to the calculation unit 34 .

[0130] The calculation unit 34 calculates the counter C obtained from the selection circuit 33 according to the above formula (4). post and C pre The calculation unit 34 calculates the time difference Δt by calculating the difference between the pre-spike 5 and the pre-spike 6. In addition, the calculation unit 34 increments the value of the counter J for the pre-spike 5.

[0131] Then, the calculation unit 34 outputs the pre spike 5 updated by setting the calculated time difference Δt and the incremented counter J to the router 4 (FIFO 41e).

[0132] When the transmission of the spike 5 is stalled, the time difference calculation circuit 3 may calculate the time difference Δt by adding the number of stall cycles to the counter C. That is, in this case, the clock for the transmission line may be virtually taken into account in the calculation of the time difference Δt. For example, the addition of the number of stall cycles to the counter C can be implemented by counting up the counter C for each clock.

[0133] Furthermore, as described above, the post spike 5 that merges with the pre spike 5 in the time difference calculation circuit 3 may be discarded in the time difference calculation circuit 3. For example, the calculation unit 34 may suppress the update of the time difference Δt and the counter J for the post spike 5, and may suppress the output of the post spike 5 (for example, discard the post spike 5).

[0134] Furthermore, if no merging of spikes 5 occurs in the time difference calculation circuit 3, for example, if one unpaired spike 5 is input to the time difference calculation circuit 3 in a certain clock, this spike 5 is a spike 5 that passes through the time difference calculation circuit 3. The time difference calculation circuit 3 may output a spike 5 that does not involve merging to the router 4 (FIFO 41e) after passing through the comparator array 31. In this case, the time difference Δt and counter J of this spike 5 are not updated. The value of counter C for this spike 5 is incremented in the FIFO 41 when this spike 5 flows into the router 4.

[0135] As described above, when the time difference calculation circuit 3 detects a merging of a pre-spike 5 and a post-spike 5, it sets the time difference Δt calculated based on the values ​​of the counters C of the pre-spike 5 and the post-spike 5 in the pre-spike 5 to be transferred. In addition, when the time difference calculation circuit 3 detects the merging, it updates the counter J of the pre-spike 5 to a value different from the initial value.

[0136] The input buffer 11a included in the ignition node 11 may have the configuration of the above-mentioned time difference calculation circuit 3. A router 4 having the above-mentioned configuration may be provided between the ignition node 11 and the time difference calculation circuit 3 adjacent to the ignition node 11. The input buffer 11a and the router 4 between the input buffer 11a and the time difference calculation circuit 3 may operate as the ignition node 11 in an operation example of the time difference calculation circuit array 2 described later.

[0137] [C-2] Example of operation of time difference calculation circuit array in NC Next, an example of the operation of the time difference calculation circuit array 2 of the NC1 according to an embodiment will be described.

[0138] [C-2-1] Example of operation of time difference calculation circuit and router First, there is described an example of a time difference calculation algorithm in the time difference calculation circuit 3 and the router 4. Figure 19 is a flowchart illustrating an example of a time difference calculation process by the time difference calculation circuit 3 and the router 4 according to an embodiment.

[0139] As illustrated in FIG. 19, the router 4 (or the time difference calculation circuit 3) increments the value of the counter C for the arriving spike 5 (process S1).

[0140] If the post spike 5 arrives at the time difference calculation circuit 3 (YES in process S2) and the pre spike 5 arrives (YES in process S3), the time difference calculation circuit 3 judges whether or not there is a merger (process S4). On the other hand, if the post spike 5 does not arrive (NO in process S2) or the pre spike 5 does not arrive (NO in process S3), the process proceeds to process S8.

[0141] In process S4, the time difference calculation circuit 3 uses the comparator array 31 to determine whether or not the source address of one spike 5 matches the destination address of the other spike 5. If they do not match (NO in process S4), the process proceeds to process S8.

[0142] For example, if the source address of post spike 5 and the destination address of pre spike 5 match (YES in process S4), the calculation unit 34 calculates the time difference Δt based on the values ​​of counters C of each of pre spike 5 and post spike 5 and the above equation (4) (process S5).

[0143] Next, the calculation unit 34 increments the value of the counter J for the pre-spike 5 (processing S6). In addition, the calculation unit 34 discards the post-spike 5 (processing S7).

[0144] In process S8, the router 4 transfers the updated pre-spike 5 (see processes S5 to S7) or the non-merged spike 5 (see each NO route in processes S2 to S4) to an adjacent router 4, and the process ends.

[0145] [C-2-2] Example of spike (time difference) transmission 20 to 23 are diagrams for explaining an example of transmission of spike 5 (time difference Δt). In the examples of Fig. 20 to 23, the path between a source neuron (e.g., the first firing node 11) and a destination neuron (e.g., the second firing node 11) is expressed one-dimensionally. For example, as shown in the upper left of Fig. 20, the path between the source neuron and the destination neuron is formed by a plurality of points (pairs of time difference calculation circuits 3 and routers 4) between the firing nodes 11 in the time difference calculation circuit array 2.

[0146] 20 to 23, the multi-hop route between the source neuron and the destination neuron (time difference calculation circuit array 2) represents one synapse between the source neuron and the destination neuron. As described above, since NC1 is a formal neuron model, the multi-hop route does not represent a physical distance.

[0147] For convenience, in the explanation of Figures 20 to 23, a set of a time difference calculation circuit 3 and a router 4 is written as a "point" and shown as a white circle or a shaded square. Also, a part connecting points (routers 4) is written as a "transmission path." Also, the subscript numbers of steps shown in Figures 20 to 23 indicate the state in which spike 5 has progressed (transmitted) one hop along the route for each clock, starting from 1.

[0148] FIG. 20 shows an example of transmission where spike 5 meets at a point between a source neuron and a destination neuron.

[0149] In step A1, the (pre)spike 5a is sent from the source neuron and arrives at the first point from the left. The value of the counter C for the spike 5a is updated to 1.

[0150] In step A2, spike 5a arrives at the second point from the left. The value of counter C of spike 5a is updated to 2.

[0151] In step A3, spike 5a arrives at the third point from the left. The value of counter C for spike 5a is updated to 3. Also, (post) spike 5b is sent from the destination neuron and arrives at the first point from the right. The value of counter C for spike 5b is updated to 1.

[0152] In step A4, spike 5a arrives at the fourth point from the left. The value of counter C for spike 5a is updated to 4. Also, spike 5b arrives at the second point from the right. The value of counter C for spike 5b is updated to 2.

[0153] In step A5, spikes 5a and 5b join at the fifth point from the left (third from the right). The value of counter C of spike 5a is updated to 5. Also, the value of counter C of spike 5b is updated to 3. The time difference calculation circuit 3 at that point calculates the difference between the value of counter C (2) of post spike 5b and the value of counter C (5) of pre spike 5a to calculate the time difference Δt (-3), and transmits pre spike 5a setting the time difference Δt and the incremented counter J. Also, the time difference calculation circuit 3 discards post spike 5b.

[0154] In step A6, spike 5a with a time difference Δt set arrives at the sixth point from the left. The value of counter C for spike 5a does not need to be updated. Also, (pre)spike 5c is sent from the source neuron and arrives at the first point from the left. The value of counter C for spike 5c is updated to 1.

[0155] In this way, the time difference calculation circuit array 2 calculates the time difference Δt between the firing timing of the post spike 5b and the firing timing of the pre spike 5a (the time difference between step A3 and step A1 in the example of FIG. 20) in the time difference calculation circuit 3 where these spikes 5 join together. Also, the counter C used to calculate the time difference Δt and the calculated time difference Δt are set in the spike 5 and transmitted. Therefore, there is no need to reserve a storage area such as a memory for the calculation and transmission of the time difference Δt, and the calculation and transmission of the time difference Δt can be made possible with a simple configuration and logic as well as a scalable configuration.

[0156] The destination neuron (eg, the second firing node 11) updates the connection strength W between the destination neuron and the source neuron based on the time difference Δt set in the spike 5a received from the time difference calculation circuit array 2.

[0157] FIG. 21 shows an example of transmission in which a pre-spike 5d from a source neuron does not merge with a post-spike 5e before arriving at the destination neuron (in which spikes 5d and 5e merge at the destination neuron).

[0158] In step B1, (pre)spike 5d is sent from the source neuron and arrives at the first point from the left. The value of counter C for spike 5d is updated to 1.

[0159] In each of steps B2 to B7, the spike 5d advances one point at a time to the right side of the paper, and the value of the counter C of the spike 5d is incremented by one.

[0160] In step B8, spike 5d arrives at the destination neuron. The value of counter C for spike 5d is updated to 8. Since the value of counter J for spike 5d remains at its initial value (0), spike 5d is held in the destination neuron.

[0161] In step B9, the value of counter C for spike 5d is updated to 9. Also, spike 5e occurs in the destination neuron. The destination neuron calculates the time difference Δt (-9) by calculating the difference between the value of counter C for spike 5e (0) and the value of counter C for spike 5d (9) in the clock that generated spike 5e, using a method similar to that used by time difference calculation circuit 3. After obtaining the time difference Δt, the destination neuron discards spikes 5d and 5e. Also, the destination neuron updates the connection strength W based on the obtained time difference Δt.

[0162] In this way, if spike 5d arrives at the destination neuron but does not merge with another spike 5, the value of counter C is incremented for each step and is held until the merge. This allows the time difference calculation circuit array 2 to properly calculate and obtain the time difference Δt between the firing timing of post spike 5e and the firing timing of pre spike 5d (the time difference between step B9 and step B1 in the example of FIG. 21).

[0163] FIG. 22 shows an example of transmission in which a post spike 5f from a destination neuron does not merge with a pre spike 5g before arriving at the source neuron (in which spikes 5f and 5g merge at the source neuron).

[0164] In step C1, (post) spike 5f is sent from the destination neuron and arrives at the first point from the right. The value of counter C for spike 5f is updated to 1.

[0165] In each of steps C2 to C7, the spike 5f advances one point at a time to the left side of the paper, and the value of the counter C of the spike 5f is incremented by one.

[0166] In step C8, spike 5f arrives at the source neuron. The value of counter C for spike 5f is updated to 8. Since the value of counter J for spike 5f remains at its initial value (0), spike 5f is held in the source neuron.

[0167] In step C9, the value of counter C for spike 5f is updated to 9. Also, spike 5g occurs in the source neuron. Using a method similar to that used by time difference calculation circuit 3, the source neuron calculates the time difference Δt (+9) by calculating the difference between the value of counter C for spike 5f (9) and the value of counter C for spike 5g (0) in the clock that generated spike 5g. After calculating the time difference Δt, the source neuron discards post spike 5f and transmits updated pre spike 5g, in which the time difference Δt and the incremented counter J are set, to the time difference calculation circuit array 2.

[0168] In step C10, pre-spike 5g arrives at the first point from the left. At this time, the router 4 and time difference calculation circuit 3 at that point may suppress updating of the value of counter C of spike 5g because counter J of spike 5g is 1 (other than 0). After step C10, pre-spike 5g advances to the point on the right side of the paper one step at a time, and is discarded after it arrives at the destination neuron (after the destination neuron acquires the time difference Δt).

[0169] In this way, if spike 5f arrives at the source neuron but does not merge with other spikes 5, the value of counter C is incremented for each step and is held until the merge. This allows the time difference calculation circuit array 2 to accurately calculate and obtain the time difference Δt between the firing timing of post spike 5f and the firing timing of pre spike 5g (the time difference between step C9 and step C1 in the example of FIG. 22).

[0170] In addition, factors such as the number of hops between the source neuron and the destination neuron and whether the value of the time difference Δt is even or odd (the firing timing of each spike 5) determine whether the merging of the spikes 5 occurs at a point (the time difference calculation circuit 3 and the router 4) or on the transmission path (between the routers 4). Since this depends on the routing method in the time difference calculation circuit array 2, it is also possible to control the merging of the spikes 5 to occur at a point (the time difference calculation circuit 3 and the router 4) by using the routing method.

[0171] Alternatively, the time difference calculation circuit array 2 may be designed so that it can calculate the time difference Δt even when the merging of the spikes 5 occurs on the transmission path (between the routers 4), for example.

[0172] As an example, when the time difference calculation circuit 3 receives a post-spike 5 that does not merge and transfers it to an adjacent point, it may hold a copy of that spike 5 for at least one clock. At this time, the time difference calculation circuit 3 may increment the value of the counter C for the copy of that spike 5 in accordance with an increase in the clock (step). When the time difference calculation circuit 3 receives a pre-spike 5 from the transmission direction (N, E, W, S) of the post-spike 5 within one clock after transmitting the post-spike 5, it may determine whether the pre-spike 5 and the copy of the post-spike 5 will merge, and calculate the time difference if they have merged.

[0173] This allows the time difference calculation circuit 3 to calculate the time difference Δt even when the merging point of the spikes 5 is on an adjacent transmission line, and to set the time difference Δt (and the counter J) in the pre-spike 5 and transmit it to the destination neuron.

[0174] FIG. 23 shows an example of operation in which a plurality of spikes 5 are sent from each of a source neuron and a destination neuron.

[0175] In step D1, (pre)spike 5h is sent from the source neuron and exists on the first transmission line from the left. The value of counter C for spike 5h remains at its initial value (0).

[0176] In step D2, spike 5h is present on the second transmission line from the left. The value of counter C for spike 5h is updated to 1 at the first point from the left.

[0177] In step D3, spike 5h is present on the third transmission path from the left. The value of counter C for spike 5h is updated to 2 at the second point from the left. Furthermore, (pre) spike 5i is sent from the source neuron and is present on the first transmission path from the left. The value of counter C for spike 5i remains at its initial value (0). Furthermore, (post) spike 5j is sent from the destination neuron and is present on the first transmission path from the right. The value of counter C for spike 5j remains at its initial value (0).

[0178] In step D4, spikes 5h and 5j join on the fourth transmission path from the left (second from the right). The value of counter C for spike 5h is updated to 3 at the third point from the left. The value of counter C for spike 5j is updated to 1 at the first point from the right. In addition, spike 5i exists on the second transmission path from the left. Furthermore, (pre)spike 5k is sent from the source neuron and exists on the first transmission path from the left. The values ​​of counter C for each of spikes 5i and 5k remain at the initial value (0).

[0179] In step D5, pre-spike 5h exists on the fifth transmission path from the left. Spike 5h is set with the time difference Δt_h(−2) calculated at the fourth point from the left and the incremented counter J(1). Note that post-spike 5j is discarded.

[0180] In step D6, pre-spike 5h with the time difference Δt_h set arrives at the destination neuron. After obtaining the time difference Δt_h, the destination neuron discards spike 5h. Furthermore, spike 5i is present on the fourth transmission path from the left. The value of counter C for spike 5i is updated to 3 at the third point from the left. Furthermore, spike 5k is present on the third transmission path from the left. The value of counter C for spike 5k is updated to 2 at the second point from the left. Furthermore, spike 5l is sent from the destination neuron and is present on the first transmission path from the right. The value of counter C for spike 5l remains at the initial value (0).

[0181] Between steps D6 and D7, spikes 5i and 5l join at the fourth point from the left (first from the right). The pre-spike 5i is set with the time difference Δt_i(−3) calculated at that point and the incremented counter J(1). The post-spike 5l is discarded.

[0182] In step D7, pre-spike 5i, to which the time difference Δt_i has been set, is present on the fifth transmission path from the left. Also, spike 5k is present on the fourth transmission path from the left. The value of counter C for spike 5k has been updated to 3 at the third point from the left. Furthermore, spike 5m is sent from the source neuron and is present on the first transmission path from the left. Also, spike 5n is sent from the destination neuron and is present on the first transmission path from the right. The values ​​of counters C for spikes 5m and 5n remain at their initial values ​​(0).

[0183] Between steps D7 and D8, spikes 5k and 5n join at the fourth point from the left (first from the right). The pre-spike 5k is set with the time difference Δt_k(−3) calculated at that point and the incremented counter J(1). The post-spike 5n is discarded.

[0184] In step D8, spike 5i arrives at the destination neuron. After acquiring the time difference Δt_i, the destination neuron discards spike 5i. Also, pre-spike 5k with time difference Δt_k set is present on the fifth transmission path from the left. The value of counter C for spike 5k is updated to 4 at the fourth point from the left. Also, spike 5m is present on the second transmission path from the left. The value of counter C for spike 5m is updated to 1 at the first point from the left.

[0185] In this way, for spikes 5h and 5j that merge on the transmission path, the time difference calculation circuit array 2 can appropriately calculate and obtain the time difference Δt between the firing timing of the post spike 5j and the firing timing of the pre spike 5h (the time difference between step D3 and step D1 in the example of Figure 23).

[0186] [D] Explanation of the firing mechanism of the firing node Next, the firing mechanism 11c (see FIG. 14) of the firing node 11 according to an embodiment will be described in detail. The firing mechanism 11c is a mechanism for generating (firing) a spike 5 when the amount (electric potential) of ion molecules flowing into a neuron exceeds a threshold.

[0187] In a neural network, each neuron has many inputs. Therefore, if a configuration for calculating an index corresponding to the amount of ion molecules flowing into a neuron, such as a configuration for adding up the connection strength W, is implemented using a tree-structured adder circuit, the number of inputs is fixed and the scale of the adder circuit becomes large, which is not practical.

[0188] It is possible to use an accumulator to add up the connection strength W. However, since NC1 is based on STDP, which uses timing, it is difficult to implement a configuration for adding up (accumulating) the connection strength W using a simple accumulator.

[0189] Therefore, in one embodiment, a method of calculating the cumulative sum of the connection weights W in STDP while taking timing into consideration will be described.

[0190] [D-1] Detailed configuration example of the firing mechanism Fig. 24 is a block diagram showing an example of a hardware configuration of the firing mechanism 7. The firing mechanism 7 is an example of the firing mechanism 11c shown in Fig. 14, and is an example of a spike generating circuit.

[0191] As illustrated in FIG. 24, the firing mechanism 7 may include a circular buffer 70, a buffer control circuit 71, comparators 72 and 75, registers 73, 77a and 77b, a summation circuit 74, counters 76a and 76b, and an adder 78.

[0192] The circular buffer 70 is an example of the circular buffer 11f shown in FIG. 14, and is an example of a buffer that stores, for each of a plurality of spikes 5 received from the time difference calculation circuit array 2, the time difference Δt set in the spike 5 and the coupling strength W between the firing node 11 that transmitted the spike 5 and its own firing node 11, in correspondence with each other.

[0193] The circular buffer 70 stores, for example, a pair of a time difference Δt and a coupling strength W input from the coupling strength mechanism 11b. The circular buffer 70 may include, for example, a circular buffer 70a that stores the time difference Δt and a circular buffer 70b that stores the coupling strength W. The pair is correlated by the spike 5 received by the input buffer 11a.

[0194] The buffer control circuit 71 manages each of the circular buffers 70a and 70b using a tail pointer Tail and a head pointer Head, thereby controlling the circular buffer 70. This ensures the order of pairs of time difference Δt and coupling strength W.

[0195] The buffer control circuit 71, for example, reads and outputs a pair of the time difference Δt and the coupling strength W from the addresses of the head pointers Head of the circular buffers 70a and 70b, and updates the head pointer Head to a value indicating the next address. For example, the time difference Δt read from the circular buffer 70a is input to a comparator 72, and the coupling strength W read from the circular buffer 70b is input to a cumulative summation unit 74.

[0196] Furthermore, the buffer control circuit 71 writes the pair of the time difference Δt and the coupling strength W received from the coupling strength mechanism 11b to the address of the tail pointer Tail of the circular buffers 70a and 70b, and updates the tail pointer Tail to a value indicating the next address.

[0197] If the circular buffer 70a or 70b has no free space (for example, if Tail=Head), the buffer control circuit 71 may transmit a Nack to the input buffer 11a via the coupling strength mechanism 11b.

[0198] Incidentally, the above-mentioned time difference calculation circuit array 2 compares the source and destination addresses of spikes 5 in order to transfer spikes 5, judge merging, calculate time differences, etc. On the other hand, the firing mechanism 7 accumulates the coupling strength W corresponding to the time difference Δt of spikes 5 for spikes 5 that have arrived at the firing node 11, making it unnecessary to distinguish between the source and destination of each spike 5.

[0199] Comparator 72 compares the absolute value of the time difference Δt input from circular buffer 70a with the target time difference Δtth input from adder 78. That is, comparator 72 identifies a time difference Δt that is within the range of 0≦[time difference |Δt|]≦target time difference Δtth. For example, comparator 72 may sequentially compare the absolute values ​​of the time difference Δt stored in circular buffer 70a with the target time difference Δtth in a search (scan) manner.

[0200] For example, when the absolute value of the time difference Δt is equal to or smaller than the target time difference Δtth, the comparator 72 sends a Found signal (count-up signal) to the counter 76a and sends a we (write enable) signal to the register 73. The target time difference Δtth is an example of a first threshold value.

[0201] In the following description, sending a signal may include changing the potential between the source and destination of the signal from a first value (e.g., Low or High) indicating that the signal is invalid to a second value (e.g., High or Low) indicating that the signal is valid.

[0202] In this way, the comparator 72 identifies the time difference Δt that is equal to or smaller than the target time difference Δtth, from among the multiple time differences Δt set in the multiple spikes 5 received from the time difference calculation circuit array 2.

[0203] The register 73 holds the cumulative sum result of the coupling strength W input from the cumulative summation unit 74 in response to the we signal input from the comparator 72, and outputs the held cumulative sum result to the comparator 75. In addition, the register 73 clears (erases) the held value in response to the clr (clear) signal input from the comparator 75.

[0204] The cumulative summation unit 74 is an example of a cumulative summation circuit (accumulator) and calculates an index corresponding to the amount of ion molecules flowing into the neuron. The cumulative summation unit 74, for example, performs a cumulative sum (for example, cumulative addition) of the connection strength W input from the circular buffer 70b and the (previous) cumulative sum result of the connection strength W input from the register 73, and outputs the cumulative sum result to the register 73. As described above, the cumulative sum result input to the register 73 is held in the register 73 when the we signal is input to the register 73. Therefore, the register 73 holds the cumulative sum result of the connection strength W pair with the time difference Δt whose absolute value is equal to or less than the target time difference Δtth.

[0205] In this way, the cumulative summation unit 74 accumulates the connection strength W between the first firing node 11 that is the source (other party) of the third spike 5, for which a time difference Δt is set such that its absolute value is less than or equal to the target time difference Δtth, and its own (our) second firing node 11. For example, when the time difference Δt read from the circulatory buffer 70a is less than or equal to the target time difference Δtth, the cumulative summation unit 74 reads from the circulatory buffer 70b the connection strength W that is stored in the circulatory buffer 70b in association with the read time difference Δt, and accumulates it.

[0206] The comparator 75 compares the cumulative sum result input from the register 73 with a predetermined ignition threshold Wth. The ignition threshold Wth is an example of a second threshold.

[0207] The comparator 75 sends out a Fire signal, an en signal, and a clr signal indicating firing when the cumulative sum result exceeds the firing threshold Wth, for example. For example, the comparator 75 may send a Fire signal to a circuit that sends a spike 5 to the time difference calculation circuit 3 (or the router 4) adjacent to its own firing node 11. The circuit may be provided in, for example, the firing mechanism 7 or the firing node 11. The comparator 75 may also send out a clr signal to, for example, the register 73 and each of the counters 76a and 76b, and send out a we signal to the registers 77a and 77b.

[0208] When the cumulative sum result exceeds the firing threshold Wth and firing occurs, and thereafter a search for the time difference Δt is not necessary, the comparator 75 may instruct the buffer control circuit 71 to update the tail pointer Tail.

[0209] In this way, the comparator 75 generates a new spike 5 (fourth spike 5) when the result of the cumulative sum exceeds the firing threshold Wth.

[0210] The counter 76a (sometimes referred to as "counter A") counts the number of neurons that contributed to firing. The counter 76a counts up a count value A every time it receives a Found signal from the comparator 72, for example, and outputs the count value A to the register 77a. The counter 76a also clears (erases) the count value A it holds in response to a clr signal input from the comparator 75. The count value A of the counter 76a indicates a logical transition over time.

[0211] In other words, the count value A indicates the number of times that the coupling strength W is accumulated during the time interval between the occurrence timing of the (fourth) spike 5 that fired immediately before and the occurrence timing of the (fifth) spike 5 that fired immediately before that spike 5. Alternatively, the count value A can be said to indicate the number of time lags Δt (spikes 5) whose absolute values ​​are determined by the comparator 72 to be equal to or less than the target time lag Δtth during that time interval.

[0212] Counter 76b (sometimes referred to as "counter B") counts the time interval between firings. Counter 76b counts up count value B, which indicates the number of steps since the previous firing, in response to a clock such as a global step, and outputs count value B to register 77b. Counter 76b also clears (erases) the held count value B in response to an input of a clr signal from comparator 75.

[0213] In other words, count value B indicates the time interval between the occurrence timing of the (fourth) spike 5 that fired immediately before and the occurrence timing of the (fifth) spike 5 that fired immediately before that spike 5.

[0214] The register 77 a holds the count value A input from the counter 76 a in response to the input of the we signal from the comparator 75 , and outputs the held count value A to the adder 78 .

[0215] The register 77 b holds the count value B input from the counter 76 b in response to the input of the we signal from the comparator 75 , and outputs the held count value B to the adder 78 .

[0216] Adder 78 updates the target time difference Δtth based on count value B input from register 77b and count value A input from register 77a. Adder 78 calculates the target time difference Δtth, for example, by adding count value B and a value obtained by inverting the sign of count value A (a negative value), and outputs the target time difference Δtth to comparator 72. That is, the target time difference Δtth may be obtained by subtracting count value A from count value B (calculating the difference between count values ​​A and B), as shown in equation (5) below. Target time difference Δtth = count value B - count value A (5)

[0217] As described above, the count values ​​A and B held by the counters 76a and 76b are written to the registers 77a and 77b at the timing of firing in the comparator 75 and are held until the timing of the next firing. Therefore, it can be said that the comparator 72 determines the time difference Δt contributing to the current firing by using the target time difference Δtth calculated based on the count values ​​A and B at the time of the previous firing.

[0218] As can be seen from Fig. 4, the smaller the time difference (time difference Δt), the larger the change in the connection strength W. Therefore, the firing mechanism 7 searches for spikes 5 with a time difference Δt such that the time (number of steps) required from the firing of the spike 5 to the merging between the other neuron and the own neuron, i.e., the time interval between the firing timings of the spikes 5, is less than a predetermined value (target time difference Δtth). Then, the firing mechanism 7 accumulates the connection strength W only for the spikes 5 identified by the search among the multiple spikes 5 flowing into the firing node 11.

[0219] This makes it possible to realize the summation of the coupling weights W in STDP while taking timing into consideration, while suppressing an increase in the circuit scale of the firing mechanism 7 including the summation unit 74.

[0220] 25 is a diagram for explaining an example of a method for calculating the target time difference Δtth. As mentioned above, the concept of time is not used in NC1, but in the following explanation, for convenience, a global step by a global counter is used as an index showing logical timing (elapsed time).

[0221] In Fig. 25, the timing of spike 5 in the other neuron, which is the source of pre-spike 5, and in the own neuron, which is the source of post-spike 5, is shown in correspondence with the global step (GS). The path length between the other neuron and the own neuron is assumed to be 5 hops.

[0222] Counter B is incremented for each GS. Counter A is incremented when it receives spike 5 with a time difference |Δt| less than or equal to the target time difference Δtth. In the example of Fig. 25, it is incremented at GS 9, 11, 14, 16, and 17. Counters A and B are also reset at the firing timing of the neuron in question (GS 7 and 17 in the example of Fig. 25).

[0223] The circular buffer 70a receives spike 5 with time differences Δt of +3, −5, and +3 from the distant neurons in GSs 9, 17, and 20, respectively. The circular buffer 70a also receives spike 5 from the other distant neurons in GSs 11, 14, and 16, respectively.

[0224] The target time difference Δtth is calculated as count value B-count value A=10-4=6 at the timing of firing of the neuron in GS7. The target time difference Δtth=6 is used in GS8-17 to specify the time difference Δt that contributes to firing in the comparator 72, in other words, to eliminate the time difference Δt that does not contribute to firing. That is, by using the target time difference Δtth, the spike 5 that has timed out is eliminated from the circular buffer 70.

[0225] In GS17, when the neuron in question fires due to the cumulative sum of the connection strength W of spike 5 having a time difference Δt=-5, the adder 78 calculates count value B-count value A=9-5=4 as the target time difference Δtth to be used in GS18 and thereafter.

[0226] [D-2] Example of firing mechanism operation Fig. 26 is a diagram for explaining an example of the operation of the firing mechanism 7. Fig. 26 explains an example of the change in state of the firing mechanism 7 in the firing node 11C of the neuron of the user along with the transition (count-up) of the value of the counter B. It is assumed that the firing node 11A of the neuron at the other end, which is 5 hops away, and the firing node 11B of the neuron at the other end, which is 3 hops away, are connected to the neuron of the user.

[0227] (Before counter B=1: not shown in Figure 26) A post spike 5x is sent from the firing node 11C to each of the firing nodes 11A and 11B. Also, a pre spike 5y is sent from the firing node 11A to the firing node 11C, and a pre spike 5z is sent from the firing node 11B to the firing node 11C.

[0228] (Counter B=1,2) The spikes 5x, 5y, and 5z each travel one hop on the time difference calculation circuit array 2 toward the destination.

[0229] (Counter B=3) In the time difference calculation circuit array 2, spikes 5x and 5y join together, and the time difference Δt=-1 calculated by the above-mentioned method is added to pre-spike 5y. Spikes 5x and 5z join together, and the time difference Δt=+1 calculated by the above-mentioned method is added to pre-spike 5z. Spike 5x is discarded. Hereinafter, spikes 5y and 5z to which the time difference Δt has been added will be referred to as spikes 5Y and 5Z, respectively.

[0230] (Counter B=4,5) The spikes 5Y and 5Z each travel one hop on the time difference calculation circuit array 2 toward the firing node 11C.

[0231] (Counter B=6) The spikes 5Y and 5Z each reach the firing node 11C, and the time difference Δt and the connection strength W of each of the spikes 5Y and 5Z are stored in the circular buffer 70 of the firing mechanism 7. For convenience, in Fig. 26, the time difference Δt and the connection strength W stored in the circular buffer 70 are represented as rectangular frames representing the spikes 5Y and 5Z.

[0232] (Counter B=7) The time difference Δt included in spike 5Z is less than or equal to the target time difference Δtth, and the coupling strength W of spike 5Z is accumulated in accumulation calculator 74. Counter A counts up from 0 to 1. Also, the time difference Δt included in spike 5Y is less than or equal to the target time difference Δtth, and the coupling strength W of spike 5Y is accumulated in accumulation calculator 74. Counter A counts up from 1 to 2.

[0233] At this time, the output of the cumulative summation unit 74 exceeds the firing threshold Wth, and a Fire signal is sent from the firing mechanism 7 (firing node 11C fires). The target time difference Δtth=7-2=5 is calculated as the logical time (number of steps) that has progressed since the previous firing, and this target time difference Δtth is used as the time difference range for searching for the time difference Δt for the next cumulative sum. This makes it possible to ignore spikes 5 whose time difference |Δt| is greater than the target time difference Δtth as time-out spikes 5 (ignoring the steps required to eliminate spikes 5 that do not contribute to firing).

[0234] [E] Explanation of the firing mechanism of the bond strength mechanism Next, the connection strength mechanism 11b (see FIG. 14) of the ignition node 11 according to an embodiment will be described in detail. The connection strength mechanism 11b reads the connection strength W corresponding to the source address of the spike 5 that has flowed into the ignition node 11 from the connection strength memory 11e, calculates an update value, and writes (writes back) the update value.

[0235] Here, since the connection strength W indicates the degree of connection between neurons, it is generally stored for each synapse site (distributed in a connection strength memory). However, if each distributed synapse site has a connection strength W, reading and writing of values ​​to each site occurs, which may consume extra resources such as the network between the external memory and each connection strength memory and communication scheduling, and may complicate NC1.

[0236] In one embodiment, an example of a method for aggregating and managing (handling) the connection strengths W within the firing node 11 by arranging a connection strength memory 11e in the connection strength mechanism 11b connected to the firing mechanism 7 will be described.

[0237] [E-1] Detailed configuration example of the firing mechanism 27 is a block diagram showing an example of a hardware configuration of the connection strength mechanism 8. The connection strength mechanism 8 is an example of the connection strength mechanism 11b shown in FIG.

[0238] The connection strength mechanism 8 is an example of a connection strength updating circuit that updates the first connection strength W between our (our) firing node 11 and the other party's (the source of the spike 5) firing node 11 based on the time difference Δt set in the spike 5 received from the time difference calculation circuit array 2.

[0239] The coupling strength mechanism 8 may include a buffer 80, registers 81 and 83, a coupling strength memory 82, and a W update circuit 84, as shown in FIG.

[0240] 14, and stores information on spike 5 input from input buffer 11a, for example, at least the time difference Δt and source address contained in spike 5. Buffer 80 outputs the time difference Δt to register 81 and firing mechanism 11c (for example, firing mechanism 7), and outputs the source address to coupling strength memory 82.

[0241] The register 81 stores the time difference Δt input from the buffer 80 and outputs it to the W update circuit 84 .

[0242] The connection strength memory 82 is an example of a memory that stores, in association with each other, information indicating each of the multiple ignition nodes 11 and the connection strength W between each of the multiple ignition nodes 11 and its own ignition node 11. The connection strength memory 82 may be realized, for example, by a storage area that stores the connection strength W associated with a source address.

[0243] The coupling strength mechanism 8, for example, searches the coupling strength memory 82 using the source address input from the buffer 80 as a key, reads out the coupling strength W associated with the source address from the coupling strength memory 82, and outputs it to each of the register 83 and the firing mechanism 11c (for example, the firing mechanism 7).

[0244] The connection strength mechanism 8 may search for the connection strength W from the connection strength memory 82 by using a mapping table that associates a source address with an address in the connection strength memory 82. The mapping table may be, for example, a table that associates a source address with a hash value of one or both of the addresses in the connection strength memory 82.

[0245] The register 83 stores the connection strength W input from the connection strength memory 82 and outputs it to the W update circuit 84 .

[0246] The W update circuit 84 calculates the updated connection strength W based on the time difference Δt input from the register 81 and the connection strength W input from the register 83. Furthermore, the W update circuit 84 updates the connection strength W stored in the connection strength memory 82 in association with the source address by writing (writing back) the calculated connection strength W to the connection strength memory 82 in association with the source address. Various methods may be used as a method for the W update circuit 84 to update the connection strength W.

[0247] The W update circuit 84 updates the coupling strength W based on, for example, the following formula (6), which is the same as the above formula (1): t In the following formula (6), W t-1 is the coupling strength W input from the register 83, and Δw(Δt) is the amount of change in the coupling strength W calculated based on the time difference Δt input from the register 81. Bond strength W t =W t-1 +Δw(Δt) (6)

[0248] In this way, the connection strength mechanism 8 and the W update circuit 84 are an example of an update circuit that reads the first connection strength W from the connection strength memory 82 based on the source address included in the spike 5 received from the time difference calculation circuit array 2, and updates the first connection strength (W) stored in the connection strength memory 82 based on the time difference Δt set in the spike 5 and the read first connection strength W.

[0249] As described above, according to the connection strength mechanism 8 of one embodiment, the connection strength W for each source address can be centrally managed and updated by the connection strength memory 82, and an appropriate pair of the time difference Δt and the connection strength W can be appropriately sent to the subsequent firing mechanism 7. This makes it possible to simplify the circuit configuration of NC1 (firing node 11) while suppressing resource consumption such as scheduling and network.

[0250] [E-2] Example of the operation of the coupling strength mechanism Next, an example of the operation of the coupling strength mechanism 8 according to one embodiment will be described with reference to FIGS.

[0251] Fig. 28 is a diagram showing a configuration example of NC1 that uses an operation example of the connection strength mechanism 8 to explain. Fig. 28 shows a plurality of firing nodes 11, and a time difference calculation circuit array 2 that includes a plurality of time difference calculation circuits 3 and a router 4. In the following explanation, attention is paid to firing nodes 11A, 11B, and 11C in neurons labeled A to C among the plurality of firing nodes 11. In the following explanation, attention is paid to the connection strength mechanism 8, input buffer 11a, and firing mechanism 11c (for example, firing mechanism 7) included in the firing node 11C.

[0252] The transmission path of the spike 5 between the firing nodes 11 has a fixed path length determined by the arrangement of each firing node 11. For example, the path length between the firing node 11A and the firing node 11C is 20 hops, and the path length between the firing node 11B and the firing node 11C is 12 hops.

[0253] In the following explanation, the firing node 11A transmits 20 pre-spikes 5A (see FIG. 29, etc.) in succession (one for 20 steps) whose destination is the firing node 11C. The firing node 11B transmits pre-spikes 5B (see FIG. 30, etc.) at a predetermined time interval (one every few steps). The firing node 11C transmits post-spikes 5C (see FIG. 33, etc.) whose destination is the firing node 11B at a predetermined timing.

[0254] 29 to 42 are diagrams for explaining an example of transmission of spikes 5 between multiple firing nodes 11 in NC1 and an example of operation of the connection strength mechanism 8. Hereinafter, with reference to Figs. 29 to 42, an example of transmission of spikes 5 between firing nodes 11A, 11B, and 11C will be shown step by step, and an example of operation of the connection strength mechanism 8 at each step will be explained.

[0255] It should be noted that each of steps E1 to E63 shown in FIGS. 29 to 42 indicates a logical transition over time, and does not indicate the passage of time.

[0256] (Steps E1 to E9) 29 and 30, in steps E1 to E9, the ignition node 11A continues to transmit a spike 5A to the ignition node 11C. In each step, the spike 5 is transmitted hop by hop along the transmission path on the time difference calculation circuit array 2. The same applies to the following explanations.

[0257] (Step E10) As shown in Fig. 30, in step E10, the firing node 11B transmits a spike 5B toward the firing node 11C. The firing node 11A continues to transmit a spike 5A toward the firing node 11C.

[0258] (Steps E11 to E19) As shown in FIGS. 30 to 32, in steps E11 to E19, the ignition node 11A continues to transmit a spike 5A consecutively toward the ignition node 11C.

[0259] (Step E20) In step E20, the firing node 11B transmits a spike 5B toward the firing node 11C. The firing node 11A continues to transmit a spike 5A toward the firing node 11C.

[0260] (Steps E21 to E23) As shown in Figures 32 and 33, in step E21, the spike 5A transmitted from the ignition node 11A reaches the ignition node 11C and is stored in the input buffer 11a. The transmission of the spike 5A from the ignition node 11A stops. In step E22, the spike 5A transmitted from the ignition node 11A and the spike 5B transmitted from the ignition node 11B reach the ignition node 11C and are stored in the input buffer 11a. In step E23, the spike 5A transmitted from the ignition node 11A reaches the ignition node 11C and is stored in the input buffer 11a.

[0261] The value of counter C of spike 5 stored in input buffer 11a is incremented for each step until it joins with spike 5 transmitted from firing node 11C (denoted as "C=C+1").

[0262] In the following explanation, the transmission of spike 5 from firing nodes 11A and 11B, the reception of spike 5 at firing node 11C, the storage of spike 5 in input buffer 11a, and the updating of counter C in input buffer 11a may be omitted.

[0263] (Step E24) In step E24, the firing mechanism 11c of the firing node 11C generates a post spike 5C whose destination is the firing node 11B. The spike 5C merges with each of the spikes 5A and 5B that are stored earliest in the input buffer 11a for each of the firing nodes 11 that are the transmission source (see symbol F1).

[0264] The logic of the merging of spikes 5 is the same as that described above for the time difference calculation circuit array 2. With the objective of calculating the coupling strength W for each firing node 11 in the coupling strength mechanism 8, one post spike 5C may be merged with each of multiple (two in FIG. 33) pre spikes 5A and 5B in the input buffer 11a as shown in step E24. In the example of step E24, the spike 5C is merged with the spike 5B from the firing node 11B, which is its destination, and therefore may be discarded in the firing node 11C. Since each spike 5 has information on the source (firing source) address and the destination address (see FIG. 13), the firing node 11C can easily detect that the spike 5C and the spike 5B have been merged. For example, the input buffer 11a of the firing node 11C may compare the source address set in the pre spikes 5A and 5B with the destination address set in the post spike 5C, and discard the post spike 5C if the comparison result indicates a match between the addresses.

[0265] (Step E25) In step E25, the input buffer 11a acquires the time difference Δt_AC between spikes 5A and 5C and the time difference Δt_BC between spikes 5B and 5C due to the merging of spike 5 in step E24. Also, the source addresses of spikes 5A and 5B are acquired.

[0266] (Step E26) 34, in step E26, the firing mechanism 11c of the firing node 11C generates a post spike 5C whose destination is the firing node 11B. The spike 5C merges with the earliest stored spike 5A among the spikes 5 stored in the input buffer 11a (see symbol F2). In addition, the time differences Δt_AC and Δt_BC acquired in step E25 and the source address are stored in the buffer 80 of the connection strength mechanism 8.

[0267] (Step E27) In step E27, the spike 5C generated in step E26 is sent from the firing node 11C to the time difference calculation circuit array 2. In the input buffer 11a, due to the merging of the spike 5 in step E26, the time difference Δt_AC between the spikes 5A and 5C and the source address of the spike 5A are obtained.

[0268] In the connection strength mechanism 8, the time difference Δt (Δt_AC) of the pair stored earliest among the time difference Δt in the buffer 80 and the source address pair is stored in the register 81 and is also transmitted to the firing mechanism 11c.

[0269] In addition, the connection strength mechanism 8 identifies a corresponding address in the connection strength memory 82 based on the sender address (denoted as "Sender addr.") of the pair stored earliest in the buffer 80, and reads out the connection strength W of the firing node 11A from the address. The read connection strength W is stored in the register 83 and is also transmitted to the firing mechanism 11c.

[0270] (Step E28) In step E28, the firing node 11C generates a spike 5C. The spike 5C merges with the spike 5A that was stored first in the input buffer 11a (see symbol F3). In addition, the time difference Δt_AC obtained in step E27 and the source address are stored in the buffer 80 of the connection strength mechanism 8.

[0271] The W update circuit 84 (denoted as "W update") calculates the updated connection strength W based on the time difference Δt and the connection strength W input from the registers 81 and 83, and updates the connection strength W of the address in the connection strength memory 82 corresponding to the source address of the ignition node 11A.

[0272] (Step E29) As shown in Fig. 35, in step E29, pre spike 5B and post spike 5C merge in the time difference calculation circuit 3 in the time difference calculation circuit array 2 (see symbol F4). Due to the merger, spike 5C is discarded and the time difference Δt_BC is set in spike 5B. For example, the time difference calculation circuit 3 may discard post spike 5C if the source address set in pre spike 5B and the destination address set in post spike 5C match (both indicating the firing node 11B). In this way, post spike 5 may be discarded in the time difference calculation circuit 3 when the source address of post spike 5 matches the destination address of pre spike 5 and the destination address of post spike 5 matches the source address of pre spike 5. The same applies to the following explanations.

[0273] Also, the spike 5C generated in step E28 is sent from the firing node 11C to the time difference calculation circuit array 2.

[0274] In the input buffer 11a, due to the merging of spike 5 in step E28, the time difference Δt_AC between spikes 5A and 5C and the source address of spike 5A are obtained.

[0275] In the connection strength mechanism 8, the time difference Δt (Δt_BC) of the pair stored earliest in the buffer 80 is stored in a register 81 and is also transmitted to the firing mechanism 11c.

[0276] Furthermore, the connection strength mechanism 8 reads out the connection strength W of the firing node 11B from the connection strength memory 82 based on the source address of the pair that was stored first in the buffer 80. The read connection strength W is stored in the register 83 and is also transmitted to the firing mechanism 11c.

[0277] (Step E30) In step E30, the firing node 11C generates a spike 5C. The spike 5C merges with the spike 5A that was stored first in the input buffer 11a (see symbol F5). In addition, the time difference Δt_AC obtained in step E29 and the source address are stored in the buffer 80 of the connection strength mechanism 8.

[0278] The W update circuit 84 calculates the updated connection strength W based on the time difference Δt and the connection strength W input from the registers 81 and 83, and updates the connection strength W of the address in the connection strength memory 82 corresponding to the source address of the firing node 11B.

[0279] (Step E31) In step E31, the spike 5C generated in step E30 is sent from the firing node 11C to the time difference calculation circuit array 2. In the input buffer 11a, due to the merging of the spike 5 in step E30, the time difference Δt_AC between the spikes 5A and 5C and the source address of the spike 5A are obtained.

[0280] In the connection strength mechanism 8, the time difference Δt (Δt_AC) of the pair stored earliest in the buffer 80 is stored in a register 81 and transmitted to the firing mechanism 11c. In addition, the connection strength mechanism 8 reads out the connection strength W of the firing node 11A from the connection strength memory 82 based on the source address of the pair stored earliest in the buffer 80. The read connection strength W is stored in a register 83 and transmitted to the firing mechanism 11c.

[0281] (Step E32) 36, in step E32, the firing node 11C generates a spike 5C. The spike 5C merges with the spike 5A that was stored first in the input buffer 11a (see symbol F6). In addition, the time difference Δt_AC acquired in step E31 and the source address are stored in the buffer 80 of the connection strength mechanism 8.

[0282] Furthermore, spike 5B which joined together in the time difference calculation circuit array 2 in step E29 reaches the firing node 11C. The input buffer 11a acquires the time difference Δt_BC contained (set) in the spike 5B and the source address.

[0283] The W update circuit 84 calculates the updated connection strength W based on the time difference Δt and the connection strength W input from the registers 81 and 83, and updates the connection strength W of the address in the connection strength memory 82 corresponding to the source address of the firing node 11A.

[0284] (Step E33) In step E33, the input buffer 11a obtains the time difference Δt_AC between spikes 5A and 5C due to the merging of spike 5 in step E32, and the source address of spike 5A. Also, the time difference Δt_BC and the source address obtained in step E32 are stored in the buffer 80 of the connection strength mechanism 8.

[0285] (Steps E34 to E42) 36 to 39, in steps E34 to E42, processing is performed according to the same logic as the above-mentioned processing. For example, in steps E34, E36, E38, E40, and E42, spike 5C occurs in firing node 11C and merges with spike 5A (see symbols F7, F9 to F12). In these next steps, the time difference Δt_AC and the source address are obtained, and spike 5C is sent to the time difference calculation circuit array 2.

[0286] Also, for example, when spike 5B and spike 5C join together in the time difference calculation circuit array 2 (step E35: see symbol F8), spike 5C is discarded and spike 5B including the time difference Δt_BC is transmitted to the firing node 11C.

[0287] In the firing node 11C, when the input buffer 11a acquires the time difference Δt (Δt_AC, Δt_BC) and the source address, in the next step this information is stored in the buffer 80. In the next step, the time difference Δt is output from the buffer 80 to the register 81 and the firing mechanism 11c, and the coupling strength W corresponding to the source address is read from the coupling strength memory 82 and output to the register 83 and the firing mechanism 11c. In the next step, the W update circuit 84 updates the coupling strength W in the coupling strength memory 82 based on the time difference Δt and the coupling strength W read from the registers 81 and 83.

[0288] In the following explanation of steps E43 to E63, the explanation of the processing contents in the time difference calculation circuit array 2 and the firing node 11C based on the same logic as the above-mentioned processing will be omitted.

[0289] (Step E43) As shown in FIG. 39, in step E43, spike 5C reaches ignition node 11B. Step E43 shows how spike 5C is stored in input buffer 11a of ignition node 11B. The value of counter C of spike 5C stored in input buffer 11a of ignition node 11B is incremented at each step until it joins with spike 5B transmitted from ignition node 11B (expressed as "C=C+1"). The value of counter C of spike 5C in ignition node 11B is updated in the same manner in the following steps.

[0290] (Steps E44 to E46) As shown in Fig. 40, in step E44, the spike group 5C travels one hop toward the ignition node 11B. In step E45, the next spike 5C reaches the ignition node 11B. In step E46, the spike group 5C travels one hop toward the ignition node 11B.

[0291] (Step E47) As shown in Fig. 41, in step E47, the firing mechanism 11c of the firing node 11B generates a pre-spike 5B whose destination is the firing node 11C. The spike 5B merges with the earliest stored spike 5C among the spikes 5C stored in the input buffer 11a (see symbol F15). The spike 5C merged with the spike 5B is discarded. In addition, the time difference Δt_BC between the spikes 5B and 5C is calculated and set in the spike 5B.

[0292] (Step E48) In step E48, the spike 5B in which the time difference Δt_BC was set in step E47 is transmitted from the firing node 11B to the time difference calculation circuit array 2.

[0293] (Steps E49 to E59) As shown in Figures 41 and 42, in steps E49 to E59 (steps E51 to E59 are omitted), the spike 5B transmitted in step E48 propagates through the time difference calculation circuit array 2 and reaches the time difference calculation circuit 3 (router 4) immediately before the firing node 11C in step E59.

[0294] (Step E60) In step E60, the spike 5B transmitted in step E48 reaches the firing node 11C, and the time difference Δt_BC and the source address set in the spike 5B are acquired in the input buffer 11a.

[0295] (Steps E61 to E63) In steps E61 to E63 (steps E61 and E62 are omitted), the time difference calculation circuit array 2 and the ignition node 11C perform processing according to logic similar to that described above. In step E63, the input buffer 11a of the ignition node 11C is empty. On the other hand, in the ignition node 11B, the spike 5B has not been transmitted, and the received spike 5C is stored in the input buffer 11a.

[0296] [F] Other The technology according to the above-described embodiment can be modified and changed as follows.

[0297] For example, the initial values ​​of counters J and C set in spike 5 according to one embodiment are not limited to 0, and various values ​​may be used as long as they are commonly defined in NC1.

[0298] Furthermore, the order in which spikes 5 are stored in input buffer 11a shown in FIGS. 32 to 42 and the order in which time differences Δt are stored in buffer 80 are not limited to the order in which spikes 5 are received, and may be different from the order in which they are received.

[0299] Furthermore, the hardware configurations of the ignition node 11, the time difference calculation circuit 3, and the router 4 are not limited to the configurations exemplified in FIGS. 14 to 18, 24, and 27, and may be modified or changed as appropriate.

[0300] [G] Notes Regarding the above embodiment, the following supplementary notes are further disclosed.

[0301] (Appendix 1) A plurality of nodes generating spikes, each node including a counter for the duration of the spike and information indicating the source of the spike; a transmission array that connects the plurality of nodes to each other and forms a transmission path for the spikes; the transmission array includes a plurality of transmission circuits that transmit the spikes by one or more transmission circuits on a transmission path in response to the spikes; Each of the plurality of transmission circuits is updating the value of the counter for said spike when forwarding said spike; when detecting a merger of a first spike transmitted from a first node to a second node among the plurality of nodes and a second spike transmitted from the second node to the first node, setting a time difference calculated based on the counter values ​​of the first spike and the second spike in the first spike to be transferred; The second node, Identifying a time difference that is equal to or less than a first threshold among a plurality of time differences set in a plurality of spikes received from the transmission array; Accumulating the coupling strength between the node that is the source of the third spike to which the identified time difference is set and the second node; generating a fourth spike if the result of the cumulative sum exceeds a second threshold; A spike generating circuit is provided. Neuromorphic computing circuits.

[0302] (Appendix 2) the spike generating circuit updates the first threshold based on a time interval between the generation timing of the fourth spike and the generation timing of a fifth spike generated immediately before the fourth spike, and on the number of times the coupling strengths are accumulated during the time interval. 2. The neuromorphic computing circuit of claim 1.

[0303] (Appendix 3) The spike generating circuit comprises: a buffer that stores, for each of the plurality of spikes received from the transmission array, the time difference set in the spike and the coupling strength between the source node of the spike and the second node in association with each other; and a cumulative summation unit that, when the time difference read from the buffer is equal to or smaller than the first threshold, reads from the buffer the binding strengths stored in the buffer in association with the read time difference and accumulates the binding strengths. 3. The neuromorphic computing circuit of claim 1 or 2.

[0304] (Appendix 4) The second node, a coupling strength update circuit for updating a first coupling strength between the second node and the first node based on the time difference set in the first spike received from the transmitting array; 4. The neuromorphic computing circuit according to claim 1, wherein the first and second components are arranged in a first direction.

[0305] (Appendix 5) The connection strength update circuit includes: a memory that stores information indicating each of the plurality of nodes and a coupling strength between each of the plurality of nodes and the second node in association with each other; reading a first coupling strength from the memory based on information indicating the transmission source included in the first spike received from the transmission array; updating the first coupling strength stored in the memory based on the time difference set in the first spike and the first coupling strength read from the memory; An update circuit, 5. The neuromorphic computing circuit of claim 4.

[0306] (Appendix 6) the coupling strength update circuit transmits the time difference set in the first spike and the first coupling strength read from the memory to the spike generation circuit; 6. The neuromorphic computing circuit of claim 5.

[0307] (Appendix 7) each of the plurality of transmission circuits and each of the plurality of nodes calculates the time difference by subtracting the counter value of the first spike from the counter value of the second spike; 7. The neuromorphic computing circuit according to claim 1,

[0308] (Appendix 8) each of the plurality of transmission circuits and each of the plurality of nodes discards the second spike when detecting the merging and calculating the time difference; 8. The neuromorphic computing circuit according to any one of claims 1 to 7.

[0309] (Appendix 9) The transmission array arranges the plurality of transmission circuits in a two-dimensional or three-dimensional mesh shape, and forms the transmission path according to the spike by routing in the order of dimensions. 9. The neuromorphic computing circuit according to any one of claims 1 to 8.

[0310] (Appendix 10) A method for controlling a neuromorphic computing circuit including a plurality of nodes and a transmission array connecting the plurality of nodes to each other, comprising the steps of: Each of the plurality of nodes generates a spike including a counter relating to the duration of the spike and information indicating a source of the spike; Each of a plurality of transmission circuits provided in the transmission array for transferring the spike by one or more transmission circuits on a transmission path corresponding to the spike, updating the value of the counter for said spike when forwarding said spike; when detecting a merger of a first spike transmitted from a first node to a second node among the plurality of nodes and a second spike transmitted from the second node to the first node, setting a time difference calculated based on the counter values ​​of the first spike and the second spike in the first spike to be transferred; A spike generating circuit provided in the second node, Identifying a time difference that is equal to or less than a first threshold among a plurality of time differences set in a plurality of spikes received from the transmission array; Accumulating the coupling strength between the node that is the source of the third spike to which the identified time difference is set and the second node; generating a fourth spike if the result of the cumulative sum exceeds a second threshold; Control methods.

[0311] (Appendix 11) the spike generating circuit updates the first threshold based on a time interval between the generation timing of the fourth spike and the generation timing of a fifth spike generated immediately before the fourth spike, and on the number of times the coupling strength is accumulated during the time interval; 11. The control method of claim 10.

[0312] (Appendix 12) The spike generating circuit, For each of the plurality of spikes received from the transmission array, read out a time difference from a buffer that stores the time difference set in the spike and the coupling strength between the source node of the spike and the second node in association with each other; when the time difference read from the buffer is equal to or smaller than the first threshold, the connection strengths stored in the buffer in association with the read time difference are read from the buffer and accumulated by an accumulator; 12. The control method according to claim 10 or 11.

[0313] (Appendix 13) A coupling strength update circuit provided in the second node, updating a first coupling strength between the second node and the first node based on the time difference set in the first spike received from the transmitting array; The control method according to any one of Supplementary Note 10 to Supplementary Note 12.

[0314] (Appendix 14) The connection strength update circuit, reading out a first coupling strength from a memory that stores information indicating each of the plurality of nodes and a coupling strength between each of the plurality of nodes and the second node in association with each other, based on information indicating the transmission source included in the first spike received from the transmission array; updating the first coupling strength stored in the memory based on the time difference set in the first spike and the first coupling strength read from the memory; 14. The control method of claim 13.

[0315] (Appendix 15) the coupling strength update circuit transmits the time difference set in the first spike and the first coupling strength read from the memory to the spike generation circuit; 15. The control method of claim 14.

[0316] (Appendix 16) each of the plurality of transmission circuits and each of the plurality of nodes calculates the time difference by subtracting the counter value of the first spike from the counter value of the second spike; The control method according to any one of Supplementary notes 10 to 15.

[0317] (Appendix 17) discarding the second spike when each of the plurality of transmission circuits and each of the plurality of nodes detects the merging and calculates the time difference; The control method according to any one of Supplementary notes 10 to 16.

[0318] (Appendix 18) The transmission array arranges the plurality of transmission circuits in a two-dimensional or three-dimensional mesh shape, and forms the transmission path according to the spike by routing in the order of dimensions. The control method according to any one of Supplementary notes 10 to 17. [Explanation of symbols]

[0319] 1 Neuromorphic Computing Hardware (NC) 10 Network Model 11, 11A~11C Ignition nodes 11a Input Buffer 11b,8 Bond strength mechanism 11c,7 Firing mechanism 11d,80 buffer 11e,82 Joint Strength Memory 11f,70,70a,70b Circular buffer 2. Time difference calculation circuit array 3 Time difference calculation circuit 31 Comparator Array 31a Comparator 32 Selection value generation circuit 33 Selection circuit 34 Calculation section 4. Router 41, 41a~41e FIFO 42 Crossbar 43 Control Unit 44 Mediation Department 45, 45a~45e Output section 5,5a~5n,5x~5z,5A~5C,5X~5Z Spike 6 Chips 71 Buffer control circuit 72,75 Comparator 73, 77a, 77b, 81, 83 Registers 74 Accumulator 76a,76b Counter 78 Adder 84W update circuit

Claims

1. A plurality of nodes generating spikes, each node including a counter for the duration of the spike and information indicating the source of the spike; a transmission array that connects the plurality of nodes to each other and forms a transmission path for the spikes; the transmission array includes a plurality of transmission circuits that transmit the spikes by one or more transmission circuits on a transmission path in response to the spikes; Each of the plurality of transmission circuits is updating the value of the counter for said spike when forwarding said spike; when detecting a merger of a first spike transmitted from a first node to a second node among the plurality of nodes and a second spike transmitted from the second node to the first node, a time difference calculated based on the values ​​of the counters of the first spike and the second spike is set in the first spike to be transferred; The second node is Identifying a time difference that is equal to or less than a first threshold among a plurality of time differences set in a plurality of spikes received from the transmission array; Accumulating the coupling strength between the node that is the source of the third spike to which the identified time difference is set and the second node; generating a fourth spike if the result of the cumulative sum exceeds a second threshold; A spike generating circuit is provided. Neuromorphic computing circuits.

2. the spike generating circuit updates the first threshold based on a time interval between the generation timing of the fourth spike and the generation timing of a fifth spike generated immediately before the fourth spike, and on the number of times the coupling strengths are accumulated during the time interval. The neuromorphic computing circuit of claim 1 .

3. The spike generating circuit comprises: a buffer that stores, for each of the plurality of spikes received from the transmission array, the time difference set in the spike and the coupling strength between the source node of the spike and the second node in association with each other; a cumulative summation unit that, when the time difference read from the buffer is equal to or smaller than the first threshold, reads from the buffer the binding strengths stored in the buffer in association with the read time difference and accumulates the binding strengths.

3. A neuromorphic computing circuit according to claim 1 or 2.

4. The second node is a coupling strength update circuit for updating a first coupling strength between the second node and the first node based on the time difference set in the first spike received from the transmit array.

3. A neuromorphic computing circuit according to claim 1 or 2.

5. The connection strength update circuit includes: a memory that stores information indicating each of the plurality of nodes and a coupling strength between each of the plurality of nodes and the second node in association with each other; reading a first coupling strength from the memory based on information indicating the transmission source included in the first spike received from the transmission array; updating the first coupling strength stored in the memory based on the time difference set in the first spike and the first coupling strength read from the memory; An update circuit, The neuromorphic computing circuit of claim 4.

6. the coupling strength update circuit transmits the time difference set in the first spike and the first coupling strength read from the memory to the spike generation circuit; The neuromorphic computing circuit of claim 5 .

7. A method for controlling a neuromorphic computing circuit including a plurality of nodes and a transmission array connecting the plurality of nodes to each other, comprising the steps of: Each of the plurality of nodes generates a spike including a counter relating to the duration of the spike and information indicating a source of the spike; Each of a plurality of transmission circuits provided in the transmission array for transferring the spike by one or more transmission circuits on a transmission path corresponding to the spike, updating the value of the counter for said spike when forwarding said spike; when detecting a merger of a first spike transmitted from a first node to a second node among the plurality of nodes and a second spike transmitted from the second node to the first node, a time difference calculated based on the values ​​of the counters of the first spike and the second spike is set in the first spike to be transferred; A spike generating circuit provided at the second node, Identifying a time difference that is equal to or less than a first threshold among a plurality of time differences set in a plurality of spikes received from the transmission array; Accumulating the coupling strength between the node that is the source of the third spike to which the identified time difference is set and the second node; generating a fourth spike if the result of the cumulative sum exceeds a second threshold; Control methods.

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