Control circuit and interleave power source

Abstract

To provide a control circuit and an interleave power source in which power factor degradation in the interleave power source can be prevented and overload operation of a main converter can be prevented.SOLUTION: A control circuit 100a, 100b includes an interleave signal input unit 110, a critical point detection unit 120, an ON width correction unit 130, an interleave control unit 140, and a drive unit 150. The ON width correction unit 130 outputs ON width information corrected to adjust an ON width of a control signal for controlling the ON / OFF of a slave switch to the interleave control unit 140 on the basis of interleave input signal information and critical point detection information. The interleave control unit 140 outputs a control signal adjusted on the basis of the critical point detection information and the corrected ON width information to the drive unit 150. The drive unit 150 turns ON / OFF a slave switch Q2, Q3 on the basis of the control signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a control circuit and an interleaved power supply. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there has been known an interleaved power supply that controls a rectifier circuit (eg, a PFC circuit) by operating a multi-stage converter in a critical state (see, for example, Patent Document 1).

[0003] For example, an interleaved power supply 900 according to the background art as follows is conceivable (see FIG. 13). That is, the interleaved power supply 900 according to the background art includes a rectifier circuit 910 and a multi-stage converter (a main converter 920 and sub converters 930 and 940). The interleaved power supply 900 can output a predetermined output voltage Vo by controlling the multi-stage converters to operate in a critical state.

[0004] The main converter 920 includes an inductor (PFC choke) L1, a main switch Q1 that performs switching operation, a diode D1, and a main switch control circuit 800 that controls the main converter 920. The main switch control circuit 800 outputs an interleaved signal to the subsequent secondary converter 930 via an IL_OUT terminal.

[0005] The slave converter 930 includes an inductor (PFC choke) L2, a slave switch Q2 that switches with a phase difference relative to the switching operation of the main switch Q1, a diode D2, and a control circuit 700a that controls the slave converter 930. The slave converter 930 receives an interleaved signal from the main converter 920 and outputs an interleaved signal to the slave converter 940.

[0006] The slave converter 940 includes an inductor (PFC choke) L3, a slave switch Q3 that switches with a phase difference relative to the switching operation of the main switch Q1, a diode D3, and a control circuit 700b that controls the slave converter 940. The interleaved signal from the slave converter 930 is input to the slave converter 940.

[0007] In each converter of the interleaved power supply 900 according to the background art, the critical point of the input current of the slave converter is detected by detecting the choke current of the inductor using an auxiliary winding arranged opposite each inductor, and critical operation is performed by turning on the main switch or the slave switch. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 5584826 Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the interleaved power supply 900 according to the background art, there is a risk that the on-periods of the slave switches Q2 and Q3 may deviate from their original on-periods (on-periods when the inductance values ​​are the same) due to variations in the inductance of the PFC chokes of each converter, which may result in a decrease in the power factor of the interleaved power supply or overload operation of the main converter.

[0010] Specifically, it is as follows. That is, when the inductance value of the inductor L1 of the main converter (hereinafter sometimes referred to as the leader) is equal to the inductance value of the inductor L2 (L3) of the slave converter (hereinafter sometimes referred to as the follower), as shown in Fig. 14, the waveform of the current (choke current (F)) flowing through the inductor of the follower becomes the same as the waveform of the current (choke current (L)) flowing through the inductor of the leader, and the resonant waveform of the drain voltage VDS (L) of the main switch Q1 becomes approximately the same as the resonant waveform of the drain voltage VDS (F) of the slave switches Q2, Q3. As a result, the ON width of the main switch Q1 (see the control signal OUT (L) of the main switch Q1) and the ON width of the slave switches Q2, Q3 (see the control signal OUT (F) of the slave switches Q2, Q3) become the same ON width, and the slave switches Q2, Q3 can perform critical operation while maintaining a certain phase difference from Q1, so that the timing at which the slave switches Q2, Q3 turn on does not deviate from the original timing.

[0011] On the other hand, if the inductance value of the inductor L1 of the main converter differs from the inductance value of the inductor L2 (L3) of the sub converter, the waveform of the current (choke current (F)) flowing through the inductor of the follower will be different from the waveform of the current (choke current (L)) flowing through the inductor of the leader, and the resonant period of the drain voltage VDS(F) of the sub switches Q2 and Q3 may differ from the resonant period of the drain voltage VDS(L) of the main switch Q1, as shown in Fig. 15. For example, in the case of Fig. 15, the resonant period of the drain voltage VDS(F) of the sub switches Q2 and Q3 becomes shorter, and the sub switches Q2 and Q3 cannot perform critical operation while maintaining a certain phase difference from the main switch Q1, so that the on-period of the sub switches Q2 and Q3 may deviate from the original on-period (the on-period when the inductance value of the main converter and the inductance value of the sub converter are the same).

[0012] If the on-timings of the slave switches Q2 and Q3 deviate from their original on-timings, the deviation will become larger with each cycle, as shown in Figure 5, and eventually the interleave detection period will be exceeded and the mask period of the main switch Q1 will be entered, causing a valley skip or preventing the slave switch Q2 from turning on until the restart operation occurs. In this case, there is a risk of a decrease in the power factor of the interleaved power supply or an overload operation of the main converter.

[0013] Therefore, the present invention has been made to solve the above problems, and has an object to provide a control circuit that is less likely to cause a drop in the power factor of an interleaved power supply or an overload operation of a main converter, and also to provide an interleaved power supply having such a control circuit. [Means for solving the problem]

[0014] A control circuit of the present invention includes a main converter having a main switch that performs a switching operation, and a slave converter having a slave switch that performs switching in a state having a phase difference with respect to the switching operation of the main switch, and is a control circuit for controlling the switching operation of the slave switch for an interleaved power supply that forms a master-slave relationship between the main converter and the slave converter. The control circuit includes an interleave signal input unit, a critical point detection unit, an on-width correction unit, an interleave control unit, and a drive unit. The interleave signal input unit obtains an interleave input signal input from the main converter or the slave converter in a previous stage, and generates an interleave signal based on the interleave input signal. The interleave input signal is output to the on-width correction unit, the critical point detection unit detects a critical point of a current flowing through an inductor of the slave converter to generate critical point detection information, and outputs the critical point detection information to the on-width correction unit and the interleave control unit, the on-width correction unit outputs on-width information to the interleave control unit for adjusting the on-width of a control signal for controlling the on-off of the slave switch based on the interleave input signal information and the critical point detection information, the interleave control unit outputs the control signal whose on-width has been adjusted based on the critical point detection information and the on-width information to the drive unit, and the drive unit turns the slave switch on and off based on the control signal.

[0015] The interleaved power supply of the present invention is characterized by comprising the control circuit of the present invention. Effect of the Invention

[0016] According to the control circuit and switching power supply of the present invention, the on-width correction unit outputs corrected on-width information to the interleave control unit so as to adjust the on-width of the control signal that controls the on-off of the slave switch based on the interleave input signal information and the critical point detection information, so that even if the on-period of the slave switch deviates from its original on-period due to variations in the inductance values ​​of the inductors in each converter, the deviation of the on-period of the slave switch from its original on-period can be suppressed to within the interleave detection period. As a result, it is possible to prevent a decrease in the power factor of the interleaved power supply and to prevent an overload operation of the main converter. [Brief description of the drawings]

[0017] [Figure 1] 1 is a circuit diagram showing an interleaved power supply 1 according to an embodiment. [Diagram 2] FIG. 2 is a block diagram shown for explaining control circuits 100a and 100b according to the embodiment. [Diagram 3] 3 is a timing chart showing the case where the timing at which the interleaved input signal information turns off is the same as the timing at which the critical point detection information turns off. In Fig. 3, OUT(L) indicates the voltage waveform of the output terminal OUT of the main converter 20, IL_IN(F) indicates the waveform of the interleaved input signal of the sub converter 30, VDS(F) indicates the waveform of the drain voltage of the sub switch Q2, ZC(F) indicates the voltage waveform of the ZC terminal, CLK indicates the voltage waveform of the clock signal, COUNTER indicates the voltage waveform of the counter, and OUT(F) indicates the voltage waveform of the output terminal OUT of the sub converter 30 (same in Figs. 4 to 11). [Figure 4] 13 is a diagram showing a timing chart when the timing at which the interleaved input signal information turns off is later than the timing at which the critical point detection information turns off. FIG. [Diagram 5] 13 is a timing chart showing a case where the ON width is not corrected in a case where the timing at which the interleaved input signal information turns off is later than the timing at which the critical point detection information turns off. [Figure 6]13 is a timing chart showing a case where the ON width is corrected in a case where the timing at which the interleaved input signal information turns off is later than the timing at which the critical point detection information turns off. [Figure 7] 13 is a diagram showing a timing chart when the timing at which the interleaved input signal information turns off is earlier than the timing at which the critical point detection information turns off. FIG. [Figure 8] 13 is a timing chart showing a case where the ON width is not corrected in a case where the timing at which the interleaved input signal information turns off is earlier than the timing at which the critical point detection information turns off. [Figure 9] 13 is a timing chart showing a case where the ON width is corrected in a case where the timing at which the interleaved input signal information turns off is earlier than the timing at which the critical point detection information turns off. [Figure 10] 13 is a timing chart showing a case where the timing at which the interleaved input signal information turns off is later than the timing at which the critical point detection information turns off in the case of Modification 1 in which the correction factor is set to three. [Figure 11] 13 is a timing chart showing a case where the timing at which the interleaved input signal information turns off is earlier than the timing at which the critical point detection information turns off in the case of Modification 1 in which the correction factor is set to three. [Figure 12] FIG. 11 is a circuit diagram showing an interleaved power supply 2 according to a second modification. [Figure 13] FIG. 9 is a circuit diagram showing an interleaved power supply 900 according to the background art. [Figure 14] 13 is a waveform diagram when the inductance of the inductor L1 of the main converter 920 and the inductance of the inductor L2 of the secondary converter 930 are equal. [Figure 15] 13 is a waveform diagram when the inductance of the inductor L1 of the main converter 920 is different from the inductance of the inductor L2 of the secondary converter 930. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The control circuit and the interleaved power supply of the present invention will be described below based on the embodiment shown in the drawings. Note that the embodiment described below does not limit the invention according to the claims. Also, not all of the elements and their combinations described in the embodiment are necessarily essential to the solution of the present invention.

[0019] [Embodiment] 1. Configuration of the interleaved power supply 1 according to the embodiment The interleaved power supply 1 according to the embodiment is an interleaved power supply in which a plurality of converters are connected in multiple stages. As shown in Fig. 1, the interleaved power supply 1 includes a rectifier circuit 10, a main converter 20 having a main switch Q1 that performs switching operation, sub converters 30 and 40 having sub switches Q2 and Q3 that perform switching in a state having a phase difference with respect to the switching operation of the main switch Q1, and an output capacitor C3, and both the main converter 20 and the sub converters 30 and 40 perform current-critical operation.

[0020] In the interleaved power supply 1, a main converter 20 and sub converters 30 and 40 are connected in parallel between a rectifier circuit 10 and an output capacitor C3. The main converter 20 and the sub converters 30 and 40 form a main-sub converter relationship.

[0021] The rectifier circuit 10 includes a bridge diode BD that, for example, full-wave rectifies the AC current of a commercial power source to make it a pulsating current, and a smoothing capacitor C2.

[0022] (1) Configuration of main converter 20 The main converter 20 (leader) includes an inductor L1, an auxiliary winding L4, a main switch Q1, a diode D1, and a main switch control circuit 200 (leader IC), and the inductor L1, the main switch Q1, and the diode D1 form a boost chopper circuit.

[0023] In the embodiment, the main switch Q1 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but may be an IGBT or other suitable switch element. An appropriate inductor may be used as the inductor L1, and an appropriate diode may be used as the diode D1. The same applies to the slave switches Q2 and Q3, the inductors L2 and L3, and the diodes D2 and D3 described later.

[0024] The main switch control circuit 200 outputs a control signal for controlling the main switch Q1 to the gate electrode of the main switch Q1, and also outputs an interleave signal to the slave converter 30. The main switch control circuit 200 has eight terminals: a Vcc terminal, an OUT terminal, a GND terminal, a ZC terminal, an OCL terminal, an IL_OUT terminal, a COMP terminal, and an FB terminal.

[0025] The Vcc terminal is connected to the external power supply Vcc and receives power from the external power supply Vcc. The OUT terminal is connected to the gate electrode of the main switch Q1 and outputs a signal to the gate electrode that controls the on / off of the main switch Q1. The GND terminal is connected to the reference potential.

[0026] The ZC terminal is connected to the auxiliary winding L4 via the resistor R1, and detects the choke current flowing through the inductor L1.

[0027] The OCL terminal is connected to a resistor R3 and a capacitor C7, and is connected to the midpoint between the source electrode of the main switch Q1 and the resistor R2 via the resistor R3. The OCL terminal is used to monitor whether an overcurrent flows through the main switch Q1 by monitoring the voltage determined by the resistor R2. The IL_OUT terminal is connected to the IL_IN terminal of the control circuit 100a (follower IC).

[0028] The COMP terminal is an output terminal of a feedback error amplifier connected to a capacitor C6. The main switch control circuit 200 uses the voltage of the COMP terminal to determine the ON width of the main switch Q1 and control the output voltage. The FB terminal is connected to a capacitor C5 and resistors R4 and R5. The voltage obtained by dividing the output voltage by resistors R4 and R5 is input to the FB terminal.

[0029] (2) Configuration of the slave converter 30 and the control circuit 100a The slave converter 30 includes an inductor L2, an auxiliary winding L5, a slave switch Q2, a diode D2, and a control circuit 100a. The inductor L2, the slave switch Q2, and the diode D2 form a boost chopper circuit.

[0030] The configuration is similar to that of the main converter 20, except that a control circuit 100a is provided instead of the main switch control circuit 200.

[0031] The control circuit 100a has an IL_IN terminal instead of the FB terminal of the main switch control circuit 200, an IL_OUT terminal instead of the COMP terminal, and a VIS terminal that is not connected to anything instead of the IL_OUT terminal.

[0032] The IL_IN terminal is a terminal for inputting an interleave signal from the main switch control circuit 200. The IL_IN terminal is connected to the IL_OUT terminal of the main switch control circuit 200 via a resistor R9.

[0033] The control circuit 100a is a control circuit that controls the switching operation of the slave switch Q2. As shown in FIG. 2, the control circuit 100a includes an interleave signal input unit 110, a mask period setting unit 112, a critical point detection unit 120, an on-width correction unit 130, a clock 132, a counter 134, an interleave control unit 140, a drive unit 150, and an interleave signal generation unit 160.

[0034] The interleaved signal input unit 110 acquires an interleaved input signal input from the previous converter (main converter 20) via the IL_IN terminal, and outputs interleaved input signal information generated based on the interleaved input signal to the on-width correction unit 130 and to the mask period setting unit 112. The interleaved input signal and the interleaved input signal information are synchronized.

[0035] The mask period setting unit 112 outputs a mask period signal to the interleave control unit 140, which prohibits the output of a control signal for turning on the slave switch Q2 to the drive unit 150 for a predetermined period after the interleave input signal is turned on based on the interleave input signal information.

[0036] The critical point detection unit 120 detects a critical point of a current (choke current) flowing through the inductor L2 of the secondary converter 30, generates critical point detection information, and outputs the critical point detection information to the on-width correction unit 130 and also outputs it as an on-trigger to the interleave control unit 140. The critical point detection unit 120 is connected to the auxiliary winding L5 via the ZC terminal and resistor R6, and detects the critical point of the choke current of the inductor L2 using the auxiliary winding L5.

[0037] The on-width correction unit 130 outputs corrected on-width information (from on-width information that is the original on-width) to the interleave control unit 140 so as to adjust the on-width of the control signal that controls the on-off of the slave switch Q2 based on the interleave input signal information and the critical point detection information. Specifically, the on-width information is corrected by adjusting the up-counting and down-counting timing of the counter 134 and the frequency of the clock signal CLK of the clock 132 based on the interleave input signal information and the critical point detection information, and the on-width of the control signal of the slave switch Q2 and the interleave output signal are adjusted. A method of correcting the on-width will be described later.

[0038] The interleave control unit 140 outputs a control signal to the drive unit 150 for turning on and off the slave switch Q2 at a timing adjusted using the counter 134 and the clock 132 based on the critical point detection information and the corrected on-width information. Also, the interleave control unit 140 outputs interleave signal output information synchronized with the control signal to the interleave signal generation unit 160.

[0039] The driver 150 outputs a switching pulse for turning on and off the slave switch Q2 based on a control signal from the interleave controller 140 to the gate electrode of the slave switch Q2 via an output terminal OUT.

[0040] The interleave signal generating section 160 generates an interleave signal based on the interleave signal output information from the interleave control section 140, and outputs the interleave signal to the IL_IN terminal of the control circuit 100b via the IL_OUT terminal.

[0041] The clock 132 repeatedly turns the clock signal on and off at a predetermined frequency A. As described later, the frequency is temporarily changed by the on-width correction unit 130, and the frequency is returned to the original frequency A after repeatedly turning the clock signal on and off at the changed frequency for a predetermined period.

[0042] The counter 134 counts up in accordance with the cycle of the clock signal from the timing when the interleave input signal turns on, and counts down in accordance with the cycle of the clock signal from the timing when the interleave input signal turns off. The on-width information is corrected so that the output voltage turns off when the count reaches 0.

[0043] (3) Configuration of the Slave Converter 40 and Control Circuit 100b The slave converter 40 includes an inductor L3, an auxiliary winding L6, a slave switch Q3, a diode D3, and a control circuit 100b, and the inductor L3, the slave switch Q3, and the diode D3 form a boost chopper circuit. The slave converter 40 and the control circuit 100b have the same configuration as the slave converter 30 and the control circuit 100a, except that the IL_OUT terminal that outputs the interleaved signal is not connected.

[0044] 2. Operation of the interleaved power supply 1 according to the embodiment In the interleaved power supply 1 according to the embodiment, a critical point of the current (choke current) flowing through the inductors L1, L2, and L3 of each converter is detected. Each converter controls the on / off of the main switch (sub switch) based on the critical point of the input current. Furthermore, the main converter 20 outputs an interleaved signal to the sub converter 30 based on a control signal that controls the on / off of the main switch Q1.

[0045] The slave converter 30 corrects the on-width of the switching operation of the slave switch Q2 based on the interleaved input signal (interleaved input signal information) input from the main converter 20 to the slave converter 30 and the critical point detection information detected based on the choke current of the inductor L2, and performs the switching operation of the slave switch Q2.

[0046] Then, the ON width correction unit 130 compares the timing when the interleave input signal information turns off with the timing when the critical point detection information turns off, and outputs the corrected ON width information to the interleave control unit 140 so as to correct the ON width of the control signal. The operation of the control circuit 100a (follower IC) of the slave converter 30 will be described below with reference to Figs. 3 to 11. For ease of explanation, the case where only the slave converter 30 is connected as the slave converter will be described as an example.

[0047] A mask period set by the mask period setting unit 112 is provided for a predetermined period from the timing when the interleaved input signal information is turned on, and the control signal OUT is controlled not to be turned on even if a critical point is detected during this period. Therefore, if a critical point is detected during the mask period and the control signal OUT is not turned on, the control signal OUT will be turned on after waiting for the next critical point detection or after the restart period set by the IC has elapsed (see "correction period" in FIG. 3).

[0048] 3 and 4, "on-width correction (widening on-width)" indicates the on-width of the main switch Q1, and "on-width correction (narrowing on-width)" indicates the original on-width of the slave switch Q2. If the timing at which the drain voltage VDS(F) and the critical point detection information ZC(F) turn off is within the range of "on-width correction (widening on-width)," the on-width of the slave switch Q2 is widened, and if it is within the range of "on-width correction (narrowing on-width)," the on-width of the slave switch Q2 is narrowed.

[0049] That is, in the interleaved power supply 1 according to the embodiment, the ON width of the control signal OUT is corrected so that the ON timing of the control signal OUT does not overlap with the mask period.

[0050] (1) When the timing at which the interleave input signal information turns off is the same as the timing at which the critical point detection information turns off In this case, the inductance value of the inductor L1 of the main switch Q1 is approximately the same as the inductance value of the inductor L2 of the sub switch Q2. As shown in Fig. 3, when the interleaved input signal IL_IN(F) turns on, the drain voltage VDS(F) of the sub switch Q2 and the critical point detection information ZC(F), which is the voltage of the ZC terminal for detecting the critical point, turn on and start counting up (see "Counter" in Fig. 3). The counter 134 counts up at the rising edge of the clock signal CLK.

[0051] Then, at the same timing as the interleave input signal IL_IN(F) turns off, the drain voltage VDS(F) of the slave switch Q2 and the critical point detection information ZC(F) turn off. At this time, the counter 134 stops counting up and starts counting down. At this time, the control signal OUT(F) and the interleave signal output information (not shown) synchronized with the control signal OUT(F) are turned on.

[0052] Then, the switch Q2 counts down by the same number of counts as the number of times it counted up (20 counts in FIG. 3), and turns off the control signal OUT(F) and the interleave signal output information when the counter reaches 0. The number of times it counted up corresponds to the on-width of the main switch Q1, and since the control signal OUT(F) is turned on for the same count, the slave switch Q2 is also turned on for the same on-width as the main switch Q1.

[0053] (2) The timing when the interleave input signal information turns off is later than the timing when the critical point detection information turns off. In this case, the inductance value of the inductor L1 of the main switch Q1 is different from the inductance value of the inductor L2 of the slave switch Q2. The on-width correction unit 130 outputs, to the interleave control unit 140, on-width information that is corrected to lengthen the on-width of the interleave input signal information as on-width information.

[0054] 4, the counter 134 starts counting up when the interleave input signal IL_IN(F) turns on. This is the same as in the above case (1). On the other hand, the drain voltage VDS(F) of the slave switch Q2 and the critical point detection information ZC(F) turn on earlier than the interleave input signal IL_IN(F) turns on (not shown).

[0055] Then, at the timing when the drain voltage VDS(F) of the slave switch Q2 and the critical point detection information ZC(F) are turned off, the control signal OUT(F) and the interleave signal output information (not shown) synchronized with the control signal OUT(F) are turned on.

[0056] Also, the frequency of the clock signal CLK of the clock 132 is lowered by a predetermined number of times among the number of times of up-counting in response to a signal from the ON width correction unit 130 to reduce the number of times of up-counting. In other words, the frequency of the clock signal CLK of the clock 132 is lowered to reduce the number of times of up-counting during the period from the timing when the critical point detection information ZC(F) turns off to the timing when the interleave input signal information IL_IN(F) turns off.

[0057] The frequency of the clock signal CLK is set to frequency B, which is determined by multiplying frequency A of the normal clock signal CLK by the reciprocal of a predetermined on-width correction rate. In the embodiment, for example, since the on-width correction rate is doubled, frequency B is 1 / 2 times the original frequency A (the period is doubled).

[0058] In the case of Fig. 4, the timing at which the drain voltage VDS(F) and critical point detection information ZC(F) of the slave switch Q2 turn off is when the up-count reaches 10 counts after the interleave input signal IL_IN(F) turns on. From this timing to the timing at which the interleave input signal information IL_IN(F) turns off, the frequency of the clock signal CLK becomes 1 / 2 the original frequency A, and the up-count is increased by 5 counts, half of the number in the case of (1). In other words, when the up-count reaches 15 counts, the down-count starts. At this time, the slave switch Q2 has an on width of 10 counts when the clock signal CLK is counted at the original frequency A.

[0059] Then, when the interleave input signal IL_IN(F) turns off, the count-up stops and the count-down starts. At this time, the frequency of the clock signal CLK is returned to the original frequency A. Then, the count-down is performed 15 times.

[0060] Then, the control signal OUT(F) and the interleave signal output information (not shown) are turned off when the counter reaches 0. The control signal OUT of the slave switch Q2 has an on width equivalent to 25 times when the clock signal CLK is counted at the original frequency A, and the on width of the slave switch Q2 is wider than the original on width.

[0061] In this way, when the timing at which the interleave input signal information IL_IN(F) turns off is later than the timing at which the critical point detection information ZC(F) turns off, the on-width correction unit 130 outputs corrected on-width information to the interleave control unit 140 to lengthen the on-width of the control signal OUT. Since the on-width of the control signal OUT becomes longer, the on-width of the slave switch Q2 becomes longer compared to the on-width of the main switch Q1.

[0062] If the on-width correction of the slave switch Q2 is not performed, as shown in Fig. 5, the timing at which the interleaved input signal IL_IN turns off will be later than the timing at which the drain voltage VDS of the slave switch Q2 and the voltage of the ZC terminal that detects the critical point turn off, so the on-timing of the slave switch Q2 (see the waveform of the control signal OUT in Fig. 5) will be earlier every cycle. If the on-timing of the slave switch Q2 falls within the mask period of the main switch Q1, the slave switch Q2 will not be able to turn on. In this case, the slave switch Q2 will wait until the next critical point is detected or will turn on after the restart period set by the IC has elapsed, creating a period in which the follower does not operate for a while, resulting in a drop in the power factor.

[0063] In contrast, in the control circuit 100a according to the embodiment, the ON width of the slave switch Q2 is widened so that the ON timing of the slave switch Q2 does not need to be longer than a predetermined value, so the follower can operate continuously and the power factor does not decrease (see OUT(F) in FIG. 6).

[0064] (3) The timing when the interleave input signal turns off is earlier than the timing when the critical point detection information turns off. In this case, the inductance value of the inductor L1 of the main switch Q1 is different from the inductance value of the inductor L2 of the slave switch Q2. The on-width correction unit 130 outputs to the interleave control unit 140 on-width information corrected to shorten the on-width of the control signal OUT(F) based on the interleave input signal information IL_IN(F) and the critical point detection information ZC(F).

[0065] 7, similarly to the above case (1), the counter 134 starts counting up when the interleaved input signal IL_IN(F) turns on. At this time, the frequency of the clock signal CLK is a predetermined frequency A. On the other hand, the timing when the drain voltage VDS(F) of the slave switch Q2 and the critical point detection information ZC(F) turn on is later than the timing when the interleaved input signal IL_IN(F) turns on.

[0066] Then, at the same timing when the interleaved input signal IL_IN(F) turns off, the count-up stops and the count-down starts. At this time, since the critical point detection information ZC(F) is not turned off, the control signal OUT(F) of the slave switch Q2 is not turned on.

[0067] Then, the frequency of the clock signal CLK is lowered a predetermined number of times (five times in this embodiment) out of the number of times the down-count is performed, thereby reducing the number of times the down-count is performed. In other words, the frequency of the clock signal CLK is lowered to reduce the number of times the down-count is performed during the period from the timing when the interleave input signal information IL_IN(F) turns off to the timing when the critical point detection information ZC(F) turns off.

[0068] The frequency of the clock signal CLK is set to frequency B, which is determined by multiplying frequency A of the normal clock signal CLK by the reciprocal of a predetermined on-width correction rate. In the embodiment, for example, since the on-width correction rate is doubled, frequency B has a period twice that of the original frequency A.

[0069] Therefore, down counting is performed more slowly than usual by 5 counts until the timing when the drain voltage VDS(F) of the slave switch Q2 and the critical point detection information ZC(F) turn off.

[0070] Then, the control signal OUT(F) and the interleave signal output information (not shown) are turned on at the timing when the drain voltage VDS(F) of the slave switch Q2 and the critical point detection information ZC(F) are turned off. From that point, the counter counts down the remaining number of times (15 times), and when the counter reaches 0, the control signal OUT(F) is turned off.

[0071] In this way, when the timing at which the interleave input signal information turns off is earlier than the timing at which the critical point detection information turns off, the on-width correction unit 130 outputs corrected on-width information to the interleave control unit 140 to shorten the on-width of the control signal OUT. Since the on-width of the control signal OUT becomes shorter, the on-width of the slave switch Q2 becomes shorter compared to the on-width of the main switch Q1.

[0072] If the on-width correction of the slave switch Q2 is not performed, as shown in Fig. 8, the timing at which the interleaved input signal IL_IN(F) turns off is earlier than the timing at which the drain voltage VDS(F) and the critical point detection information ZC(F) of the slave switch Q2 turn off, so the on-timing of the slave switch Q2 (see the waveform of the control signal OUT in Fig. 8) becomes later every cycle. Then, when the on-timing of the slave switch Q2 falls within the mask period of the main switch Q1 in the next cycle, the slave switch Q2 cannot be turned on. In this case, the slave switch Q2 will wait until the next critical point is detected or will turn on after the restart period set by the IC has elapsed, creating a period in which the follower does not operate for a while, resulting in a drop in the power factor.

[0073] In contrast, in the control circuit 100a according to the embodiment, even if the ON period of the slave switch Q2 deviates from the original ON period (the ON period when the inductance value is the same), the deviation of the ON timing of the slave switch Q2 can be suppressed within the interleave detection period (the period excluding the mask period) as shown in Fig. 9. Since the follower can operate continuously, the power factor does not decrease (see OUT(F) in Fig. 9).

[0074] (4) Regarding the slave converter 40 and the control circuit 100b The slave converter 40 and the control circuit 100b are the same as those of the slave converter 30 and the control circuit 100a, except that the interleaved input signal is output from the slave converter 30. In Figs. 3 to 9, the case of two stages of converters has been described as an example, but in the case of three stages, an interleaved signal synchronized with the control signal OUT(F) of the slave switch Q2, not the main switch Q1, is input, so that each of the three converters can be turned on for a predetermined period (for example, 120 degrees each). In this way, an interleaved power supply suitable for interleaving multiple stages of converters in parallel is provided.

[0075] 3. Effects of the control circuits 100a and 100b and the interleaved power supply 1 according to the embodiment According to the control circuits 100a and 100b and the interleaved power supply 1 of the embodiment, the on-width correction unit 130 outputs corrected on-width information to the interleave control unit 140 so as to adjust the on-width of the control signal OUT(F) that controls the on-off of the slave switches Q2 and Q3 based on the interleave input signal information IL_IN(F) and the critical point detection information ZC(F), so that even if the on-periods of the slave switches Q2 and Q3 deviate from their original on-periods due to variations in the inductance values ​​of the inductors L1, L2, and L3 of the converters, the deviation of the on-periods of the slave switches Q2 and Q3 from their original on-periods can be suppressed to within the interleave detection period. As a result, it is possible to prevent a decrease in the power factor of the interleaved power supply and prevent an overload operation of the main converter.

[0076] Incidentally, it is also possible to adjust the phase shift by transmitting the off timing from the main converter 20 to the sub converters 30 and 40. In this case, however, a terminal for transmitting the off timing to the control circuit of the main converter 20 is required, which increases the number of terminals. This may result in problems such as an increase in size or the need for design changes.

[0077] In contrast, the control circuits 100a, 100b and the interleaved power supply 1 according to the embodiment have the above-mentioned configuration, and therefore the ON widths of the slave switches Q2, Q3 can be corrected simply by changing the circuit layout of the control circuits 100a, 100b according to the embodiment. Therefore, there is no need to increase the number of terminals for transmitting the OFF timing to the control circuit 100a of the main converter 20, and it is possible to prevent problems such as an increase in size or the need for design changes.

[0078] According to the control circuits 100a and 100b of the embodiment, the on-width correction unit 130 determines the on-width of the control signal OUT(F) by comparing the timing when the interleaved input signal information IL_IN(F) turns off with the timing when the critical point detection information ZC(F) turns off, so that the on-width of the control signal OUT(F) can be determined according to the difference in the inductance values ​​of the inductors L1, L2, and L3, and the deviation in the on-period of the slave switch can be appropriately adjusted.

[0079] According to the control circuits 100a and 100b of the embodiment, when the timing at which the interleave input signal information IL_IN(F) turns off is later than the timing at which the critical point detection information ZC(F) turns off, the on-width correction unit 130 outputs to the interleave control unit 140 on-width information corrected to lengthen the on-width of the control signal OUT(F). This prevents the on-timing of the slave switches Q2 and Q3 from gradually becoming earlier than their original on-timing, and makes it possible to suppress the deviation in the on-period of the slave switches Q2 and Q3 within the interleave detection period.

[0080] In addition, when the timing at which the interleave input signal information IL_IN(F) turns off is earlier than the timing at which the critical point detection information ZC(F) turns off, on-width information corrected to shorten the on-width of the control signal OUT(F) is output to the interleave control unit 140, thereby preventing the on-timing of the slave switches Q2, Q3 from gradually becoming slower than their original on-timing, and making it possible to suppress the deviation in the on-period of the slave switches Q2, Q3 within the interleave detection period.

[0081] According to the control circuits 100a and 100b of the embodiment, when the timing at which the interleaved input signal information IL_IN(F) turns off is later than the timing at which the critical point detection information ZC(F) turns off, the on-width correction unit 130 lowers the frequency of the clock signal CLK by a predetermined number of times out of the number of times up-counting is performed to reduce the number of up-counts, thereby lengthening the on-period of the slave switches Q2 and Q3. This prevents a situation in which the on-width becomes too long due to an excessively large correction of the on-period, causing the on-width to gradually become slower than the original on-timing and exceed the interleave detection period.

[0082] In addition, when the timing at which the interleave input signal information IL_IN(F) turns off is earlier than the timing at which the critical point detection information ZC(F) turns off, the frequency of the clock signal CLK is lowered by a predetermined number of down-counts to reduce the number of down-counts, thereby lengthening the on-period of the slave switches Q2, Q3 and preventing a situation in which the on-width becomes too long due to an excessively large correction of the on-period, causing the on-timing to gradually become slower than the original on-timing and exceed the interleave detection period.

[0083] According to the control circuits 100a and 100b of the embodiment, when the timing at which the interleaved input signal information IL_IN(F) turns off is later than the timing at which the critical point detection information ZC(F) turns off, the on-width correction unit 130 lowers the frequency of the clock signal CLK to reduce the number of up-counts from the timing at which the critical point detection information ZC(F) turns off to the timing at which the interleaved input signal information IL_IN(F) turns off. Therefore, even in this case, the on-period of the slave switches Q2 and Q3 is extended, and it is possible to prevent a situation in which the on-width becomes too long due to too large a correction of the on-period, causing the on-width to gradually become slower than the original on-timing and exceed the interleaved detection period.

[0084] In addition, when the timing at which the interleave input signal information IL_IN(F) turns off is earlier than the timing at which the critical point detection information ZC(F) turns off, the frequency of the clock signal CLK is lowered to reduce the number of down-counts between the timing at which the interleave input signal information IL_IN(F) turns off or the timing at which the critical point detection information ZC(F) turns off. Therefore, even in this case, the on-period of the slave switches Q2, Q3 is shortened, and it is possible to prevent a situation in which the on-width becomes too short due to an excessively large correction of the on-period, causing the on-timing to gradually become earlier than the original on-timing and exceed the interleave detection period.

[0085] According to the control circuits 100a and 100b of the embodiment, the on-width correction unit 130 repeatedly turns on and off the clock signal CLK of the clock 132 at a frequency determined by multiplying a predetermined frequency of the clock signal CLK by the inverse of the on-width correction magnification, and therefore can determine an on-width correction magnification corresponding to the variation in the inductance values ​​of the inductors L1, L2, and L3, and adjust the on-widths of the slave switches Q2 and Q3.

[0086] According to the control circuits 100a and 100b of the embodiment, a mask period is provided during which the control signal OUT(F) cannot be output to the drive unit 150 for a predetermined period after the interleaved input signal information IL_IN(F) is turned on. Therefore, when the on-periods of the main converter 20 and the sub converters 30 and 40 significantly differ due to on-width correction, resulting in a phase difference that makes interleaved operation impossible, the sub converters 30 and 40 can be reset by restarting them to maintain interleaved operation.

[0087] According to the interleaved power supply 1 of the embodiment, since it is provided with multiple (two stages) slave converters as slave converters, the load of each converter can be better distributed and overload operation of the main converter 20 can be more reliably prevented.

[0088] [Variation 1] The interleaved power supply (not shown) of variant example 1 basically has the same configuration as the interleaved power supply 1 of the embodiment, but differs from the interleaved power supply 1 of the embodiment in that the on-width correction magnification is 3x instead of 2x.

[0089] For example, if the timing at which the interleaved input signal information IL_IN(F)IL_IN(F) turns off is later than the timing at which the critical point detection information ZC(F) turns off, the result will be as shown in Fig. 10. That is, from the timing at which the drain voltage VDS(F) of the slave switch Q2 and the voltage of the ZC terminal that detects the critical point go low to the timing at which the interleaved input signal information IL_IN(F) turns off (three up-counts), the clock frequency of the clock becomes 1 / 3 times (the period is three times) the normal frequency A.

[0090] Accordingly, at the timing when the interleaved input signal information IL_IN(F) turns off, the slave switch Q2 has counted 10 times, and then counts down 13 times (10 counts up + 3 times) until the counter reaches 0, at which point the slave switch Q2 is turned off. This makes it possible to extend the on-period of the slave switch Q2 by 3 counts longer than the on-period of the main switch Q1.

[0091] For example, if the timing at which the interleave input signal information IL_IN(F) turns off is earlier than the timing at which the critical point detection information ZC(F) turns off, the result will be as shown in Fig. 11. That is, from the timing at which the interleave input signal information IL_IN(F) turns off to the timing at which the drain voltage VDS(F) of the slave switch Q2 and the critical point detection information ZC(F) go low (three down-counts), the frequency of the clock signal CLK of the clock 132 becomes 1 / 3 times (three times the period) the normal frequency A.

[0092] Accordingly, the control signal OUT(F) and the interleave signal output information are turned on when the drain voltage VDS(F) and the critical point detection information ZC(F) of the slave switch Q2 are turned off. From that point, the counter counts down the remaining number of times (17 times), and turns off the control signal OUT(F) when the counter reaches 0. This makes it possible to make the on period of the slave switch Q2 three counts shorter than the on period of the main switch Q1.

[0093] Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment. It can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0094] (1) The positions, connections, quantities, etc. described in the above embodiment (including each modified example; the same applies below) are merely examples and may be changed without impairing the effects of the present invention.

[0095] (2) In the above embodiment, two stages of slave converters are provided (three stages in total), but the present invention is not limited to this. One stage of slave converters (two stages in total) may be provided, or three or more stages of slave converters (four or more stages in total) may be provided.

[0096] (3) In the above embodiment, the ON width correction magnification is set to 2 times, and in the above modification, the ON width correction magnification is set to 3 times, but the present invention is not limited to this. The ON width correction magnification can be set to an appropriate value as long as the correction does not cause a phase shift.

[0097] (4) In the above embodiment, the critical point of the input current of the slave converter is detected by detecting the choke current of the inductor using an auxiliary winding arranged opposite the inductor, but the present invention is not limited to this. The critical point of the input current of the slave converter may be detected by detecting a zero voltage point from the drain voltage of the master switch or the slave switch (see FIG. 12, interleaved power supply 2 according to modification 2).

[0098] (5) In the above embodiment, the ON width of the control signal is adjusted by comparing the timing when the interleave input signal information switches OFF with the timing when the critical point detection information switches OFF, but the present invention is not limited to this. The ON width of the control signal may be adjusted by comparing the timing when the interleave input signal information switches ON with the timing when the critical point detection information switches ON. [Explanation of symbols]

[0099] 1...interleaved power supply, 10...rectifier circuit, 20...main converter, 30, 40...slave converter, 100a, 100b...control circuit (follower IC), 110...interleaved signal input section, 112...mask period setting section, 120...critical point detection section, 130...on-width correction section, 132...clock, 134...counter, 140...interleaved control section, 150...drive section, 160...interleaved signal generation section, 200...main switch control section (leader IC), IL_IN(F)...interleaved input signal information, OUT(F)...control signal, Q1...main switch, Q2, Q3...slave switches, ZC(F)...critical point detection information

Claims

1. A control circuit for controlling the switching operation of the slave switch for an interleaved power supply including a main converter having a main switch that performs a switching operation, and a slave converter having a slave switch that performs switching in a state having a phase difference with respect to the switching operation of the main switch, the control circuit comprising: the control circuit includes an interleave signal input unit, a critical point detection unit, an on-width correction unit, an interleave control unit, and a drive unit; The interleaved signal input unit acquires an interleaved input signal input from the main converter or the preceding sub converter, and outputs interleaved input signal information generated based on the interleaved input signal to the on-width correction unit; the critical point detection unit detects a critical point of a current flowing through an inductor of the slave converter to generate critical point detection information, and outputs the critical point detection information to the on-width correction unit and the interleave control unit; the on-width correction unit outputs, to the interleave control unit, on-width information corrected to adjust an on-width of a control signal that controls on / off of the slave switch based on the interleave input signal information and the critical point detection information; The interleave control unit outputs the control signal, the on-width of which is adjusted based on the critical point detection information and the corrected on-width information, to the driving unit; The control circuit is characterized in that the drive unit turns on and off the slave switch based on the control signal.

2. The control circuit according to claim 1, characterized in that the on-width correction unit outputs corrected on-width information to the interleave control unit so as to adjust the on-width of the control signal by comparing the timing at which the interleave input signal information switches on or off with the timing at which the critical point detection information switches on or off.

3. The on-width correction unit is When the timing at which the interleave input signal information switches on or off is later than the timing at which the critical point detection information switches on or off, the on-width information corrected to increase the on-width of the control signal is output to the interleave control unit; The control circuit according to claim 1, characterized in that when the timing at which the interleave input signal information switches on or off is earlier than the timing at which the critical point detection information switches on or off, the on-width information corrected to shorten the on-width of the control signal is output to the interleave control unit.

4. A clock that outputs a clock signal that repeats on and off at a predetermined frequency; a counter that counts up in accordance with a cycle of the clock signal from the timing when the interleaved input signal is turned on or off, and counts down in accordance with a cycle of the clock signal from the timing when the interleaved input signal is turned off or on, The on-width correction unit is When the timing at which the interleave input signal information switches to ON or OFF is slower than the timing at which the critical point detection information switches to ON or OFF, the frequency of the clock signal is lowered by a predetermined number of times among the number of times the up-count is performed to reduce the number of times the up-count is performed; A control circuit as described in any one of claims 1 to 3, characterized in that when the timing at which the interleaved input signal information switches on or off is earlier than the timing at which the critical point detection information switches on or off, the frequency of the clock signal is lowered by a predetermined number of times out of the number of times the down-count is performed, thereby reducing the number of times the down-count is performed.

5. A clock that outputs a clock signal that repeats on and off at a predetermined frequency; a counter that counts up in accordance with a cycle of the clock signal from the timing when the interleave input signal is turned on or off, and counts down in accordance with a cycle of the clock signal from the timing when the interleave input signal is turned on or off, The on-width correction unit is When the timing at which the interleave input signal information is switched on or off is later than the timing at which the critical point detection information is switched on or off, the frequency of the clock signal is lowered to reduce the number of up-counts during the period from the timing at which the critical point detection information is switched on or off to the timing at which the interleave input signal information is switched on or off; A control circuit as described in any one of claims 1 to 3, characterized in that when the timing at which the interleaved input signal information switches on or off is earlier than the timing at which the critical point detection information switches on or off, the frequency of the clock signal is lowered to reduce the number of down-counts from the timing at which the interleaved input signal information switches on or off to the timing at which the critical point detection information switches on or off.

6. 5. The control circuit according to claim 4, wherein, when the frequency of the clock signal is lowered, the clock signal is repeatedly turned on and off at a frequency determined by multiplying a predetermined frequency by the reciprocal of an on-width correction magnification factor.

7. 6. The control circuit according to claim 5, wherein, when the frequency of the clock signal is lowered, the clock signal is repeatedly turned on and off at a frequency determined by multiplying a predetermined frequency by the reciprocal of an on-width correction magnification.

8. A control circuit as described in any one of claims 1 to 3, characterized in that a mask period is provided in which the control signal cannot be output to the drive unit for a predetermined period after the interleaved input signal information is switched on or off.

9. An interleaved power supply comprising the control circuit according to any one of claims 1 to 3.

10. The slave converter includes a plurality of slave converters, 10. The interleaved power supply according to claim 9, wherein each of the plurality of slave converters comprises a control circuit according to any one of claims 1 to 3.

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