Storage device

Abstract

To provide a storage device having high data holding performance.SOLUTION: A storage device according to an embodiment includes a transistor, a capacitor, a plate line, and a bit line. The transistor comprises an oxide semiconductor and includes a first end, a second end, and a gate. The capacitor includes a third end and a fourth end connected to the second end. The plate line is connected to the third end. The bit line is connected to the first end. A second voltage lower than the first voltage is applied to the plate line during a first period in which a first voltage is applied to the gate, and a fourth voltage higher than the second voltage is applied to the plate line during at least a part of a second period in which a third voltage lower than the first voltage is applied to the gate.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments generally relate to storage devices. [Background technology]

[0002] DRAM (Dynamic Random Access Memory) is known as a type of storage device. A DRAM memory cell includes a capacitor and a transistor. The memory cell holds data based on the charge stored in the capacitor. A sense amplifier amplifies a voltage based on the data of a memory cell that is the target of data reading, thereby determining the stored data. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-168622 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention aims to provide a storage device having high data retention performance. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a transistor, a capacitor, a plate line, and a bit line. The transistor includes an oxide semiconductor and includes a first end, a second end, and a gate. The capacitor includes a third end and a fourth end connected to the second end. The plate line is connected to the third end. The bit line is connected to the first end. A second voltage lower than the first voltage is applied to the plate line during a first period in which a first voltage is applied to the gate, and a fourth voltage higher than the second voltage is applied to the plate line during at least a portion of a second period in which a third voltage lower than the first voltage is applied to the gate. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 shows components of a storage device according to a first embodiment and connections between the components. [Diagram 2] FIG. 2 shows components of the core circuit of the memory device of the first embodiment and connections of the components. [Diagram 3] FIG. 3 shows some components and connections of the components of the sub-core circuit of the memory device of the first embodiment. [Figure 4] FIG. 4 shows an example of components and connections of the components in the memory cell array of the memory device of the first embodiment. [Diagram 5] FIG. 5 shows another example of components and connections of the components in the memory cell array of the memory device of the first embodiment. [Figure 6] FIG. 6 illustrates an example of the structure of a memory cell array in the memory device of the first embodiment. [Figure 7] FIG. 7 shows some components and connections of the components of the sense amplifier of the memory device of the first embodiment. [Figure 8] FIG. 8 shows some components and connections of the components of the voltage generating circuit and the driver of the memory device of the first embodiment. [Figure 9] FIG. 9 shows the potentials of some wirings, nodes, and signals in the memory device of the first embodiment over time. [Figure 10] FIG. 10 shows a first example of one state during operation of the storage device of the first embodiment. [Figure 11] FIG. 11 shows a second example of a state during operation of the storage device of the first embodiment. [Figure 12] FIG. 12 shows the potential difference in the memory devices of the comparative example and the first embodiment. [Figure 13] FIG. 13 shows some components and connections of the components of the driver of the storage device of the second embodiment. [Figure 14] FIG. 14 shows the potentials of some wirings, nodes, and signals in the memory device of the second embodiment over time. [Figure 15] FIG. 15 shows some components and connections of the components of the driver of the storage device of the third embodiment. [Figure 16] FIG. 16 shows the potentials of some wirings, nodes, and signals in the memory device of the third embodiment over time. [Figure 17] FIG. 17 shows some components and connections of the components of the voltage generating circuit and the driver of the memory device of the fourth embodiment. [Figure 18] FIG. 18 shows the relationship between voltage and temperature in the memory device of the fourth embodiment. [Figure 19] FIG. 19 shows some components and connections of the components in a voltage generating circuit of a memory device according to the fourth embodiment. [Figure 20] FIG. 20 shows some components and connections of the components of the voltage generating circuit and the driver of the memory device of the fifth embodiment. [Figure 21] FIG. 21 shows the relationship between voltage and temperature in the memory device of the fifth embodiment. [Figure 22] FIG. 22 shows some components and connections of the components in a voltage generating circuit of a memory device according to the fifth embodiment. [Diagram 23] FIG. 23 shows some components and connections of the components in a voltage generating circuit of a memory device according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In an embodiment or different embodiments, a plurality of components having substantially the same functions and configurations may be distinguished from each other by adding an additional number or letter to the end of the reference numeral. In the embodiment following a certain described embodiment, the differences from the described embodiment will be mainly described. All descriptions of one embodiment are applicable to the description of another embodiment, unless expressly or obviously excluded.

[0008] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is constantly or selectively conductive.

[0009] 1. First embodiment 1.1.Configuration (Structure) Overall 1 shows components and connections of the memory device of the first embodiment. The memory device 1 is a device for storing data. The memory device 1 includes a core circuit 11, an input / output circuit 12, a control circuit 13, a decode circuit 14, a page buffer 15, a voltage generation circuit 16, and a driver 17.

[0010] The core circuit 11 is a circuit including memory cells MC, wiring for accessing the memory cells MC, and peripheral circuits. The memory cells MC are elements that store data in a non-volatile manner. The wiring includes word lines WL and bit lines BL. Each memory cell MC is connected to one word line WL and one bit line BL. The word line WL is assigned one row address. The bit line BL is assigned one column address. One memory cell MC is specified by selecting one row and one column.

[0011] The input / output circuit 12 is a circuit that inputs and outputs data and signals. The input / output circuit 12 receives a control signal CNT, a command CMD, an address signal ADD, and data DAT to be written to memory cells MC from outside the memory device 1, for example, from a memory controller. The data DAT to be written to memory cells MC may be referred to as write data WD. The input / output circuit 12 transmits data DAT read from memory cells MC to outside the memory device 1, for example, a memory controller. The data DAT read from memory cells MC may be referred to as read data RD. For example, the input / output circuit 12 complies with DDR5 (Double Data rate 5).

[0012] The control circuit 13 is a circuit that controls the overall operation of the memory device 1. The control circuit 13 receives a command CMD and a control signal CNT from the input / output circuit 12. The control circuit 13 controls the core circuit 11 and controls reading data from and writing data to the memory cells MC based on the control instructed by the command CMD and the control signal CNT. The control circuit 13 controls the voltage generation circuit 16 and the driver 17 based on the control instructed by the command CMD and the control signal CNT.

[0013] The decode circuit 14 is a circuit that decodes the address signal ADD. The decode circuit 14 receives the address signal ADD from the input / output circuit 12. The address signal ADD includes a pair of a row address and a column address that specifies a memory cell MC from which data is to be read or written. The decode circuit 14 decodes the address signal ADD, and generates a signal for selecting a memory cell MC from which data is to be read or written based on the result of the decoding. The generated signal is transmitted to the core circuit 11.

[0014] The page buffer 15 is a circuit that temporarily stores data of a certain size. When writing data to the memory cells MC, the page buffer 15 receives write data WD from the input / output circuit 12, temporarily stores the write data WD, and transfers the write data WD to the core circuit 11. When reading data from the memory cells MC, the page buffer 15 receives read data RD from the core circuit 11, temporarily stores the read data RD, and transfers the stored read data RD to the input / output circuit 12.

[0015] The voltage generating circuit 16 is a circuit that generates various voltages used in the memory device 1. The voltage generating circuit 16 receives a power supply voltage Vdd and a ground (common) voltage Vss, and generates a voltage based on the control of the control circuit 13 using the power supply voltage Vdd and the ground voltage Vss. The ground voltage Vss is 0V. The power supply voltage Vdd and the ground voltage Vss are power supply voltages that the memory device 1 receives from the outside. Alternatively, the power supply voltage Vdd and the ground voltage Vss are internal power supply voltages that are generated from the power supply voltage that the memory device 1 receives from the outside and are used throughout the memory device 1.

[0016] The driver 17 is a circuit that controls the application of a voltage to wiring in the core circuit 11. The driver 17 receives a voltage from the voltage generating circuit 16, and applies the received voltage to the core circuit 11 based on the control of the control circuit 13.

[0017] 1.1.2. Core Circuit Fig. 2 shows components and connections of the components in the core circuit of the memory device of Embodiment 1. As shown in Fig. 2, the core circuit 11 includes a sub-core circuit group SCCG.

[0018] The sub-core circuit group SCCG is a set of a plurality of sub-core circuits SCC. Each sub-core circuit SCC is a circuit including a plurality of memory cells MC, wiring for accessing the memory cells MC, and peripheral circuits. The wiring includes word lines WL and bit lines BL.

[0019] Each sub-core circuit SCC receives a row address and a column address. The row address includes information for identifying one of the plurality of sub-core circuit groups SCCG and information for identifying one of the plurality of sub-core circuits SCC. When each sub-core circuit group SCCG receives the row address including the information for identifying itself, it becomes in a selected state. Sub-core circuit groups SCCG other than the selected sub-core circuit group SCCG remain in a non-selected state.

[0020] When each sub-core circuit SCC receives a row address including information for identifying itself, it enters a selected state. Sub-core circuits SCC other than the selected sub-core circuit SCC remain in a non-selected state.

[0021] In one example, the information identifying the sub-core circuit group SCCG is the value of certain upper bits of a row address, and the information identifying the sub-core circuit SCC is the value of certain middle bits of the row address. The information of certain lower bits of the row address identifies one word line WL. In this case, the sub-core circuits SCC belonging to a certain sub-core circuit group SCCG have a common value in the bit of the row address that identifies the sub-core circuit group SCCG. On the other hand, the sub-core circuits SCC belonging to different sub-core circuit groups SCCG may have different values ​​in the bit of the row address that identifies the sub-core circuit group SCCG, and may have a common value in the bit of the row address that identifies the sub-core circuit SCC.

[0022] 3 shows some components and connections of the sub-core circuits SCC of the memory device of the first embodiment. The sub-core circuits SCC have the same configuration. Each sub-core circuit SCC includes a memory cell array MCA, a plurality of word lines WL, a plurality of bit lines BL, a plate line PL, a row selector RS, and a column selector CS.

[0023] The memory cell array MCA is a set of a plurality of arranged memory cells MC. In the memory cell array MCA, a plurality of word lines WL, a plurality of bit lines BL, and a plate line PL are also arranged.

[0024] The row selector RS is a circuit for selecting one row of the memory cell array (or a corresponding memory cell array) MCA of the sub-core circuit SCC in which the row selector RS is included. The row selector RS receives a row address and places one of the word lines WL in a selected state based on the received row address. When the row selector RS receives a row address that identifies the sub-core circuit SCC and the sub-core circuit group SCCG in which the row selector RS is included, the row selector RS places one of the word lines WL in a selected state based on the received row address. The row selector RS includes a plurality of switches.

[0025] During data read, the sense amplifier SA amplifies the potential on the bit line BL in order to determine the data stored in the memory cell MC from which data is to be read. The sense amplifier SA amplifies the potentials on a plurality of bit lines BL.

[0026] The column selector CS is a circuit for selecting one column of the memory cell array (or the corresponding memory cell array) MCA of the sub-core circuit SCC including the column selector CS. The column selector CS receives a column address and outputs one of the potentials (data) corresponding to the multiple bit lines BL stored in the sense amplifier SA based on the received column address. The column selector CS includes multiple switches.

[0027] Memory Cell Array 4 shows an example of components and connections of the components of the memory cell array of the memory device of the first embodiment. The memory cell array MCA includes a plurality of memory cells MC. In the memory cell array MCA, M word lines WL_0 to WL_M-1, N bit lines BL_0 to BL_N-1, and plate lines PL are also arranged. M and N are positive integers.

[0028] As described above with reference to FIG. 1 and shown in FIG. 4, each memory cell MC is connected to one word line WL and one bit line BL. Each memory cell MC is further connected to a plate line PL. Each memory cell MC includes a cell capacitor CC and a cell transistor CT. The cell transistor CT is an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) CT. Hereinafter, one of the source and drain of a transistor may be referred to as one end of the transistor, and the other may be referred to as the other end of the transistor.

[0029] One end of the cell capacitor CC is connected to the plate line PL, and the other end is connected to one end of the cell transistor CT. The cell capacitor CC stores data using charges accumulated at a node connected to the cell transistor CT. The node of the cell capacitor CC connected to the cell transistor CT may be hereinafter referred to as a storage node SN.

[0030] The state of whether the storage node SN has accumulated charge corresponds to the state in which the memory cell MC stores data "1" or data "0." In the following, as an example, the state in which the potential of the storage node SN is positive relative to the potential of the plate line PL is treated as the state in which the memory cell MC stores data "1," and the state in which the potential of the storage node SN is negative relative to the potential of the plate line PL is treated as the state in which the memory cell MC stores data "0."

[0031] The cell transistor CT is connected to one bit line BL at the other end, and is connected to one word line WL at the gate. The semiconductor constituting a part of the cell transistor CT provides at least a region (channel region) in which a channel is formed. The semiconductor material includes an oxide semiconductor or is substantially composed of an oxide semiconductor. In this specification and claims, "substantially composed" means that the element "substantially composed" is allowed to contain unintended impurities. An oxide semiconductor refers to an oxide having semiconductor properties. An example of an oxide semiconductor is an oxide containing one or more of indium (In), gallium (Ga), aluminum (Al), zinc (Zn), and tin (Sn). In one example, the oxide semiconductor is composed of, for example, In, Ga, Zn, and O. In another example, it is composed of In, Al, Zn, and O.

[0032] 5 shows another example of components of the memory cell array of the memory device of the first embodiment and connections of the components. The memory cell array MCA may have a hierarchical structure as shown in FIG. 5. As shown in FIG. 5, the memory cell array MCA includes P global bit lines GBL_0 to GBL_P-1, N selection lines SBL_0 to SBL_N-1, M word lines WL_0 to WL_M-1, and N sets of bit lines BL_0 to BL_N-1. The set of bit lines BL_0 includes P bit lines BL_0. Similarly, the set of bit lines BL_α includes P bit lines BL_α for all cases where α is an integer value between 1 and N-1.

[0033] Each global bit line GBL is connected to a bit line BL_0 via a selection transistor GT0. Similarly, for all cases where β is an integer value between 1 and N-1, each global bit line GBL is connected to a bit line BL_β via a selection transistor GT_β. The gates of the P selection transistors GT_0 connected to the global bit lines GBL_0 to GBL_P-1, respectively, are connected to a selection line SBL_0. Similarly, for all cases where β is an integer value between 1 and N-1, each global bit line GBL is connected to a selection line SBL_β.

[0034] Fig. 6 shows a schematic example of a structure of a memory cell array of the memory device of the first embodiment. Fig. 6 shows a structure for realizing the type of memory cell array shown in Fig. 5. As shown in Fig. 6, memory cells MC are arranged three-dimensionally. The structure of the memory cell array MCA includes a plurality of sub-structures 20. The sub-structures 20 are arranged in the Y direction. Each sub-structure 20 includes a plurality of memory cells MC, a plurality of switches SW1, a plurality of switches SW2, a plurality of conductors 22, a plurality of conductors 23, and conductors 24, 25, and 26.

[0035] Each sub-structure 20 includes a set of memory cells MC aligned in the X direction. The memory cells MC aligned in the X direction constitute a memory cell set MCS. The memory cells MC in the memory cell set MCS are connected to one conductor 21 at the gate of the cell transistor CT (not shown). The conductor 21 functions as a word line WL. The conductor 21 extends in the X direction.

[0036] One end of a cell capacitor CC (not shown) of each memory cell MC in the memory cell set MCS is connected to one conductor 22. The conductor 22 functions as a part of a plate line PL. The conductor 22 extends in the X direction.

[0037] One end of the conductor 21 is connected to one end of the switch SW1. In one example, the switch SW1 is a metal oxide semiconductor (MOSFET). The other end of the switch SW1 is connected to the conductor 25. The conductor 25 is connected to the voltage generating circuit 16 and receives, for example, a voltage applied to an unselected word line WL.

[0038] The other end of the conductor 21 is connected to the other end of the switch SW2. In one example, the switch SW2 is a MOSFET. The other end of the switch SW2 is connected to a conductor 26. The conductor 26 is connected to the voltage generating circuit 16 and receives, for example, a voltage applied to a selected word line WL.

[0039] A plurality of sets each consisting of one memory cell set MCS, conductors 21 and 22 connected to the memory cell set MCS, and switches SW1 and SW2 connected to the conductor 21 are provided in the Z direction.

[0040] Each of the memory cells MC aligned in the Z direction has one end of the cell transistor CT connected to one conductor 23. The conductor 23 extends in the Z direction. The conductor 23 functions as a bit line BL.

[0041] The multiple conductors 22 aligned in the Z direction are connected to the conductors 24. The conductors 24 function as part of the plate lines PL. The conductors 22 and 24 may be provided integrally, and may extend in a planar manner in the X and Z directions, for example.

[0042] Each conductor 23 is connected at its upper end in the Z direction to one end of one selection transistor GT. The gates of the multiple selection transistors GT aligned in the X direction are connected to a conductor 28. The conductor 28 extends in the X direction. The conductor 28 functions as a selection line SBL.

[0043] The other end of each selection transistor GT is connected to a conductor 29. The conductor 29 is located above the selection transistor GT. The conductor 29 extends in the Y direction. The conductor 29 functions as a global bit line GBL.

[0044] Sense Amplifiers Fig. 7 shows some components and connections of the components of the sense amplifier of the memory device of Embodiment 1. As shown in Fig. 7, each sense amplifier SA includes a sense amplifier circuit SAC and an equalizer circuit EQC.

[0045] The sense amplifier circuit SAC is a circuit that amplifies the potential on the bit line BL in order to determine the data stored in the memory cell MC from which data is to be read. The sense amplifier circuit SAC receives a power supply voltage Vdd and a ground voltage Vss from the voltage generating circuit 16, and operates using the received voltages. The sense amplifier circuit SAC is connected to one bit line BL and one complementary bit line BL. The complementary bit line BL functions as a node having a reference potential (or standard potential). The reference potential is used to determine the data stored in the memory cell MC from which data is to be read.

[0046] The equalizer circuit EQC is a circuit that applies a voltage of a certain magnitude to a circuit connected to the equalizer circuit EQC. The equalizer circuit EQC is connected to one bit line BL and one complementary bit line BL. The equalizer circuit EQC receives a signal EQ and is enabled or disabled based on the signal EQ. When the equalizer circuit EQC is enabled, it applies a precharge voltage to both the bit line BL and the complementary bit line BL. The precharge voltage has a magnitude between the power supply voltage Vdd and the ground voltage Vss, for example, a magnitude of (Vdd-Vss) / 2, i.e., a magnitude of Vdd / 2. The signal EQ is supplied from the control circuit 13.

[0047] An example of the details of the sense amplifier SA will be described below. The sense amplifier circuit SAC includes p-type MOSFETs TP1 and TP2, and n-type MOSFETs TN1, TN2, TN3, TN4, TN5, and TN6. The equalizer circuit EQC includes transistors TN11, TN12, and TN13.

[0048] The transistor TP1 is connected between a node SAP and a node SAt. In one example, the node SAP receives a voltage from the voltage generating circuit 16. In one example, the node SAP receives a power supply voltage Vdd. The transistor TP1 has a gate connected to the node SAc.

[0049] The transistor TN1 is connected between a node SAt and a node SAN. In one example, the node SAN receives a voltage from a voltage generating circuit 16. In one example, the node SAN receives a ground voltage Vss. The transistor TN1 has a gate connected to a complementary bit line BL.

[0050] The transistor TP2 is connected between the node SAP and the node SAc, and has a gate connected to the node SAt.

[0051] The transistor TN2 is connected between the node SAc and the node SAN. The gate of the transistor TN2 is connected to the bit line BL.

[0052] The transistor TN3 is connected between the node SAt and the bit line BL. The transistor TN3 receives a signal ISO at its gate. In one example, the signal ISO is provided from the control circuit 13.

[0053] The transistor TN4 is connected between the node SAc and the complementary bit line BL, and receives the signal ISO at its gate.

[0054] The transistor TN5 is connected between the node SAt and the gate of the transistor TN1. The transistor TN5 receives a signal OC at its gate. In one example, the signal OC is provided from the control circuit 13.

[0055] The transistor TN6 is connected between the node SAc and the gate of the transistor TN2, and receives the signal OC at its gate.

[0056] The transistor TN11 is connected between the bit line BL and a node NBP. The node NBP receives a precharge voltage from the voltage generating circuit 16. The precharge voltage is (Vdd-Vss) / 2, i.e., Vdd / 2, and also functions as a reference voltage. The transistor TN11 receives a signal EQ at its gate. The signal EQ is supplied from, for example, the control circuit 13.

[0057] The transistor TN12 is connected between the complementary bit line BL and a node NBP, and receives a signal EQ at its gate.

[0058] The transistor TN13 is connected between the bit line BL and the complementary bit line BL, and receives a signal EQ at its gate.

[0059] The transistors TN5 and TN6 are provided to correct the variation between the threshold voltage of the transistor TN1 and the threshold voltage of the transistor TN2, and are not essential. The transistors TN3 and TN4 are also not essential. Therefore, the transistors TN3, TN4, TN5, and TN6 may be omitted. In this case, the gate of the transistor TP1 is connected to the complementary bit line BL, and the gate of the transistor TP2 is connected to the bit line BL.

[0060] Voltage Generation Circuit FIG. 8 shows some components and connections of the components of the voltage generating circuit and the driver of the memory device of the first embodiment.

[0061] As shown in FIG. 8, the voltage generating circuit 16 includes a Vdd / 2 generating circuit 161, a Vnn generating circuit 163, a Vpp generating circuit 164, and a Vdd / 2 generating circuit 165.

[0062] The Vdd / 2 generation circuit 161 is a circuit that generates a voltage Vdd / 2 from a voltage received by the memory device 1. In one example, the Vdd / 2 generation circuit 161 includes a regulator circuit. The Vdd / 2 generation circuit 161 is enabled or disabled by a control signal EN1. The control signal EN1 is supplied from the control circuit 13.

[0063] The Vnn generation circuit 163 is a circuit that generates a voltage Vnn from a voltage received by the memory device 1. The voltage Vnn is lower than the ground voltage Vss and is a negative voltage. In one example, the Vnn generation circuit 163 includes a charge pump circuit. The Vnn generation circuit 163 is enabled or disabled by a control signal EN2. The control signal EN2 is supplied from the control circuit 13.

[0064] The Vpp generation circuit 164 is a circuit that generates a voltage Vpp from the voltage received by the storage device 1. The voltage Vpp is higher than the power supply voltage Vdd. In one example, the Vpp generation circuit 164 includes a charge pump circuit. The Vpp generation circuit 164 is enabled or disabled by a control signal EN3. The control signal EN3 is supplied from the control circuit 13.

[0065] The Vdd / 2 generation circuit 165 is a circuit that generates a voltage Vdd / 2 from a voltage received by the memory device 1. In one example, the Vdd / 2 generation circuit 165 includes a regulator circuit. The Vdd / 2 generation circuit 165 supplies the voltage Vdd / 2 to the equalizer circuit EQC. The Vdd / 2 generation circuit 165 is enabled or disabled by a control signal EN4. The control signal EN4 is supplied from the control circuit 13.

[0066] The driver 17 includes PL driver circuits 171 and 172 and WL driver circuits 173 and 174 .

[0067] The PL driver circuits 171 and 172 are circuits that control the voltage of the plate line PL. The PL driver circuit 171 receives a voltage Vdd / 2 from the Vdd / 2 generation circuit 161. The PL driver circuit 171 is enabled or disabled based on the control of the control circuit 13. While the PL driver circuit 171 is enabled, it applies the voltage Vdd / 2 to the plate line PL.

[0068] The PL driver circuit 172 receives a power supply voltage Vdd. The PL driver circuit 172 is enabled or disabled under the control of the control circuit 13. While the PL driver circuit 172 is enabled, it applies the power supply voltage Vdd to the plate line PL. By enabling only one of the PL driver circuits 171 and 172, the voltage received by the enabled PL driver circuit 171 or 172 is applied to the plate line PL.

[0069] The WL driver circuit 173 receives the voltage Vnn from the Vnn generation circuit 163. The WL driver circuit 173 is enabled or disabled based on the control of the control circuit 13. While enabled, the WL driver circuit 173 applies the voltage Vnn to the word line WL.

[0070] The WL driver circuit 174 receives the voltage Vpp. The WL driver circuit 174 is enabled or disabled based on the control of the control circuit 13. The WL driver circuit 174 applies the voltage Vpp to the word line WL while it is enabled. By enabling only one of the WL driver circuits 173 and 174, the voltage received by the enabled WL driver circuit 173 or 174 is applied to the word line WL.

[0071] 1.2.Operation 9 shows the potentials of some of the wiring, nodes, and signals of the memory device of the first embodiment over time. In the following description, the potentials of the wiring, nodes, and signals are maintained until the time when they transition to another magnitude, as described.

[0072] The memory cell MC from which data is read may be referred to as a selected memory cell MC. The word line WL whose potential is shown in Fig. 9 is the word line WL connected to the selected memory cell MC, and may be referred to as a selected word line WL hereinafter. Fig. 9 also shows the potential of word lines WL (unselected word lines WL) other than the word line WL connected to the selected memory cell MC by dashed lines.

[0073] The bit line BL whose potential is shown in FIG. 9 is the bit line BL connected to the selected memory cell MC during data read, and may be referred to as the selected bit line BL below. The complementary bit line BL whose potential is shown in FIG. 9 is the complementary bit line BL connected to the selected bit line BL via the sense amplifier circuit SAC. When a voltage is applied to the wiring shown in the figure or the wiring transmitting a signal, the wiring has a potential substantially equal to the applied voltage. For example, a certain wiring has a power supply potential Vdd, so that the power supply voltage Vdd is applied to the wiring. The signal EQ whose potential is shown in FIG. 9 is the signal EQ supplied to the equalizer circuit EQC of the SA of the sense amplifier connected to the selected bit line BL.

[0074] Hereinafter, when the selected memory cell MC stores "0" data, it may be referred to as the "0" data storage case, and when the selected memory cell MC stores "1" data, it may be referred to as the "1" data storage case.

[0075] At the start of the period shown in Figure 9, each line and signal has the potential described below. The word line WL has a potential Vnn. Therefore, the cell transistor CT of the selected memory cell MC is turned off. The potential Vnn is used to apply a large reverse bias to the cell transistor CT to suppress leakage current of the cell transistor CT.

[0076] The signal EQ has the power supply potential Vdd. Therefore, the transistors TN11 and TN12 are on. Therefore, in both the "0" data storage case and the "1" data storage case, the bit line BL and the complementary bit line BL are precharged (equalized) and have a potential Vdd / 2.

[0077] Plate line PL has a potential Vdd / 2, which is accomplished by enabling PL driver circuit 171 and disabling the other driver circuits (including PL driver circuit 172) connected to plate line PL.

[0078] The period from time t1 to time t6 is a read period. At time t1, the signal EQ is set to the ground potential Vss. This ends the precharge, and the bit line BL and the complementary bit line BL have independent potentials.

[0079] At time t2, a voltage Vpp is applied to the word line WL. The voltage Vpp is higher than the ground voltage Vss and has a magnitude sufficient to turn on the cell transistor CT. Due to the application of the voltage Vpp, the potential of the word line WL continues to rise from time t2 to the potential Vpp.

[0080] The potential of the word line WL continues to rise, and at time t3, the cell transistor CT of the memory cell MC turns on. This starts charge sharing. Due to charge sharing, the charge stored in the bit line BL and the charge stored in the storage node SN of the selected memory cell MC are shared. As a result, the potential of the bit line BL rises or falls based on the data stored in the selected memory cell MC.

[0081] In the case of storing data "0", the potential of the bit line BL falls toward the potential of the storage node SN and the potential of the storage node SN rises toward the potential of the bit line BL. The bit line BL and the storage node SN are in a state where they have a potential equal to the falling potential of the bit line BL and the rising potential of the storage node SN. The potential of the complementary bit line BL is maintained.

[0082] In the case of storing data "1", the potential of the storage node SN falls toward the potential of the bit line BL and the potential of the bit line BL rises toward the potential of the storage node SN. The bit line BL and the storage node SN are in a state where they have a potential equal to the rising potential of the bit line BL and the falling potential of the storage node SN. The potential of the complementary bit line BL is maintained.

[0083] At time t4, the sense amplifier circuit SAC is enabled, whereby the potential of the bit line BL or the complementary bit line BL, whichever has the higher potential, is raised to the power supply potential Vdd, and the potential of the one having the lower potential is lowered to the ground potential Vss.

[0084] At time t5, the voltage Vnn is applied to the word line WL. Due to the application of the voltage Vnn, the potential of the word line WL continues to drop from time t5 to the potential Vnn, which turns off the cell transistor CT of the selected memory cell MC.

[0085] Between time t1 and time t5, the potential of the word lines WL other than the word line WL connected to the selected memory cell MC, ie, the unselected word lines WL, is maintained at the potential Vnn.

[0086] The period after time t6 is a precharge (or equalization) period. At time t6, the potential of the signal EQ is set to the power supply potential Vdd. Also, at time t6, the sense amplifier circuit SAC is disabled.

[0087] The potential of the signal EQ rises, and at time t7, the transistors TN11 and TN12 are turned on, so that the bit line BL and the complementary bit line BL are precharged to the potential Vdd / 2.

[0088] At time t8, the potential of the plate line PL is raised. As a result, the potential of the storage node SN rises by the same amount as the increase in the potential of the plate line PL due to the capacitive coupling between the storage node SN and the plate line PL via the cell capacitor CC, since the storage node SN is in a floating state. In one example, the potential of the plate line PL is set to the power supply potential Vdd. Therefore, the potential of the plate line PL rises by Vdd / 2. The following description is based on this example. Due to the increase in the potential of the plate line PL, the potential of the storage node SN rises by Vdd / 2. In the case of storing data "0", the potential of the storage node SN is Vdd / 2. In the case of storing data "1", the potential of the storage node SN is Vdd+Vdd / 2.

[0089] At time t9, the potential of the plate line PL is set to the potential Vdd / 2. As a result, the potential of the floating storage node SN drops by Vdd / 2 due to capacitive coupling between the storage node SN and the plate line PL via the cell capacitor CC. As a result of the change in the signal voltage at time t9, the potentials of the lines, nodes, and signals return to the potentials at the start of the period shown in FIG.

[0090] The change of the potential of the plate line PL to the potential Vdd / 2 at time t9 is performed when the memory device 1 receives a command for starting data reading after time t8. That is, when the memory device 1 receives the command for starting data reading, the control circuit 13 sets the potential of the plate line PL to the potential Vdd / 2 in order to start data reading, similar to the data reading from time t1. The command for starting data reading is an active command based on an example in which the input / output circuit 12 complies with DDR5.

[0091] The control described above with reference to Fig. 9 may be applied to sub-core circuits SCC other than the sub-core circuit SCC including the selected memory cell MC. However, in a sub-core circuit SCC that does not include the selected memory cell MC, the potential of the word line WL is maintained at potential Vnn, as described above, as an example. Hereinafter, the sub-core circuit SCC including the selected memory cell MC may be referred to as a selected sub-core circuit SCC_s. A sub-core circuit SCC other than the selected sub-core circuit SCC_s may be referred to as an unselected sub-core circuit SCC_n.

[0092] In one example, while the potential of the plate line PL is set to the power supply potential Vdd, the Vdd / 2 generation circuit 161 is disabled.

[0093] Fig. 10 shows a first example of a state during operation of the memory device of the first embodiment. As shown in Fig. 10, in all unselected sub-core circuits SCC_n in the selected sub-core circuit group SCCG_s, the potential of the plate line PL is set to the potential Vdd during precharge. In addition, in all unselected sub-core circuits SCC_n in the selected sub-core circuit group SCCG_s, the potential of the plate line PL is also set to Vdd during data read from the selected sub-core circuit SCC_s.

[0094] 11 shows a second example of a state during operation of the memory device of the first embodiment. The second example relates to sub-core circuit groups SCCG other than the selected sub-core circuit group SCCG_s. The sub-core circuit groups SCCG other than the selected sub-core circuit group SCCG_s may be referred to as unselected sub-core circuit groups SCCG_n.

[0095] As shown in Fig. 11, during precharge, the potential of the plate lines PL is set to the potential Vdd in all sub-core circuits SCC_n of the unselected sub-core circuit group SCCG_n in addition to all unselected sub-core circuits SCC_n of the selected sub-core circuit group SCCG_s shown in Fig. 10. Furthermore, the potential of the plate lines PL is set to Vdd in all sub-core circuits SCC_n of the unselected sub-core circuit group SCCG_n even during data read from the selected sub-core circuit SCC_s.

[0096] 1.3. Advantages (Effects) According to the first embodiment, as described below, it is possible to provide a storage device having high data retention performance.

[0097] The data retention performance during precharging of a memory cell of a DRAM including a transistor having an oxide semiconductor as a region in which a channel is formed (hereinafter, may be referred to as an oxide semiconductor DRAM) depends on the potential difference Vgs between the gate and source of the cell transistor, not the potential difference Vds between the source and drain of the cell transistor. That is, as shown in FIG. 12 as a comparative example, in a "1" data storage case, the potential difference Vds is Vdd-Vdd / 2 because the storage node SN has the power supply potential Vdd and the bit line BL has the potential Vdd / 2. In a "0" data storage case, the potential difference Vds is Vdd / 2 because the storage node SN has the ground potential Vss and the bit line BL has the potential Vdd / 2. The potential difference between the source and drain of the cell transistor CT is the same in the "1" data storage case and the "0" data storage case.

[0098] On the other hand, in the case of storing data "1", the potential difference Vgs is Vnn-Vdd / 2 because the gate (i.e., the word line WL) has a potential Vnn and the source (i.e., the bit line BL) has a potential Vdd / 2. Therefore, a large reverse bias of Vnn-Vdd / 2 is applied between the gate and the source, so the current leaking through the cell transistor CT is small. In the case of storing data "0", the potential difference Vgs is Vnn-Vss because the gate has a potential Vnn and the source (i.e., the storage node SN) has a potential Vss.

[0099] Vnn-Vss in the "0" data storage case is smaller than Vnn-Vdd / 2 in the "1" data storage case. Therefore, the reverse bias applied between the gate and source is small, and a leakage current may flow through the cell transistor CT. The leakage current deteriorates the data retention performance of the memory cell. Therefore, in order to improve the data retention performance of the memory cell, it is desirable to improve the retention performance in the "0" data storage case.

[0100] According to the first embodiment, during precharge, the potential of the plate line PL is set to the power supply potential Vdd. Therefore, during precharge, the potential of the storage node SN has a magnitude of Vdd / 2 in the case of storing data "0" and a magnitude of Vdd+Vdd / 2 in the case of storing data "1". In the case of storing data "0", the gate of the cell transistor CT has a potential Vnn and the potential of the source is Vdd / 2, so the potential difference Vgs is Vnn-Vdd / 2. This has a larger negative absolute value than Vnn-Vss in the comparative example. Therefore, the current leaking through the cell transistor CT is suppressed more than in the comparative example, and the memory device 1 has high data retention performance. The case of storing data "1" in the first embodiment is the same as that in the comparative example.

[0101] According to the first embodiment, during precharge, the potential of the plate line PL is set to the power supply potential Vdd. Therefore, during precharge, the Vdd / 2 generation circuit 161 can be disabled. The operation of the Vdd / 2 generation circuit 161 for generating the voltage Vdd / 2 consumes current. Therefore, disabling the Vdd / 2 generation circuit 161 and applying the power supply potential Vdd consumes less current. Thus, the current consumption during precharge is suppressed, and the current consumption of the memory device 1 is suppressed. In addition, since there is no need to apply the potential Vdd / 2 to a large number of word lines WL, the Vdd / 2 generation circuit 161 does not need to have high capability (or capacity), and the area of ​​the Vdd / 2 generation circuit 161 may be small.

[0102] In DDR5, a mode called MPSM (Maximum Power Saving Mode) is defined. MPSM starts when a storage device in an idle state receives a command to enter MPSM. In MPSM, the storage device stops (disables) the operation of many parts, so that it consumes less current than in the idle state. On the other hand, a storage device in MPSM does not guarantee retention of data stored before entering MPSM. Storage device 1 has high data retention performance during precharge. Therefore, data can be guaranteed even in MPSM.

[0103] 2. Second embodiment The second embodiment differs from the first embodiment in the voltage applied to the word line WL during precharging.

[0104] 13 shows some components and connections of the components of the driver of the memory device of the second embodiment. Fig. 13 also shows a voltage generating circuit 16. The driver 17b of the memory device 1b of the second embodiment further includes a WL driver circuit 177.

[0105] The WL driver circuit 177 receives a ground voltage Vss. The WL driver circuit 177 is enabled or disabled based on the control of the control circuit 13. The WL driver circuit 177 applies the ground voltage Vss to the word line WL while it is enabled. By enabling only one of the WL driver circuit 173, the WL driver circuit 174, and the WL driver circuit 177, the voltage received by the enabled WL driver circuit 173, 174, or 177 is applied to the word line WL.

[0106] 14 shows the potentials of some lines, nodes, and signals of the memory device of the second embodiment over time. At time t8, the potential of the word line WL is set to the ground potential Vss. As described above in the first embodiment, the potential of the plate line PL is set to the power supply potential Vdd during precharge, so that the potential difference Vgs between the gate and source of the cell transistor CT is large. Therefore, even if the potential of the word line WL is not as low as the potential Vnn during precharge, data is maintained in the memory cell MC. The potential of the word line WL is set to the potential Vnn at time t9.

[0107] In one example, while the potential of the word line WL is set to the ground potential Vss, the Vnn generating circuit 163 is disabled.

[0108] According to the second embodiment, the potential of the plate line PL is set to the power supply potential Vdd during the precharge, thereby providing the same advantages as the first embodiment.

[0109] According to the second embodiment, the potential of the word line WL is set to the ground potential Vss during the precharge. The potential of the plate line PL is set to the power supply potential Vdd during the precharge, so that data is maintained in the memory cell MC even if the potential of the word line WL is not as low as the potential Vnn during the precharge. Therefore, the Vnn generation circuit 163 can be disabled during the precharge. This reduces the current consumption during the precharge, and reduces the current consumption of the memory device 1.

[0110] 3. Third embodiment The third embodiment differs from the first embodiment in the voltage applied to the bit line BL during precharging.

[0111] 15 shows some components and connections of the components of the driver of the memory device of the third embodiment. 15 also shows a voltage generating circuit 16. The driver 17c of the memory device 1c of the third embodiment further includes a driver circuit 178.

[0112] The driver circuit 178 receives the ground voltage Vdd. The driver circuit 178 is enabled or disabled based on the control of the control circuit 13. While the driver circuit 178 is enabled, it applies the ground voltage Vdd to the node NBP of the equalizer circuit EQC. By enabling only one of the driver circuit 178 and the Vdd / 2 generation circuit 165, the voltage of the enabled driver circuit 178 or the Vdd / 2 generation circuit 165 is applied to the node NBP of the equalizer circuit EQC.

[0113] 16 shows the potentials of some lines, nodes, and signals over time in the memory device of the third embodiment. At time t8, the potential of the bit line BL is set to the power supply potential Vdd. This causes the potential of the complementary bit line BL to also be set to the power supply potential Vdd.

[0114] In one example, while the potential of the bit line BL is set to the power supply potential Vdd, the Vdd / 2 generation circuit 165 is disabled.

[0115] According to the third embodiment, the potential of the plate line PL is set to the power supply potential Vdd during the precharge, thereby providing the same advantages as the first embodiment.

[0116] According to the third embodiment, during precharge, the potential of the bit line BL is set to the ground potential Vdd. Therefore, during precharge, the Vdd / 2 generation circuit 165 can be disabled. This allows the regulator circuit of the Vdd / 2 generation circuit 165 to be stopped, so that the current consumption during precharge is suppressed, and the current consumption of the memory device 1 is suppressed.

[0117] The third embodiment may be combined with the second embodiment. When the third embodiment is combined with the second embodiment, the Vdd / 2 generation circuit 161, the Vnn generation circuit 163, the Vpp generation circuit 164, and the Vdd / 2 generation circuit 165 can all be disabled during precharge. Therefore, the current consumption during precharge is further suppressed.

[0118] 4. Fourth embodiment The fourth embodiment is additionally applied to the first, second or third embodiment, and relates to a voltage applied to the plate line PL.

[0119] FIG. 17 shows some components and connections of the components of the voltage generating circuit and the driver of the memory device of the fourth embodiment. FIG. 17 shows an example in which the fourth embodiment is applied to the third embodiment. As shown in FIG. 17, the voltage generating circuit 16d of the memory device 1d of the fourth embodiment further includes a Vpl generating circuit 167. The Vpl generating circuit 167 is a circuit that generates a voltage Vpl. The voltage Vpl has a variable magnitude. The voltage Vpl is applied to the plate line PL instead of the power supply voltage Vdd applied to the plate line PL in the first, second, or third embodiment.

[0120] A driver 17d of the memory device 1d further includes a PL driver circuit 179 instead of the PL driver circuit 172. The PL driver circuit 179 receives a voltage Vpl. The PL driver circuit 179 is enabled or disabled based on the control of the control circuit 13. While enabled, the PL driver circuit 179 applies the voltage Vpl to the plate line PL.

[0121] FIG. 18 shows the relationship between voltage and temperature of the memory device of the fourth embodiment. As shown in FIG. 18, the voltage Vpl depends on the temperature. The voltage Vpl has a positive temperature coefficient, i.e., the higher the temperature of the memory device 1, the higher the voltage Vpl. Therefore, the difference between the voltage Vpl applied to the plate line PL during precharge (between time t8 and time t9 in FIG. 9) and the voltage Vdd / 2 applied to the plate line PL during the rest of the period (between time t1 and time t8 and after time t9 in FIG. 9) is larger when the temperature of the memory device 1 is higher.

[0122] 19 shows some components and connections of the components of the voltage generation circuit of the memory device of the fourth embodiment. As shown in FIG. 19, the Vpl generation circuit 167 includes a reference voltage generation circuit 31, a charge pump 32, and a voltage comparison circuit 33.

[0123] The reference voltage generating circuit 31 is a circuit that generates a reference voltage Vref1 that functions as a reference for generating the voltage Vpl. The reference voltage Vref1 has a variable magnitude. The reference voltage generating circuit 31 includes a temperature sensor 34. The temperature sensor 34 generates a temperature signal based on the temperature at the position where the temperature sensor 34 is located. The reference voltage generating circuit 31 generates the reference voltage Vref1 using the temperature signal from the temperature sensor 34. The reference voltage Vref1 has a positive temperature coefficient like the voltage Vpl, and has the same temperature coefficient as the voltage Vpl.

[0124] The charge pump 32 is a circuit that uses a voltage received by the charge pump 32 to generate a voltage different from the voltage received by the charge pump 32. The charge pump 32 receives a power supply voltage Vdd and a ground voltage Vss, and generates a voltage Vpl using the power supply voltage Vdd and the ground voltage Vss. The charge pump 32 changes the magnitude of the voltage Vpl based on a control signal CN1 from the voltage comparison circuit 33.

[0125] The voltage comparison circuit 33 is a circuit that compares the voltages it receives and outputs a signal based on the comparison. The voltage comparison circuit 33 receives the voltage Vpl and a reference voltage Vref1. When the voltage Vpl exceeds the reference voltage Vref1 by a certain amount or more, the voltage comparison circuit 33 supplies the charge pump 32 with a control signal CN1 that instructs the charge pump 32 to lower the magnitude of the voltage Vpl. When the voltage Vpl falls below the reference voltage Vref1 by a certain amount or more, the voltage comparison circuit 33 supplies the charge pump 32 with a control signal CN1 that instructs the charge pump 32 to increase the magnitude of the voltage Vpl.

[0126] According to the fourth embodiment, the voltage Vpl has a positive temperature coefficient, which makes it possible to provide a memory device 1d that has high data retention performance even at high temperatures.

[0127] In the fourth embodiment, instead of the power supply voltage Vdd applied to the bit line BL in the third embodiment, a voltage having a variable magnitude depending on temperature may be applied. This variable voltage may have, for example, a positive temperature coefficient, and in this case, the higher the temperature of the memory device 1, the higher the voltage. The variable voltage may be generated by a circuit having a similar configuration to the Vpl generation circuit 167, and the generated voltage is input to the driver circuit 178. This configuration also makes it possible to control the voltage applied between the gate and the source, and to provide a memory device 1d having high data retention performance even at high temperatures.

[0128] 5. Fifth embodiment The fifth embodiment is additionally applied to the first, second, third or fourth embodiment, and relates to a voltage applied to the word line WL.

[0129] FIG. 20 shows some components and connections of the components of the voltage generating circuit and the driver of the memory device of the fifth embodiment. FIG. 20 shows an example in which the fifth embodiment is applied to the fourth embodiment. As shown in FIG. 20, the Vnn generating circuit 163e of the memory device 1e of the fifth embodiment generates a voltage Vnnv. The voltage Vnnv has a variable magnitude. The Vpp generating circuit 164e of the memory device 1e of the fifth embodiment generates a voltage Vppv. The voltage Vppv has a variable magnitude.

[0130] The WL driver circuit 173 receives a voltage Vnnv instead of the voltage Vnn, and the WL driver circuit 174 receives a voltage Vppv instead of the voltage Vpp.

[0131] FIG. 21 shows the relationship between voltage and temperature of the storage device of the fifth embodiment. As shown in FIG. 21, the voltage Vppv depends on temperature. The voltage Vppv has a negative temperature coefficient, that is, the higher the temperature of the storage device 1, the lower the voltage Vppv is. The voltage Vnnv has a negative temperature coefficient. The temperature coefficient of the voltage Vppv is different from the temperature coefficient of the voltage Vnnv.

[0132] 22 shows some components and connections of the components of the voltage generating circuit of the memory device of the fifth embodiment. As shown in FIG. 22, the Vnn generating circuit 163e includes a reference voltage generating circuit 41, a charge pump 42, and a voltage comparing circuit 43.

[0133] The reference voltage generating circuit 41 is a circuit that generates a reference voltage Vref2 that functions as a reference for generating the voltage Vnnv. The reference voltage Vref2 has a variable magnitude. The reference voltage generating circuit 41 includes a temperature sensor 44. The temperature sensor 44 generates a temperature signal based on the temperature at the position where the temperature sensor 44 is disposed. The reference voltage generating circuit 41 generates the reference voltage Vref2 using the temperature signal of the temperature sensor 44. The reference voltage Vref2 has a negative temperature coefficient like the voltage Vnnv, and has the same temperature coefficient as the voltage Vnnv.

[0134] The charge pump 42 is a circuit that uses a voltage received by the charge pump 42 to generate a voltage different from the voltage received by the charge pump 42. The charge pump 42 receives a power supply voltage Vdd and a ground voltage Vss, and generates a voltage Vnnv using the power supply voltage Vdd and the ground voltage Vss. The charge pump 42 changes the magnitude of the voltage Vnnv based on a control signal CN2 from a voltage comparison circuit 43.

[0135] The voltage comparison circuit 43 is a circuit that compares the voltages it receives and outputs a signal based on the comparison. The voltage comparison circuit 43 receives the voltage Vnnv and the reference voltage Vref2. When the voltage Vnnv exceeds the reference voltage Vref2 by a certain amount or more, the voltage comparison circuit 43 supplies the charge pump 42 with a control signal CN2 that instructs the charge pump 42 to lower the voltage Vnnv. When the voltage Vnnv falls below the reference voltage Vref2 by a certain amount or more, the voltage comparison circuit 43 supplies the charge pump 42 with a control signal CN2 that instructs the charge pump 42 to increase the voltage Vnnv.

[0136] 23 shows some components and connections of the components of the voltage generation circuit of the memory device of the fifth embodiment. As shown in FIG. 23, the Vpp generation circuit 164e includes a reference voltage generation circuit 51, a charge pump 52, and a voltage comparison circuit 53.

[0137] The reference voltage generating circuit 51 is a circuit that generates a reference voltage Vref3 that functions as a reference for generating the voltage Vnnv. The reference voltage Vref3 has a variable magnitude. The reference voltage generating circuit 51 includes a temperature sensor 54. The temperature sensor 54 generates a temperature signal based on the temperature at the position where the temperature sensor 54 is disposed. The reference voltage generating circuit 51 generates the reference voltage Vref3 using the temperature signal of the temperature sensor 54. The reference voltage Vref3 has a negative temperature coefficient like the voltage Vppv, and has the same temperature coefficient as the voltage Vppv.

[0138] The charge pump 52 is a circuit that uses a voltage received by the charge pump 52 to generate a voltage different from the voltage received by the charge pump 52. The charge pump 52 receives a power supply voltage Vdd and a ground voltage Vss, and generates a voltage Vppv using the power supply voltage Vdd and the ground voltage Vss. The charge pump 52 changes the magnitude of the voltage Vppv based on a control signal CN3 from the voltage comparison circuit 53.

[0139] The voltage comparison circuit 53 is a circuit that compares the voltages it receives and outputs a signal based on the comparison. The voltage comparison circuit 53 receives the voltage Vppv and the reference voltage Vref3. When the voltage Vppv exceeds the reference voltage Vref3 by a certain amount or more, the voltage comparison circuit 53 supplies the charge pump 52 with a control signal CN3 that instructs the charge pump 52 to lower the voltage Vppv. When the voltage Vppv falls below the reference voltage Vref3 by a certain amount or more, the voltage comparison circuit 53 supplies the charge pump 52 with a control signal CN3 that instructs the charge pump 52 to increase the voltage Vppv.

[0140] The on-current of a transistor containing silicon has a negative temperature coefficient. The on-current is a current that flows between the source and drain of a transistor while the transistor is on. On the other hand, the cell transistor CT containing an oxide semiconductor has a positive temperature coefficient. Therefore, even if a voltage smaller than that at low temperatures is applied to the gate of the cell transistor CT at high temperatures, the cell transistor CT can pass a sufficient on-current. Based on this, according to the fifth embodiment, the voltages Vnnv and Vppv have negative temperature coefficients. Therefore, it is possible to suppress the current consumption in the memory device 1e at high temperatures. In addition, since the voltage applied to the gate of the cell transistor CT at high temperatures is suppressed, it is possible to improve the reliability of the cell transistor CT, and therefore the memory device 1e.

[0141] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0142] 1...Storage device, 11...Core circuit, 12...input / output circuit, 13...Control circuit, 14...Decoding circuit, 15...Page buffer, 16...Voltage generating circuit, 17…Driver, MC: memory cell, WL...word line, BL...bit line, SCC: Sub-core circuit, SCCG: Sub-core circuit group, MCA: memory cell array, RS: Row selector, CS... column selector, SA: Sense amplifier, PL: Plate line, CC: cell capacitor, CT: Cell transistor

Claims

1. a transistor including an oxide semiconductor and including a first end, a second end, and a gate; a capacitor including a third end and a fourth end coupled to the second end; a plate line connected to the third end; a bit line connected to the first end; Equipped with During a first period during which a first voltage is applied to the gate, a second voltage lower than the first voltage is applied to the plate line; a fourth voltage higher than the second voltage is applied to the plate line during at least a part of a second period during which a third voltage lower than the first voltage is applied to the gate; storage device.

2. a first voltage generating circuit configured to generate the second voltage; the first voltage generating circuit is disabled at least during a period during which the fourth voltage is applied to the plate line; The storage device according to claim 1 .

3. After the first period, a fifth voltage lower than the third voltage is applied to the gate, and after the application of the fifth voltage, the third voltage is applied to the gate. The storage device according to claim 1 .

4. the third voltage is applied to the gate during at least a portion of a period during which the fourth voltage is applied to the plate line; The storage device according to claim 3.

5. a second voltage generating circuit configured to generate the fifth voltage; the second voltage generating circuit is disabled at least during a period during which the third voltage is applied to the gate; The storage device according to claim 3.

6. A second bit line; a sense amplifier connected to the bit line and a second bit line; Further equipped with the third voltage is a ground voltage; The storage device according to claim 3.

7. After the first period, a sixth voltage higher than the third voltage is applied to the bit line, and after the application of the sixth voltage, a seventh voltage higher than the sixth voltage is applied to the bit line. The storage device according to claim 1 .

8. the seventh voltage is applied to the bit line during at least a portion of a period during which the fourth voltage is applied to the plate line; The storage device according to claim 7.

9. a third voltage generating circuit configured to generate the sixth voltage; the third voltage generating circuit is disabled at least during a period during which the seventh voltage is applied to the bit line; The storage device according to claim 7.

10. the seventh voltage is a power supply voltage; The storage device according to claim 7.

11. a first circuit including the transistor, the capacitor, the plate line, the bit line, and a sense amplifier connected to the bit line, the first circuit having a first row address; a second circuit including a second memory cell including a transistor and a capacitor connected in series, a second plate line connected to one end of the second memory cell, a second bit line connected to the other end of the second memory cell, and a second sense amplifier connected to the second bit line, the second circuit having a second row address; a third circuit including a third memory cell including a transistor and a capacitor connected in series, a third plate line connected to one end of the third memory cell, a third bit line connected to the other end of the third memory cell, and a third sense amplifier connected to the third bit line, the third circuit having a third row address; Equipped with the first row address and the second row address have the same value in a first portion and different values ​​in a second portion; the third row address has a value in the first portion that is different from values ​​of the first row address and the first portion of the second row address; the fourth voltage is applied to the third plate line during at least a portion of the second period; The storage device according to claim 1 .

12. the fourth voltage is applied to the second plate line during at least a portion of the second period; The storage device according to claim 11.

13. the fourth voltage has a first magnitude when the temperature of the storage device is a first temperature, and has a second magnitude when the temperature is a second temperature; the second temperature is greater than the first temperature; the second height is greater than the first height; The storage device according to claim 1 .

14. the first voltage has a third magnitude when the temperature of the storage device is a first temperature, and has a fourth magnitude when the temperature is a second temperature; the second temperature is greater than the first temperature; the fourth height is less than the third height; The storage device according to claim 1 .

15. a fourth voltage generating circuit that generates a first reference voltage; a first charge pump that outputs the first voltage based on a first control signal; a first comparison circuit that receives the first voltage and the first reference voltage and outputs the first control signal based on a comparison between the first voltage and the first reference voltage; Further comprising: The storage device of claim 14.

16. the third voltage has a fifth magnitude when the temperature is the first temperature and a sixth magnitude when the temperature is the second temperature; the sixth height is less than the fifth height; The storage device of claim 14.

17. a fifth voltage generating circuit that generates a second reference voltage; a second charge pump that outputs the third voltage based on a second control signal; a second comparison circuit that receives the third voltage and the second reference voltage and outputs the second control signal based on a comparison between the third voltage and the second reference voltage; Further comprising: The storage device of claim 16.

18. a rate of change from the third height to the fourth height based on a change in temperature is different from a rate of change from the fifth height to the sixth height based on a change in temperature. The storage device of claim 16.

19. an eighth voltage is applied to the bit line during the second period; The storage device according to any one of claims 1 to 18.

20. Further comprising a third bit line; During the second period, the bit line is connected to the third bit line.

20. The storage device of claim 19.

21. the fourth voltage is a power supply voltage; The storage device according to any one of claims 1 to 18.

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